1 /*
2 * Core definitions and data structures shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#85 $
41 *
42 * $FreeBSD$
43 */
44
45 #ifndef _AIC7XXX_H_
46 #define _AIC7XXX_H_
47
48 /* Register Definitions */
49 #include "aic7xxx_reg.h"
50
51 /************************* Forward Declarations *******************************/
52 struct ahc_platform_data;
53 struct scb_platform_data;
54 struct seeprom_descriptor;
55
56 /****************************** Useful Macros *********************************/
57 #ifndef TRUE
58 #define TRUE 1
59 #endif
60 #ifndef FALSE
61 #define FALSE 0
62 #endif
63
64 #define ALL_CHANNELS '\0'
65 #define ALL_TARGETS_MASK 0xFFFF
66 #define INITIATOR_WILDCARD (~0)
67
68 #define SCSIID_TARGET(ahc, scsiid) \
69 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \
70 >> TID_SHIFT)
71 #define SCSIID_OUR_ID(scsiid) \
72 ((scsiid) & OID)
73 #define SCSIID_CHANNEL(ahc, scsiid) \
74 ((((ahc)->features & AHC_TWIN) != 0) \
75 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \
76 : 'A')
77 #define SCB_IS_SCSIBUS_B(ahc, scb) \
78 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B')
79 #define SCB_GET_OUR_ID(scb) \
80 SCSIID_OUR_ID((scb)->hscb->scsiid)
81 #define SCB_GET_TARGET(ahc, scb) \
82 SCSIID_TARGET((ahc), (scb)->hscb->scsiid)
83 #define SCB_GET_CHANNEL(ahc, scb) \
84 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
85 #define SCB_GET_LUN(scb) \
86 ((scb)->hscb->lun & LID)
87 #define SCB_GET_TARGET_OFFSET(ahc, scb) \
88 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0))
89 #define SCB_GET_TARGET_MASK(ahc, scb) \
90 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
91 #ifdef AHC_DEBUG
92 #define SCB_IS_SILENT(scb) \
93 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \
94 && (((scb)->flags & SCB_SILENT) != 0))
95 #else
96 #define SCB_IS_SILENT(scb) \
97 (((scb)->flags & SCB_SILENT) != 0)
98 #endif
99 #define TCL_TARGET_OFFSET(tcl) \
100 ((((tcl) >> 4) & TID) >> 4)
101 #define TCL_LUN(tcl) \
102 (tcl & (AHC_NUM_LUNS - 1))
103 #define BUILD_TCL(scsiid, lun) \
104 ((lun) | (((scsiid) & TID) << 4))
105
106 #ifndef AHC_TARGET_MODE
107 #undef AHC_TMODE_ENABLE
108 #define AHC_TMODE_ENABLE 0
109 #endif
110
111 /**************************** Driver Constants ********************************/
112 /*
113 * The maximum number of supported targets.
114 */
115 #define AHC_NUM_TARGETS 16
116
117 /*
118 * The maximum number of supported luns.
119 * The identify message only supports 64 luns in SPI3.
120 * You can have 2^64 luns when information unit transfers are enabled,
121 * but it is doubtful this driver will ever support IUTs.
122 */
123 #define AHC_NUM_LUNS 64
124
125 /*
126 * The maximum transfer per S/G segment.
127 */
128 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
129
130 /*
131 * The maximum amount of SCB storage in hardware on a controller.
132 * This value represents an upper bound. Controllers vary in the number
133 * they actually support.
134 */
135 #define AHC_SCB_MAX 255
136
137 /*
138 * The maximum number of concurrent transactions supported per driver instance.
139 * Sequencer Control Blocks (SCBs) store per-transaction information. Although
140 * the space for SCBs on the host adapter varies by model, the driver will
141 * page the SCBs between host and controller memory as needed. We are limited
142 * to 253 because:
143 * 1) The 8bit nature of the RISC engine holds us to an 8bit value.
144 * 2) We reserve one value, 255, to represent the invalid element.
145 * 3) Our input queue scheme requires one SCB to always be reserved
146 * in advance of queuing any SCBs. This takes us down to 254.
147 * 4) To handle our output queue correctly on machines that only
148 * support 32bit stores, we must clear the array 4 bytes at a
149 * time. To avoid colliding with a DMA write from the sequencer,
150 * we must be sure that 4 slots are empty when we write to clear
151 * the queue. This reduces us to 253 SCBs: 1 that just completed
152 * and the known three additional empty slots in the queue that
153 * precede it.
154 */
155 #define AHC_MAX_QUEUE 253
156
157 /*
158 * The maximum amount of SCB storage we allocate in host memory. This
159 * number should reflect the 1 additional SCB we require to handle our
160 * qinfifo mechanism.
161 */
162 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1)
163
164 /*
165 * Ring Buffer of incoming target commands.
166 * We allocate 256 to simplify the logic in the sequencer
167 * by using the natural wrap point of an 8bit counter.
168 */
169 #define AHC_TMODE_CMDS 256
170
171 /* Reset line assertion time in us */
172 #define AHC_BUSRESET_DELAY 25
173
174 /******************* Chip Characteristics/Operating Settings *****************/
175 /*
176 * Chip Type
177 * The chip order is from least sophisticated to most sophisticated.
178 */
179 typedef enum {
180 AHC_NONE = 0x0000,
181 AHC_CHIPID_MASK = 0x00FF,
182 AHC_AIC7770 = 0x0001,
183 AHC_AIC7850 = 0x0002,
184 AHC_AIC7855 = 0x0003,
185 AHC_AIC7859 = 0x0004,
186 AHC_AIC7860 = 0x0005,
187 AHC_AIC7870 = 0x0006,
188 AHC_AIC7880 = 0x0007,
189 AHC_AIC7895 = 0x0008,
190 AHC_AIC7895C = 0x0009,
191 AHC_AIC7890 = 0x000a,
192 AHC_AIC7896 = 0x000b,
193 AHC_AIC7892 = 0x000c,
194 AHC_AIC7899 = 0x000d,
195 AHC_VL = 0x0100, /* Bus type VL */
196 AHC_EISA = 0x0200, /* Bus type EISA */
197 AHC_PCI = 0x0400, /* Bus type PCI */
198 AHC_BUS_MASK = 0x0F00
199 } ahc_chip;
200
201 /*
202 * Features available in each chip type.
203 */
204 typedef enum {
205 AHC_FENONE = 0x00000,
206 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */
207 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */
208 AHC_WIDE = 0x00004, /* Wide Channel */
209 AHC_TWIN = 0x00008, /* Twin Channel */
210 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */
211 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */
212 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */
213 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */
214 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */
215 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */
216 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */
217 AHC_DT = 0x00800, /* Double Transition transfers */
218 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */
219 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */
220 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */
221 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/
222 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */
223 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */
224 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */
225 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */
226 AHC_HVD = 0x100000, /* HVD rather than SE */
227 AHC_AIC7770_FE = AHC_FENONE,
228 /*
229 * The real 7850 does not support Ultra modes, but there are
230 * several cards that use the generic 7850 PCI ID even though
231 * they are using an Ultra capable chip (7859/7860). We start
232 * out with the AHC_ULTRA feature set and then check the DEVSTATUS
233 * register to determine if the capability is really present.
234 */
235 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA,
236 AHC_AIC7860_FE = AHC_AIC7850_FE,
237 AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE,
238 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA,
239 /*
240 * Although we have space for both the initiator and
241 * target roles on ULTRA2 chips, we currently disable
242 * the initiator role to allow multi-scsi-id target mode
243 * configurations. We can only respond on the same SCSI
244 * ID as our initiator role if we allow initiator operation.
245 * At some point, we should add a configuration knob to
246 * allow both roles to be loaded.
247 */
248 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2
249 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID
250 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS
251 |AHC_TARGETMODE,
252 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE,
253 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE
254 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS,
255 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID,
256 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC,
257 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC
258 } ahc_feature;
259
260 /*
261 * Bugs in the silicon that we work around in software.
262 */
263 typedef enum {
264 AHC_BUGNONE = 0x00,
265 /*
266 * On all chips prior to the U2 product line,
267 * the WIDEODD S/G segment feature does not
268 * work during scsi->HostBus transfers.
269 */
270 AHC_TMODE_WIDEODD_BUG = 0x01,
271 /*
272 * On the aic7890/91 Rev 0 chips, the autoflush
273 * feature does not work. A manual flush of
274 * the DMA FIFO is required.
275 */
276 AHC_AUTOFLUSH_BUG = 0x02,
277 /*
278 * On many chips, cacheline streaming does not work.
279 */
280 AHC_CACHETHEN_BUG = 0x04,
281 /*
282 * On the aic7896/97 chips, cacheline
283 * streaming must be enabled.
284 */
285 AHC_CACHETHEN_DIS_BUG = 0x08,
286 /*
287 * PCI 2.1 Retry failure on non-empty data fifo.
288 */
289 AHC_PCI_2_1_RETRY_BUG = 0x10,
290 /*
291 * Controller does not handle cacheline residuals
292 * properly on S/G segments if PCI MWI instructions
293 * are allowed.
294 */
295 AHC_PCI_MWI_BUG = 0x20,
296 /*
297 * An SCB upload using the SCB channel's
298 * auto array entry copy feature may
299 * corrupt data. This appears to only
300 * occur on 66MHz systems.
301 */
302 AHC_SCBCHAN_UPLOAD_BUG = 0x40
303 } ahc_bug;
304
305 /*
306 * Configuration specific settings.
307 * The driver determines these settings by probing the
308 * chip/controller's configuration.
309 */
310 typedef enum {
311 AHC_FNONE = 0x000,
312 AHC_PRIMARY_CHANNEL = 0x003, /*
313 * The channel that should
314 * be probed first.
315 */
316 AHC_USEDEFAULTS = 0x004, /*
317 * For cards without an seeprom
318 * or a BIOS to initialize the chip's
319 * SRAM, we use the default target
320 * settings.
321 */
322 AHC_SEQUENCER_DEBUG = 0x008,
323 AHC_SHARED_SRAM = 0x010,
324 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */
325 AHC_RESET_BUS_A = 0x040,
326 AHC_RESET_BUS_B = 0x080,
327 AHC_EXTENDED_TRANS_A = 0x100,
328 AHC_EXTENDED_TRANS_B = 0x200,
329 AHC_TERM_ENB_A = 0x400,
330 AHC_TERM_ENB_B = 0x800,
331 AHC_INITIATORROLE = 0x1000, /*
332 * Allow initiator operations on
333 * this controller.
334 */
335 AHC_TARGETROLE = 0x2000, /*
336 * Allow target operations on this
337 * controller.
338 */
339 AHC_NEWEEPROM_FMT = 0x4000,
340 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */
341 AHC_INT50_SPEEDFLEX = 0x20000, /*
342 * Internal 50pin connector
343 * sits behind an aic3860
344 */
345 AHC_SCB_BTT = 0x40000, /*
346 * The busy targets table is
347 * stored in SCB space rather
348 * than SRAM.
349 */
350 AHC_BIOS_ENABLED = 0x80000,
351 AHC_ALL_INTERRUPTS = 0x100000,
352 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */
353 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */
354 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */
355 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */
356 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */
357 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */
358 AHC_DISABLE_PCI_PERR = 0x10000000,
359 AHC_HAS_TERM_LOGIC = 0x20000000
360 } ahc_flag;
361
362 /************************* Hardware SCB Definition ***************************/
363
364 /*
365 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
366 * consists of a "hardware SCB" mirroring the fields available on the card
367 * and additional information the kernel stores for each transaction.
368 *
369 * To minimize space utilization, a portion of the hardware scb stores
370 * different data during different portions of a SCSI transaction.
371 * As initialized by the host driver for the initiator role, this area
372 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
373 * the cdb has been presented to the target, this area serves to store
374 * residual transfer information and the SCSI status byte.
375 * For the target role, the contents of this area do not change, but
376 * still serve a different purpose than for the initiator role. See
377 * struct target_data for details.
378 */
379
380 /*
381 * Status information embedded in the shared poriton of
382 * an SCB after passing the cdb to the target. The kernel
383 * driver will only read this data for transactions that
384 * complete abnormally (non-zero status byte).
385 */
386 struct status_pkt {
387 uint32_t residual_datacnt; /* Residual in the current S/G seg */
388 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
389 uint8_t scsi_status; /* Standard SCSI status byte */
390 };
391
392 /*
393 * Target mode version of the shared data SCB segment.
394 */
395 struct target_data {
396 uint32_t residual_datacnt; /* Residual in the current S/G seg */
397 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
398 uint8_t scsi_status; /* SCSI status to give to initiator */
399 uint8_t target_phases; /* Bitmap of phases to execute */
400 uint8_t data_phase; /* Data-In or Data-Out */
401 uint8_t initiator_tag; /* Initiator's transaction tag */
402 };
403
404 struct hardware_scb {
405 /*0*/ union {
406 /*
407 * If the cdb is 12 bytes or less, we embed it directly
408 * in the SCB. For longer cdbs, we embed the address
409 * of the cdb payload as seen by the chip and a DMA
410 * is used to pull it in.
411 */
412 uint8_t cdb[12];
413 uint32_t cdb_ptr;
414 struct status_pkt status;
415 struct target_data tdata;
416 } shared_data;
417 /*
418 * A word about residuals.
419 * The scb is presented to the sequencer with the dataptr and datacnt
420 * fields initialized to the contents of the first S/G element to
421 * transfer. The sgptr field is initialized to the bus address for
422 * the S/G element that follows the first in the in core S/G array
423 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
424 * S/G entry for this transfer (single S/G element transfer with the
425 * first elements address and length preloaded in the dataptr/datacnt
426 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
427 * The SG_FULL_RESID flag ensures that the residual will be correctly
428 * noted even if no data transfers occur. Once the data phase is entered,
429 * the residual sgptr and datacnt are loaded from the sgptr and the
430 * datacnt fields. After each S/G element's dataptr and length are
431 * loaded into the hardware, the residual sgptr is advanced. After
432 * each S/G element is expired, its datacnt field is checked to see
433 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
434 * residual sg ptr and the transfer is considered complete. If the
435 * sequencer determines that there is a residual in the tranfer, it
436 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into
437 * host memory. To sumarize:
438 *
439 * Sequencer:
440 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
441 * or residual_sgptr does not have SG_LIST_NULL set.
442 *
443 * o We are transferring the last segment if residual_datacnt has
444 * the SG_LAST_SEG flag set.
445 *
446 * Host:
447 * o A residual has occurred if a completed scb has the
448 * SG_RESID_VALID flag set.
449 *
450 * o residual_sgptr and sgptr refer to the "next" sg entry
451 * and so may point beyond the last valid sg entry for the
452 * transfer.
453 */
454 /*12*/ uint32_t dataptr;
455 /*16*/ uint32_t datacnt; /*
456 * Byte 3 (numbered from 0) of
457 * the datacnt is really the
458 * 4th byte in that data address.
459 */
460 /*20*/ uint32_t sgptr;
461 #define SG_PTR_MASK 0xFFFFFFF8
462 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */
463 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */
464 /*26*/ uint8_t lun;
465 /*27*/ uint8_t tag; /*
466 * Index into our kernel SCB array.
467 * Also used as the tag for tagged I/O
468 */
469 /*28*/ uint8_t cdb_len;
470 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */
471 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */
472 /*31*/ uint8_t next; /*
473 * Used for threading SCBs in the
474 * "Waiting for Selection" and
475 * "Disconnected SCB" lists down
476 * in the sequencer.
477 */
478 /*32*/ uint8_t cdb32[32]; /*
479 * CDB storage for cdbs of size
480 * 13->32. We store them here
481 * because hardware scbs are
482 * allocated from DMA safe
483 * memory so we are guaranteed
484 * the controller can access
485 * this data.
486 */
487 };
488
489 /************************ Kernel SCB Definitions ******************************/
490 /*
491 * Some fields of the SCB are OS dependent. Here we collect the
492 * definitions for elements that all OS platforms need to include
493 * in there SCB definition.
494 */
495
496 /*
497 * Definition of a scatter/gather element as transferred to the controller.
498 * The aic7xxx chips only support a 24bit length. We use the top byte of
499 * the length to store additional address bits and a flag to indicate
500 * that a given segment terminates the transfer. This gives us an
501 * addressable range of 512GB on machines with 64bit PCI or with chips
502 * that can support dual address cycles on 32bit PCI busses.
503 */
504 struct ahc_dma_seg {
505 uint32_t addr;
506 uint32_t len;
507 #define AHC_DMA_LAST_SEG 0x80000000
508 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000
509 #define AHC_SG_LEN_MASK 0x00FFFFFF
510 };
511
512 struct sg_map_node {
513 bus_dmamap_t sg_dmamap;
514 dma_addr_t sg_physaddr;
515 struct ahc_dma_seg* sg_vaddr;
516 SLIST_ENTRY(sg_map_node) links;
517 };
518
519 /*
520 * The current state of this SCB.
521 */
522 typedef enum {
523 SCB_FREE = 0x0000,
524 SCB_OTHERTCL_TIMEOUT = 0x0002,/*
525 * Another device was active
526 * during the first timeout for
527 * this SCB so we gave ourselves
528 * an additional timeout period
529 * in case it was hogging the
530 * bus.
531 */
532 SCB_DEVICE_RESET = 0x0004,
533 SCB_SENSE = 0x0008,
534 SCB_CDB32_PTR = 0x0010,
535 SCB_RECOVERY_SCB = 0x0020,
536 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */
537 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */
538 SCB_ABORT = 0x0100,
539 SCB_UNTAGGEDQ = 0x0200,
540 SCB_ACTIVE = 0x0400,
541 SCB_TARGET_IMMEDIATE = 0x0800,
542 SCB_TRANSMISSION_ERROR = 0x1000,/*
543 * We detected a parity or CRC
544 * error that has effected the
545 * payload of the command. This
546 * flag is checked when normal
547 * status is returned to catch
548 * the case of a target not
549 * responding to our attempt
550 * to report the error.
551 */
552 SCB_TARGET_SCB = 0x2000,
553 SCB_SILENT = 0x4000 /*
554 * Be quiet about transmission type
555 * errors. They are expected and we
556 * don't want to upset the user. This
557 * flag is typically used during DV.
558 */
559 } scb_flag;
560
561 struct scb {
562 struct hardware_scb *hscb;
563 union {
564 SLIST_ENTRY(scb) sle;
565 TAILQ_ENTRY(scb) tqe;
566 } links;
567 LIST_ENTRY(scb) pending_links;
568 ahc_io_ctx_t io_ctx;
569 struct ahc_softc *ahc_softc;
570 scb_flag flags;
571 struct scb_platform_data *platform_data;
572 struct sg_map_node *sg_map;
573 struct ahc_dma_seg *sg_list;
574 dma_addr_t sg_list_phys;
575 u_int sg_count;/* How full ahc_dma_seg is */
576 };
577
578 struct scb_data {
579 SLIST_HEAD(, scb) free_scbs; /*
580 * Pool of SCBs ready to be assigned
581 * commands to execute.
582 */
583 struct scb *scbindex[256]; /*
584 * Mapping from tag to SCB.
585 * As tag identifiers are an
586 * 8bit value, we provide space
587 * for all possible tag values.
588 * Any lookups to entries at or
589 * above AHC_SCB_MAX_ALLOC will
590 * always fail.
591 */
592 struct hardware_scb *hscbs; /* Array of hardware SCBs */
593 struct scb *scbarray; /* Array of kernel SCBs */
594 struct scsi_sense_data *sense; /* Per SCB sense data */
595
596 /*
597 * "Bus" addresses of our data structures.
598 */
599 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
600 bus_dmamap_t hscb_dmamap;
601 dma_addr_t hscb_busaddr;
602 bus_dma_tag_t sense_dmat;
603 bus_dmamap_t sense_dmamap;
604 dma_addr_t sense_busaddr;
605 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
606 SLIST_HEAD(, sg_map_node) sg_maps;
607 uint8_t numscbs;
608 uint8_t maxhscbs; /* Number of SCBs on the card */
609 uint8_t init_level; /*
610 * How far we've initialized
611 * this structure.
612 */
613 };
614
615 /************************ Target Mode Definitions *****************************/
616
617 /*
618 * Connection descriptor for select-in requests in target mode.
619 */
620 struct target_cmd {
621 uint8_t scsiid; /* Our ID and the initiator's ID */
622 uint8_t identify; /* Identify message */
623 uint8_t bytes[22]; /*
624 * Bytes contains any additional message
625 * bytes terminated by 0xFF. The remainder
626 * is the cdb to execute.
627 */
628 uint8_t cmd_valid; /*
629 * When a command is complete, the firmware
630 * will set cmd_valid to all bits set.
631 * After the host has seen the command,
632 * the bits are cleared. This allows us
633 * to just peek at host memory to determine
634 * if more work is complete. cmd_valid is on
635 * an 8 byte boundary to simplify setting
636 * it on aic7880 hardware which only has
637 * limited direct access to the DMA FIFO.
638 */
639 uint8_t pad[7];
640 };
641
642 /*
643 * Number of events we can buffer up if we run out
644 * of immediate notify ccbs.
645 */
646 #define AHC_TMODE_EVENT_BUFFER_SIZE 8
647 struct ahc_tmode_event {
648 uint8_t initiator_id;
649 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
650 #define EVENT_TYPE_BUS_RESET 0xFF
651 uint8_t event_arg;
652 };
653
654 /*
655 * Per enabled lun target mode state.
656 * As this state is directly influenced by the host OS'es target mode
657 * environment, we let the OS module define it. Forward declare the
658 * structure here so we can store arrays of them, etc. in OS neutral
659 * data structures.
660 */
661 #ifdef AHC_TARGET_MODE
662 struct ahc_tmode_lstate {
663 struct cam_path *path;
664 struct ccb_hdr_slist accept_tios;
665 struct ccb_hdr_slist immed_notifies;
666 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE];
667 uint8_t event_r_idx;
668 uint8_t event_w_idx;
669 };
670 #else
671 struct ahc_tmode_lstate;
672 #endif
673
674 /******************** Transfer Negotiation Datastructures *********************/
675 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */
676 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
677 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */
678 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */
679
680 #define AHC_WIDTH_UNKNOWN 0xFF
681 #define AHC_PERIOD_UNKNOWN 0xFF
682 #define AHC_OFFSET_UNKNOWN 0xFF
683 #define AHC_PPR_OPTS_UNKNOWN 0xFF
684
685 /*
686 * Transfer Negotiation Information.
687 */
688 struct ahc_transinfo {
689 uint8_t protocol_version; /* SCSI Revision level */
690 uint8_t transport_version; /* SPI Revision level */
691 uint8_t width; /* Bus width */
692 uint8_t period; /* Sync rate factor */
693 uint8_t offset; /* Sync offset */
694 uint8_t ppr_options; /* Parallel Protocol Request options */
695 };
696
697 /*
698 * Per-initiator current, goal and user transfer negotiation information. */
699 struct ahc_initiator_tinfo {
700 uint8_t scsirate; /* Computed value for SCSIRATE reg */
701 struct ahc_transinfo curr;
702 struct ahc_transinfo goal;
703 struct ahc_transinfo user;
704 };
705
706 /*
707 * Per enabled target ID state.
708 * Pointers to lun target state as well as sync/wide negotiation information
709 * for each initiator<->target mapping. For the initiator role we pretend
710 * that we are the target and the targets are the initiators since the
711 * negotiation is the same regardless of role.
712 */
713 struct ahc_tmode_tstate {
714 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS];
715 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS];
716
717 /*
718 * Per initiator state bitmasks.
719 */
720 uint16_t auto_negotiate;/* Auto Negotiation Required */
721 uint16_t ultraenb; /* Using ultra sync rate */
722 uint16_t discenable; /* Disconnection allowed */
723 uint16_t tagenable; /* Tagged Queuing allowed */
724 };
725
726 /*
727 * Data structure for our table of allowed synchronous transfer rates.
728 */
729 struct ahc_syncrate {
730 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */
731 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */
732 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */
733 #define ST_SXFR 0x010 /* Rate Single Transition Only */
734 #define DT_SXFR 0x040 /* Rate Double Transition Only */
735 uint8_t period; /* Period to send to SCSI target */
736 const char *rate;
737 };
738
739 /* Safe and valid period for async negotiations. */
740 #define AHC_ASYNC_XFER_PERIOD 0x45
741 #define AHC_ULTRA2_XFER_PERIOD 0x0a
742
743 /*
744 * Indexes into our table of syncronous transfer rates.
745 */
746 #define AHC_SYNCRATE_DT 0
747 #define AHC_SYNCRATE_ULTRA2 1
748 #define AHC_SYNCRATE_ULTRA 3
749 #define AHC_SYNCRATE_FAST 6
750 #define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT
751 #define AHC_SYNCRATE_MIN 13
752
753 /***************************** Lookup Tables **********************************/
754 /*
755 * Phase -> name and message out response
756 * to parity errors in each phase table.
757 */
758 struct ahc_phase_table_entry {
759 uint8_t phase;
760 uint8_t mesg_out; /* Message response to parity errors */
761 char *phasemsg;
762 };
763
764 /************************** Serial EEPROM Format ******************************/
765
766 struct seeprom_config {
767 /*
768 * Per SCSI ID Configuration Flags
769 */
770 uint16_t device_flags[16]; /* words 0-15 */
771 #define CFXFER 0x0007 /* synchronous transfer rate */
772 #define CFSYNCH 0x0008 /* enable synchronous transfer */
773 #define CFDISC 0x0010 /* enable disconnection */
774 #define CFWIDEB 0x0020 /* wide bus device */
775 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/
776 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */
777 #define CFSTART 0x0100 /* send start unit SCSI command */
778 #define CFINCBIOS 0x0200 /* include in BIOS scan */
779 #define CFRNFOUND 0x0400 /* report even if not found */
780 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
781 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */
782 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */
783
784 /*
785 * BIOS Control Bits
786 */
787 uint16_t bios_control; /* word 16 */
788 #define CFSUPREM 0x0001 /* support all removeable drives */
789 #define CFSUPREMB 0x0002 /* support removeable boot drives */
790 #define CFBIOSEN 0x0004 /* BIOS enabled */
791 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */
792 #define CFSM2DRV 0x0010 /* support more than two drives */
793 #define CFSTPWLEVEL 0x0010 /* Termination level control */
794 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */
795 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
796 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */
797 #define CFEXTEND 0x0080 /* extended translation enabled */
798 #define CFSCAMEN 0x0100 /* SCAM enable */
799 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
800 #define CFMSG_VERBOSE 0x0000
801 #define CFMSG_SILENT 0x0200
802 #define CFMSG_DIAG 0x0400
803 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */
804 /* UNUSED 0xff00 */
805
806 /*
807 * Host Adapter Control Bits
808 */
809 uint16_t adapter_control; /* word 17 */
810 #define CFAUTOTERM 0x0001 /* Perform Auto termination */
811 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */
812 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */
813 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */
814 #define CFSTERM 0x0004 /* SCSI low byte termination */
815 #define CFWSTERM 0x0008 /* SCSI high byte termination */
816 #define CFSPARITY 0x0010 /* SCSI parity */
817 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */
818 #define CFMULTILUN 0x0020
819 #define CFRESETB 0x0040 /* reset SCSI bus at boot */
820 #define CFCLUSTERENB 0x0080 /* Cluster Enable */
821 #define CFBOOTCHAN 0x0300 /* probe this channel first */
822 #define CFBOOTCHANSHIFT 8
823 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/
824 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */
825 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */
826 #define CFENABLEDV 0x4000 /* Perform Domain Validation*/
827
828 /*
829 * Bus Release Time, Host Adapter ID
830 */
831 uint16_t brtime_id; /* word 18 */
832 #define CFSCSIID 0x000f /* host adapter SCSI ID */
833 /* UNUSED 0x00f0 */
834 #define CFBRTIME 0xff00 /* bus release time */
835
836 /*
837 * Maximum targets
838 */
839 uint16_t max_targets; /* word 19 */
840 #define CFMAXTARG 0x00ff /* maximum targets */
841 #define CFBOOTLUN 0x0f00 /* Lun to boot from */
842 #define CFBOOTID 0xf000 /* Target to boot from */
843 uint16_t res_1[10]; /* words 20-29 */
844 uint16_t signature; /* Signature == 0x250 */
845 #define CFSIGNATURE 0x250
846 #define CFSIGNATURE2 0x300
847 uint16_t checksum; /* word 31 */
848 };
849
850 /**************************** Message Buffer *********************************/
851 typedef enum {
852 MSG_TYPE_NONE = 0x00,
853 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
854 MSG_TYPE_INITIATOR_MSGIN = 0x02,
855 MSG_TYPE_TARGET_MSGOUT = 0x03,
856 MSG_TYPE_TARGET_MSGIN = 0x04
857 } ahc_msg_type;
858
859 typedef enum {
860 MSGLOOP_IN_PROG,
861 MSGLOOP_MSGCOMPLETE,
862 MSGLOOP_TERMINATED
863 } msg_loop_stat;
864
865 /*********************** Software Configuration Structure *********************/
866 TAILQ_HEAD(scb_tailq, scb);
867
868 struct ahc_aic7770_softc {
869 /*
870 * Saved register state used for chip_init().
871 */
872 uint8_t busspd;
873 uint8_t bustime;
874 };
875
876 struct ahc_pci_softc {
877 /*
878 * Saved register state used for chip_init().
879 */
880 uint32_t devconfig;
881 uint16_t targcrccnt;
882 uint8_t command;
883 uint8_t csize_lattime;
884 uint8_t optionmode;
885 uint8_t crccontrol1;
886 uint8_t dscommand0;
887 uint8_t dspcistatus;
888 uint8_t scbbaddr;
889 uint8_t dff_thrsh;
890 };
891
892 union ahc_bus_softc {
893 struct ahc_aic7770_softc aic7770_softc;
894 struct ahc_pci_softc pci_softc;
895 };
896
897 typedef void (*ahc_bus_intr_t)(struct ahc_softc *);
898 typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *);
899 typedef int (*ahc_bus_suspend_t)(struct ahc_softc *);
900 typedef int (*ahc_bus_resume_t)(struct ahc_softc *);
901 typedef void ahc_callback_t (void *);
902
903 struct ahc_softc {
904 bus_space_tag_t tag;
905 bus_space_handle_t bsh;
906 struct scb_data *scb_data;
907
908 struct scb *next_queued_scb;
909
910 /*
911 * SCBs that have been sent to the controller
912 */
913 BSD_LIST_HEAD(, scb) pending_scbs;
914
915 /*
916 * Counting lock for deferring the release of additional
917 * untagged transactions from the untagged_queues. When
918 * the lock is decremented to 0, all queues in the
919 * untagged_queues array are run.
920 */
921 u_int untagged_queue_lock;
922
923 /*
924 * Per-target queue of untagged-transactions. The
925 * transaction at the head of the queue is the
926 * currently pending untagged transaction for the
927 * target. The driver only allows a single untagged
928 * transaction per target.
929 */
930 struct scb_tailq untagged_queues[AHC_NUM_TARGETS];
931
932 /*
933 * Bus attachment specific data.
934 */
935 union ahc_bus_softc bus_softc;
936
937 /*
938 * Platform specific data.
939 */
940 struct ahc_platform_data *platform_data;
941
942 /*
943 * Platform specific device information.
944 */
945 ahc_dev_softc_t dev_softc;
946 struct device *dev;
947
948 /*
949 * Bus specific device information.
950 */
951 ahc_bus_intr_t bus_intr;
952
953 /*
954 * Bus specific initialization required
955 * after a chip reset.
956 */
957 ahc_bus_chip_init_t bus_chip_init;
958
959 /*
960 * Target mode related state kept on a per enabled lun basis.
961 * Targets that are not enabled will have null entries.
962 * As an initiator, we keep one target entry for our initiator
963 * ID to store our sync/wide transfer settings.
964 */
965 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS];
966
967 /*
968 * The black hole device responsible for handling requests for
969 * disabled luns on enabled targets.
970 */
971 struct ahc_tmode_lstate *black_hole;
972
973 /*
974 * Device instance currently on the bus awaiting a continue TIO
975 * for a command that was not given the disconnect priveledge.
976 */
977 struct ahc_tmode_lstate *pending_device;
978
979 /*
980 * Card characteristics
981 */
982 ahc_chip chip;
983 ahc_feature features;
984 ahc_bug bugs;
985 ahc_flag flags;
986 struct seeprom_config *seep_config;
987
988 /* Values to store in the SEQCTL register for pause and unpause */
989 uint8_t unpause;
990 uint8_t pause;
991
992 /* Command Queues */
993 uint8_t qoutfifonext;
994 uint8_t qinfifonext;
995 uint8_t *qoutfifo;
996 uint8_t *qinfifo;
997
998 /* Critical Section Data */
999 struct cs *critical_sections;
1000 u_int num_critical_sections;
1001
1002 /* Channel Names ('A', 'B', etc.) */
1003 char channel;
1004 char channel_b;
1005
1006 /* Initiator Bus ID */
1007 uint8_t our_id;
1008 uint8_t our_id_b;
1009
1010 /*
1011 * PCI error detection.
1012 */
1013 int unsolicited_ints;
1014
1015 /*
1016 * Target incoming command FIFO.
1017 */
1018 struct target_cmd *targetcmds;
1019 uint8_t tqinfifonext;
1020
1021 /*
1022 * Cached copy of the sequencer control register.
1023 */
1024 uint8_t seqctl;
1025
1026 /*
1027 * Incoming and outgoing message handling.
1028 */
1029 uint8_t send_msg_perror;
1030 ahc_msg_type msg_type;
1031 uint8_t msgout_buf[12];/* Message we are sending */
1032 uint8_t msgin_buf[12];/* Message we are receiving */
1033 u_int msgout_len; /* Length of message to send */
1034 u_int msgout_index; /* Current index in msgout */
1035 u_int msgin_index; /* Current index in msgin */
1036
1037 /*
1038 * Mapping information for data structures shared
1039 * between the sequencer and kernel.
1040 */
1041 bus_dma_tag_t parent_dmat;
1042 bus_dma_tag_t shared_data_dmat;
1043 bus_dmamap_t shared_data_dmamap;
1044 dma_addr_t shared_data_busaddr;
1045
1046 /*
1047 * Bus address of the one byte buffer used to
1048 * work-around a DMA bug for chips <= aic7880
1049 * in target mode.
1050 */
1051 dma_addr_t dma_bug_buf;
1052
1053 /* Number of enabled target mode device on this card */
1054 u_int enabled_luns;
1055
1056 /* Initialization level of this data structure */
1057 u_int init_level;
1058
1059 /* PCI cacheline size. */
1060 u_int pci_cachesize;
1061
1062 /*
1063 * Count of parity errors we have seen as a target.
1064 * We auto-disable parity error checking after seeing
1065 * AHC_PCI_TARGET_PERR_THRESH number of errors.
1066 */
1067 u_int pci_target_perr_count;
1068 #define AHC_PCI_TARGET_PERR_THRESH 10
1069
1070 /* Maximum number of sequencer instructions supported. */
1071 u_int instruction_ram_size;
1072
1073 /* Per-Unit descriptive information */
1074 const char *description;
1075 char *name;
1076 int unit;
1077
1078 /* Selection Timer settings */
1079 int seltime;
1080 int seltime_b;
1081
1082 uint16_t user_discenable;/* Disconnection allowed */
1083 uint16_t user_tagenable;/* Tagged Queuing allowed */
1084 };
1085
1086 /************************ Active Device Information ***************************/
1087 typedef enum {
1088 ROLE_UNKNOWN,
1089 ROLE_INITIATOR,
1090 ROLE_TARGET
1091 } role_t;
1092
1093 struct ahc_devinfo {
1094 int our_scsiid;
1095 int target_offset;
1096 uint16_t target_mask;
1097 u_int target;
1098 u_int lun;
1099 char channel;
1100 role_t role; /*
1101 * Only guaranteed to be correct if not
1102 * in the busfree state.
1103 */
1104 };
1105
1106 /****************************** PCI Structures ********************************/
1107 typedef int (ahc_device_setup_t)(struct ahc_softc *);
1108
1109 struct ahc_pci_identity {
1110 uint64_t full_id;
1111 uint64_t id_mask;
1112 const char *name;
1113 ahc_device_setup_t *setup;
1114 };
1115
1116 /***************************** VL/EISA Declarations ***************************/
1117 struct aic7770_identity {
1118 uint32_t full_id;
1119 uint32_t id_mask;
1120 const char *name;
1121 ahc_device_setup_t *setup;
1122 };
1123 extern struct aic7770_identity aic7770_ident_table[];
1124 extern const int ahc_num_aic7770_devs;
1125
1126 #define AHC_EISA_SLOT_OFFSET 0xc00
1127 #define AHC_EISA_IOSIZE 0x100
1128
1129 /*************************** Function Declarations ****************************/
1130 /******************************************************************************/
1131
1132 /***************************** PCI Front End *********************************/
1133 const struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t);
1134 int ahc_pci_config(struct ahc_softc *,
1135 const struct ahc_pci_identity *);
1136 int ahc_pci_test_register_access(struct ahc_softc *);
1137 #ifdef CONFIG_PM
1138 void ahc_pci_resume(struct ahc_softc *ahc);
1139 #endif
1140
1141 /*************************** EISA/VL Front End ********************************/
1142 struct aic7770_identity *aic7770_find_device(uint32_t);
1143 int aic7770_config(struct ahc_softc *ahc,
1144 struct aic7770_identity *,
1145 u_int port);
1146
1147 /************************** SCB and SCB queue management **********************/
1148 int ahc_probe_scbs(struct ahc_softc *);
1149 void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc,
1150 struct scb *scb);
1151 int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb,
1152 int target, char channel, int lun,
1153 u_int tag, role_t role);
1154
1155 /****************************** Initialization ********************************/
1156 struct ahc_softc *ahc_alloc(void *platform_arg, char *name);
1157 int ahc_softc_init(struct ahc_softc *);
1158 void ahc_controller_info(struct ahc_softc *ahc, char *buf);
1159 int ahc_chip_init(struct ahc_softc *ahc);
1160 int ahc_init(struct ahc_softc *ahc);
1161 void ahc_intr_enable(struct ahc_softc *ahc, int enable);
1162 void ahc_pause_and_flushwork(struct ahc_softc *ahc);
1163 #ifdef CONFIG_PM
1164 int ahc_suspend(struct ahc_softc *ahc);
1165 int ahc_resume(struct ahc_softc *ahc);
1166 #endif
1167 void ahc_set_unit(struct ahc_softc *, int);
1168 void ahc_set_name(struct ahc_softc *, char *);
1169 void ahc_free(struct ahc_softc *ahc);
1170 int ahc_reset(struct ahc_softc *ahc, int reinit);
1171
1172 /***************************** Error Recovery *********************************/
1173 typedef enum {
1174 SEARCH_COMPLETE,
1175 SEARCH_COUNT,
1176 SEARCH_REMOVE
1177 } ahc_search_action;
1178 int ahc_search_qinfifo(struct ahc_softc *ahc, int target,
1179 char channel, int lun, u_int tag,
1180 role_t role, uint32_t status,
1181 ahc_search_action action);
1182 int ahc_search_untagged_queues(struct ahc_softc *ahc,
1183 ahc_io_ctx_t ctx,
1184 int target, char channel,
1185 int lun, uint32_t status,
1186 ahc_search_action action);
1187 int ahc_search_disc_list(struct ahc_softc *ahc, int target,
1188 char channel, int lun, u_int tag,
1189 int stop_on_first, int remove,
1190 int save_state);
1191 int ahc_reset_channel(struct ahc_softc *ahc, char channel,
1192 int initiate_reset);
1193
1194 /*************************** Utility Functions ********************************/
1195 void ahc_compile_devinfo(struct ahc_devinfo *devinfo,
1196 u_int our_id, u_int target,
1197 u_int lun, char channel,
1198 role_t role);
1199 /************************** Transfer Negotiation ******************************/
1200 const struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1201 u_int *ppr_options, u_int maxsync);
1202 u_int ahc_find_period(struct ahc_softc *ahc,
1203 u_int scsirate, u_int maxsync);
1204 /*
1205 * Negotiation types. These are used to qualify if we should renegotiate
1206 * even if our goal and current transport parameters are identical.
1207 */
1208 typedef enum {
1209 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1210 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1211 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */
1212 } ahc_neg_type;
1213 int ahc_update_neg_request(struct ahc_softc*,
1214 struct ahc_devinfo*,
1215 struct ahc_tmode_tstate*,
1216 struct ahc_initiator_tinfo*,
1217 ahc_neg_type);
1218 void ahc_set_width(struct ahc_softc *ahc,
1219 struct ahc_devinfo *devinfo,
1220 u_int width, u_int type, int paused);
1221 void ahc_set_syncrate(struct ahc_softc *ahc,
1222 struct ahc_devinfo *devinfo,
1223 const struct ahc_syncrate *syncrate,
1224 u_int period, u_int offset,
1225 u_int ppr_options,
1226 u_int type, int paused);
1227 typedef enum {
1228 AHC_QUEUE_NONE,
1229 AHC_QUEUE_BASIC,
1230 AHC_QUEUE_TAGGED
1231 } ahc_queue_alg;
1232
1233 /**************************** Target Mode *************************************/
1234 #ifdef AHC_TARGET_MODE
1235 void ahc_send_lstate_events(struct ahc_softc *,
1236 struct ahc_tmode_lstate *);
1237 void ahc_handle_en_lun(struct ahc_softc *ahc,
1238 struct cam_sim *sim, union ccb *ccb);
1239 cam_status ahc_find_tmode_devs(struct ahc_softc *ahc,
1240 struct cam_sim *sim, union ccb *ccb,
1241 struct ahc_tmode_tstate **tstate,
1242 struct ahc_tmode_lstate **lstate,
1243 int notfound_failure);
1244 #ifndef AHC_TMODE_ENABLE
1245 #define AHC_TMODE_ENABLE 0
1246 #endif
1247 #endif
1248 /******************************* Debug ***************************************/
1249 #ifdef AHC_DEBUG
1250 extern uint32_t ahc_debug;
1251 #define AHC_SHOW_MISC 0x0001
1252 #define AHC_SHOW_SENSE 0x0002
1253 #define AHC_DUMP_SEEPROM 0x0004
1254 #define AHC_SHOW_TERMCTL 0x0008
1255 #define AHC_SHOW_MEMORY 0x0010
1256 #define AHC_SHOW_MESSAGES 0x0020
1257 #define AHC_SHOW_DV 0x0040
1258 #define AHC_SHOW_SELTO 0x0080
1259 #define AHC_SHOW_QFULL 0x0200
1260 #define AHC_SHOW_QUEUE 0x0400
1261 #define AHC_SHOW_TQIN 0x0800
1262 #define AHC_SHOW_MASKED_ERRORS 0x1000
1263 #define AHC_DEBUG_SEQUENCER 0x2000
1264 #endif
1265 void ahc_print_devinfo(struct ahc_softc *ahc,
1266 struct ahc_devinfo *dev);
1267 void ahc_dump_card_state(struct ahc_softc *ahc);
1268 int ahc_print_register(const ahc_reg_parse_entry_t *table,
1269 u_int num_entries,
1270 const char *name,
1271 u_int address,
1272 u_int value,
1273 u_int *cur_column,
1274 u_int wrap_point);
1275 /******************************* SEEPROM *************************************/
1276 int ahc_acquire_seeprom(struct ahc_softc *ahc,
1277 struct seeprom_descriptor *sd);
1278 void ahc_release_seeprom(struct seeprom_descriptor *sd);
1279 #endif /* _AIC7XXX_H_ */