1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 #define FDOMAIN_REGION_SIZE 0x10
4 #define FDOMAIN_BIOS_SIZE 0x2000
5
6 enum {
7 in_arbitration = 0x02,
8 in_selection = 0x04,
9 in_other = 0x08,
10 disconnect = 0x10,
11 aborted = 0x20,
12 sent_ident = 0x40,
13 };
14
15 /* (@) = not present on TMC1800, (#) = not present on TMC1800 and TMC18C50 */
16 #define REG_SCSI_DATA 0 /* R/W: SCSI Data (with ACK) */
17 #define REG_BSTAT 1 /* R: SCSI Bus Status */
18 #define BSTAT_BSY BIT(0) /* Busy */
19 #define BSTAT_MSG BIT(1) /* Message */
20 #define BSTAT_IO BIT(2) /* Input/Output */
21 #define BSTAT_CMD BIT(3) /* Command/Data */
22 #define BSTAT_REQ BIT(4) /* Request and Not Ack */
23 #define BSTAT_SEL BIT(5) /* Select */
24 #define BSTAT_ACK BIT(6) /* Acknowledge and Request */
25 #define BSTAT_ATN BIT(7) /* Attention */
26 #define REG_BCTL 1 /* W: SCSI Bus Control */
27 #define BCTL_RST BIT(0) /* Bus Reset */
28 #define BCTL_SEL BIT(1) /* Select */
29 #define BCTL_BSY BIT(2) /* Busy */
30 #define BCTL_ATN BIT(3) /* Attention */
31 #define BCTL_IO BIT(4) /* Input/Output */
32 #define BCTL_CMD BIT(5) /* Command/Data */
33 #define BCTL_MSG BIT(6) /* Message */
34 #define BCTL_BUSEN BIT(7) /* Enable bus drivers */
35 #define REG_ASTAT 2 /* R: Adapter Status 1 */
36 #define ASTAT_IRQ BIT(0) /* Interrupt active */
37 #define ASTAT_ARB BIT(1) /* Arbitration complete */
38 #define ASTAT_PARERR BIT(2) /* Parity error */
39 #define ASTAT_RST BIT(3) /* SCSI reset occurred */
40 #define ASTAT_FIFODIR BIT(4) /* FIFO direction */
41 #define ASTAT_FIFOEN BIT(5) /* FIFO enabled */
42 #define ASTAT_PAREN BIT(6) /* Parity enabled */
43 #define ASTAT_BUSEN BIT(7) /* Bus drivers enabled */
44 #define REG_ICTL 2 /* W: Interrupt Control */
45 #define ICTL_FIFO_MASK 0x0f /* FIFO threshold, 1/16 FIFO size */
46 #define ICTL_FIFO BIT(4) /* Int. on FIFO count */
47 #define ICTL_ARB BIT(5) /* Int. on Arbitration complete */
48 #define ICTL_SEL BIT(6) /* Int. on SCSI Select */
49 #define ICTL_REQ BIT(7) /* Int. on SCSI Request */
50 #define REG_FSTAT 3 /* R: Adapter Status 2 (FIFO) - (@) */
51 #define FSTAT_ONOTEMPTY BIT(0) /* Output FIFO not empty */
52 #define FSTAT_INOTEMPTY BIT(1) /* Input FIFO not empty */
53 #define FSTAT_NOTEMPTY BIT(2) /* Main FIFO not empty */
54 #define FSTAT_NOTFULL BIT(3) /* Main FIFO not full */
55 #define REG_MCTL 3 /* W: SCSI Data Mode Control */
56 #define MCTL_ACK_MASK 0x0f /* Acknowledge period */
57 #define MCTL_ACTDEASS BIT(4) /* Active deassert of REQ and ACK */
58 #define MCTL_TARGET BIT(5) /* Enable target mode */
59 #define MCTL_FASTSYNC BIT(6) /* Enable Fast Synchronous */
60 #define MCTL_SYNC BIT(7) /* Enable Synchronous */
61 #define REG_INTCOND 4 /* R: Interrupt Condition - (@) */
62 #define IRQ_FIFO BIT(1) /* FIFO interrupt */
63 #define IRQ_REQ BIT(2) /* SCSI Request interrupt */
64 #define IRQ_SEL BIT(3) /* SCSI Select interrupt */
65 #define IRQ_ARB BIT(4) /* SCSI Arbitration interrupt */
66 #define IRQ_RST BIT(5) /* SCSI Reset interrupt */
67 #define IRQ_FORCED BIT(6) /* Forced interrupt */
68 #define IRQ_TIMEOUT BIT(7) /* Bus timeout */
69 #define REG_ACTL 4 /* W: Adapter Control 1 */
70 #define ACTL_RESET BIT(0) /* Reset FIFO, parity, reset int. */
71 #define ACTL_FIRQ BIT(1) /* Set Forced interrupt */
72 #define ACTL_ARB BIT(2) /* Initiate Bus Arbitration */
73 #define ACTL_PAREN BIT(3) /* Enable SCSI Parity */
74 #define ACTL_IRQEN BIT(4) /* Enable interrupts */
75 #define ACTL_CLRFIRQ BIT(5) /* Clear Forced interrupt */
76 #define ACTL_FIFOWR BIT(6) /* FIFO Direction (1=write) */
77 #define ACTL_FIFOEN BIT(7) /* Enable FIFO */
78 #define REG_ID_LSB 5 /* R: ID Code (LSB) */
79 #define REG_ACTL2 5 /* Adapter Control 2 - (@) */
80 #define ACTL2_RAMOVRLY BIT(0) /* Enable RAM overlay */
81 #define ACTL2_SLEEP BIT(7) /* Sleep mode */
82 #define REG_ID_MSB 6 /* R: ID Code (MSB) */
83 #define REG_LOOPBACK 7 /* R/W: Loopback */
84 #define REG_SCSI_DATA_NOACK 8 /* R/W: SCSI Data (no ACK) */
85 #define REG_ASTAT3 9 /* R: Adapter Status 3 */
86 #define ASTAT3_ACTDEASS BIT(0) /* Active deassert enabled */
87 #define ASTAT3_RAMOVRLY BIT(1) /* RAM overlay enabled */
88 #define ASTAT3_TARGERR BIT(2) /* Target error */
89 #define ASTAT3_IRQEN BIT(3) /* Interrupts enabled */
90 #define ASTAT3_IRQMASK 0xf0 /* Enabled interrupts mask */
91 #define REG_CFG1 10 /* R: Configuration Register 1 */
92 #define CFG1_BUS BIT(0) /* 0 = ISA */
93 #define CFG1_IRQ_MASK 0x0e /* IRQ jumpers */
94 #define CFG1_IO_MASK 0x30 /* I/O base jumpers */
95 #define CFG1_BIOS_MASK 0xc0 /* BIOS base jumpers */
96 #define REG_CFG2 11 /* R/W: Configuration Register 2 (@) */
97 #define CFG2_ROMDIS BIT(0) /* ROM disabled */
98 #define CFG2_RAMDIS BIT(1) /* RAM disabled */
99 #define CFG2_IRQEDGE BIT(2) /* Edge-triggered interrupts */
100 #define CFG2_NOWS BIT(3) /* No wait states */
101 #define CFG2_32BIT BIT(7) /* 32-bit mode */
102 #define REG_FIFO 12 /* R/W: FIFO */
103 #define REG_FIFO_COUNT 14 /* R: FIFO Data Count */
104
105 #ifdef CONFIG_PM_SLEEP
106 static const struct dev_pm_ops fdomain_pm_ops;
107 #define FDOMAIN_PM_OPS (&fdomain_pm_ops)
108 #else
109 #define FDOMAIN_PM_OPS NULL
110 #endif /* CONFIG_PM_SLEEP */
111
112 struct Scsi_Host *fdomain_create(int base, int irq, int this_id,
113 struct device *dev);
114 int fdomain_destroy(struct Scsi_Host *sh);