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7 #ifndef __QLA_MR_H
8 #define __QLA_MR_H
9
10 #include "qla_dsd.h"
11
12
13
14
15 #define PCI_DEVICE_ID_QLOGIC_ISPF001 0xF001
16
17
18
19 #define FX00_COMMAND_TYPE_7 0x07
20 struct cmd_type_7_fx00 {
21 uint8_t entry_type;
22 uint8_t entry_count;
23 uint8_t sys_define;
24 uint8_t entry_status;
25
26 uint32_t handle;
27 uint8_t reserved_0;
28 uint8_t port_path_ctrl;
29 uint16_t reserved_1;
30
31 __le16 tgt_idx;
32 uint16_t timeout;
33
34 __le16 dseg_count;
35 uint8_t scsi_rsp_dsd_len;
36 uint8_t reserved_2;
37
38 struct scsi_lun lun;
39
40 uint8_t cntrl_flags;
41
42 uint8_t task_mgmt_flags;
43
44 uint8_t task;
45
46 uint8_t crn;
47
48 uint8_t fcp_cdb[MAX_CMDSZ];
49 __le32 byte_count;
50
51 struct dsd64 dsd;
52 };
53
54 #define STATUS_TYPE_FX00 0x01
55 struct sts_entry_fx00 {
56 uint8_t entry_type;
57 uint8_t entry_count;
58 uint8_t sys_define;
59 uint8_t entry_status;
60
61 uint32_t handle;
62 uint32_t reserved_3;
63
64 __le16 comp_status;
65 uint16_t reserved_0;
66
67 __le32 residual_len;
68
69 uint16_t reserved_1;
70 uint16_t state_flags;
71
72 uint16_t reserved_2;
73 __le16 scsi_status;
74
75 uint32_t sense_len;
76 uint8_t data[32];
77 };
78
79
80 #define MAX_HANDLE_COUNT 15
81 #define MULTI_STATUS_TYPE_FX00 0x0D
82
83 struct multi_sts_entry_fx00 {
84 uint8_t entry_type;
85 uint8_t entry_count;
86 uint8_t handle_count;
87 uint8_t entry_status;
88
89 __le32 handles[MAX_HANDLE_COUNT];
90 };
91
92 #define TSK_MGMT_IOCB_TYPE_FX00 0x05
93 struct tsk_mgmt_entry_fx00 {
94 uint8_t entry_type;
95 uint8_t entry_count;
96 uint8_t sys_define;
97 uint8_t entry_status;
98
99 __le32 handle;
100
101 uint32_t reserved_0;
102
103 __le16 tgt_id;
104
105 uint16_t reserved_1;
106 uint16_t reserved_3;
107 uint16_t reserved_4;
108
109 struct scsi_lun lun;
110
111 __le32 control_flags;
112
113 uint8_t reserved_2[32];
114 };
115
116
117 #define ABORT_IOCB_TYPE_FX00 0x08
118 struct abort_iocb_entry_fx00 {
119 uint8_t entry_type;
120 uint8_t entry_count;
121 uint8_t sys_define;
122 uint8_t entry_status;
123
124 __le32 handle;
125 __le32 reserved_0;
126
127 __le16 tgt_id_sts;
128 __le16 options;
129
130 __le32 abort_handle;
131 __le32 reserved_2;
132
133 __le16 req_que_no;
134 uint8_t reserved_1[38];
135 };
136
137 #define IOCTL_IOSB_TYPE_FX00 0x0C
138 struct ioctl_iocb_entry_fx00 {
139 uint8_t entry_type;
140 uint8_t entry_count;
141 uint8_t sys_define;
142 uint8_t entry_status;
143
144 uint32_t handle;
145 uint32_t reserved_0;
146
147 uint16_t comp_func_num;
148 __le16 fw_iotcl_flags;
149
150 __le32 dataword_r;
151 uint32_t adapid;
152 uint32_t dataword_r_extra;
153
154 __le32 seq_no;
155 uint8_t reserved_2[20];
156 uint32_t residuallen;
157 __le32 status;
158 };
159
160 #define STATUS_CONT_TYPE_FX00 0x04
161
162 #define FX00_IOCB_TYPE 0x0B
163 struct fxdisc_entry_fx00 {
164 uint8_t entry_type;
165 uint8_t entry_count;
166 uint8_t sys_define;
167 uint8_t entry_status;
168
169 __le32 handle;
170 __le32 reserved_0;
171
172 __le16 func_num;
173 __le16 req_xfrcnt;
174 __le16 req_dsdcnt;
175 __le16 rsp_xfrcnt;
176 __le16 rsp_dsdcnt;
177 uint8_t flags;
178 uint8_t reserved_1;
179
180 struct dsd64 dseg_rq;
181 struct dsd64 dseg_rsp;
182
183 __le32 dataword;
184 __le32 adapid;
185 __le32 adapid_hi;
186 __le32 dataword_extra;
187 };
188
189 struct qlafx00_tgt_node_info {
190 uint8_t tgt_node_wwpn[WWN_SIZE];
191 uint8_t tgt_node_wwnn[WWN_SIZE];
192 uint32_t tgt_node_state;
193 uint8_t reserved[128];
194 uint32_t reserved_1[8];
195 uint64_t reserved_2[4];
196 } __packed;
197
198 #define QLAFX00_TGT_NODE_INFO sizeof(struct qlafx00_tgt_node_info)
199
200 #define QLAFX00_LINK_STATUS_DOWN 0x10
201 #define QLAFX00_LINK_STATUS_UP 0x11
202
203 #define QLAFX00_PORT_SPEED_2G 0x2
204 #define QLAFX00_PORT_SPEED_4G 0x4
205 #define QLAFX00_PORT_SPEED_8G 0x8
206 #define QLAFX00_PORT_SPEED_10G 0xa
207 struct port_info_data {
208 uint8_t port_state;
209 uint8_t port_type;
210 uint16_t port_identifier;
211 uint32_t up_port_state;
212 uint8_t fw_ver_num[32];
213 uint8_t portal_attrib;
214 uint16_t host_option;
215 uint8_t reset_delay;
216 uint8_t pdwn_retry_cnt;
217 uint16_t max_luns2tgt;
218 uint8_t risc_ver;
219 uint8_t pconn_option;
220 uint16_t risc_option;
221 uint16_t max_frame_len;
222 uint16_t max_iocb_alloc;
223 uint16_t exec_throttle;
224 uint8_t retry_cnt;
225 uint8_t retry_delay;
226 uint8_t port_name[8];
227 uint8_t port_id[3];
228 uint8_t link_status;
229 uint8_t plink_rate;
230 uint32_t link_config;
231 uint16_t adap_haddr;
232 uint8_t tgt_disc;
233 uint8_t log_tout;
234 uint8_t node_name[8];
235 uint16_t erisc_opt1;
236 uint8_t resp_acc_tmr;
237 uint8_t intr_del_tmr;
238 uint8_t erisc_opt2;
239 uint8_t alt_port_name[8];
240 uint8_t alt_node_name[8];
241 uint8_t link_down_tout;
242 uint8_t conn_type;
243 uint8_t fc_fw_mode;
244 uint32_t uiReserved[48];
245 } __packed;
246
247
248 #define OS_TYPE_UNKNOWN 0
249 #define OS_TYPE_LINUX 2
250
251
252 #define SYSNAME_LENGTH 128
253 #define NODENAME_LENGTH 64
254 #define RELEASE_LENGTH 64
255 #define VERSION_LENGTH 64
256 #define MACHINE_LENGTH 64
257 #define DOMNAME_LENGTH 64
258
259 struct host_system_info {
260 uint32_t os_type;
261 char sysname[SYSNAME_LENGTH];
262 char nodename[NODENAME_LENGTH];
263 char release[RELEASE_LENGTH];
264 char version[VERSION_LENGTH];
265 char machine[MACHINE_LENGTH];
266 char domainname[DOMNAME_LENGTH];
267 char hostdriver[VERSION_LENGTH];
268 uint32_t reserved[64];
269 } __packed;
270
271 struct register_host_info {
272 struct host_system_info hsi;
273 uint64_t utc;
274 uint32_t reserved[64];
275 } __packed;
276
277
278 #define QLAFX00_PORT_DATA_INFO (sizeof(struct port_info_data))
279 #define QLAFX00_TGT_NODE_LIST_SIZE (sizeof(uint32_t) * 32)
280
281 struct config_info_data {
282 uint8_t model_num[16];
283 uint8_t model_description[80];
284 uint8_t reserved0[160];
285 uint8_t symbolic_name[64];
286 uint8_t serial_num[32];
287 uint8_t hw_version[16];
288 uint8_t fw_version[16];
289 uint8_t uboot_version[16];
290 uint8_t fru_serial_num[32];
291
292 uint8_t fc_port_count;
293 uint8_t iscsi_port_count;
294 uint8_t reserved1[2];
295
296 uint8_t mode;
297 uint8_t log_level;
298 uint8_t reserved2[2];
299
300 uint32_t log_size;
301
302 uint8_t tgt_pres_mode;
303 uint8_t iqn_flags;
304 uint8_t lun_mapping;
305
306 uint64_t adapter_id;
307
308 uint32_t cluster_key_len;
309 uint8_t cluster_key[16];
310
311 uint64_t cluster_master_id;
312 uint64_t cluster_slave_id;
313 uint8_t cluster_flags;
314 uint32_t enabled_capabilities;
315 uint32_t nominal_temp_value;
316 } __packed;
317
318 #define FXDISC_GET_CONFIG_INFO 0x01
319 #define FXDISC_GET_PORT_INFO 0x02
320 #define FXDISC_GET_TGT_NODE_INFO 0x80
321 #define FXDISC_GET_TGT_NODE_LIST 0x81
322 #define FXDISC_REG_HOST_INFO 0x99
323 #define FXDISC_ABORT_IOCTL 0xff
324
325 #define QLAFX00_HBA_ICNTRL_REG 0x20B08
326 #define QLAFX00_ICR_ENB_MASK 0x80000000
327 #define QLAFX00_ICR_DIS_MASK 0x7fffffff
328 #define QLAFX00_HST_RST_REG 0x18264
329 #define QLAFX00_SOC_TEMP_REG 0x184C4
330 #define QLAFX00_HST_TO_HBA_REG 0x20A04
331 #define QLAFX00_HBA_TO_HOST_REG 0x21B70
332 #define QLAFX00_HST_INT_STS_BITS 0x7
333 #define QLAFX00_BAR1_BASE_ADDR_REG 0x40018
334 #define QLAFX00_PEX0_WIN0_BASE_ADDR_REG 0x41824
335
336 #define QLAFX00_INTR_MB_CMPLT 0x1
337 #define QLAFX00_INTR_RSP_CMPLT 0x2
338 #define QLAFX00_INTR_ASYNC_CMPLT 0x4
339
340 #define QLAFX00_MBA_SYSTEM_ERR 0x8002
341 #define QLAFX00_MBA_TEMP_OVER 0x8005
342 #define QLAFX00_MBA_TEMP_NORM 0x8006
343 #define QLAFX00_MBA_TEMP_CRIT 0x8007
344 #define QLAFX00_MBA_LINK_UP 0x8011
345 #define QLAFX00_MBA_LINK_DOWN 0x8012
346 #define QLAFX00_MBA_PORT_UPDATE 0x8014
347 #define QLAFX00_MBA_SHUTDOWN_RQSTD 0x8062
348
349 #define SOC_SW_RST_CONTROL_REG_CORE0 0x0020800
350 #define SOC_FABRIC_RST_CONTROL_REG 0x0020840
351 #define SOC_FABRIC_CONTROL_REG 0x0020200
352 #define SOC_FABRIC_CONFIG_REG 0x0020204
353 #define SOC_PWR_MANAGEMENT_PWR_DOWN_REG 0x001820C
354
355 #define SOC_INTERRUPT_SOURCE_I_CONTROL_REG 0x0020B00
356 #define SOC_CORE_TIMER_REG 0x0021850
357 #define SOC_IRQ_ACK_REG 0x00218b4
358
359 #define CONTINUE_A64_TYPE_FX00 0x03
360
361 #define QLAFX00_SET_HST_INTR(ha, value) \
362 WRT_REG_DWORD((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \
363 value)
364
365 #define QLAFX00_CLR_HST_INTR(ha, value) \
366 WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
367 ~value)
368
369 #define QLAFX00_RD_INTR_REG(ha) \
370 RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)
371
372 #define QLAFX00_CLR_INTR_REG(ha, value) \
373 WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
374 ~value)
375
376 #define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\
377 WRT_REG_DWORD((ha)->cregbase + off, val)
378
379 #define QLAFX00_GET_HBA_SOC_REG(ha, off)\
380 RD_REG_DWORD((ha)->cregbase + off)
381
382 #define QLAFX00_HBA_RST_REG(ha, val)\
383 WRT_REG_DWORD((ha)->cregbase + QLAFX00_HST_RST_REG, val)
384
385 #define QLAFX00_RD_ICNTRL_REG(ha) \
386 RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)
387
388 #define QLAFX00_ENABLE_ICNTRL_REG(ha) \
389 WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
390 (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) | \
391 QLAFX00_ICR_ENB_MASK))
392
393 #define QLAFX00_DISABLE_ICNTRL_REG(ha) \
394 WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
395 (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) & \
396 QLAFX00_ICR_DIS_MASK))
397
398 #define QLAFX00_RD_REG(ha, off) \
399 RD_REG_DWORD((ha)->cregbase + off)
400
401 #define QLAFX00_WR_REG(ha, off, val) \
402 WRT_REG_DWORD((ha)->cregbase + off, val)
403
404 struct qla_mt_iocb_rqst_fx00 {
405 __le32 reserved_0;
406
407 __le16 func_type;
408 uint8_t flags;
409 uint8_t reserved_1;
410
411 __le32 dataword;
412
413 __le32 adapid;
414 __le32 adapid_hi;
415
416 __le32 dataword_extra;
417
418 __le16 req_len;
419 __le16 reserved_2;
420
421 __le16 rsp_len;
422 __le16 reserved_3;
423 };
424
425 struct qla_mt_iocb_rsp_fx00 {
426 uint32_t reserved_1;
427
428 uint16_t func_type;
429 __le16 ioctl_flags;
430
431 __le32 ioctl_data;
432
433 uint32_t adapid;
434 uint32_t adapid_hi;
435
436 uint32_t reserved_2;
437 __le32 seq_number;
438
439 uint8_t reserved_3[20];
440
441 int32_t res_count;
442
443 __le32 status;
444 };
445
446
447 #define MAILBOX_REGISTER_COUNT_FX00 16
448 #define AEN_MAILBOX_REGISTER_COUNT_FX00 8
449 #define MAX_FIBRE_DEVICES_FX00 512
450 #define MAX_LUNS_FX00 0x1024
451 #define MAX_TARGETS_FX00 MAX_ISA_DEVICES
452 #define REQUEST_ENTRY_CNT_FX00 512
453 #define RESPONSE_ENTRY_CNT_FX00 256
454
455
456
457
458 #define FSTATE_FX00_CONFIG_WAIT 0x0000
459
460
461 #define FSTATE_FX00_INITIALIZED 0x1000
462
463
464
465 #define FX00_DEF_RATOV 10
466
467 struct mr_data_fx00 {
468 uint8_t symbolic_name[64];
469 uint8_t serial_num[32];
470 uint8_t hw_version[16];
471 uint8_t fw_version[16];
472 uint8_t uboot_version[16];
473 uint8_t fru_serial_num[32];
474 fc_port_t fcport;
475
476
477
478 uint8_t fw_hbt_en;
479 uint8_t fw_hbt_cnt;
480 uint8_t fw_hbt_miss_cnt;
481 uint32_t old_fw_hbt_cnt;
482 uint16_t fw_reset_timer_tick;
483 uint8_t fw_reset_timer_exp;
484 uint16_t fw_critemp_timer_tick;
485 uint32_t old_aenmbx0_state;
486 uint32_t critical_temperature;
487 bool extended_io_enabled;
488 bool host_info_resend;
489 uint8_t hinfo_resend_timer_tick;
490 };
491
492 #define QLAFX00_EXTENDED_IO_EN_MASK 0x20
493
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505
506 #define QLAFX00_GET_TEMPERATURE(ha) ((3153000 - (10000 * \
507 ((QLAFX00_RD_REG(ha, QLAFX00_SOC_TEMP_REG) & 0x3FE) >> 1))) / 13825)
508
509
510 #define QLAFX00_LOOP_DOWN_TIME 615
511 #define QLAFX00_HEARTBEAT_INTERVAL 6
512 #define QLAFX00_HEARTBEAT_MISS_CNT 3
513 #define QLAFX00_RESET_INTERVAL 120
514 #define QLAFX00_MAX_RESET_INTERVAL 600
515 #define QLAFX00_CRITEMP_INTERVAL 60
516 #define QLAFX00_HINFO_RESEND_INTERVAL 60
517
518 #define QLAFX00_CRITEMP_THRSHLD 80
519
520
521 #define QLAFX00_MAX_CANQUEUE 1024
522
523
524 #define QLAFX00_IOCTL_ICOB_ABORT_SUCCESS 0x68
525
526 #endif