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7 #ifndef __QLA_BSG_H
8 #define __QLA_BSG_H
9
10
11 #define QL_VND_LOOPBACK 0x01
12 #define QL_VND_A84_RESET 0x02
13 #define QL_VND_A84_UPDATE_FW 0x03
14 #define QL_VND_A84_MGMT_CMD 0x04
15 #define QL_VND_IIDMA 0x05
16 #define QL_VND_FCP_PRIO_CFG_CMD 0x06
17 #define QL_VND_READ_FLASH 0x07
18 #define QL_VND_UPDATE_FLASH 0x08
19 #define QL_VND_SET_FRU_VERSION 0x0B
20 #define QL_VND_READ_FRU_STATUS 0x0C
21 #define QL_VND_WRITE_FRU_STATUS 0x0D
22 #define QL_VND_DIAG_IO_CMD 0x0A
23 #define QL_VND_WRITE_I2C 0x10
24 #define QL_VND_READ_I2C 0x11
25 #define QL_VND_FX00_MGMT_CMD 0x12
26 #define QL_VND_SERDES_OP 0x13
27 #define QL_VND_SERDES_OP_EX 0x14
28 #define QL_VND_GET_FLASH_UPDATE_CAPS 0x15
29 #define QL_VND_SET_FLASH_UPDATE_CAPS 0x16
30 #define QL_VND_GET_BBCR_DATA 0x17
31 #define QL_VND_GET_PRIV_STATS 0x18
32 #define QL_VND_DPORT_DIAGNOSTICS 0x19
33 #define QL_VND_GET_PRIV_STATS_EX 0x1A
34 #define QL_VND_SS_GET_FLASH_IMAGE_STATUS 0x1E
35
36
37 #define EXT_STATUS_OK 0
38 #define EXT_STATUS_ERR 1
39 #define EXT_STATUS_BUSY 2
40 #define EXT_STATUS_INVALID_PARAM 6
41 #define EXT_STATUS_DATA_OVERRUN 7
42 #define EXT_STATUS_DATA_UNDERRUN 8
43 #define EXT_STATUS_MAILBOX 11
44 #define EXT_STATUS_NO_MEMORY 17
45 #define EXT_STATUS_DEVICE_OFFLINE 22
46
47
48
49
50
51 #define EXT_STATUS_NOT_SUPPORTED 27
52 #define EXT_STATUS_INVALID_CFG 28
53 #define EXT_STATUS_DMA_ERR 29
54 #define EXT_STATUS_TIMEOUT 30
55 #define EXT_STATUS_THREAD_FAILED 31
56 #define EXT_STATUS_DATA_CMP_FAILED 32
57
58
59 #define INT_DEF_LB_LOOPBACK_CMD 0
60 #define INT_DEF_LB_ECHO_CMD 1
61
62
63 #define INTERNAL_LOOPBACK 0xF1
64 #define EXTERNAL_LOOPBACK 0xF2
65 #define ENABLE_INTERNAL_LOOPBACK 0x02
66 #define ENABLE_EXTERNAL_LOOPBACK 0x04
67 #define INTERNAL_LOOPBACK_MASK 0x000E
68 #define MAX_ELS_FRAME_PAYLOAD 252
69 #define ELS_OPCODE_BYTE 0x10
70
71
72 #define A84_ISSUE_WRITE_TYPE_CMD 0
73 #define A84_ISSUE_READ_TYPE_CMD 1
74 #define A84_CLEANUP_CMD 2
75 #define A84_ISSUE_RESET_OP_FW 3
76 #define A84_ISSUE_RESET_DIAG_FW 4
77 #define A84_ISSUE_UPDATE_OPFW_CMD 5
78 #define A84_ISSUE_UPDATE_DIAGFW_CMD 6
79
80 struct qla84_mgmt_param {
81 union {
82 struct {
83 uint32_t start_addr;
84 } mem;
85 struct {
86 uint32_t id;
87 #define QLA84_MGMT_CONFIG_ID_UIF 1
88 #define QLA84_MGMT_CONFIG_ID_FCOE_COS 2
89 #define QLA84_MGMT_CONFIG_ID_PAUSE 3
90 #define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4
91
92 uint32_t param0;
93 uint32_t param1;
94 } config;
95
96 struct {
97 uint32_t type;
98 #define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1
99 #define QLA84_MGMT_INFO_LOG_DATA 2
100 #define QLA84_MGMT_INFO_PORT_STAT 3
101 #define QLA84_MGMT_INFO_LIF_STAT 4
102 #define QLA84_MGMT_INFO_ASIC_STAT 5
103 #define QLA84_MGMT_INFO_CONFIG_PARAMS 6
104 #define QLA84_MGMT_INFO_PANIC_LOG 7
105
106 uint32_t context;
107
108
109
110 #define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0
111 #define IC_LOG_DATA_LOG_ID_LEARN_LOG 1
112 #define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2
113 #define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3
114 #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4
115 #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5
116 #define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6
117 #define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7
118 #define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8
119 #define IC_LOG_DATA_LOG_ID_DCX_LOG 9
120
121
122
123
124 #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0
125 #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1
126 #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2
127 #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3
128 #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4
129 #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5
130
131
132
133
134
135 #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0
136 #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1
137 #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2
138 #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3
139 #define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6
140
141 } info;
142 } u;
143 };
144
145 struct qla84_msg_mgmt {
146 uint16_t cmd;
147 #define QLA84_MGMT_READ_MEM 0x00
148 #define QLA84_MGMT_WRITE_MEM 0x01
149 #define QLA84_MGMT_CHNG_CONFIG 0x02
150 #define QLA84_MGMT_GET_INFO 0x03
151 uint16_t rsrvd;
152 struct qla84_mgmt_param mgmtp;
153 uint32_t len;
154 uint8_t payload[0];
155 };
156
157 struct qla_bsg_a84_mgmt {
158 struct qla84_msg_mgmt mgmt;
159 } __attribute__ ((packed));
160
161 struct qla_scsi_addr {
162 uint16_t bus;
163 uint16_t target;
164 } __attribute__ ((packed));
165
166 struct qla_ext_dest_addr {
167 union {
168 uint8_t wwnn[8];
169 uint8_t wwpn[8];
170 uint8_t id[4];
171 struct qla_scsi_addr scsi_addr;
172 } dest_addr;
173 uint16_t dest_type;
174 #define EXT_DEF_TYPE_WWPN 2
175 uint16_t lun;
176 uint16_t padding[2];
177 } __attribute__ ((packed));
178
179 struct qla_port_param {
180 struct qla_ext_dest_addr fc_scsi_addr;
181 uint16_t mode;
182 uint16_t speed;
183 } __attribute__ ((packed));
184
185
186
187
188 #define MAX_FRU_SIZE 36
189
190 struct qla_field_address {
191 uint16_t offset;
192 uint16_t device;
193 uint16_t option;
194 } __packed;
195
196 struct qla_field_info {
197 uint8_t version[MAX_FRU_SIZE];
198 } __packed;
199
200 struct qla_image_version {
201 struct qla_field_address field_address;
202 struct qla_field_info field_info;
203 } __packed;
204
205 struct qla_image_version_list {
206 uint32_t count;
207 struct qla_image_version version[0];
208 } __packed;
209
210 struct qla_status_reg {
211 struct qla_field_address field_address;
212 uint8_t status_reg;
213 uint8_t reserved[7];
214 } __packed;
215
216 struct qla_i2c_access {
217 uint16_t device;
218 uint16_t offset;
219 uint16_t option;
220 uint16_t length;
221 uint8_t buffer[0x40];
222 } __packed;
223
224
225
226
227 #define INT_SC_SERDES_READ_REG 1
228 #define INT_SC_SERDES_WRITE_REG 2
229
230 struct qla_serdes_reg {
231 uint16_t cmd;
232 uint16_t addr;
233 uint16_t val;
234 } __packed;
235
236 struct qla_serdes_reg_ex {
237 uint16_t cmd;
238 uint32_t addr;
239 uint32_t val;
240 } __packed;
241
242 struct qla_flash_update_caps {
243 uint64_t capabilities;
244 uint32_t outage_duration;
245 uint8_t reserved[20];
246 } __packed;
247
248
249 #define QLA_BBCR_STATUS_DISABLED 0
250 #define QLA_BBCR_STATUS_ENABLED 1
251 #define QLA_BBCR_STATUS_UNKNOWN 2
252
253
254 #define QLA_BBCR_STATE_OFFLINE 0
255 #define QLA_BBCR_STATE_ONLINE 1
256
257
258 #define QLA_BBCR_REASON_PORT_SPEED 1
259 #define QLA_BBCR_REASON_PEER_PORT 2
260 #define QLA_BBCR_REASON_SWITCH 3
261 #define QLA_BBCR_REASON_LOGIN_REJECT 4
262
263 struct qla_bbcr_data {
264 uint8_t status;
265 uint8_t state;
266 uint8_t configured_bbscn;
267 uint8_t negotiated_bbscn;
268 uint8_t offline_reason_code;
269 uint16_t mbx1;
270 uint8_t reserved[9];
271 } __packed;
272
273 struct qla_dport_diag {
274 uint16_t options;
275 uint32_t buf[16];
276 uint8_t unused[62];
277 } __packed;
278
279
280 #define QLA_DPORT_RESULT 0x0
281 #define QLA_DPORT_START 0x2
282
283
284 struct qla_active_regions {
285 uint8_t global_image;
286 uint8_t board_config;
287 uint8_t vpd_nvram;
288 uint8_t npiv_config_0_1;
289 uint8_t npiv_config_2_3;
290 uint8_t reserved[32];
291 } __packed;
292
293 #endif