This source file includes following definitions.
- be_id_to_le
- le_id_to_be
- be_to_port_id
- port_id_to_be_id
- qla2xxx_is_valid_mbs
1
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3
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5
6
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28 #include <linux/btree.h>
29
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_cmnd.h>
34 #include <scsi/scsi_transport_fc.h>
35 #include <scsi/scsi_bsg_fc.h>
36
37
38 typedef struct {
39 uint8_t domain;
40 uint8_t area;
41 uint8_t al_pa;
42 } be_id_t;
43
44
45 typedef struct {
46 uint8_t al_pa;
47 uint8_t area;
48 uint8_t domain;
49 } le_id_t;
50
51 #include "qla_bsg.h"
52 #include "qla_dsd.h"
53 #include "qla_nx.h"
54 #include "qla_nx2.h"
55 #include "qla_nvme.h"
56 #define QLA2XXX_DRIVER_NAME "qla2xxx"
57 #define QLA2XXX_APIDEV "ql2xapidev"
58 #define QLA2XXX_MANUFACTURER "QLogic Corporation"
59
60
61
62
63
64
65 #define MAILBOX_REGISTER_COUNT_2100 8
66 #define MAILBOX_REGISTER_COUNT_2200 24
67 #define MAILBOX_REGISTER_COUNT 32
68
69 #define QLA2200A_RISC_ROM_VER 4
70 #define FPM_2300 6
71 #define FPM_2310 7
72
73 #include "qla_settings.h"
74
75 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
76
77
78
79
80 #define BIT_0 0x1
81 #define BIT_1 0x2
82 #define BIT_2 0x4
83 #define BIT_3 0x8
84 #define BIT_4 0x10
85 #define BIT_5 0x20
86 #define BIT_6 0x40
87 #define BIT_7 0x80
88 #define BIT_8 0x100
89 #define BIT_9 0x200
90 #define BIT_10 0x400
91 #define BIT_11 0x800
92 #define BIT_12 0x1000
93 #define BIT_13 0x2000
94 #define BIT_14 0x4000
95 #define BIT_15 0x8000
96 #define BIT_16 0x10000
97 #define BIT_17 0x20000
98 #define BIT_18 0x40000
99 #define BIT_19 0x80000
100 #define BIT_20 0x100000
101 #define BIT_21 0x200000
102 #define BIT_22 0x400000
103 #define BIT_23 0x800000
104 #define BIT_24 0x1000000
105 #define BIT_25 0x2000000
106 #define BIT_26 0x4000000
107 #define BIT_27 0x8000000
108 #define BIT_28 0x10000000
109 #define BIT_29 0x20000000
110 #define BIT_30 0x40000000
111 #define BIT_31 0x80000000
112
113 #define LSB(x) ((uint8_t)(x))
114 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
115
116 #define LSW(x) ((uint16_t)(x))
117 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
118
119 #define LSD(x) ((uint32_t)((uint64_t)(x)))
120 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
121
122 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
123
124
125
126
127
128 #define RD_REG_BYTE(addr) readb(addr)
129 #define RD_REG_WORD(addr) readw(addr)
130 #define RD_REG_DWORD(addr) readl(addr)
131 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
132 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
133 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
134 #define WRT_REG_BYTE(addr, data) writeb(data, addr)
135 #define WRT_REG_WORD(addr, data) writew(data, addr)
136 #define WRT_REG_DWORD(addr, data) writel(data, addr)
137
138
139
140
141 #define QLA83XX_LED_PORT0 0x00201320
142 #define QLA83XX_LED_PORT1 0x00201328
143 #define QLA83XX_IDC_DEV_STATE 0x22102384
144 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
145 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
146 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
147 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
148 #define QLA83XX_IDC_CONTROL 0x22102390
149 #define QLA83XX_IDC_AUDIT 0x22102394
150 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
151 #define QLA83XX_DRIVER_LOCKID 0x22102104
152 #define QLA83XX_DRIVER_LOCK 0x8111c028
153 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
154 #define QLA83XX_FLASH_LOCKID 0x22102100
155 #define QLA83XX_FLASH_LOCK 0x8111c010
156 #define QLA83XX_FLASH_UNLOCK 0x8111c014
157 #define QLA83XX_DEV_PARTINFO1 0x221023e0
158 #define QLA83XX_DEV_PARTINFO2 0x221023e4
159 #define QLA83XX_FW_HEARTBEAT 0x221020b0
160 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
161 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
162
163
164 #define IDC_DEVICE_STATE_CHANGE BIT_0
165 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
166 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
167 #define IDC_HEARTBEAT_FAILURE BIT_3
168
169
170 #define ERR_LEVEL_NON_FATAL 0x1
171 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
172 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
173
174
175 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
176 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
177
178
179 #define QLA83XX_NIC_CORE_RESET 0x1
180 #define QLA83XX_IDC_STATE_HANDLER 0x2
181 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
182
183
184 #define QLA83XX_IDC_RESET_DISABLED BIT_0
185 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
186
187
188 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
189 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
190 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
191
192
193 #define QLA83XX_CLASS_TYPE_NONE 0x0
194 #define QLA83XX_CLASS_TYPE_NIC 0x1
195 #define QLA83XX_CLASS_TYPE_FCOE 0x2
196 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
197
198
199 #define IDC_LOCK_RECOVERY_STAGE1 0x1
200
201
202 #define IDC_LOCK_RECOVERY_STAGE2 0x2
203
204
205 #define IDC_AUDIT_TIMESTAMP 0x0
206
207
208
209 #define IDC_AUDIT_COMPLETION 0x1
210
211
212
213
214 #define PORT_0_2031 0x00201340
215 #define PORT_1_2031 0x00201350
216 #define LASER_ON_2031 0x01800100
217 #define LASER_OFF_2031 0x01800180
218
219
220
221
222
223 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
224 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr))
225
226
227
228
229 #define WWN_SIZE 8
230 #define MAX_FIBRE_DEVICES_2100 512
231 #define MAX_FIBRE_DEVICES_2400 2048
232 #define MAX_FIBRE_DEVICES_LOOP 128
233 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
234 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
235 #define MAX_FIBRE_LUNS 0xFFFF
236 #define MAX_HOST_COUNT 16
237
238
239
240
241 #define MAX_BUSES 1
242 #define MIN_LUNS 8
243 #define MAX_LUNS MAX_FIBRE_LUNS
244 #define MAX_CMDS_PER_LUN 255
245
246
247
248
249 #define SNS_LAST_LOOP_ID_2100 0xfe
250 #define SNS_LAST_LOOP_ID_2300 0x7ff
251
252 #define LAST_LOCAL_LOOP_ID 0x7d
253 #define SNS_FL_PORT 0x7e
254 #define FABRIC_CONTROLLER 0x7f
255 #define SIMPLE_NAME_SERVER 0x80
256 #define SNS_FIRST_LOOP_ID 0x81
257 #define MANAGEMENT_SERVER 0xfe
258 #define BROADCAST 0xff
259
260
261
262
263
264 #define NPH_LAST_HANDLE 0x7ee
265 #define NPH_MGMT_SERVER 0x7ef
266 #define NPH_SNS 0x7fc
267 #define NPH_FABRIC_CONTROLLER 0x7fd
268 #define NPH_F_PORT 0x7fe
269 #define NPH_IP_BROADCAST 0x7ff
270
271 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
272
273 #define MAX_CMDSZ 16
274 #include "qla_fw.h"
275
276 struct name_list_extended {
277 struct get_name_list_extended *l;
278 dma_addr_t ldma;
279 struct list_head fcports;
280 u32 size;
281 u8 sent;
282 };
283
284
285
286 #define PORT_RETRY_TIME 1
287 #define LOOP_DOWN_TIMEOUT 60
288 #define LOOP_DOWN_TIME 255
289 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
290
291 #define DEFAULT_OUTSTANDING_COMMANDS 4096
292 #define MIN_OUTSTANDING_COMMANDS 128
293
294
295 #define REQUEST_ENTRY_CNT_2100 128
296 #define REQUEST_ENTRY_CNT_2200 2048
297 #define REQUEST_ENTRY_CNT_24XX 2048
298 #define REQUEST_ENTRY_CNT_83XX 8192
299 #define RESPONSE_ENTRY_CNT_83XX 4096
300 #define RESPONSE_ENTRY_CNT_2100 64
301 #define RESPONSE_ENTRY_CNT_2300 512
302 #define RESPONSE_ENTRY_CNT_MQ 128
303 #define ATIO_ENTRY_CNT_24XX 4096
304 #define RESPONSE_ENTRY_CNT_FX00 256
305 #define FW_DEF_EXCHANGES_CNT 2048
306 #define FW_MAX_EXCHANGES_CNT (32 * 1024)
307 #define REDUCE_EXCHANGES_CNT (8 * 1024)
308
309 struct req_que;
310 struct qla_tgt_sess;
311
312
313
314
315 struct srb_cmd {
316 struct scsi_cmnd *cmd;
317 uint32_t request_sense_length;
318 uint32_t fw_sense_length;
319 uint8_t *request_sense_ptr;
320 struct ct6_dsd *ct6_ctx;
321 struct crc_context *crc_ctx;
322 };
323
324
325
326
327 #define SRB_DMA_VALID BIT_0
328 #define SRB_FCP_CMND_DMA_VALID BIT_12
329 #define SRB_CRC_CTX_DMA_VALID BIT_2
330 #define SRB_CRC_PROT_DMA_VALID BIT_4
331 #define SRB_CRC_CTX_DSD_VALID BIT_5
332 #define SRB_WAKEUP_ON_COMP BIT_6
333 #define SRB_DIF_BUNDL_DMA_VALID BIT_7
334
335
336 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
337
338
339
340
341 typedef union {
342 uint32_t b24 : 24;
343
344 struct {
345 #ifdef __BIG_ENDIAN
346 uint8_t domain;
347 uint8_t area;
348 uint8_t al_pa;
349 #elif defined(__LITTLE_ENDIAN)
350 uint8_t al_pa;
351 uint8_t area;
352 uint8_t domain;
353 #else
354 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
355 #endif
356 uint8_t rsvd_1;
357 } b;
358 } port_id_t;
359 #define INVALID_PORT_ID 0xFFFFFF
360
361 static inline le_id_t be_id_to_le(be_id_t id)
362 {
363 le_id_t res;
364
365 res.domain = id.domain;
366 res.area = id.area;
367 res.al_pa = id.al_pa;
368
369 return res;
370 }
371
372 static inline be_id_t le_id_to_be(le_id_t id)
373 {
374 be_id_t res;
375
376 res.domain = id.domain;
377 res.area = id.area;
378 res.al_pa = id.al_pa;
379
380 return res;
381 }
382
383 static inline port_id_t be_to_port_id(be_id_t id)
384 {
385 port_id_t res;
386
387 res.b.domain = id.domain;
388 res.b.area = id.area;
389 res.b.al_pa = id.al_pa;
390 res.b.rsvd_1 = 0;
391
392 return res;
393 }
394
395 static inline be_id_t port_id_to_be_id(port_id_t port_id)
396 {
397 be_id_t res;
398
399 res.domain = port_id.b.domain;
400 res.area = port_id.b.area;
401 res.al_pa = port_id.b.al_pa;
402
403 return res;
404 }
405
406 struct els_logo_payload {
407 uint8_t opcode;
408 uint8_t rsvd[3];
409 uint8_t s_id[3];
410 uint8_t rsvd1[1];
411 uint8_t wwpn[WWN_SIZE];
412 };
413
414 struct els_plogi_payload {
415 uint8_t opcode;
416 uint8_t rsvd[3];
417 uint8_t data[112];
418 };
419
420 struct ct_arg {
421 void *iocb;
422 u16 nport_handle;
423 dma_addr_t req_dma;
424 dma_addr_t rsp_dma;
425 u32 req_size;
426 u32 rsp_size;
427 u32 req_allocated_size;
428 u32 rsp_allocated_size;
429 void *req;
430 void *rsp;
431 port_id_t id;
432 };
433
434
435
436
437 struct srb_iocb {
438 union {
439 struct {
440 uint16_t flags;
441 #define SRB_LOGIN_RETRIED BIT_0
442 #define SRB_LOGIN_COND_PLOGI BIT_1
443 #define SRB_LOGIN_SKIP_PRLI BIT_2
444 #define SRB_LOGIN_NVME_PRLI BIT_3
445 #define SRB_LOGIN_PRLI_ONLY BIT_4
446 uint16_t data[2];
447 u32 iop[2];
448 } logio;
449 struct {
450 #define ELS_DCMD_TIMEOUT 20
451 #define ELS_DCMD_LOGO 0x5
452 uint32_t flags;
453 uint32_t els_cmd;
454 struct completion comp;
455 struct els_logo_payload *els_logo_pyld;
456 dma_addr_t els_logo_pyld_dma;
457 } els_logo;
458 struct els_plogi {
459 #define ELS_DCMD_PLOGI 0x3
460 uint32_t flags;
461 uint32_t els_cmd;
462 struct completion comp;
463 struct els_plogi_payload *els_plogi_pyld;
464 struct els_plogi_payload *els_resp_pyld;
465 u32 tx_size;
466 u32 rx_size;
467 dma_addr_t els_plogi_pyld_dma;
468 dma_addr_t els_resp_pyld_dma;
469 uint32_t fw_status[3];
470 __le16 comp_status;
471 __le16 len;
472 } els_plogi;
473 struct {
474
475
476
477
478
479 uint64_t lun;
480 uint32_t flags;
481 uint32_t data;
482 struct completion comp;
483 __le16 comp_status;
484 } tmf;
485 struct {
486 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
487 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
488 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
489 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
490 #define FXDISC_TIMEOUT 20
491 uint8_t flags;
492 uint32_t req_len;
493 uint32_t rsp_len;
494 void *req_addr;
495 void *rsp_addr;
496 dma_addr_t req_dma_handle;
497 dma_addr_t rsp_dma_handle;
498 __le32 adapter_id;
499 __le32 adapter_id_hi;
500 __le16 req_func_type;
501 __le32 req_data;
502 __le32 req_data_extra;
503 __le32 result;
504 __le32 seq_number;
505 __le16 fw_flags;
506 struct completion fxiocb_comp;
507 __le32 reserved_0;
508 uint8_t reserved_1;
509 } fxiocb;
510 struct {
511 uint32_t cmd_hndl;
512 __le16 comp_status;
513 __le16 req_que_no;
514 struct completion comp;
515 } abt;
516 struct ct_arg ctarg;
517 #define MAX_IOCB_MB_REG 28
518 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
519 struct {
520 __le16 in_mb[MAX_IOCB_MB_REG];
521 __le16 out_mb[MAX_IOCB_MB_REG];
522 void *out, *in;
523 dma_addr_t out_dma, in_dma;
524 struct completion comp;
525 int rc;
526 } mbx;
527 struct {
528 struct imm_ntfy_from_isp *ntfy;
529 } nack;
530 struct {
531 __le16 comp_status;
532 uint16_t rsp_pyld_len;
533 uint8_t aen_op;
534 void *desc;
535
536
537 int cmd_len;
538 int rsp_len;
539 dma_addr_t cmd_dma;
540 dma_addr_t rsp_dma;
541 enum nvmefc_fcp_datadir dir;
542 uint32_t dl;
543 uint32_t timeout_sec;
544 struct list_head entry;
545 } nvme;
546 struct {
547 u16 cmd;
548 u16 vp_index;
549 } ctrlvp;
550 } u;
551
552 struct timer_list timer;
553 void (*timeout)(void *);
554 };
555
556
557 #define SRB_LOGIN_CMD 1
558 #define SRB_LOGOUT_CMD 2
559 #define SRB_ELS_CMD_RPT 3
560 #define SRB_ELS_CMD_HST 4
561 #define SRB_CT_CMD 5
562 #define SRB_ADISC_CMD 6
563 #define SRB_TM_CMD 7
564 #define SRB_SCSI_CMD 8
565 #define SRB_BIDI_CMD 9
566 #define SRB_FXIOCB_DCMD 10
567 #define SRB_FXIOCB_BCMD 11
568 #define SRB_ABT_CMD 12
569 #define SRB_ELS_DCMD 13
570 #define SRB_MB_IOCB 14
571 #define SRB_CT_PTHRU_CMD 15
572 #define SRB_NACK_PLOGI 16
573 #define SRB_NACK_PRLI 17
574 #define SRB_NACK_LOGO 18
575 #define SRB_NVME_CMD 19
576 #define SRB_NVME_LS 20
577 #define SRB_PRLI_CMD 21
578 #define SRB_CTRL_VP 22
579 #define SRB_PRLO_CMD 23
580
581 enum {
582 TYPE_SRB,
583 TYPE_TGT_CMD,
584 TYPE_TGT_TMCMD,
585 };
586
587 typedef struct srb {
588
589
590
591
592 uint8_t cmd_type;
593 uint8_t pad[3];
594 struct kref cmd_kref;
595 void *priv;
596 wait_queue_head_t nvme_ls_waitq;
597 struct fc_port *fcport;
598 struct scsi_qla_host *vha;
599 unsigned int start_timer:1;
600 unsigned int abort:1;
601 unsigned int aborted:1;
602 unsigned int completed:1;
603
604 uint32_t handle;
605 uint16_t flags;
606 uint16_t type;
607 const char *name;
608 int iocbs;
609 struct qla_qpair *qpair;
610 struct srb *cmd_sp;
611 struct list_head elem;
612 u32 gen1;
613 u32 gen2;
614 int rc;
615 int retry_count;
616 struct completion *comp;
617 union {
618 struct srb_iocb iocb_cmd;
619 struct bsg_job *bsg_job;
620 struct srb_cmd scmd;
621 } u;
622
623
624
625
626
627 void (*done)(struct srb *sp, int res);
628
629 void (*free)(struct srb *sp);
630
631
632
633
634 void (*put_fn)(struct kref *kref);
635 } srb_t;
636
637 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
638
639 #define GET_CMD_SENSE_LEN(sp) \
640 (sp->u.scmd.request_sense_length)
641 #define SET_CMD_SENSE_LEN(sp, len) \
642 (sp->u.scmd.request_sense_length = len)
643 #define GET_CMD_SENSE_PTR(sp) \
644 (sp->u.scmd.request_sense_ptr)
645 #define SET_CMD_SENSE_PTR(sp, ptr) \
646 (sp->u.scmd.request_sense_ptr = ptr)
647 #define GET_FW_SENSE_LEN(sp) \
648 (sp->u.scmd.fw_sense_length)
649 #define SET_FW_SENSE_LEN(sp, len) \
650 (sp->u.scmd.fw_sense_length = len)
651
652 struct msg_echo_lb {
653 dma_addr_t send_dma;
654 dma_addr_t rcv_dma;
655 uint16_t req_sg_cnt;
656 uint16_t rsp_sg_cnt;
657 uint16_t options;
658 uint32_t transfer_size;
659 uint32_t iteration_count;
660 };
661
662
663
664
665 struct device_reg_2xxx {
666 uint16_t flash_address;
667 uint16_t flash_data;
668 uint16_t unused_1[1];
669 uint16_t ctrl_status;
670 #define CSR_FLASH_64K_BANK BIT_3
671 #define CSR_FLASH_ENABLE BIT_1
672 #define CSR_ISP_SOFT_RESET BIT_0
673
674 uint16_t ictrl;
675 #define ICR_EN_INT BIT_15
676 #define ICR_EN_RISC BIT_3
677
678 uint16_t istatus;
679 #define ISR_RISC_INT BIT_3
680
681 uint16_t semaphore;
682 uint16_t nvram;
683 #define NVR_DESELECT 0
684 #define NVR_BUSY BIT_15
685 #define NVR_WRT_ENABLE BIT_14
686 #define NVR_PR_ENABLE BIT_13
687 #define NVR_DATA_IN BIT_3
688 #define NVR_DATA_OUT BIT_2
689 #define NVR_SELECT BIT_1
690 #define NVR_CLOCK BIT_0
691
692 #define NVR_WAIT_CNT 20000
693
694 union {
695 struct {
696 uint16_t mailbox0;
697 uint16_t mailbox1;
698 uint16_t mailbox2;
699 uint16_t mailbox3;
700 uint16_t mailbox4;
701 uint16_t mailbox5;
702 uint16_t mailbox6;
703 uint16_t mailbox7;
704 uint16_t unused_2[59];
705 } __attribute__((packed)) isp2100;
706 struct {
707
708 uint16_t req_q_in;
709 uint16_t req_q_out;
710
711 uint16_t rsp_q_in;
712 uint16_t rsp_q_out;
713
714
715 uint32_t host_status;
716 #define HSR_RISC_INT BIT_15
717 #define HSR_RISC_PAUSED BIT_8
718
719
720 uint16_t host_semaphore;
721 uint16_t unused_3[17];
722 uint16_t mailbox0;
723 uint16_t mailbox1;
724 uint16_t mailbox2;
725 uint16_t mailbox3;
726 uint16_t mailbox4;
727 uint16_t mailbox5;
728 uint16_t mailbox6;
729 uint16_t mailbox7;
730 uint16_t mailbox8;
731 uint16_t mailbox9;
732 uint16_t mailbox10;
733 uint16_t mailbox11;
734 uint16_t mailbox12;
735 uint16_t mailbox13;
736 uint16_t mailbox14;
737 uint16_t mailbox15;
738 uint16_t mailbox16;
739 uint16_t mailbox17;
740 uint16_t mailbox18;
741 uint16_t mailbox19;
742 uint16_t mailbox20;
743 uint16_t mailbox21;
744 uint16_t mailbox22;
745 uint16_t mailbox23;
746 uint16_t mailbox24;
747 uint16_t mailbox25;
748 uint16_t mailbox26;
749 uint16_t mailbox27;
750 uint16_t mailbox28;
751 uint16_t mailbox29;
752 uint16_t mailbox30;
753 uint16_t mailbox31;
754 uint16_t fb_cmd;
755 uint16_t unused_4[10];
756 } __attribute__((packed)) isp2300;
757 } u;
758
759 uint16_t fpm_diag_config;
760 uint16_t unused_5[0x4];
761 uint16_t risc_hw;
762 uint16_t unused_5_1;
763 uint16_t pcr;
764 uint16_t unused_6[0x5];
765 uint16_t mctr;
766 uint16_t unused_7[0x3];
767 uint16_t fb_cmd_2100;
768 uint16_t unused_8[0x3];
769 uint16_t hccr;
770 #define HCCR_HOST_INT BIT_7
771 #define HCCR_RISC_PAUSE BIT_5
772
773 #define HCCR_RESET_RISC 0x1000
774 #define HCCR_PAUSE_RISC 0x2000
775 #define HCCR_RELEASE_RISC 0x3000
776 #define HCCR_SET_HOST_INT 0x5000
777 #define HCCR_CLR_HOST_INT 0x6000
778 #define HCCR_CLR_RISC_INT 0x7000
779 #define HCCR_DISABLE_PARITY_PAUSE 0x4001
780 #define HCCR_ENABLE_PARITY 0xA000
781
782 uint16_t unused_9[5];
783 uint16_t gpiod;
784 uint16_t gpioe;
785 #define GPIO_LED_MASK 0x00C0
786 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
787 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
788 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
789 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
790 #define GPIO_LED_ALL_OFF 0x0000
791 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001
792 #define GPIO_LED_RGA_ON 0x00C1
793
794 union {
795 struct {
796 uint16_t unused_10[8];
797 uint16_t mailbox8;
798 uint16_t mailbox9;
799 uint16_t mailbox10;
800 uint16_t mailbox11;
801 uint16_t mailbox12;
802 uint16_t mailbox13;
803 uint16_t mailbox14;
804 uint16_t mailbox15;
805 uint16_t mailbox16;
806 uint16_t mailbox17;
807 uint16_t mailbox18;
808 uint16_t mailbox19;
809 uint16_t mailbox20;
810 uint16_t mailbox21;
811 uint16_t mailbox22;
812 uint16_t mailbox23;
813 } __attribute__((packed)) isp2200;
814 } u_end;
815 };
816
817 struct device_reg_25xxmq {
818 uint32_t req_q_in;
819 uint32_t req_q_out;
820 uint32_t rsp_q_in;
821 uint32_t rsp_q_out;
822 uint32_t atio_q_in;
823 uint32_t atio_q_out;
824 };
825
826
827 struct device_reg_fx00 {
828 uint32_t mailbox0;
829 uint32_t mailbox1;
830 uint32_t mailbox2;
831 uint32_t mailbox3;
832 uint32_t mailbox4;
833 uint32_t mailbox5;
834 uint32_t mailbox6;
835 uint32_t mailbox7;
836 uint32_t mailbox8;
837 uint32_t mailbox9;
838 uint32_t mailbox10;
839 uint32_t mailbox11;
840 uint32_t mailbox12;
841 uint32_t mailbox13;
842 uint32_t mailbox14;
843 uint32_t mailbox15;
844 uint32_t mailbox16;
845 uint32_t mailbox17;
846 uint32_t mailbox18;
847 uint32_t mailbox19;
848 uint32_t mailbox20;
849 uint32_t mailbox21;
850 uint32_t mailbox22;
851 uint32_t mailbox23;
852 uint32_t mailbox24;
853 uint32_t mailbox25;
854 uint32_t mailbox26;
855 uint32_t mailbox27;
856 uint32_t mailbox28;
857 uint32_t mailbox29;
858 uint32_t mailbox30;
859 uint32_t mailbox31;
860 uint32_t aenmailbox0;
861 uint32_t aenmailbox1;
862 uint32_t aenmailbox2;
863 uint32_t aenmailbox3;
864 uint32_t aenmailbox4;
865 uint32_t aenmailbox5;
866 uint32_t aenmailbox6;
867 uint32_t aenmailbox7;
868
869 uint32_t req_q_in;
870 uint32_t req_q_out;
871
872 uint32_t rsp_q_in;
873 uint32_t rsp_q_out;
874
875 uint32_t initval0;
876 uint32_t initval1;
877 uint32_t initval2;
878 uint32_t initval3;
879 uint32_t initval4;
880 uint32_t initval5;
881 uint32_t initval6;
882 uint32_t initval7;
883 uint32_t fwheartbeat;
884 uint32_t pseudoaen;
885 };
886
887
888
889 typedef union {
890 struct device_reg_2xxx isp;
891 struct device_reg_24xx isp24;
892 struct device_reg_25xxmq isp25mq;
893 struct device_reg_82xx isp82;
894 struct device_reg_fx00 ispfx00;
895 } __iomem device_reg_t;
896
897 #define ISP_REQ_Q_IN(ha, reg) \
898 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
899 &(reg)->u.isp2100.mailbox4 : \
900 &(reg)->u.isp2300.req_q_in)
901 #define ISP_REQ_Q_OUT(ha, reg) \
902 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
903 &(reg)->u.isp2100.mailbox4 : \
904 &(reg)->u.isp2300.req_q_out)
905 #define ISP_RSP_Q_IN(ha, reg) \
906 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
907 &(reg)->u.isp2100.mailbox5 : \
908 &(reg)->u.isp2300.rsp_q_in)
909 #define ISP_RSP_Q_OUT(ha, reg) \
910 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
911 &(reg)->u.isp2100.mailbox5 : \
912 &(reg)->u.isp2300.rsp_q_out)
913
914 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
915 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
916
917 #define MAILBOX_REG(ha, reg, num) \
918 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
919 (num < 8 ? \
920 &(reg)->u.isp2100.mailbox0 + (num) : \
921 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
922 &(reg)->u.isp2300.mailbox0 + (num))
923 #define RD_MAILBOX_REG(ha, reg, num) \
924 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
925 #define WRT_MAILBOX_REG(ha, reg, num, data) \
926 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
927
928 #define FB_CMD_REG(ha, reg) \
929 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
930 &(reg)->fb_cmd_2100 : \
931 &(reg)->u.isp2300.fb_cmd)
932 #define RD_FB_CMD_REG(ha, reg) \
933 RD_REG_WORD(FB_CMD_REG(ha, reg))
934 #define WRT_FB_CMD_REG(ha, reg, data) \
935 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
936
937 typedef struct {
938 uint32_t out_mb;
939 uint32_t in_mb;
940 uint16_t mb[MAILBOX_REGISTER_COUNT];
941 long buf_size;
942 void *bufp;
943 uint32_t tov;
944 uint8_t flags;
945 #define MBX_DMA_IN BIT_0
946 #define MBX_DMA_OUT BIT_1
947 #define IOCTL_CMD BIT_2
948 } mbx_cmd_t;
949
950 struct mbx_cmd_32 {
951 uint32_t out_mb;
952 uint32_t in_mb;
953 uint32_t mb[MAILBOX_REGISTER_COUNT];
954 long buf_size;
955 void *bufp;
956 uint32_t tov;
957 uint8_t flags;
958 #define MBX_DMA_IN BIT_0
959 #define MBX_DMA_OUT BIT_1
960 #define IOCTL_CMD BIT_2
961 };
962
963
964 #define MBX_TOV_SECONDS 30
965
966
967
968
969 #define PROD_ID_1 0x4953
970 #define PROD_ID_2 0x0000
971 #define PROD_ID_2a 0x5020
972 #define PROD_ID_3 0x2020
973
974
975
976
977 #define MBS_FRM_ALIVE 0
978 #define MBS_CHKSUM_ERR 1
979 #define MBS_BUSY 4
980
981
982
983
984 #define MBS_COMMAND_COMPLETE 0x4000
985 #define MBS_INVALID_COMMAND 0x4001
986 #define MBS_HOST_INTERFACE_ERROR 0x4002
987 #define MBS_TEST_FAILED 0x4003
988 #define MBS_COMMAND_ERROR 0x4005
989 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
990 #define MBS_PORT_ID_USED 0x4007
991 #define MBS_LOOP_ID_USED 0x4008
992 #define MBS_ALL_IDS_IN_USE 0x4009
993 #define MBS_NOT_LOGGED_IN 0x400A
994 #define MBS_LINK_DOWN_ERROR 0x400B
995 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
996
997 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs)
998 {
999 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR;
1000 }
1001
1002
1003
1004
1005 #define MBA_ASYNC_EVENT 0x8000
1006 #define MBA_RESET 0x8001
1007 #define MBA_SYSTEM_ERR 0x8002
1008 #define MBA_REQ_TRANSFER_ERR 0x8003
1009 #define MBA_RSP_TRANSFER_ERR 0x8004
1010 #define MBA_WAKEUP_THRES 0x8005
1011 #define MBA_LIP_OCCURRED 0x8010
1012
1013 #define MBA_LOOP_UP 0x8011
1014 #define MBA_LOOP_DOWN 0x8012
1015 #define MBA_LIP_RESET 0x8013
1016 #define MBA_PORT_UPDATE 0x8014
1017 #define MBA_RSCN_UPDATE 0x8015
1018 #define MBA_LIP_F8 0x8016
1019 #define MBA_LOOP_INIT_ERR 0x8017
1020 #define MBA_FABRIC_AUTH_REQ 0x801b
1021 #define MBA_SCSI_COMPLETION 0x8020
1022 #define MBA_CTIO_COMPLETION 0x8021
1023 #define MBA_IP_COMPLETION 0x8022
1024 #define MBA_IP_RECEIVE 0x8023
1025 #define MBA_IP_BROADCAST 0x8024
1026 #define MBA_IP_LOW_WATER_MARK 0x8025
1027 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026
1028 #define MBA_IP_HDR_DATA_SPLIT 0x8027
1029
1030 #define MBA_TRACE_NOTIFICATION 0x8028
1031 #define MBA_POINT_TO_POINT 0x8030
1032 #define MBA_CMPLT_1_16BIT 0x8031
1033 #define MBA_CMPLT_2_16BIT 0x8032
1034 #define MBA_CMPLT_3_16BIT 0x8033
1035 #define MBA_CMPLT_4_16BIT 0x8034
1036 #define MBA_CMPLT_5_16BIT 0x8035
1037 #define MBA_CHG_IN_CONNECTION 0x8036
1038 #define MBA_RIO_RESPONSE 0x8040
1039 #define MBA_ZIO_RESPONSE 0x8040
1040 #define MBA_CMPLT_2_32BIT 0x8042
1041 #define MBA_BYPASS_NOTIFICATION 0x8043
1042 #define MBA_DISCARD_RND_FRAME 0x8048
1043 #define MBA_REJECTED_FCP_CMD 0x8049
1044 #define MBA_FW_NOT_STARTED 0x8050
1045 #define MBA_FW_STARTING 0x8051
1046 #define MBA_FW_RESTART_CMPLT 0x8060
1047 #define MBA_INIT_REQUIRED 0x8061
1048 #define MBA_SHUTDOWN_REQUESTED 0x8062
1049 #define MBA_TEMPERATURE_ALERT 0x8070
1050 #define MBA_DPORT_DIAGNOSTICS 0x8080
1051 #define MBA_TRANS_INSERT 0x8130
1052 #define MBA_FW_INIT_FAILURE 0x8401
1053 #define MBA_MIRROR_LUN_CHANGE 0x8402
1054
1055 #define MBA_FW_POLL_STATE 0x8600
1056 #define MBA_FW_RESET_FCT 0x8502
1057 #define MBA_FW_INIT_INPROGRESS 0x8500
1058
1059 #define MBA_IDC_AEN 0x8200
1060
1061
1062 #define INTR_ROM_MB_SUCCESS 0x1
1063 #define INTR_ROM_MB_FAILED 0x2
1064 #define INTR_MB_SUCCESS 0x10
1065 #define INTR_MB_FAILED 0x11
1066 #define INTR_ASYNC_EVENT 0x12
1067 #define INTR_RSP_QUE_UPDATE 0x13
1068 #define INTR_RSP_QUE_UPDATE_83XX 0x14
1069 #define INTR_ATIO_QUE_UPDATE 0x1C
1070 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
1071 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E
1072
1073
1074 #define MBS_LB_RESET 0x17
1075
1076
1077
1078 #define FO1_AE_ON_LIPF8 BIT_0
1079 #define FO1_AE_ALL_LIP_RESET BIT_1
1080 #define FO1_CTIO_RETRY BIT_3
1081 #define FO1_DISABLE_LIP_F7_SW BIT_4
1082 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1083 #define FO1_DISABLE_GPIO6_7 BIT_6
1084 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
1085 #define FO1_SET_EMPHASIS_SWING BIT_8
1086 #define FO1_AE_AUTO_BYPASS BIT_9
1087 #define FO1_ENABLE_PURE_IOCB BIT_10
1088 #define FO1_AE_PLOGI_RJT BIT_11
1089 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1090 #define FO1_AE_QUEUE_FULL BIT_13
1091
1092 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1093 #define FO2_REV_LOOPBACK BIT_1
1094
1095 #define FO3_ENABLE_EMERG_IOCB BIT_0
1096 #define FO3_AE_RND_ERROR BIT_1
1097
1098
1099 #define ADD_FO_COUNT 3
1100 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6
1101 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1102
1103 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1104
1105 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1106
1107
1108
1109
1110 #define MBC_LOAD_RAM 1
1111 #define MBC_EXECUTE_FIRMWARE 2
1112 #define MBC_READ_RAM_WORD 5
1113 #define MBC_MAILBOX_REGISTER_TEST 6
1114 #define MBC_VERIFY_CHECKSUM 7
1115 #define MBC_GET_FIRMWARE_VERSION 8
1116 #define MBC_LOAD_RISC_RAM 9
1117 #define MBC_DUMP_RISC_RAM 0xa
1118 #define MBC_SECURE_FLASH_UPDATE 0xa
1119 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb
1120 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc
1121 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd
1122 #define MBC_READ_RAM_EXTENDED 0xf
1123 #define MBC_IOCB_COMMAND 0x12
1124 #define MBC_STOP_FIRMWARE 0x14
1125 #define MBC_ABORT_COMMAND 0x15
1126 #define MBC_ABORT_DEVICE 0x16
1127 #define MBC_ABORT_TARGET 0x17
1128 #define MBC_RESET 0x18
1129 #define MBC_GET_ADAPTER_LOOP_ID 0x20
1130 #define MBC_GET_SET_ZIO_THRESHOLD 0x21
1131 #define MBC_GET_RETRY_COUNT 0x22
1132 #define MBC_DISABLE_VI 0x24
1133 #define MBC_ENABLE_VI 0x25
1134 #define MBC_GET_FIRMWARE_OPTION 0x28
1135 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34
1136 #define MBC_SET_FIRMWARE_OPTION 0x38
1137 #define MBC_LOOP_PORT_BYPASS 0x40
1138 #define MBC_LOOP_PORT_ENABLE 0x41
1139 #define MBC_GET_RESOURCE_COUNTS 0x42
1140 #define MBC_NON_PARTICIPATE 0x43
1141 #define MBC_DIAGNOSTIC_ECHO 0x44
1142 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45
1143 #define MBC_ONLINE_SELF_TEST 0x46
1144 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47
1145 #define MBC_CONFIGURE_VF 0x4b
1146 #define MBC_RESET_LINK_STATUS 0x52
1147 #define MBC_IOCB_COMMAND_A64 0x54
1148 #define MBC_PORT_LOGOUT 0x56
1149 #define MBC_SEND_RNID_ELS 0x57
1150 #define MBC_SET_RNID_PARAMS 0x59
1151 #define MBC_GET_RNID_PARAMS 0x5a
1152 #define MBC_DATA_RATE 0x5d
1153 #define MBC_INITIALIZE_FIRMWARE 0x60
1154 #define MBC_INITIATE_LIP 0x62
1155
1156 #define MBC_GET_FC_AL_POSITION_MAP 0x63
1157 #define MBC_GET_PORT_DATABASE 0x64
1158 #define MBC_CLEAR_ACA 0x65
1159 #define MBC_TARGET_RESET 0x66
1160 #define MBC_CLEAR_TASK_SET 0x67
1161 #define MBC_ABORT_TASK_SET 0x68
1162 #define MBC_GET_FIRMWARE_STATE 0x69
1163 #define MBC_GET_PORT_NAME 0x6a
1164 #define MBC_GET_LINK_STATUS 0x6b
1165 #define MBC_LIP_RESET 0x6c
1166 #define MBC_SEND_SNS_COMMAND 0x6e
1167
1168 #define MBC_LOGIN_FABRIC_PORT 0x6f
1169 #define MBC_SEND_CHANGE_REQUEST 0x70
1170 #define MBC_LOGOUT_FABRIC_PORT 0x71
1171 #define MBC_LIP_FULL_LOGIN 0x72
1172 #define MBC_LOGIN_LOOP_PORT 0x74
1173 #define MBC_PORT_NODE_NAME_LIST 0x75
1174 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77
1175 #define MBC_UNLOAD_IP 0x79
1176 #define MBC_GET_ID_LIST 0x7C
1177 #define MBC_SEND_LFA_COMMAND 0x7D
1178 #define MBC_LUN_RESET 0x7E
1179
1180
1181
1182
1183
1184 #define MBC_MR_DRV_SHUTDOWN 0x6A
1185
1186
1187
1188
1189 #define MBC_WRITE_SERDES 0x3
1190 #define MBC_READ_SERDES 0x4
1191 #define MBC_LOAD_DUMP_MPI_RAM 0x5
1192 #define MBC_SERDES_PARAMS 0x10
1193 #define MBC_GET_IOCB_STATUS 0x12
1194 #define MBC_PORT_PARAMS 0x1A
1195 #define MBC_GET_TIMEOUT_PARAMS 0x22
1196 #define MBC_TRACE_CONTROL 0x27
1197 #define MBC_GEN_SYSTEM_ERROR 0x2a
1198 #define MBC_WRITE_SFP 0x30
1199 #define MBC_READ_SFP 0x31
1200 #define MBC_SET_TIMEOUT_PARAMS 0x32
1201 #define MBC_DPORT_DIAGNOSTICS 0x47
1202 #define MBC_MID_INITIALIZE_FIRMWARE 0x48
1203 #define MBC_MID_GET_VP_DATABASE 0x49
1204 #define MBC_MID_GET_VP_ENTRY 0x4a
1205 #define MBC_HOST_MEMORY_COPY 0x53
1206 #define MBC_SEND_RNFT_ELS 0x5e
1207 #define MBC_GET_LINK_PRIV_STATS 0x6d
1208 #define MBC_LINK_INITIALIZATION 0x72
1209 #define MBC_SET_VENDOR_ID 0x76
1210 #define MBC_PORT_RESET 0x120
1211 #define MBC_SET_PORT_CONFIG 0x122
1212 #define MBC_GET_PORT_CONFIG 0x123
1213
1214
1215
1216
1217 #define MBC_WRITE_MPI_REGISTER 0x01
1218
1219
1220
1221
1222 #define MBC_SET_GET_ETH_SERDES_REG 0x150
1223 #define HCS_WRITE_SERDES 0x3
1224 #define HCS_READ_SERDES 0x4
1225
1226
1227 #define FCAL_MAP_SIZE 128
1228
1229
1230 #define MBX_31 BIT_31
1231 #define MBX_30 BIT_30
1232 #define MBX_29 BIT_29
1233 #define MBX_28 BIT_28
1234 #define MBX_27 BIT_27
1235 #define MBX_26 BIT_26
1236 #define MBX_25 BIT_25
1237 #define MBX_24 BIT_24
1238 #define MBX_23 BIT_23
1239 #define MBX_22 BIT_22
1240 #define MBX_21 BIT_21
1241 #define MBX_20 BIT_20
1242 #define MBX_19 BIT_19
1243 #define MBX_18 BIT_18
1244 #define MBX_17 BIT_17
1245 #define MBX_16 BIT_16
1246 #define MBX_15 BIT_15
1247 #define MBX_14 BIT_14
1248 #define MBX_13 BIT_13
1249 #define MBX_12 BIT_12
1250 #define MBX_11 BIT_11
1251 #define MBX_10 BIT_10
1252 #define MBX_9 BIT_9
1253 #define MBX_8 BIT_8
1254 #define MBX_7 BIT_7
1255 #define MBX_6 BIT_6
1256 #define MBX_5 BIT_5
1257 #define MBX_4 BIT_4
1258 #define MBX_3 BIT_3
1259 #define MBX_2 BIT_2
1260 #define MBX_1 BIT_1
1261 #define MBX_0 BIT_0
1262
1263 #define RNID_TYPE_PORT_LOGIN 0x7
1264 #define RNID_TYPE_SET_VERSION 0x9
1265 #define RNID_TYPE_ASIC_TEMP 0xC
1266
1267
1268
1269
1270 #define FSTATE_CONFIG_WAIT 0
1271 #define FSTATE_WAIT_AL_PA 1
1272 #define FSTATE_WAIT_LOGIN 2
1273 #define FSTATE_READY 3
1274 #define FSTATE_LOSS_OF_SYNC 4
1275 #define FSTATE_ERROR 5
1276 #define FSTATE_REINIT 6
1277 #define FSTATE_NON_PART 7
1278
1279 #define FSTATE_CONFIG_CORRECT 0
1280 #define FSTATE_P2P_RCV_LIP 1
1281 #define FSTATE_P2P_CHOOSE_LOOP 2
1282 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1283 #define FSTATE_FATAL_ERROR 4
1284 #define FSTATE_LOOP_BACK_CONN 5
1285
1286 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1287 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1288 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1289 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1290 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1291 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
1292 #define QLA27XX_DEFAULT_IMAGE 0
1293 #define QLA27XX_PRIMARY_IMAGE 1
1294 #define QLA27XX_SECONDARY_IMAGE 2
1295
1296
1297
1298
1299
1300 #define PORT_DATABASE_SIZE 128
1301 typedef struct {
1302 uint8_t options;
1303 uint8_t control;
1304 uint8_t master_state;
1305 uint8_t slave_state;
1306 uint8_t reserved[2];
1307 uint8_t hard_address;
1308 uint8_t reserved_1;
1309 uint8_t port_id[4];
1310 uint8_t node_name[WWN_SIZE];
1311 uint8_t port_name[WWN_SIZE];
1312 uint16_t execution_throttle;
1313 uint16_t execution_count;
1314 uint8_t reset_count;
1315 uint8_t reserved_2;
1316 uint16_t resource_allocation;
1317 uint16_t current_allocation;
1318 uint16_t queue_head;
1319 uint16_t queue_tail;
1320 uint16_t transmit_execution_list_next;
1321 uint16_t transmit_execution_list_previous;
1322 uint16_t common_features;
1323 uint16_t total_concurrent_sequences;
1324 uint16_t RO_by_information_category;
1325 uint8_t recipient;
1326 uint8_t initiator;
1327 uint16_t receive_data_size;
1328 uint16_t concurrent_sequences;
1329 uint16_t open_sequences_per_exchange;
1330 uint16_t lun_abort_flags;
1331 uint16_t lun_stop_flags;
1332 uint16_t stop_queue_head;
1333 uint16_t stop_queue_tail;
1334 uint16_t port_retry_timer;
1335 uint16_t next_sequence_id;
1336 uint16_t frame_count;
1337 uint16_t PRLI_payload_length;
1338 uint8_t prli_svc_param_word_0[2];
1339
1340 uint8_t prli_svc_param_word_3[2];
1341
1342 uint16_t loop_id;
1343 uint16_t extended_lun_info_list_pointer;
1344 uint16_t extended_lun_stop_list_pointer;
1345 } port_database_t;
1346
1347
1348
1349
1350 #define PD_STATE_DISCOVERY 0
1351 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1352 #define PD_STATE_PORT_LOGIN 2
1353 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1354 #define PD_STATE_PROCESS_LOGIN 4
1355 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1356 #define PD_STATE_PORT_LOGGED_IN 6
1357 #define PD_STATE_PORT_UNAVAILABLE 7
1358 #define PD_STATE_PROCESS_LOGOUT 8
1359 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1360 #define PD_STATE_PORT_LOGOUT 10
1361 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1362
1363
1364 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1365 #define QLA_ZIO_DISABLED 0
1366 #define QLA_ZIO_DEFAULT_TIMER 2
1367
1368
1369
1370
1371
1372 #define ICB_VERSION 1
1373 typedef struct {
1374 uint8_t version;
1375 uint8_t reserved_1;
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396 uint8_t firmware_options[2];
1397
1398 uint16_t frame_payload_size;
1399 uint16_t max_iocb_allocation;
1400 uint16_t execution_throttle;
1401 uint8_t retry_count;
1402 uint8_t retry_delay;
1403 uint8_t port_name[WWN_SIZE];
1404 uint16_t hard_address;
1405 uint8_t inquiry_data;
1406 uint8_t login_timeout;
1407 uint8_t node_name[WWN_SIZE];
1408
1409 uint16_t request_q_outpointer;
1410 uint16_t response_q_inpointer;
1411 uint16_t request_q_length;
1412 uint16_t response_q_length;
1413 __le64 request_q_address __packed;
1414 __le64 response_q_address __packed;
1415
1416 uint16_t lun_enables;
1417 uint8_t command_resource_count;
1418 uint8_t immediate_notify_resource_count;
1419 uint16_t timeout;
1420 uint8_t reserved_2[2];
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441 uint8_t add_firmware_options[2];
1442
1443 uint8_t response_accumulation_timer;
1444 uint8_t interrupt_delay_timer;
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465 uint8_t special_options[2];
1466
1467 uint8_t reserved_3[26];
1468 } init_cb_t;
1469
1470
1471
1472
1473 #define GLSO_SEND_RPS BIT_0
1474 #define GLSO_USE_DID BIT_3
1475
1476 struct link_statistics {
1477 uint32_t link_fail_cnt;
1478 uint32_t loss_sync_cnt;
1479 uint32_t loss_sig_cnt;
1480 uint32_t prim_seq_err_cnt;
1481 uint32_t inval_xmit_word_cnt;
1482 uint32_t inval_crc_cnt;
1483 uint32_t lip_cnt;
1484 uint32_t link_up_cnt;
1485 uint32_t link_down_loop_init_tmo;
1486 uint32_t link_down_los;
1487 uint32_t link_down_loss_rcv_clk;
1488 uint32_t reserved0[5];
1489 uint32_t port_cfg_chg;
1490 uint32_t reserved1[11];
1491 uint32_t rsp_q_full;
1492 uint32_t atio_q_full;
1493 uint32_t drop_ae;
1494 uint32_t els_proto_err;
1495 uint32_t reserved2;
1496 uint32_t tx_frames;
1497 uint32_t rx_frames;
1498 uint32_t discarded_frames;
1499 uint32_t dropped_frames;
1500 uint32_t reserved3;
1501 uint32_t nos_rcvd;
1502 uint32_t reserved4[4];
1503 uint32_t tx_prjt;
1504 uint32_t rcv_exfail;
1505 uint32_t rcv_abts;
1506 uint32_t seq_frm_miss;
1507 uint32_t corr_err;
1508 uint32_t mb_rqst;
1509 uint32_t nport_full;
1510 uint32_t eofa;
1511 uint32_t reserved5;
1512 uint32_t fpm_recv_word_cnt_lo;
1513 uint32_t fpm_recv_word_cnt_hi;
1514 uint32_t fpm_disc_word_cnt_lo;
1515 uint32_t fpm_disc_word_cnt_hi;
1516 uint32_t fpm_xmit_word_cnt_lo;
1517 uint32_t fpm_xmit_word_cnt_hi;
1518 uint32_t reserved6[70];
1519 };
1520
1521
1522
1523
1524 #define NV_START_BIT BIT_2
1525 #define NV_WRITE_OP (BIT_26+BIT_24)
1526 #define NV_READ_OP (BIT_26+BIT_25)
1527 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1528 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1529 #define NV_DELAY_COUNT 10
1530
1531
1532
1533
1534 typedef struct {
1535
1536
1537
1538 uint8_t id[4];
1539 uint8_t nvram_version;
1540 uint8_t reserved_0;
1541
1542
1543
1544
1545 uint8_t parameter_block_version;
1546 uint8_t reserved_1;
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567 uint8_t firmware_options[2];
1568
1569 uint16_t frame_payload_size;
1570 uint16_t max_iocb_allocation;
1571 uint16_t execution_throttle;
1572 uint8_t retry_count;
1573 uint8_t retry_delay;
1574 uint8_t port_name[WWN_SIZE];
1575 uint16_t hard_address;
1576 uint8_t inquiry_data;
1577 uint8_t login_timeout;
1578 uint8_t node_name[WWN_SIZE];
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599 uint8_t add_firmware_options[2];
1600
1601 uint8_t response_accumulation_timer;
1602 uint8_t interrupt_delay_timer;
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623 uint8_t special_options[2];
1624
1625
1626 uint8_t reserved_2[22];
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665 uint8_t seriallink_options[4];
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688 uint8_t host_p[2];
1689
1690 uint8_t boot_node_name[WWN_SIZE];
1691 uint8_t boot_lun_number;
1692 uint8_t reset_delay;
1693 uint8_t port_down_retry_count;
1694 uint8_t boot_id_number;
1695 uint16_t max_luns_per_target;
1696 uint8_t fcode_boot_port_name[WWN_SIZE];
1697 uint8_t alternate_port_name[WWN_SIZE];
1698 uint8_t alternate_node_name[WWN_SIZE];
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710 uint8_t efi_parameters;
1711
1712 uint8_t link_down_timeout;
1713
1714 uint8_t adapter_id[16];
1715
1716 uint8_t alt1_boot_node_name[WWN_SIZE];
1717 uint16_t alt1_boot_lun_number;
1718 uint8_t alt2_boot_node_name[WWN_SIZE];
1719 uint16_t alt2_boot_lun_number;
1720 uint8_t alt3_boot_node_name[WWN_SIZE];
1721 uint16_t alt3_boot_lun_number;
1722 uint8_t alt4_boot_node_name[WWN_SIZE];
1723 uint16_t alt4_boot_lun_number;
1724 uint8_t alt5_boot_node_name[WWN_SIZE];
1725 uint16_t alt5_boot_lun_number;
1726 uint8_t alt6_boot_node_name[WWN_SIZE];
1727 uint16_t alt6_boot_lun_number;
1728 uint8_t alt7_boot_node_name[WWN_SIZE];
1729 uint16_t alt7_boot_lun_number;
1730
1731 uint8_t reserved_3[2];
1732
1733
1734 uint8_t model_number[16];
1735
1736
1737 uint8_t oem_specific[16];
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760 uint8_t adapter_features[2];
1761
1762 uint8_t reserved_4[16];
1763
1764
1765 uint16_t subsystem_vendor_id_2200;
1766
1767
1768 uint16_t subsystem_device_id_2200;
1769
1770 uint8_t reserved_5;
1771 uint8_t checksum;
1772 } nvram_t;
1773
1774
1775
1776
1777 typedef struct {
1778 uint8_t entry_type;
1779 uint8_t entry_count;
1780 uint8_t sys_define;
1781 uint8_t entry_status;
1782 uint32_t handle;
1783 uint8_t data[52];
1784 uint32_t signature;
1785 #define RESPONSE_PROCESSED 0xDEADDEAD
1786 } response_t;
1787
1788
1789
1790
1791 struct atio {
1792 uint8_t entry_type;
1793 uint8_t entry_count;
1794 __le16 attr_n_length;
1795 uint8_t data[56];
1796 uint32_t signature;
1797 #define ATIO_PROCESSED 0xDEADDEAD
1798 };
1799
1800 typedef union {
1801 uint16_t extended;
1802 struct {
1803 uint8_t reserved;
1804 uint8_t standard;
1805 } id;
1806 } target_id_t;
1807
1808 #define SET_TARGET_ID(ha, to, from) \
1809 do { \
1810 if (HAS_EXTENDED_IDS(ha)) \
1811 to.extended = cpu_to_le16(from); \
1812 else \
1813 to.id.standard = (uint8_t)from; \
1814 } while (0)
1815
1816
1817
1818
1819 #define COMMAND_TYPE 0x11
1820 typedef struct {
1821 uint8_t entry_type;
1822 uint8_t entry_count;
1823 uint8_t sys_define;
1824 uint8_t entry_status;
1825 uint32_t handle;
1826 target_id_t target;
1827 uint16_t lun;
1828 uint16_t control_flags;
1829 #define CF_WRITE BIT_6
1830 #define CF_READ BIT_5
1831 #define CF_SIMPLE_TAG BIT_3
1832 #define CF_ORDERED_TAG BIT_2
1833 #define CF_HEAD_TAG BIT_1
1834 uint16_t reserved_1;
1835 uint16_t timeout;
1836 uint16_t dseg_count;
1837 uint8_t scsi_cdb[MAX_CMDSZ];
1838 uint32_t byte_count;
1839 union {
1840 struct dsd32 dsd32[3];
1841 struct dsd64 dsd64[2];
1842 };
1843 } cmd_entry_t;
1844
1845
1846
1847
1848 #define COMMAND_A64_TYPE 0x19
1849 typedef struct {
1850 uint8_t entry_type;
1851 uint8_t entry_count;
1852 uint8_t sys_define;
1853 uint8_t entry_status;
1854 uint32_t handle;
1855 target_id_t target;
1856 uint16_t lun;
1857 uint16_t control_flags;
1858 uint16_t reserved_1;
1859 uint16_t timeout;
1860 uint16_t dseg_count;
1861 uint8_t scsi_cdb[MAX_CMDSZ];
1862 uint32_t byte_count;
1863 struct dsd64 dsd[2];
1864 } cmd_a64_entry_t, request_t;
1865
1866
1867
1868
1869 #define CONTINUE_TYPE 0x02
1870 typedef struct {
1871 uint8_t entry_type;
1872 uint8_t entry_count;
1873 uint8_t sys_define;
1874 uint8_t entry_status;
1875 uint32_t reserved;
1876 struct dsd32 dsd[7];
1877 } cont_entry_t;
1878
1879
1880
1881
1882 #define CONTINUE_A64_TYPE 0x0A
1883 typedef struct {
1884 uint8_t entry_type;
1885 uint8_t entry_count;
1886 uint8_t sys_define;
1887 uint8_t entry_status;
1888 struct dsd64 dsd[5];
1889 } cont_a64_entry_t;
1890
1891 #define PO_MODE_DIF_INSERT 0
1892 #define PO_MODE_DIF_REMOVE 1
1893 #define PO_MODE_DIF_PASS 2
1894 #define PO_MODE_DIF_REPLACE 3
1895 #define PO_MODE_DIF_TCP_CKSUM 6
1896 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1897 #define PO_DISABLE_GUARD_CHECK BIT_4
1898 #define PO_DISABLE_INCR_REF_TAG BIT_5
1899 #define PO_DIS_HEADER_MODE BIT_7
1900 #define PO_ENABLE_DIF_BUNDLING BIT_8
1901 #define PO_DIS_FRAME_MODE BIT_9
1902 #define PO_DIS_VALD_APP_ESC BIT_10
1903 #define PO_DIS_VALD_APP_REF_ESC BIT_11
1904
1905 #define PO_DIS_APP_TAG_REPL BIT_12
1906 #define PO_DIS_REF_TAG_REPL BIT_13
1907 #define PO_DIS_APP_TAG_VALD BIT_14
1908 #define PO_DIS_REF_TAG_VALD BIT_15
1909
1910
1911
1912
1913 struct crc_context {
1914 uint32_t handle;
1915 __le32 ref_tag;
1916 __le16 app_tag;
1917 uint8_t ref_tag_mask[4];
1918 uint8_t app_tag_mask[2];
1919 __le16 guard_seed;
1920 __le16 prot_opts;
1921 __le16 blk_size;
1922 uint16_t runt_blk_guard;
1923
1924 __le32 byte_count;
1925
1926 union {
1927 struct {
1928 uint32_t reserved_1;
1929 uint16_t reserved_2;
1930 uint16_t reserved_3;
1931 uint32_t reserved_4;
1932 struct dsd64 data_dsd[1];
1933 uint32_t reserved_5[2];
1934 uint32_t reserved_6;
1935 } nobundling;
1936 struct {
1937 __le32 dif_byte_count;
1938
1939 uint16_t reserved_1;
1940 __le16 dseg_count;
1941 uint32_t reserved_2;
1942 struct dsd64 data_dsd[1];
1943 struct dsd64 dif_dsd;
1944 } bundling;
1945 } u;
1946
1947 struct fcp_cmnd fcp_cmnd;
1948 dma_addr_t crc_ctx_dma;
1949
1950 struct list_head dsd_list;
1951
1952
1953 struct list_head ldif_dsd_list;
1954 u8 no_ldif_dsd;
1955
1956 struct list_head ldif_dma_hndl_list;
1957 u32 dif_bundl_len;
1958 u8 no_dif_bundl;
1959
1960 };
1961
1962 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1963 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1964
1965
1966
1967
1968 #define STATUS_TYPE 0x03
1969 typedef struct {
1970 uint8_t entry_type;
1971 uint8_t entry_count;
1972 uint8_t sys_define;
1973 uint8_t entry_status;
1974 uint32_t handle;
1975 uint16_t scsi_status;
1976 uint16_t comp_status;
1977 uint16_t state_flags;
1978 uint16_t status_flags;
1979 uint16_t rsp_info_len;
1980 uint16_t req_sense_length;
1981 uint32_t residual_length;
1982 uint8_t rsp_info[8];
1983 uint8_t req_sense_data[32];
1984 } sts_entry_t;
1985
1986
1987
1988
1989 #define RF_RQ_DMA_ERROR BIT_6
1990 #define RF_INV_E_ORDER BIT_5
1991 #define RF_INV_E_COUNT BIT_4
1992 #define RF_INV_E_PARAM BIT_3
1993 #define RF_INV_E_TYPE BIT_2
1994 #define RF_BUSY BIT_1
1995 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1996 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1997 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1998 RF_INV_E_TYPE)
1999
2000
2001
2002
2003 #define SS_MASK 0xfff
2004 #define SS_RESIDUAL_UNDER BIT_11
2005 #define SS_RESIDUAL_OVER BIT_10
2006 #define SS_SENSE_LEN_VALID BIT_9
2007 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
2008 #define SS_SCSI_STATUS_BYTE 0xff
2009
2010 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
2011 #define SS_BUSY_CONDITION BIT_3
2012 #define SS_CONDITION_MET BIT_2
2013 #define SS_CHECK_CONDITION BIT_1
2014
2015
2016
2017
2018 #define CS_COMPLETE 0x0
2019 #define CS_INCOMPLETE 0x1
2020 #define CS_DMA 0x2
2021 #define CS_TRANSPORT 0x3
2022 #define CS_RESET 0x4
2023 #define CS_ABORTED 0x5
2024 #define CS_TIMEOUT 0x6
2025 #define CS_DATA_OVERRUN 0x7
2026 #define CS_DIF_ERROR 0xC
2027
2028 #define CS_DATA_UNDERRUN 0x15
2029 #define CS_QUEUE_FULL 0x1C
2030 #define CS_PORT_UNAVAILABLE 0x28
2031
2032 #define CS_PORT_LOGGED_OUT 0x29
2033 #define CS_PORT_CONFIG_CHG 0x2A
2034 #define CS_PORT_BUSY 0x2B
2035 #define CS_COMPLETE_CHKCOND 0x30
2036 #define CS_IOCB_ERROR 0x31
2037
2038 #define CS_BAD_PAYLOAD 0x80
2039 #define CS_UNKNOWN 0x81
2040 #define CS_RETRY 0x82
2041 #define CS_LOOP_DOWN_ABORT 0x83
2042
2043 #define CS_BIDIR_RD_OVERRUN 0x700
2044 #define CS_BIDIR_RD_WR_OVERRUN 0x707
2045 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
2046 #define CS_BIDIR_RD_UNDERRUN 0x1500
2047 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
2048 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
2049 #define CS_BIDIR_DMA 0x200
2050
2051
2052
2053 #define SF_ABTS_TERMINATED BIT_10
2054 #define SF_LOGOUT_SENT BIT_13
2055
2056
2057
2058
2059 #define STATUS_CONT_TYPE 0x10
2060 typedef struct {
2061 uint8_t entry_type;
2062 uint8_t entry_count;
2063 uint8_t sys_define;
2064 uint8_t entry_status;
2065 uint8_t data[60];
2066 } sts_cont_entry_t;
2067
2068
2069
2070
2071
2072 #define STATUS_TYPE_21 0x21
2073 typedef struct {
2074 uint8_t entry_type;
2075 uint8_t entry_count;
2076 uint8_t handle_count;
2077 uint8_t entry_status;
2078 uint32_t handle[15];
2079 } sts21_entry_t;
2080
2081
2082
2083
2084
2085 #define STATUS_TYPE_22 0x22
2086 typedef struct {
2087 uint8_t entry_type;
2088 uint8_t entry_count;
2089 uint8_t handle_count;
2090 uint8_t entry_status;
2091 uint16_t handle[30];
2092 } sts22_entry_t;
2093
2094
2095
2096
2097 #define MARKER_TYPE 0x04
2098 typedef struct {
2099 uint8_t entry_type;
2100 uint8_t entry_count;
2101 uint8_t handle_count;
2102 uint8_t entry_status;
2103 uint32_t sys_define_2;
2104 target_id_t target;
2105 uint8_t modifier;
2106 #define MK_SYNC_ID_LUN 0
2107 #define MK_SYNC_ID 1
2108 #define MK_SYNC_ALL 2
2109 #define MK_SYNC_LIP 3
2110
2111
2112 uint8_t reserved_1;
2113 uint16_t sequence_number;
2114 uint16_t lun;
2115 uint8_t reserved_2[48];
2116 } mrk_entry_t;
2117
2118
2119
2120
2121 #define MS_IOCB_TYPE 0x29
2122 typedef struct {
2123 uint8_t entry_type;
2124 uint8_t entry_count;
2125 uint8_t handle_count;
2126 uint8_t entry_status;
2127 uint32_t handle1;
2128 target_id_t loop_id;
2129 uint16_t status;
2130 uint16_t control_flags;
2131 uint16_t reserved2;
2132 uint16_t timeout;
2133 uint16_t cmd_dsd_count;
2134 uint16_t total_dsd_count;
2135 uint8_t type;
2136 uint8_t r_ctl;
2137 uint16_t rx_id;
2138 uint16_t reserved3;
2139 uint32_t handle2;
2140 uint32_t rsp_bytecount;
2141 uint32_t req_bytecount;
2142 struct dsd64 req_dsd;
2143 struct dsd64 rsp_dsd;
2144 } ms_iocb_entry_t;
2145
2146
2147
2148
2149
2150 #define MBX_IOCB_TYPE 0x39
2151 struct mbx_entry {
2152 uint8_t entry_type;
2153 uint8_t entry_count;
2154 uint8_t sys_define1;
2155
2156 #define SOURCE_SCSI 0x00
2157 #define SOURCE_IP 0x01
2158 #define SOURCE_VI 0x02
2159 #define SOURCE_SCTP 0x03
2160 #define SOURCE_MP 0x04
2161 #define SOURCE_MPIOCTL 0x05
2162 #define SOURCE_ASYNC_IOCB 0x07
2163
2164 uint8_t entry_status;
2165
2166 uint32_t handle;
2167 target_id_t loop_id;
2168
2169 uint16_t status;
2170 uint16_t state_flags;
2171 uint16_t status_flags;
2172
2173 uint32_t sys_define2[2];
2174
2175 uint16_t mb0;
2176 uint16_t mb1;
2177 uint16_t mb2;
2178 uint16_t mb3;
2179 uint16_t mb6;
2180 uint16_t mb7;
2181 uint16_t mb9;
2182 uint16_t mb10;
2183 uint32_t reserved_2[2];
2184 uint8_t node_name[WWN_SIZE];
2185 uint8_t port_name[WWN_SIZE];
2186 };
2187
2188 #ifndef IMMED_NOTIFY_TYPE
2189 #define IMMED_NOTIFY_TYPE 0x0D
2190
2191
2192
2193
2194
2195
2196
2197 struct imm_ntfy_from_isp {
2198 uint8_t entry_type;
2199 uint8_t entry_count;
2200 uint8_t sys_define;
2201 uint8_t entry_status;
2202 union {
2203 struct {
2204 uint32_t sys_define_2;
2205 target_id_t target;
2206 uint16_t lun;
2207 uint8_t target_id;
2208 uint8_t reserved_1;
2209 uint16_t status_modifier;
2210 uint16_t status;
2211 uint16_t task_flags;
2212 uint16_t seq_id;
2213 uint16_t srr_rx_id;
2214 uint32_t srr_rel_offs;
2215 uint16_t srr_ui;
2216 #define SRR_IU_DATA_IN 0x1
2217 #define SRR_IU_DATA_OUT 0x5
2218 #define SRR_IU_STATUS 0x7
2219 uint16_t srr_ox_id;
2220 uint8_t reserved_2[28];
2221 } isp2x;
2222 struct {
2223 uint32_t reserved;
2224 uint16_t nport_handle;
2225 uint16_t reserved_2;
2226 uint16_t flags;
2227 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2228 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2229 uint16_t srr_rx_id;
2230 uint16_t status;
2231 uint8_t status_subcode;
2232 uint8_t fw_handle;
2233 uint32_t exchange_address;
2234 uint32_t srr_rel_offs;
2235 uint16_t srr_ui;
2236 uint16_t srr_ox_id;
2237 union {
2238 struct {
2239 uint8_t node_name[8];
2240 } plogi;
2241 struct {
2242
2243 uint16_t wd3_lo;
2244 uint8_t resv0[6];
2245 } prli;
2246 struct {
2247 uint8_t port_id[3];
2248 uint8_t resv1;
2249 uint16_t nport_handle;
2250 uint16_t resv2;
2251 } req_els;
2252 } u;
2253 uint8_t port_name[8];
2254 uint8_t resv3[3];
2255 uint8_t vp_index;
2256 uint32_t reserved_5;
2257 uint8_t port_id[3];
2258 uint8_t reserved_6;
2259 } isp24;
2260 } u;
2261 uint16_t reserved_7;
2262 uint16_t ox_id;
2263 } __packed;
2264 #endif
2265
2266
2267
2268
2269 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2270 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
2271
2272
2273
2274
2275
2276
2277 typedef struct {
2278 port_id_t d_id;
2279 uint8_t node_name[WWN_SIZE];
2280 uint8_t port_name[WWN_SIZE];
2281 uint8_t fabric_port_name[WWN_SIZE];
2282 uint16_t fp_speed;
2283 uint8_t fc4_type;
2284 uint8_t fc4f_nvme;
2285 } sw_info_t;
2286
2287
2288 #define FC4_TYPE_FCP_SCSI 0x08
2289 #define FC4_TYPE_NVME 0x28
2290 #define FC4_TYPE_OTHER 0x0
2291 #define FC4_TYPE_UNKNOWN 0xff
2292
2293
2294 struct mbx_24xx_entry {
2295 uint8_t entry_type;
2296 uint8_t entry_count;
2297 uint8_t sys_define1;
2298 uint8_t entry_status;
2299 uint32_t handle;
2300 uint16_t mb[28];
2301 };
2302
2303 #define IOCB_SIZE 64
2304
2305
2306
2307
2308 typedef enum {
2309 FCT_UNKNOWN,
2310 FCT_RSCN,
2311 FCT_SWITCH,
2312 FCT_BROADCAST,
2313 FCT_INITIATOR,
2314 FCT_TARGET,
2315 FCT_NVME_INITIATOR = 0x10,
2316 FCT_NVME_TARGET = 0x20,
2317 FCT_NVME_DISCOVERY = 0x40,
2318 FCT_NVME = 0xf0,
2319 } fc_port_type_t;
2320
2321 enum qla_sess_deletion {
2322 QLA_SESS_DELETION_NONE = 0,
2323 QLA_SESS_DELETION_IN_PROGRESS,
2324 QLA_SESS_DELETED,
2325 };
2326
2327 enum qlt_plogi_link_t {
2328 QLT_PLOGI_LINK_SAME_WWN,
2329 QLT_PLOGI_LINK_CONFLICT,
2330 QLT_PLOGI_LINK_MAX
2331 };
2332
2333 struct qlt_plogi_ack_t {
2334 struct list_head list;
2335 struct imm_ntfy_from_isp iocb;
2336 port_id_t id;
2337 int ref_count;
2338 void *fcport;
2339 };
2340
2341 struct ct_sns_desc {
2342 struct ct_sns_pkt *ct_sns;
2343 dma_addr_t ct_sns_dma;
2344 };
2345
2346 enum discovery_state {
2347 DSC_DELETED,
2348 DSC_GNN_ID,
2349 DSC_GNL,
2350 DSC_LOGIN_PEND,
2351 DSC_LOGIN_FAILED,
2352 DSC_GPDB,
2353 DSC_UPD_FCPORT,
2354 DSC_LOGIN_COMPLETE,
2355 DSC_ADISC,
2356 DSC_DELETE_PEND,
2357 };
2358
2359 enum login_state {
2360 DSC_LS_LLIOCB_SENT = 2,
2361 DSC_LS_PLOGI_PEND,
2362 DSC_LS_PLOGI_COMP,
2363 DSC_LS_PRLI_PEND,
2364 DSC_LS_PRLI_COMP,
2365 DSC_LS_PORT_UNAVAIL,
2366 DSC_LS_PRLO_PEND = 9,
2367 DSC_LS_LOGO_PEND,
2368 };
2369
2370 enum rscn_addr_format {
2371 RSCN_PORT_ADDR,
2372 RSCN_AREA_ADDR,
2373 RSCN_DOM_ADDR,
2374 RSCN_FAB_ADDR,
2375 };
2376
2377
2378
2379
2380 typedef struct fc_port {
2381 struct list_head list;
2382 struct scsi_qla_host *vha;
2383
2384 uint8_t node_name[WWN_SIZE];
2385 uint8_t port_name[WWN_SIZE];
2386 port_id_t d_id;
2387 uint16_t loop_id;
2388 uint16_t old_loop_id;
2389
2390 unsigned int conf_compl_supported:1;
2391 unsigned int deleted:2;
2392 unsigned int free_pending:1;
2393 unsigned int local:1;
2394 unsigned int logout_on_delete:1;
2395 unsigned int logo_ack_needed:1;
2396 unsigned int keep_nport_handle:1;
2397 unsigned int send_els_logo:1;
2398 unsigned int login_pause:1;
2399 unsigned int login_succ:1;
2400 unsigned int query:1;
2401 unsigned int id_changed:1;
2402 unsigned int scan_needed:1;
2403 unsigned int n2n_flag:1;
2404 unsigned int explicit_logout:1;
2405 unsigned int prli_pend_timer:1;
2406
2407 struct completion nvme_del_done;
2408 uint32_t nvme_prli_service_param;
2409 #define NVME_PRLI_SP_CONF BIT_7
2410 #define NVME_PRLI_SP_INITIATOR BIT_5
2411 #define NVME_PRLI_SP_TARGET BIT_4
2412 #define NVME_PRLI_SP_DISCOVERY BIT_3
2413 #define NVME_PRLI_SP_FIRST_BURST BIT_0
2414 uint8_t nvme_flag;
2415 uint32_t nvme_first_burst_size;
2416 #define NVME_FLAG_REGISTERED 4
2417 #define NVME_FLAG_DELETING 2
2418 #define NVME_FLAG_RESETTING 1
2419
2420 struct fc_port *conflict;
2421 unsigned char logout_completed;
2422 int generation;
2423
2424 struct se_session *se_sess;
2425 struct kref sess_kref;
2426 struct qla_tgt *tgt;
2427 unsigned long expires;
2428 struct list_head del_list_entry;
2429 struct work_struct free_work;
2430 struct work_struct reg_work;
2431 uint64_t jiffies_at_registration;
2432 unsigned long prli_expired;
2433 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2434
2435 uint16_t tgt_id;
2436 uint16_t old_tgt_id;
2437 uint16_t sec_since_registration;
2438
2439 uint8_t fcp_prio;
2440
2441 uint8_t fabric_port_name[WWN_SIZE];
2442 uint16_t fp_speed;
2443
2444 fc_port_type_t port_type;
2445
2446 atomic_t state;
2447 uint32_t flags;
2448
2449 int login_retry;
2450
2451 struct fc_rport *rport, *drport;
2452 u32 supported_classes;
2453
2454 uint8_t fc4_type;
2455 uint8_t fc4f_nvme;
2456 uint8_t scan_state;
2457
2458 unsigned long last_queue_full;
2459 unsigned long last_ramp_up;
2460
2461 uint16_t port_id;
2462
2463 struct nvme_fc_remote_port *nvme_remote_port;
2464
2465 unsigned long retry_delay_timestamp;
2466 struct qla_tgt_sess *tgt_session;
2467 struct ct_sns_desc ct_desc;
2468 enum discovery_state disc_state;
2469 enum discovery_state next_disc_state;
2470 enum login_state fw_login_state;
2471 unsigned long dm_login_expire;
2472 unsigned long plogi_nack_done_deadline;
2473
2474 u32 login_gen, last_login_gen;
2475 u32 rscn_gen, last_rscn_gen;
2476 u32 chip_reset;
2477 struct list_head gnl_entry;
2478 struct work_struct del_work;
2479 u8 iocb[IOCB_SIZE];
2480 u8 current_login_state;
2481 u8 last_login_state;
2482 u16 n2n_link_reset_cnt;
2483 u16 n2n_chip_reset;
2484 } fc_port_t;
2485
2486 #define QLA_FCPORT_SCAN 1
2487 #define QLA_FCPORT_FOUND 2
2488
2489 struct event_arg {
2490 fc_port_t *fcport;
2491 srb_t *sp;
2492 port_id_t id;
2493 u16 data[2], rc;
2494 u8 port_name[WWN_SIZE];
2495 u32 iop[2];
2496 };
2497
2498 #include "qla_mr.h"
2499
2500
2501
2502
2503 #define FCS_UNCONFIGURED 1
2504 #define FCS_DEVICE_DEAD 2
2505 #define FCS_DEVICE_LOST 3
2506 #define FCS_ONLINE 4
2507
2508 extern const char *const port_state_str[5];
2509
2510
2511
2512
2513 #define FCF_FABRIC_DEVICE BIT_0
2514 #define FCF_LOGIN_NEEDED BIT_1
2515 #define FCF_FCP2_DEVICE BIT_2
2516 #define FCF_ASYNC_SENT BIT_3
2517 #define FCF_CONF_COMP_SUPPORTED BIT_4
2518 #define FCF_ASYNC_ACTIVE BIT_5
2519
2520
2521 #define FC_NO_LOOP_ID 0x1000
2522
2523
2524
2525
2526
2527
2528
2529 #define CT_REJECT_RESPONSE 0x8001
2530 #define CT_ACCEPT_RESPONSE 0x8002
2531 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2532 #define CT_REASON_CANNOT_PERFORM 0x09
2533 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2534 #define CT_EXPL_ALREADY_REGISTERED 0x10
2535 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2536 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2537 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2538 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2539 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2540 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2541 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2542 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2543 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2544 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2545 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2546
2547 #define NS_N_PORT_TYPE 0x01
2548 #define NS_NL_PORT_TYPE 0x02
2549 #define NS_NX_PORT_TYPE 0x7F
2550
2551 #define GA_NXT_CMD 0x100
2552 #define GA_NXT_REQ_SIZE (16 + 4)
2553 #define GA_NXT_RSP_SIZE (16 + 620)
2554
2555 #define GPN_FT_CMD 0x172
2556 #define GPN_FT_REQ_SIZE (16 + 4)
2557 #define GNN_FT_CMD 0x173
2558 #define GNN_FT_REQ_SIZE (16 + 4)
2559
2560 #define GID_PT_CMD 0x1A1
2561 #define GID_PT_REQ_SIZE (16 + 4)
2562
2563 #define GPN_ID_CMD 0x112
2564 #define GPN_ID_REQ_SIZE (16 + 4)
2565 #define GPN_ID_RSP_SIZE (16 + 8)
2566
2567 #define GNN_ID_CMD 0x113
2568 #define GNN_ID_REQ_SIZE (16 + 4)
2569 #define GNN_ID_RSP_SIZE (16 + 8)
2570
2571 #define GFT_ID_CMD 0x117
2572 #define GFT_ID_REQ_SIZE (16 + 4)
2573 #define GFT_ID_RSP_SIZE (16 + 32)
2574
2575 #define GID_PN_CMD 0x121
2576 #define GID_PN_REQ_SIZE (16 + 8)
2577 #define GID_PN_RSP_SIZE (16 + 4)
2578
2579 #define RFT_ID_CMD 0x217
2580 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2581 #define RFT_ID_RSP_SIZE 16
2582
2583 #define RFF_ID_CMD 0x21F
2584 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2585 #define RFF_ID_RSP_SIZE 16
2586
2587 #define RNN_ID_CMD 0x213
2588 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2589 #define RNN_ID_RSP_SIZE 16
2590
2591 #define RSNN_NN_CMD 0x239
2592 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2593 #define RSNN_NN_RSP_SIZE 16
2594
2595 #define GFPN_ID_CMD 0x11C
2596 #define GFPN_ID_REQ_SIZE (16 + 4)
2597 #define GFPN_ID_RSP_SIZE (16 + 8)
2598
2599 #define GPSC_CMD 0x127
2600 #define GPSC_REQ_SIZE (16 + 8)
2601 #define GPSC_RSP_SIZE (16 + 2 + 2)
2602
2603 #define GFF_ID_CMD 0x011F
2604 #define GFF_ID_REQ_SIZE (16 + 4)
2605 #define GFF_ID_RSP_SIZE (16 + 128)
2606
2607
2608
2609
2610 #define FDMI_HBA_ATTR_COUNT 9
2611 #define FDMIV2_HBA_ATTR_COUNT 17
2612 #define FDMI_HBA_NODE_NAME 0x1
2613 #define FDMI_HBA_MANUFACTURER 0x2
2614 #define FDMI_HBA_SERIAL_NUMBER 0x3
2615 #define FDMI_HBA_MODEL 0x4
2616 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2617 #define FDMI_HBA_HARDWARE_VERSION 0x6
2618 #define FDMI_HBA_DRIVER_VERSION 0x7
2619 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2620 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2621 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2622 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2623 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2624 #define FDMI_HBA_VENDOR_ID 0xd
2625 #define FDMI_HBA_NUM_PORTS 0xe
2626 #define FDMI_HBA_FABRIC_NAME 0xf
2627 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2628 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0
2629
2630 struct ct_fdmi_hba_attr {
2631 uint16_t type;
2632 uint16_t len;
2633 union {
2634 uint8_t node_name[WWN_SIZE];
2635 uint8_t manufacturer[64];
2636 uint8_t serial_num[32];
2637 uint8_t model[16+1];
2638 uint8_t model_desc[80];
2639 uint8_t hw_version[32];
2640 uint8_t driver_version[32];
2641 uint8_t orom_version[16];
2642 uint8_t fw_version[32];
2643 uint8_t os_version[128];
2644 uint32_t max_ct_len;
2645 } a;
2646 };
2647
2648 struct ct_fdmi_hba_attributes {
2649 uint32_t count;
2650 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2651 };
2652
2653 struct ct_fdmiv2_hba_attr {
2654 uint16_t type;
2655 uint16_t len;
2656 union {
2657 uint8_t node_name[WWN_SIZE];
2658 uint8_t manufacturer[64];
2659 uint8_t serial_num[32];
2660 uint8_t model[16+1];
2661 uint8_t model_desc[80];
2662 uint8_t hw_version[16];
2663 uint8_t driver_version[32];
2664 uint8_t orom_version[16];
2665 uint8_t fw_version[32];
2666 uint8_t os_version[128];
2667 uint32_t max_ct_len;
2668 uint8_t sym_name[256];
2669 uint32_t vendor_id;
2670 uint32_t num_ports;
2671 uint8_t fabric_name[WWN_SIZE];
2672 uint8_t bios_name[32];
2673 uint8_t vendor_identifier[8];
2674 } a;
2675 };
2676
2677 struct ct_fdmiv2_hba_attributes {
2678 uint32_t count;
2679 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT];
2680 };
2681
2682
2683
2684
2685 #define FDMI_PORT_ATTR_COUNT 6
2686 #define FDMIV2_PORT_ATTR_COUNT 16
2687 #define FDMI_PORT_FC4_TYPES 0x1
2688 #define FDMI_PORT_SUPPORT_SPEED 0x2
2689 #define FDMI_PORT_CURRENT_SPEED 0x3
2690 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2691 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2692 #define FDMI_PORT_HOST_NAME 0x6
2693 #define FDMI_PORT_NODE_NAME 0x7
2694 #define FDMI_PORT_NAME 0x8
2695 #define FDMI_PORT_SYM_NAME 0x9
2696 #define FDMI_PORT_TYPE 0xa
2697 #define FDMI_PORT_SUPP_COS 0xb
2698 #define FDMI_PORT_FABRIC_NAME 0xc
2699 #define FDMI_PORT_FC4_TYPE 0xd
2700 #define FDMI_PORT_STATE 0x101
2701 #define FDMI_PORT_COUNT 0x102
2702 #define FDMI_PORT_ID 0x103
2703
2704 #define FDMI_PORT_SPEED_1GB 0x1
2705 #define FDMI_PORT_SPEED_2GB 0x2
2706 #define FDMI_PORT_SPEED_10GB 0x4
2707 #define FDMI_PORT_SPEED_4GB 0x8
2708 #define FDMI_PORT_SPEED_8GB 0x10
2709 #define FDMI_PORT_SPEED_16GB 0x20
2710 #define FDMI_PORT_SPEED_32GB 0x40
2711 #define FDMI_PORT_SPEED_64GB 0x80
2712 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2713
2714 #define FC_CLASS_2 0x04
2715 #define FC_CLASS_3 0x08
2716 #define FC_CLASS_2_3 0x0C
2717
2718 struct ct_fdmiv2_port_attr {
2719 uint16_t type;
2720 uint16_t len;
2721 union {
2722 uint8_t fc4_types[32];
2723 uint32_t sup_speed;
2724 uint32_t cur_speed;
2725 uint32_t max_frame_size;
2726 uint8_t os_dev_name[32];
2727 uint8_t host_name[256];
2728 uint8_t node_name[WWN_SIZE];
2729 uint8_t port_name[WWN_SIZE];
2730 uint8_t port_sym_name[128];
2731 uint32_t port_type;
2732 uint32_t port_supported_cos;
2733 uint8_t fabric_name[WWN_SIZE];
2734 uint8_t port_fc4_type[32];
2735 uint32_t port_state;
2736 uint32_t num_ports;
2737 uint32_t port_id;
2738 } a;
2739 };
2740
2741
2742
2743
2744 struct ct_fdmiv2_port_attributes {
2745 uint32_t count;
2746 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT];
2747 };
2748
2749 struct ct_fdmi_port_attr {
2750 uint16_t type;
2751 uint16_t len;
2752 union {
2753 uint8_t fc4_types[32];
2754 uint32_t sup_speed;
2755 uint32_t cur_speed;
2756 uint32_t max_frame_size;
2757 uint8_t os_dev_name[32];
2758 uint8_t host_name[256];
2759 } a;
2760 };
2761
2762 struct ct_fdmi_port_attributes {
2763 uint32_t count;
2764 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2765 };
2766
2767
2768 #define GRHL_CMD 0x100
2769 #define GHAT_CMD 0x101
2770 #define GRPL_CMD 0x102
2771 #define GPAT_CMD 0x110
2772
2773 #define RHBA_CMD 0x200
2774 #define RHBA_RSP_SIZE 16
2775
2776 #define RHAT_CMD 0x201
2777 #define RPRT_CMD 0x210
2778
2779 #define RPA_CMD 0x211
2780 #define RPA_RSP_SIZE 16
2781
2782 #define DHBA_CMD 0x300
2783 #define DHBA_REQ_SIZE (16 + 8)
2784 #define DHBA_RSP_SIZE 16
2785
2786 #define DHAT_CMD 0x301
2787 #define DPRT_CMD 0x310
2788 #define DPA_CMD 0x311
2789
2790
2791 struct ct_cmd_hdr {
2792 uint8_t revision;
2793 uint8_t in_id[3];
2794 uint8_t gs_type;
2795 uint8_t gs_subtype;
2796 uint8_t options;
2797 uint8_t reserved;
2798 };
2799
2800
2801 struct ct_sns_req {
2802 struct ct_cmd_hdr header;
2803 uint16_t command;
2804 uint16_t max_rsp_size;
2805 uint8_t fragment_id;
2806 uint8_t reserved[3];
2807
2808 union {
2809
2810 struct {
2811 uint8_t reserved;
2812 be_id_t port_id;
2813 } port_id;
2814
2815 struct {
2816 uint8_t reserved;
2817 uint8_t domain;
2818 uint8_t area;
2819 uint8_t port_type;
2820 } gpn_ft;
2821
2822 struct {
2823 uint8_t port_type;
2824 uint8_t domain;
2825 uint8_t area;
2826 uint8_t reserved;
2827 } gid_pt;
2828
2829 struct {
2830 uint8_t reserved;
2831 be_id_t port_id;
2832 uint8_t fc4_types[32];
2833 } rft_id;
2834
2835 struct {
2836 uint8_t reserved;
2837 be_id_t port_id;
2838 uint16_t reserved2;
2839 uint8_t fc4_feature;
2840 uint8_t fc4_type;
2841 } rff_id;
2842
2843 struct {
2844 uint8_t reserved;
2845 be_id_t port_id;
2846 uint8_t node_name[8];
2847 } rnn_id;
2848
2849 struct {
2850 uint8_t node_name[8];
2851 uint8_t name_len;
2852 uint8_t sym_node_name[255];
2853 } rsnn_nn;
2854
2855 struct {
2856 uint8_t hba_identifier[8];
2857 } ghat;
2858
2859 struct {
2860 uint8_t hba_identifier[8];
2861 uint32_t entry_count;
2862 uint8_t port_name[8];
2863 struct ct_fdmi_hba_attributes attrs;
2864 } rhba;
2865
2866 struct {
2867 uint8_t hba_identifier[8];
2868 uint32_t entry_count;
2869 uint8_t port_name[8];
2870 struct ct_fdmiv2_hba_attributes attrs;
2871 } rhba2;
2872
2873 struct {
2874 uint8_t hba_identifier[8];
2875 struct ct_fdmi_hba_attributes attrs;
2876 } rhat;
2877
2878 struct {
2879 uint8_t port_name[8];
2880 struct ct_fdmi_port_attributes attrs;
2881 } rpa;
2882
2883 struct {
2884 uint8_t port_name[8];
2885 struct ct_fdmiv2_port_attributes attrs;
2886 } rpa2;
2887
2888 struct {
2889 uint8_t port_name[8];
2890 } dhba;
2891
2892 struct {
2893 uint8_t port_name[8];
2894 } dhat;
2895
2896 struct {
2897 uint8_t port_name[8];
2898 } dprt;
2899
2900 struct {
2901 uint8_t port_name[8];
2902 } dpa;
2903
2904 struct {
2905 uint8_t port_name[8];
2906 } gpsc;
2907
2908 struct {
2909 uint8_t reserved;
2910 uint8_t port_id[3];
2911 } gff_id;
2912
2913 struct {
2914 uint8_t port_name[8];
2915 } gid_pn;
2916 } req;
2917 };
2918
2919
2920 struct ct_rsp_hdr {
2921 struct ct_cmd_hdr header;
2922 uint16_t response;
2923 uint16_t residual;
2924 uint8_t fragment_id;
2925 uint8_t reason_code;
2926 uint8_t explanation_code;
2927 uint8_t vendor_unique;
2928 };
2929
2930 struct ct_sns_gid_pt_data {
2931 uint8_t control_byte;
2932 be_id_t port_id;
2933 };
2934
2935
2936 struct ct_sns_gpnft_rsp {
2937 struct {
2938 struct ct_cmd_hdr header;
2939 uint16_t response;
2940 uint16_t residual;
2941 uint8_t fragment_id;
2942 uint8_t reason_code;
2943 uint8_t explanation_code;
2944 uint8_t vendor_unique;
2945 };
2946
2947 struct ct_sns_gpn_ft_data {
2948 u8 control_byte;
2949 u8 port_id[3];
2950 u32 reserved;
2951 u8 port_name[8];
2952 } entries[1];
2953 };
2954
2955
2956 struct ct_sns_rsp {
2957 struct ct_rsp_hdr header;
2958
2959 union {
2960 struct {
2961 uint8_t port_type;
2962 be_id_t port_id;
2963 uint8_t port_name[8];
2964 uint8_t sym_port_name_len;
2965 uint8_t sym_port_name[255];
2966 uint8_t node_name[8];
2967 uint8_t sym_node_name_len;
2968 uint8_t sym_node_name[255];
2969 uint8_t init_proc_assoc[8];
2970 uint8_t node_ip_addr[16];
2971 uint8_t class_of_service[4];
2972 uint8_t fc4_types[32];
2973 uint8_t ip_address[16];
2974 uint8_t fabric_port_name[8];
2975 uint8_t reserved;
2976 uint8_t hard_address[3];
2977 } ga_nxt;
2978
2979 struct {
2980
2981 struct ct_sns_gid_pt_data
2982 entries[MAX_FIBRE_DEVICES_MAX];
2983 } gid_pt;
2984
2985 struct {
2986 uint8_t port_name[8];
2987 } gpn_id;
2988
2989 struct {
2990 uint8_t node_name[8];
2991 } gnn_id;
2992
2993 struct {
2994 uint8_t fc4_types[32];
2995 } gft_id;
2996
2997 struct {
2998 uint32_t entry_count;
2999 uint8_t port_name[8];
3000 struct ct_fdmi_hba_attributes attrs;
3001 } ghat;
3002
3003 struct {
3004 uint8_t port_name[8];
3005 } gfpn_id;
3006
3007 struct {
3008 uint16_t speeds;
3009 uint16_t speed;
3010 } gpsc;
3011
3012 #define GFF_FCP_SCSI_OFFSET 7
3013 #define GFF_NVME_OFFSET 23
3014 struct {
3015 uint8_t fc4_features[128];
3016 } gff_id;
3017 struct {
3018 uint8_t reserved;
3019 uint8_t port_id[3];
3020 } gid_pn;
3021 } rsp;
3022 };
3023
3024 struct ct_sns_pkt {
3025 union {
3026 struct ct_sns_req req;
3027 struct ct_sns_rsp rsp;
3028 } p;
3029 };
3030
3031 struct ct_sns_gpnft_pkt {
3032 union {
3033 struct ct_sns_req req;
3034 struct ct_sns_gpnft_rsp rsp;
3035 } p;
3036 };
3037
3038 enum scan_flags_t {
3039 SF_SCANNING = BIT_0,
3040 SF_QUEUED = BIT_1,
3041 };
3042
3043 enum fc4type_t {
3044 FS_FC4TYPE_FCP = BIT_0,
3045 FS_FC4TYPE_NVME = BIT_1,
3046 FS_FCP_IS_N2N = BIT_7,
3047 };
3048
3049 struct fab_scan_rp {
3050 port_id_t id;
3051 enum fc4type_t fc4type;
3052 u8 port_name[8];
3053 u8 node_name[8];
3054 };
3055
3056 struct fab_scan {
3057 struct fab_scan_rp *l;
3058 u32 size;
3059 u16 scan_retry;
3060 #define MAX_SCAN_RETRIES 5
3061 enum scan_flags_t scan_flags;
3062 struct delayed_work scan_work;
3063 };
3064
3065
3066
3067
3068 #define RFT_ID_SNS_SCMD_LEN 22
3069 #define RFT_ID_SNS_CMD_SIZE 60
3070 #define RFT_ID_SNS_DATA_SIZE 16
3071
3072 #define RNN_ID_SNS_SCMD_LEN 10
3073 #define RNN_ID_SNS_CMD_SIZE 36
3074 #define RNN_ID_SNS_DATA_SIZE 16
3075
3076 #define GA_NXT_SNS_SCMD_LEN 6
3077 #define GA_NXT_SNS_CMD_SIZE 28
3078 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
3079
3080 #define GID_PT_SNS_SCMD_LEN 6
3081 #define GID_PT_SNS_CMD_SIZE 28
3082
3083
3084
3085
3086 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
3087
3088 #define GPN_ID_SNS_SCMD_LEN 6
3089 #define GPN_ID_SNS_CMD_SIZE 28
3090 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
3091
3092 #define GNN_ID_SNS_SCMD_LEN 6
3093 #define GNN_ID_SNS_CMD_SIZE 28
3094 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
3095
3096 struct sns_cmd_pkt {
3097 union {
3098 struct {
3099 uint16_t buffer_length;
3100 uint16_t reserved_1;
3101 __le64 buffer_address __packed;
3102 uint16_t subcommand_length;
3103 uint16_t reserved_2;
3104 uint16_t subcommand;
3105 uint16_t size;
3106 uint32_t reserved_3;
3107 uint8_t param[36];
3108 } cmd;
3109
3110 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3111 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3112 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3113 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3114 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3115 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3116 } p;
3117 };
3118
3119 struct fw_blob {
3120 char *name;
3121 uint32_t segs[4];
3122 const struct firmware *fw;
3123 };
3124
3125
3126 struct gid_list_info {
3127 uint8_t al_pa;
3128 uint8_t area;
3129 uint8_t domain;
3130 uint8_t loop_id_2100;
3131 uint16_t loop_id;
3132 uint16_t reserved_1;
3133 };
3134
3135
3136 typedef struct vport_info {
3137 uint8_t port_name[WWN_SIZE];
3138 uint8_t node_name[WWN_SIZE];
3139 int vp_id;
3140 uint16_t loop_id;
3141 unsigned long host_no;
3142 uint8_t port_id[3];
3143 int loop_state;
3144 } vport_info_t;
3145
3146 typedef struct vport_params {
3147 uint8_t port_name[WWN_SIZE];
3148 uint8_t node_name[WWN_SIZE];
3149 uint32_t options;
3150 #define VP_OPTS_RETRY_ENABLE BIT_0
3151 #define VP_OPTS_VP_DISABLE BIT_1
3152 } vport_params_t;
3153
3154
3155 #define VP_RET_CODE_OK 0
3156 #define VP_RET_CODE_FATAL 1
3157 #define VP_RET_CODE_WRONG_ID 2
3158 #define VP_RET_CODE_WWPN 3
3159 #define VP_RET_CODE_RESOURCES 4
3160 #define VP_RET_CODE_NO_MEM 5
3161 #define VP_RET_CODE_NOT_FOUND 6
3162
3163 struct qla_hw_data;
3164 struct rsp_que;
3165
3166
3167
3168 struct isp_operations {
3169
3170 int (*pci_config) (struct scsi_qla_host *);
3171 int (*reset_chip)(struct scsi_qla_host *);
3172 int (*chip_diag) (struct scsi_qla_host *);
3173 void (*config_rings) (struct scsi_qla_host *);
3174 int (*reset_adapter)(struct scsi_qla_host *);
3175 int (*nvram_config) (struct scsi_qla_host *);
3176 void (*update_fw_options) (struct scsi_qla_host *);
3177 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3178
3179 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t);
3180 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3181
3182 irq_handler_t intr_handler;
3183 void (*enable_intrs) (struct qla_hw_data *);
3184 void (*disable_intrs) (struct qla_hw_data *);
3185
3186 int (*abort_command) (srb_t *);
3187 int (*target_reset) (struct fc_port *, uint64_t, int);
3188 int (*lun_reset) (struct fc_port *, uint64_t, int);
3189 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3190 uint8_t, uint8_t, uint16_t *, uint8_t);
3191 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3192 uint8_t, uint8_t);
3193
3194 uint16_t (*calc_req_entries) (uint16_t);
3195 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3196 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3197 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3198 uint32_t);
3199
3200 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
3201 uint32_t, uint32_t);
3202 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
3203 uint32_t);
3204
3205 void (*fw_dump) (struct scsi_qla_host *, int);
3206
3207 int (*beacon_on) (struct scsi_qla_host *);
3208 int (*beacon_off) (struct scsi_qla_host *);
3209 void (*beacon_blink) (struct scsi_qla_host *);
3210
3211 void *(*read_optrom)(struct scsi_qla_host *, void *,
3212 uint32_t, uint32_t);
3213 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
3214 uint32_t);
3215
3216 int (*get_flash_version) (struct scsi_qla_host *, void *);
3217 int (*start_scsi) (srb_t *);
3218 int (*start_scsi_mq) (srb_t *);
3219 int (*abort_isp) (struct scsi_qla_host *);
3220 int (*iospace_config)(struct qla_hw_data *);
3221 int (*initialize_adapter)(struct scsi_qla_host *);
3222 };
3223
3224
3225
3226 #define QLA_MSIX_CHIP_REV_24XX 3
3227 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3228 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3229
3230 #define QLA_BASE_VECTORS 2
3231 #define QLA_MSIX_RSP_Q 0x01
3232 #define QLA_ATIO_VECTOR 0x02
3233 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3234
3235 #define QLA_MIDX_DEFAULT 0
3236 #define QLA_MIDX_RSP_Q 1
3237 #define QLA_PCI_MSIX_CONTROL 0xa2
3238 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
3239
3240 struct scsi_qla_host;
3241
3242
3243 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1
3244
3245 struct qla_msix_entry {
3246 int have_irq;
3247 int in_use;
3248 uint32_t vector;
3249 uint16_t entry;
3250 char name[30];
3251 void *handle;
3252 int cpuid;
3253 };
3254
3255 #define WATCH_INTERVAL 1
3256
3257
3258 enum qla_work_type {
3259 QLA_EVT_AEN,
3260 QLA_EVT_IDC_ACK,
3261 QLA_EVT_ASYNC_LOGIN,
3262 QLA_EVT_ASYNC_LOGOUT,
3263 QLA_EVT_ASYNC_LOGOUT_DONE,
3264 QLA_EVT_ASYNC_ADISC,
3265 QLA_EVT_UEVENT,
3266 QLA_EVT_AENFX,
3267 QLA_EVT_GPNID,
3268 QLA_EVT_UNMAP,
3269 QLA_EVT_NEW_SESS,
3270 QLA_EVT_GPDB,
3271 QLA_EVT_PRLI,
3272 QLA_EVT_GPSC,
3273 QLA_EVT_GNL,
3274 QLA_EVT_NACK,
3275 QLA_EVT_RELOGIN,
3276 QLA_EVT_ASYNC_PRLO,
3277 QLA_EVT_ASYNC_PRLO_DONE,
3278 QLA_EVT_GPNFT,
3279 QLA_EVT_GPNFT_DONE,
3280 QLA_EVT_GNNFT_DONE,
3281 QLA_EVT_GNNID,
3282 QLA_EVT_GFPNID,
3283 QLA_EVT_SP_RETRY,
3284 QLA_EVT_IIDMA,
3285 QLA_EVT_ELS_PLOGI,
3286 };
3287
3288
3289 struct qla_work_evt {
3290 struct list_head list;
3291 enum qla_work_type type;
3292 u32 flags;
3293 #define QLA_EVT_FLAG_FREE 0x1
3294
3295 union {
3296 struct {
3297 enum fc_host_event_code code;
3298 u32 data;
3299 } aen;
3300 struct {
3301 #define QLA_IDC_ACK_REGS 7
3302 uint16_t mb[QLA_IDC_ACK_REGS];
3303 } idc_ack;
3304 struct {
3305 struct fc_port *fcport;
3306 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
3307 u16 data[2];
3308 } logio;
3309 struct {
3310 u32 code;
3311 #define QLA_UEVENT_CODE_FW_DUMP 0
3312 } uevent;
3313 struct {
3314 uint32_t evtcode;
3315 uint32_t mbx[8];
3316 uint32_t count;
3317 } aenfx;
3318 struct {
3319 srb_t *sp;
3320 } iosb;
3321 struct {
3322 port_id_t id;
3323 } gpnid;
3324 struct {
3325 port_id_t id;
3326 u8 port_name[8];
3327 u8 node_name[8];
3328 void *pla;
3329 u8 fc4_type;
3330 } new_sess;
3331 struct {
3332 fc_port_t *fcport;
3333 u8 opt;
3334 } fcport;
3335 struct {
3336 fc_port_t *fcport;
3337 u8 iocb[IOCB_SIZE];
3338 int type;
3339 } nack;
3340 struct {
3341 u8 fc4_type;
3342 srb_t *sp;
3343 } gpnft;
3344 } u;
3345 };
3346
3347 struct qla_chip_state_84xx {
3348 struct list_head list;
3349 struct kref kref;
3350
3351 void *bus;
3352 spinlock_t access_lock;
3353 struct mutex fw_update_mutex;
3354 uint32_t fw_update;
3355 uint32_t op_fw_version;
3356 uint32_t op_fw_size;
3357 uint32_t op_fw_seq_size;
3358 uint32_t diag_fw_version;
3359 uint32_t gold_fw_version;
3360 };
3361
3362 struct qla_dif_statistics {
3363 uint64_t dif_input_bytes;
3364 uint64_t dif_output_bytes;
3365 uint64_t dif_input_requests;
3366 uint64_t dif_output_requests;
3367 uint32_t dif_guard_err;
3368 uint32_t dif_ref_tag_err;
3369 uint32_t dif_app_tag_err;
3370 };
3371
3372 struct qla_statistics {
3373 uint32_t total_isp_aborts;
3374 uint64_t input_bytes;
3375 uint64_t output_bytes;
3376 uint64_t input_requests;
3377 uint64_t output_requests;
3378 uint32_t control_requests;
3379
3380 uint64_t jiffies_at_last_reset;
3381 uint32_t stat_max_pend_cmds;
3382 uint32_t stat_max_qfull_cmds_alloc;
3383 uint32_t stat_max_qfull_cmds_dropped;
3384
3385 struct qla_dif_statistics qla_dif_stats;
3386 };
3387
3388 struct bidi_statistics {
3389 unsigned long long io_count;
3390 unsigned long long transfer_bytes;
3391 };
3392
3393 struct qla_tc_param {
3394 struct scsi_qla_host *vha;
3395 uint32_t blk_sz;
3396 uint32_t bufflen;
3397 struct scatterlist *sg;
3398 struct scatterlist *prot_sg;
3399 struct crc_context *ctx;
3400 uint8_t *ctx_dsd_alloced;
3401 };
3402
3403
3404 #define MBC_INITIALIZE_MULTIQ 0x1f
3405 #define QLA_QUE_PAGE 0X1000
3406 #define QLA_MQ_SIZE 32
3407 #define QLA_MAX_QUEUES 256
3408 #define ISP_QUE_REG(ha, id) \
3409 ((ha->mqenable || IS_QLA83XX(ha) || \
3410 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
3411 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3412 ((void __iomem *)ha->iobase))
3413 #define QLA_REQ_QUE_ID(tag) \
3414 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3415 #define QLA_DEFAULT_QUE_QOS 5
3416 #define QLA_PRECONFIG_VPORTS 32
3417 #define QLA_MAX_VPORTS_QLA24XX 128
3418 #define QLA_MAX_VPORTS_QLA25XX 256
3419
3420 struct qla_tgt_counters {
3421 uint64_t qla_core_sbt_cmd;
3422 uint64_t core_qla_que_buf;
3423 uint64_t qla_core_ret_ctio;
3424 uint64_t core_qla_snd_status;
3425 uint64_t qla_core_ret_sta_ctio;
3426 uint64_t core_qla_free_cmd;
3427 uint64_t num_q_full_sent;
3428 uint64_t num_alloc_iocb_failed;
3429 uint64_t num_term_xchg_sent;
3430 };
3431
3432 struct qla_qpair;
3433
3434
3435 struct rsp_que {
3436 dma_addr_t dma;
3437 response_t *ring;
3438 response_t *ring_ptr;
3439 uint32_t __iomem *rsp_q_in;
3440 uint32_t __iomem *rsp_q_out;
3441 uint16_t ring_index;
3442 uint16_t out_ptr;
3443 uint16_t *in_ptr;
3444 uint16_t length;
3445 uint16_t options;
3446 uint16_t rid;
3447 uint16_t id;
3448 uint16_t vp_idx;
3449 struct qla_hw_data *hw;
3450 struct qla_msix_entry *msix;
3451 struct req_que *req;
3452 srb_t *status_srb;
3453 struct qla_qpair *qpair;
3454
3455 dma_addr_t dma_fx00;
3456 response_t *ring_fx00;
3457 uint16_t length_fx00;
3458 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3459 };
3460
3461
3462 struct req_que {
3463 dma_addr_t dma;
3464 request_t *ring;
3465 request_t *ring_ptr;
3466 uint32_t __iomem *req_q_in;
3467 uint32_t __iomem *req_q_out;
3468 uint16_t ring_index;
3469 uint16_t in_ptr;
3470 uint16_t *out_ptr;
3471 uint16_t cnt;
3472 uint16_t length;
3473 uint16_t options;
3474 uint16_t rid;
3475 uint16_t id;
3476 uint16_t qos;
3477 uint16_t vp_idx;
3478 struct rsp_que *rsp;
3479 srb_t **outstanding_cmds;
3480 uint32_t current_outstanding_cmd;
3481 uint16_t num_outstanding_cmds;
3482 int max_q_depth;
3483
3484 dma_addr_t dma_fx00;
3485 request_t *ring_fx00;
3486 uint16_t length_fx00;
3487 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3488 };
3489
3490
3491 struct qla_qpair {
3492 spinlock_t qp_lock;
3493 atomic_t ref_count;
3494 uint32_t lun_cnt;
3495
3496
3497
3498
3499 spinlock_t *qp_lock_ptr;
3500 struct scsi_qla_host *vha;
3501 u32 chip_reset;
3502
3503
3504
3505
3506
3507
3508 uint32_t online:1;
3509
3510 uint32_t difdix_supported:1;
3511 uint32_t delete_in_progress:1;
3512 uint32_t fw_started:1;
3513 uint32_t enable_class_2:1;
3514 uint32_t enable_explicit_conf:1;
3515 uint32_t use_shadow_reg:1;
3516
3517 uint16_t id;
3518 uint16_t vp_idx;
3519 mempool_t *srb_mempool;
3520
3521 struct pci_dev *pdev;
3522 void (*reqq_start_iocbs)(struct qla_qpair *);
3523
3524
3525 struct req_que *req;
3526 struct rsp_que *rsp;
3527 struct atio_que *atio;
3528 struct qla_msix_entry *msix;
3529 struct qla_hw_data *hw;
3530 struct work_struct q_work;
3531 struct list_head qp_list_elem;
3532 struct list_head hints_list;
3533 uint16_t cpuid;
3534 uint16_t retry_term_cnt;
3535 uint32_t retry_term_exchg_addr;
3536 uint64_t retry_term_jiff;
3537 struct qla_tgt_counters tgt_counters;
3538 };
3539
3540
3541 struct qlfc_fw {
3542 void *fw_buf;
3543 dma_addr_t fw_dma;
3544 uint32_t len;
3545 };
3546
3547 struct scsi_qlt_host {
3548 void *target_lport_ptr;
3549 struct mutex tgt_mutex;
3550 struct mutex tgt_host_action_mutex;
3551 struct qla_tgt *qla_tgt;
3552 };
3553
3554 struct qlt_hw_data {
3555
3556 uint32_t node_name_set:1;
3557
3558 dma_addr_t atio_dma;
3559 struct atio *atio_ring;
3560 struct atio *atio_ring_ptr;
3561 uint16_t atio_ring_index;
3562 uint16_t atio_q_length;
3563 uint32_t __iomem *atio_q_in;
3564 uint32_t __iomem *atio_q_out;
3565
3566 struct qla_tgt_func_tmpl *tgt_ops;
3567 struct qla_tgt_vp_map *tgt_vp_map;
3568
3569 int saved_set;
3570 uint16_t saved_exchange_count;
3571 uint32_t saved_firmware_options_1;
3572 uint32_t saved_firmware_options_2;
3573 uint32_t saved_firmware_options_3;
3574 uint8_t saved_firmware_options[2];
3575 uint8_t saved_add_firmware_options[2];
3576
3577 uint8_t tgt_node_name[WWN_SIZE];
3578
3579 struct dentry *dfs_tgt_sess;
3580 struct dentry *dfs_tgt_port_database;
3581 struct dentry *dfs_naqp;
3582
3583 struct list_head q_full_list;
3584 uint32_t num_pend_cmds;
3585 uint32_t num_qfull_cmds_alloc;
3586 uint32_t num_qfull_cmds_dropped;
3587 spinlock_t q_full_lock;
3588 uint32_t leak_exchg_thresh_hold;
3589 spinlock_t sess_lock;
3590 int num_act_qpairs;
3591 #define DEFAULT_NAQP 2
3592 spinlock_t atio_lock ____cacheline_aligned;
3593 struct btree_head32 host_map;
3594 };
3595
3596 #define MAX_QFULL_CMDS_ALLOC 8192
3597 #define Q_FULL_THRESH_HOLD_PERCENT 90
3598 #define Q_FULL_THRESH_HOLD(ha) \
3599 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3600
3601 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75
3602
3603
3604
3605
3606 struct qla_hw_data {
3607 struct pci_dev *pdev;
3608
3609 #define SRB_MIN_REQ 128
3610 mempool_t *srb_mempool;
3611
3612 volatile struct {
3613 uint32_t mbox_int :1;
3614 uint32_t mbox_busy :1;
3615 uint32_t disable_risc_code_load :1;
3616 uint32_t enable_64bit_addressing :1;
3617 uint32_t enable_lip_reset :1;
3618 uint32_t enable_target_reset :1;
3619 uint32_t enable_lip_full_login :1;
3620 uint32_t enable_led_scheme :1;
3621
3622 uint32_t msi_enabled :1;
3623 uint32_t msix_enabled :1;
3624 uint32_t disable_serdes :1;
3625 uint32_t gpsc_supported :1;
3626 uint32_t npiv_supported :1;
3627 uint32_t pci_channel_io_perm_failure :1;
3628 uint32_t fce_enabled :1;
3629 uint32_t fac_supported :1;
3630
3631 uint32_t chip_reset_done :1;
3632 uint32_t running_gold_fw :1;
3633 uint32_t eeh_busy :1;
3634 uint32_t disable_msix_handshake :1;
3635 uint32_t fcp_prio_enabled :1;
3636 uint32_t isp82xx_fw_hung:1;
3637 uint32_t nic_core_hung:1;
3638
3639 uint32_t quiesce_owner:1;
3640 uint32_t nic_core_reset_hdlr_active:1;
3641 uint32_t nic_core_reset_owner:1;
3642 uint32_t isp82xx_no_md_cap:1;
3643 uint32_t host_shutting_down:1;
3644 uint32_t idc_compl_status:1;
3645 uint32_t mr_reset_hdlr_active:1;
3646 uint32_t mr_intr_valid:1;
3647
3648 uint32_t dport_enabled:1;
3649 uint32_t fawwpn_enabled:1;
3650 uint32_t exlogins_enabled:1;
3651 uint32_t exchoffld_enabled:1;
3652
3653 uint32_t lip_ae:1;
3654 uint32_t n2n_ae:1;
3655 uint32_t fw_started:1;
3656 uint32_t fw_init_done:1;
3657
3658 uint32_t detected_lr_sfp:1;
3659 uint32_t using_lr_setting:1;
3660 uint32_t rida_fmt2:1;
3661 uint32_t purge_mbox:1;
3662 uint32_t n2n_bigger:1;
3663 uint32_t secure_adapter:1;
3664 uint32_t secure_fw:1;
3665 } flags;
3666
3667 uint16_t max_exchg;
3668 uint16_t long_range_distance;
3669 #define LR_DISTANCE_5K 1
3670 #define LR_DISTANCE_10K 0
3671
3672
3673
3674
3675
3676
3677
3678
3679 spinlock_t hardware_lock ____cacheline_aligned;
3680 int bars;
3681 int mem_only;
3682 device_reg_t *iobase;
3683 resource_size_t pio_address;
3684
3685 #define MIN_IOBASE_LEN 0x100
3686 dma_addr_t bar0_hdl;
3687
3688 void __iomem *cregbase;
3689 dma_addr_t bar2_hdl;
3690 #define BAR0_LEN_FX00 (1024 * 1024)
3691 #define BAR2_LEN_FX00 (128 * 1024)
3692
3693 uint32_t rqstq_intr_code;
3694 uint32_t mbx_intr_code;
3695 uint32_t req_que_len;
3696 uint32_t rsp_que_len;
3697 uint32_t req_que_off;
3698 uint32_t rsp_que_off;
3699
3700
3701 device_reg_t *mqiobase;
3702 device_reg_t *msixbase;
3703 uint16_t msix_count;
3704 uint8_t mqenable;
3705 struct req_que **req_q_map;
3706 struct rsp_que **rsp_q_map;
3707 struct qla_qpair **queue_pair_map;
3708 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3709 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3710 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3711 / sizeof(unsigned long)];
3712 uint8_t max_req_queues;
3713 uint8_t max_rsp_queues;
3714 uint8_t max_qpairs;
3715 uint8_t num_qpairs;
3716 struct qla_qpair *base_qpair;
3717 struct qla_npiv_entry *npiv_info;
3718 uint16_t nvram_npiv_size;
3719
3720 uint16_t switch_cap;
3721 #define FLOGI_SEQ_DEL BIT_8
3722 #define FLOGI_MID_SUPPORT BIT_10
3723 #define FLOGI_VSAN_SUPPORT BIT_12
3724 #define FLOGI_SP_SUPPORT BIT_13
3725
3726 uint8_t port_no;
3727 uint8_t exch_starvation;
3728
3729
3730 uint8_t loop_down_abort_time;
3731 atomic_t loop_down_timer;
3732 uint8_t link_down_timeout;
3733 uint16_t max_loop_id;
3734 uint16_t max_fibre_devices;
3735
3736 uint16_t fb_rev;
3737 uint16_t min_external_loopid;
3738
3739 #define PORT_SPEED_UNKNOWN 0xFFFF
3740 #define PORT_SPEED_1GB 0x00
3741 #define PORT_SPEED_2GB 0x01
3742 #define PORT_SPEED_AUTO 0x02
3743 #define PORT_SPEED_4GB 0x03
3744 #define PORT_SPEED_8GB 0x04
3745 #define PORT_SPEED_16GB 0x05
3746 #define PORT_SPEED_32GB 0x06
3747 #define PORT_SPEED_64GB 0x07
3748 #define PORT_SPEED_10GB 0x13
3749 uint16_t link_data_rate;
3750 uint16_t set_data_rate;
3751
3752 uint8_t current_topology;
3753 uint8_t prev_topology;
3754 #define ISP_CFG_NL 1
3755 #define ISP_CFG_N 2
3756 #define ISP_CFG_FL 4
3757 #define ISP_CFG_F 8
3758
3759 uint8_t operating_mode;
3760 #define LOOP 0
3761 #define P2P 1
3762 #define LOOP_P2P 2
3763 #define P2P_LOOP 3
3764 uint8_t interrupts_on;
3765 uint32_t isp_abort_cnt;
3766 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3767 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3768 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3769 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3770 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3771 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3772 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3773 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3774 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
3775 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
3776 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
3777 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
3778 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
3779
3780 uint32_t isp_type;
3781 #define DT_ISP2100 BIT_0
3782 #define DT_ISP2200 BIT_1
3783 #define DT_ISP2300 BIT_2
3784 #define DT_ISP2312 BIT_3
3785 #define DT_ISP2322 BIT_4
3786 #define DT_ISP6312 BIT_5
3787 #define DT_ISP6322 BIT_6
3788 #define DT_ISP2422 BIT_7
3789 #define DT_ISP2432 BIT_8
3790 #define DT_ISP5422 BIT_9
3791 #define DT_ISP5432 BIT_10
3792 #define DT_ISP2532 BIT_11
3793 #define DT_ISP8432 BIT_12
3794 #define DT_ISP8001 BIT_13
3795 #define DT_ISP8021 BIT_14
3796 #define DT_ISP2031 BIT_15
3797 #define DT_ISP8031 BIT_16
3798 #define DT_ISPFX00 BIT_17
3799 #define DT_ISP8044 BIT_18
3800 #define DT_ISP2071 BIT_19
3801 #define DT_ISP2271 BIT_20
3802 #define DT_ISP2261 BIT_21
3803 #define DT_ISP2061 BIT_22
3804 #define DT_ISP2081 BIT_23
3805 #define DT_ISP2089 BIT_24
3806 #define DT_ISP2281 BIT_25
3807 #define DT_ISP2289 BIT_26
3808 #define DT_ISP_LAST (DT_ISP2289 << 1)
3809
3810 uint32_t device_type;
3811 #define DT_T10_PI BIT_25
3812 #define DT_IIDMA BIT_26
3813 #define DT_FWI2 BIT_27
3814 #define DT_ZIO_SUPPORTED BIT_28
3815 #define DT_OEM_001 BIT_29
3816 #define DT_ISP2200A BIT_30
3817 #define DT_EXTENDED_IDS BIT_31
3818
3819 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
3820 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
3821 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
3822 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
3823 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
3824 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
3825 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
3826 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
3827 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
3828 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
3829 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
3830 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
3831 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
3832 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3833 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
3834 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
3835 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
3836 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
3837 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
3838 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
3839 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
3840 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3841 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3842 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
3843 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
3844 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
3845
3846 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
3847 IS_QLA6312(ha) || IS_QLA6322(ha))
3848 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
3849 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
3850 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
3851 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
3852 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
3853 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
3854 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
3855 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
3856 IS_QLA84XX(ha))
3857 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
3858 IS_QLA8031(ha) || IS_QLA8044(ha))
3859 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
3860 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
3861 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
3862 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
3863 IS_QLA8044(ha) || IS_QLA27XX(ha) || \
3864 IS_QLA28XX(ha))
3865 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3866 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3867 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
3868 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3869 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3870 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3871 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3872 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
3873
3874 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
3875 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3876 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3877 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3878 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3879 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3880 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3881 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
3882 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3883 #define IS_BIDI_CAPABLE(ha) \
3884 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3885
3886 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3887 ((ha)->fw_attributes_ext[0] & BIT_0))
3888 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3889 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3890 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3891 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3892 IS_QLA28XX(ha))
3893 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3894 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
3895 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3896 IS_QLA28XX(ha))
3897 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3898 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
3899 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3900 IS_QLA28XX(ha))
3901 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3902 IS_QLA28XX(ha))
3903 #define IS_EXCHG_OFFLD_CAPABLE(ha) \
3904 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3905 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
3906 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3907 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3908 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
3909 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3910
3911
3912 uint8_t serial0;
3913 uint8_t serial1;
3914 uint8_t serial2;
3915
3916
3917 #define MAX_NVRAM_SIZE 4096
3918 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2)
3919 uint16_t nvram_size;
3920 uint16_t nvram_base;
3921 void *nvram;
3922 uint16_t vpd_size;
3923 uint16_t vpd_base;
3924 void *vpd;
3925
3926 uint16_t loop_reset_delay;
3927 uint8_t retry_count;
3928 uint8_t login_timeout;
3929 uint16_t r_a_tov;
3930 int port_down_retry_count;
3931 uint8_t mbx_count;
3932 uint8_t aen_mbx_count;
3933 atomic_t num_pend_mbx_stage1;
3934 atomic_t num_pend_mbx_stage2;
3935 atomic_t num_pend_mbx_stage3;
3936 uint16_t frame_payload_size;
3937
3938 uint32_t login_retry_count;
3939
3940 ms_iocb_entry_t *ms_iocb;
3941 dma_addr_t ms_iocb_dma;
3942 struct ct_sns_pkt *ct_sns;
3943 dma_addr_t ct_sns_dma;
3944
3945 struct sns_cmd_pkt *sns_cmd;
3946 dma_addr_t sns_cmd_dma;
3947
3948 #define SFP_DEV_SIZE 512
3949 #define SFP_BLOCK_SIZE 64
3950 void *sfp_data;
3951 dma_addr_t sfp_data_dma;
3952
3953 void *flt;
3954 dma_addr_t flt_dma;
3955
3956 #define XGMAC_DATA_SIZE 4096
3957 void *xgmac_data;
3958 dma_addr_t xgmac_data_dma;
3959
3960 #define DCBX_TLV_DATA_SIZE 4096
3961 void *dcbx_tlv;
3962 dma_addr_t dcbx_tlv_dma;
3963
3964 struct task_struct *dpc_thread;
3965 uint8_t dpc_active;
3966
3967 dma_addr_t gid_list_dma;
3968 struct gid_list_info *gid_list;
3969 int gid_list_info_size;
3970
3971
3972 #define DMA_POOL_SIZE 256
3973 struct dma_pool *s_dma_pool;
3974
3975 dma_addr_t init_cb_dma;
3976 init_cb_t *init_cb;
3977 int init_cb_size;
3978 dma_addr_t ex_init_cb_dma;
3979 struct ex_init_cb_81xx *ex_init_cb;
3980
3981 void *async_pd;
3982 dma_addr_t async_pd_dma;
3983
3984 #define ENABLE_EXTENDED_LOGIN BIT_7
3985
3986
3987 void *exlogin_buf;
3988 dma_addr_t exlogin_buf_dma;
3989 int exlogin_size;
3990
3991 #define ENABLE_EXCHANGE_OFFLD BIT_2
3992
3993
3994 void *exchoffld_buf;
3995 dma_addr_t exchoffld_buf_dma;
3996 int exchoffld_size;
3997 int exchoffld_count;
3998
3999
4000 struct els_plogi_payload plogi_els_payld;
4001
4002 void *swl;
4003
4004
4005 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
4006 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
4007 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
4008
4009 mbx_cmd_t *mcp;
4010 struct mbx_cmd_32 *mcp32;
4011
4012 unsigned long mbx_cmd_flags;
4013 #define MBX_INTERRUPT 1
4014 #define MBX_INTR_WAIT 2
4015 #define MBX_UPDATE_FLASH_ACTIVE 3
4016
4017 struct mutex vport_lock;
4018 spinlock_t vport_slock;
4019 struct mutex mq_lock;
4020 struct completion mbx_cmd_comp;
4021 struct completion mbx_intr_comp;
4022 struct completion dcbx_comp;
4023 struct completion lb_portup_comp;
4024
4025 #define DCBX_COMP_TIMEOUT 20
4026 #define LB_PORTUP_COMP_TIMEOUT 10
4027
4028 int notify_dcbx_comp;
4029 int notify_lb_portup_comp;
4030 struct mutex selflogin_lock;
4031
4032
4033 uint16_t fw_major_version;
4034 uint16_t fw_minor_version;
4035 uint16_t fw_subminor_version;
4036 uint16_t fw_attributes;
4037 uint16_t fw_attributes_h;
4038 #define FW_ATTR_H_NVME_FBURST BIT_1
4039 #define FW_ATTR_H_NVME BIT_10
4040 #define FW_ATTR_H_NVME_UPDATED BIT_14
4041
4042 uint16_t fw_attributes_ext[2];
4043 uint32_t fw_memory_size;
4044 uint32_t fw_transfer_size;
4045 uint32_t fw_srisc_address;
4046 #define RISC_START_ADDRESS_2100 0x1000
4047 #define RISC_START_ADDRESS_2300 0x800
4048 #define RISC_START_ADDRESS_2400 0x100000
4049
4050 uint16_t orig_fw_tgt_xcb_count;
4051 uint16_t cur_fw_tgt_xcb_count;
4052 uint16_t orig_fw_xcb_count;
4053 uint16_t cur_fw_xcb_count;
4054 uint16_t orig_fw_iocb_count;
4055 uint16_t cur_fw_iocb_count;
4056 uint16_t fw_max_fcf_count;
4057
4058 uint32_t fw_shared_ram_start;
4059 uint32_t fw_shared_ram_end;
4060 uint32_t fw_ddr_ram_start;
4061 uint32_t fw_ddr_ram_end;
4062
4063 uint16_t fw_options[16];
4064 uint8_t fw_seriallink_options[4];
4065 uint16_t fw_seriallink_options24[4];
4066
4067 uint8_t serdes_version[3];
4068 uint8_t mpi_version[3];
4069 uint32_t mpi_capabilities;
4070 uint8_t phy_version[3];
4071 uint8_t pep_version[3];
4072
4073
4074 struct fwdt {
4075 void *template;
4076 ulong length;
4077 ulong dump_size;
4078 } fwdt[2];
4079 struct qla2xxx_fw_dump *fw_dump;
4080 uint32_t fw_dump_len;
4081 u32 fw_dump_alloc_len;
4082 bool fw_dumped;
4083 bool fw_dump_mpi;
4084 unsigned long fw_dump_cap_flags;
4085 #define RISC_PAUSE_CMPL 0
4086 #define DMA_SHUTDOWN_CMPL 1
4087 #define ISP_RESET_CMPL 2
4088 #define RISC_RDY_AFT_RESET 3
4089 #define RISC_SRAM_DUMP_CMPL 4
4090 #define RISC_EXT_MEM_DUMP_CMPL 5
4091 #define ISP_MBX_RDY 6
4092 #define ISP_SOFT_RESET_CMPL 7
4093 int fw_dump_reading;
4094 int prev_minidump_failed;
4095 dma_addr_t eft_dma;
4096 void *eft;
4097
4098 #define MCTP_DUMP_SIZE 0x086064
4099 dma_addr_t mctp_dump_dma;
4100 void *mctp_dump;
4101 int mctp_dumped;
4102 int mctp_dump_reading;
4103 uint32_t chain_offset;
4104 struct dentry *dfs_dir;
4105 struct dentry *dfs_fce;
4106 struct dentry *dfs_tgt_counters;
4107 struct dentry *dfs_fw_resource_cnt;
4108
4109 dma_addr_t fce_dma;
4110 void *fce;
4111 uint32_t fce_bufs;
4112 uint16_t fce_mb[8];
4113 uint64_t fce_wr, fce_rd;
4114 struct mutex fce_mutex;
4115
4116 uint32_t pci_attr;
4117 uint16_t chip_revision;
4118
4119 uint16_t product_id[4];
4120
4121 uint8_t model_number[16+1];
4122 char model_desc[80];
4123 uint8_t adapter_id[16+1];
4124
4125
4126 char *optrom_buffer;
4127 uint32_t optrom_size;
4128 int optrom_state;
4129 #define QLA_SWAITING 0
4130 #define QLA_SREADING 1
4131 #define QLA_SWRITING 2
4132 uint32_t optrom_region_start;
4133 uint32_t optrom_region_size;
4134 struct mutex optrom_mutex;
4135
4136
4137 #define ROM_CODE_TYPE_BIOS 0
4138 #define ROM_CODE_TYPE_FCODE 1
4139 #define ROM_CODE_TYPE_EFI 3
4140 uint8_t bios_revision[2];
4141 uint8_t efi_revision[2];
4142 uint8_t fcode_revision[16];
4143 uint32_t fw_revision[4];
4144
4145 uint32_t gold_fw_version[4];
4146
4147
4148 uint32_t flash_conf_off;
4149 uint32_t flash_data_off;
4150 uint32_t nvram_conf_off;
4151 uint32_t nvram_data_off;
4152
4153 uint32_t fdt_wrt_disable;
4154 uint32_t fdt_wrt_enable;
4155 uint32_t fdt_erase_cmd;
4156 uint32_t fdt_block_size;
4157 uint32_t fdt_unprotect_sec_cmd;
4158 uint32_t fdt_protect_sec_cmd;
4159 uint32_t fdt_wrt_sts_reg_cmd;
4160
4161 struct {
4162 uint32_t flt_region_flt;
4163 uint32_t flt_region_fdt;
4164 uint32_t flt_region_boot;
4165 uint32_t flt_region_boot_sec;
4166 uint32_t flt_region_fw;
4167 uint32_t flt_region_fw_sec;
4168 uint32_t flt_region_vpd_nvram;
4169 uint32_t flt_region_vpd_nvram_sec;
4170 uint32_t flt_region_vpd;
4171 uint32_t flt_region_vpd_sec;
4172 uint32_t flt_region_nvram;
4173 uint32_t flt_region_nvram_sec;
4174 uint32_t flt_region_npiv_conf;
4175 uint32_t flt_region_gold_fw;
4176 uint32_t flt_region_fcp_prio;
4177 uint32_t flt_region_bootload;
4178 uint32_t flt_region_img_status_pri;
4179 uint32_t flt_region_img_status_sec;
4180 uint32_t flt_region_aux_img_status_pri;
4181 uint32_t flt_region_aux_img_status_sec;
4182 };
4183 uint8_t active_image;
4184
4185
4186 uint16_t beacon_blink_led;
4187 uint8_t beacon_color_state;
4188 #define QLA_LED_GRN_ON 0x01
4189 #define QLA_LED_YLW_ON 0x02
4190 #define QLA_LED_ABR_ON 0x04
4191 #define QLA_LED_ALL_ON 0x07
4192
4193 uint16_t zio_mode;
4194 uint16_t zio_timer;
4195
4196 struct qla_msix_entry *msix_entries;
4197
4198 struct list_head vp_list;
4199 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4200 sizeof(unsigned long)];
4201 uint16_t num_vhosts;
4202 uint16_t num_vsans;
4203 uint16_t max_npiv_vports;
4204 int cur_vport_count;
4205
4206 struct qla_chip_state_84xx *cs84xx;
4207 struct isp_operations *isp_ops;
4208 struct workqueue_struct *wq;
4209 struct qlfc_fw fw_buf;
4210
4211
4212 struct qla_fcp_prio_cfg *fcp_prio_cfg;
4213
4214 struct dma_pool *dl_dma_pool;
4215 #define DSD_LIST_DMA_POOL_SIZE 512
4216
4217 struct dma_pool *fcp_cmnd_dma_pool;
4218 mempool_t *ctx_mempool;
4219 #define FCP_CMND_DMA_POOL_SIZE 512
4220
4221 void __iomem *nx_pcibase;
4222 void __iomem *nxdb_rd_ptr;
4223 void __iomem *nxdb_wr_ptr;
4224
4225 uint32_t crb_win;
4226 uint32_t curr_window;
4227 uint32_t ddr_mn_window;
4228 unsigned long mn_win_crb;
4229 unsigned long ms_win_crb;
4230 int qdr_sn_window;
4231 uint32_t fcoe_dev_init_timeout;
4232 uint32_t fcoe_reset_timeout;
4233 rwlock_t hw_lock;
4234 uint16_t portnum;
4235 int link_width;
4236 struct fw_blob *hablob;
4237 struct qla82xx_legacy_intr_set nx_legacy_intr;
4238
4239 uint16_t gbl_dsd_inuse;
4240 uint16_t gbl_dsd_avail;
4241 struct list_head gbl_dsd_list;
4242 #define NUM_DSD_CHAIN 4096
4243
4244 uint8_t fw_type;
4245 __le32 file_prd_off;
4246
4247 uint32_t md_template_size;
4248 void *md_tmplt_hdr;
4249 dma_addr_t md_tmplt_hdr_dma;
4250 void *md_dump;
4251 uint32_t md_dump_size;
4252
4253 void *loop_id_map;
4254
4255
4256 uint32_t idc_audit_ts;
4257 uint32_t idc_extend_tmo;
4258
4259
4260 struct workqueue_struct *dpc_lp_wq;
4261 struct work_struct idc_aen;
4262
4263 struct workqueue_struct *dpc_hp_wq;
4264 struct work_struct nic_core_reset;
4265 struct work_struct idc_state_handler;
4266 struct work_struct nic_core_unrecoverable;
4267 struct work_struct board_disable;
4268
4269 struct mr_data_fx00 mr;
4270 uint32_t chip_reset;
4271
4272 struct qlt_hw_data tgt;
4273 int allow_cna_fw_dump;
4274 uint32_t fw_ability_mask;
4275 uint16_t min_supported_speed;
4276 uint16_t max_supported_speed;
4277
4278
4279 struct dma_pool *dif_bundl_pool;
4280 #define DIF_BUNDLING_DMA_POOL_SIZE 1024
4281 struct {
4282 struct {
4283 struct list_head head;
4284 uint count;
4285 } good;
4286 struct {
4287 struct list_head head;
4288 uint count;
4289 } unusable;
4290 } pool;
4291
4292 unsigned long long dif_bundle_crossed_pages;
4293 unsigned long long dif_bundle_reads;
4294 unsigned long long dif_bundle_writes;
4295 unsigned long long dif_bundle_kallocs;
4296 unsigned long long dif_bundle_dma_allocs;
4297
4298 atomic_t nvme_active_aen_cnt;
4299 uint16_t nvme_last_rptd_aen;
4300
4301 atomic_t zio_threshold;
4302 uint16_t last_zio_threshold;
4303
4304 #define DEFAULT_ZIO_THRESHOLD 5
4305 };
4306
4307 struct active_regions {
4308 uint8_t global;
4309 struct {
4310 uint8_t board_config;
4311 uint8_t vpd_nvram;
4312 uint8_t npiv_config_0_1;
4313 uint8_t npiv_config_2_3;
4314 } aux;
4315 };
4316
4317 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4318 #define FW_ABILITY_MAX_SPEED_16G 0x0
4319 #define FW_ABILITY_MAX_SPEED_32G 0x1
4320 #define FW_ABILITY_MAX_SPEED(ha) \
4321 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4322
4323 #define QLA_GET_DATA_RATE 0
4324 #define QLA_SET_DATA_RATE_NOLR 1
4325 #define QLA_SET_DATA_RATE_LR 2
4326
4327
4328
4329
4330 typedef struct scsi_qla_host {
4331 struct list_head list;
4332 struct list_head vp_fcports;
4333 struct list_head work_list;
4334 spinlock_t work_lock;
4335 struct work_struct iocb_work;
4336
4337
4338 struct Scsi_Host *host;
4339 unsigned long host_no;
4340 uint8_t host_str[16];
4341
4342 volatile struct {
4343 uint32_t init_done :1;
4344 uint32_t online :1;
4345 uint32_t reset_active :1;
4346
4347 uint32_t management_server_logged_in :1;
4348 uint32_t process_response_queue :1;
4349 uint32_t difdix_supported:1;
4350 uint32_t delete_progress:1;
4351
4352 uint32_t fw_tgt_reported:1;
4353 uint32_t bbcr_enable:1;
4354 uint32_t qpairs_available:1;
4355 uint32_t qpairs_req_created:1;
4356 uint32_t qpairs_rsp_created:1;
4357 uint32_t nvme_enabled:1;
4358 uint32_t nvme_first_burst:1;
4359 } flags;
4360
4361 atomic_t loop_state;
4362 #define LOOP_TIMEOUT 1
4363 #define LOOP_DOWN 2
4364 #define LOOP_UP 3
4365 #define LOOP_UPDATE 4
4366 #define LOOP_READY 5
4367 #define LOOP_DEAD 6
4368
4369 unsigned long relogin_jif;
4370 unsigned long dpc_flags;
4371 #define RESET_MARKER_NEEDED 0
4372 #define RESET_ACTIVE 1
4373 #define ISP_ABORT_NEEDED 2
4374 #define ABORT_ISP_ACTIVE 3
4375 #define LOOP_RESYNC_NEEDED 4
4376 #define LOOP_RESYNC_ACTIVE 5
4377 #define LOCAL_LOOP_UPDATE 6
4378 #define RSCN_UPDATE 7
4379 #define RELOGIN_NEEDED 8
4380 #define REGISTER_FC4_NEEDED 9
4381 #define ISP_ABORT_RETRY 10
4382 #define BEACON_BLINK_NEEDED 11
4383 #define REGISTER_FDMI_NEEDED 12
4384 #define FCPORT_UPDATE_NEEDED 13
4385 #define VP_DPC_NEEDED 14
4386 #define UNLOADING 15
4387 #define NPIV_CONFIG_NEEDED 16
4388 #define ISP_UNRECOVERABLE 17
4389 #define FCOE_CTX_RESET_NEEDED 18
4390 #define MPI_RESET_NEEDED 19
4391 #define ISP_QUIESCE_NEEDED 20
4392 #define N2N_LINK_RESET 21
4393 #define PORT_UPDATE_NEEDED 22
4394 #define FX00_RESET_RECOVERY 23
4395 #define FX00_TARGET_SCAN 24
4396 #define FX00_CRITEMP_RECOVERY 25
4397 #define FX00_HOST_INFO_RESEND 26
4398 #define QPAIR_ONLINE_CHECK_NEEDED 27
4399 #define SET_NVME_ZIO_THRESHOLD_NEEDED 28
4400 #define DETECT_SFP_CHANGE 29
4401 #define N2N_LOGIN_NEEDED 30
4402 #define IOCB_WORK_ACTIVE 31
4403 #define SET_ZIO_THRESHOLD_NEEDED 32
4404 #define ISP_ABORT_TO_ROM 33
4405 #define VPORT_DELETE 34
4406
4407 unsigned long pci_flags;
4408 #define PFLG_DISCONNECTED 0
4409 #define PFLG_DRIVER_REMOVING 1
4410 #define PFLG_DRIVER_PROBING 2
4411
4412 uint32_t device_flags;
4413 #define SWITCH_FOUND BIT_0
4414 #define DFLG_NO_CABLE BIT_1
4415 #define DFLG_DEV_FAILED BIT_5
4416
4417
4418 uint16_t loop_id;
4419 uint16_t self_login_loop_id;
4420
4421
4422 fc_port_t bidir_fcport;
4423
4424
4425
4426
4427 port_id_t d_id;
4428 uint8_t marker_needed;
4429 uint16_t mgmt_svr_loop_id;
4430
4431
4432
4433
4434 uint8_t loop_down_abort_time;
4435 atomic_t loop_down_timer;
4436 uint8_t link_down_timeout;
4437
4438 uint32_t timer_active;
4439 struct timer_list timer;
4440
4441 uint8_t node_name[WWN_SIZE];
4442 uint8_t port_name[WWN_SIZE];
4443 uint8_t fabric_node_name[WWN_SIZE];
4444
4445 struct nvme_fc_local_port *nvme_local_port;
4446 struct completion nvme_del_done;
4447
4448 uint16_t fcoe_vlan_id;
4449 uint16_t fcoe_fcf_idx;
4450 uint8_t fcoe_vn_port_mac[6];
4451
4452
4453 struct list_head qla_cmd_list;
4454 struct list_head qla_sess_op_cmd_list;
4455 struct list_head unknown_atio_list;
4456 spinlock_t cmd_list_lock;
4457 struct delayed_work unknown_atio_work;
4458
4459
4460 atomic_t generation_tick;
4461
4462 int total_fcport_update_gen;
4463
4464 struct list_head logo_list;
4465
4466 struct list_head plogi_ack_list;
4467
4468 struct list_head qp_list;
4469
4470 uint32_t vp_abort_cnt;
4471
4472 struct fc_vport *fc_vport;
4473 uint16_t vp_idx;
4474 struct qla_qpair *qpair;
4475
4476 unsigned long vp_flags;
4477 #define VP_IDX_ACQUIRED 0
4478 #define VP_CREATE_NEEDED 1
4479 #define VP_BIND_NEEDED 2
4480 #define VP_DELETE_NEEDED 3
4481 #define VP_SCR_NEEDED 4
4482 #define VP_CONFIG_OK 5
4483 atomic_t vp_state;
4484 #define VP_OFFLINE 0
4485 #define VP_ACTIVE 1
4486 #define VP_FAILED 2
4487
4488 uint16_t vp_err_state;
4489 uint16_t vp_prev_err_state;
4490 #define VP_ERR_UNKWN 0
4491 #define VP_ERR_PORTDWN 1
4492 #define VP_ERR_FAB_UNSUPPORTED 2
4493 #define VP_ERR_FAB_NORESOURCES 3
4494 #define VP_ERR_FAB_LOGOUT 4
4495 #define VP_ERR_ADAP_NORESOURCES 5
4496 struct qla_hw_data *hw;
4497 struct scsi_qlt_host vha_tgt;
4498 struct req_que *req;
4499 int fw_heartbeat_counter;
4500 int seconds_since_last_heartbeat;
4501 struct fc_host_statistics fc_host_stat;
4502 struct qla_statistics qla_stats;
4503 struct bidi_statistics bidi_stats;
4504 atomic_t vref_count;
4505 struct qla8044_reset_template reset_tmplt;
4506 uint16_t bbcr;
4507
4508 uint16_t u_ql2xexchoffld;
4509 uint16_t u_ql2xiniexchg;
4510 uint16_t qlini_mode;
4511 uint16_t ql2xexchoffld;
4512 uint16_t ql2xiniexchg;
4513
4514 struct name_list_extended gnl;
4515
4516 int fcport_count;
4517 wait_queue_head_t fcport_waitQ;
4518 wait_queue_head_t vref_waitq;
4519 uint8_t min_supported_speed;
4520 uint8_t n2n_node_name[WWN_SIZE];
4521 uint8_t n2n_port_name[WWN_SIZE];
4522 uint16_t n2n_id;
4523 struct list_head gpnid_list;
4524 struct fab_scan scan;
4525
4526 unsigned int irq_offset;
4527 } scsi_qla_host_t;
4528
4529 struct qla27xx_image_status {
4530 uint8_t image_status_mask;
4531 uint16_t generation;
4532 uint8_t ver_major;
4533 uint8_t ver_minor;
4534 uint8_t bitmap;
4535 uint8_t reserved[2];
4536 uint32_t checksum;
4537 uint32_t signature;
4538 } __packed;
4539
4540
4541 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
4542 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
4543 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
4544 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
4545
4546 #define SET_VP_IDX 1
4547 #define SET_AL_PA 2
4548 #define RESET_VP_IDX 3
4549 #define RESET_AL_PA 4
4550 struct qla_tgt_vp_map {
4551 uint8_t idx;
4552 scsi_qla_host_t *vha;
4553 };
4554
4555 struct qla2_sgx {
4556 dma_addr_t dma_addr;
4557 uint32_t dma_len;
4558
4559 uint32_t tot_bytes;
4560 struct scatterlist *cur_sg;
4561
4562
4563 uint32_t bytes_consumed;
4564 uint32_t num_bytes;
4565 uint32_t tot_partial;
4566
4567
4568 uint32_t num_sg;
4569 srb_t *sp;
4570 };
4571
4572 #define QLA_FW_STARTED(_ha) { \
4573 int i; \
4574 _ha->flags.fw_started = 1; \
4575 _ha->base_qpair->fw_started = 1; \
4576 for (i = 0; i < _ha->max_qpairs; i++) { \
4577 if (_ha->queue_pair_map[i]) \
4578 _ha->queue_pair_map[i]->fw_started = 1; \
4579 } \
4580 }
4581
4582 #define QLA_FW_STOPPED(_ha) { \
4583 int i; \
4584 _ha->flags.fw_started = 0; \
4585 _ha->base_qpair->fw_started = 0; \
4586 for (i = 0; i < _ha->max_qpairs; i++) { \
4587 if (_ha->queue_pair_map[i]) \
4588 _ha->queue_pair_map[i]->fw_started = 0; \
4589 } \
4590 }
4591
4592
4593 #define SFUB_CHECKSUM_SIZE 4
4594
4595 struct secure_flash_update_block {
4596 uint32_t block_info;
4597 uint32_t signature_lo;
4598 uint32_t signature_hi;
4599 uint32_t signature_upper[0x3e];
4600 };
4601
4602 struct secure_flash_update_block_pk {
4603 uint32_t block_info;
4604 uint32_t signature_lo;
4605 uint32_t signature_hi;
4606 uint32_t signature_upper[0x3e];
4607 uint32_t public_key[0x41];
4608 };
4609
4610
4611
4612
4613 #define LOOP_TRANSITION(ha) \
4614 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4615 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4616 atomic_read(&ha->loop_state) == LOOP_DOWN)
4617
4618 #define STATE_TRANSITION(ha) \
4619 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4620 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4621
4622 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4623 atomic_inc(&__vha->vref_count); \
4624 mb(); \
4625 if (__vha->flags.delete_progress) { \
4626 atomic_dec(&__vha->vref_count); \
4627 wake_up(&__vha->vref_waitq); \
4628 __bail = 1; \
4629 } else { \
4630 __bail = 0; \
4631 } \
4632 } while (0)
4633
4634 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4635 atomic_dec(&__vha->vref_count); \
4636 wake_up(&__vha->vref_waitq); \
4637 } while (0) \
4638
4639 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4640 atomic_inc(&__qpair->ref_count); \
4641 mb(); \
4642 if (__qpair->delete_in_progress) { \
4643 atomic_dec(&__qpair->ref_count); \
4644 __bail = 1; \
4645 } else { \
4646 __bail = 0; \
4647 } \
4648 } while (0)
4649
4650 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
4651 atomic_dec(&__qpair->ref_count); \
4652
4653
4654 #define QLA_ENA_CONF(_ha) {\
4655 int i;\
4656 _ha->base_qpair->enable_explicit_conf = 1; \
4657 for (i = 0; i < _ha->max_qpairs; i++) { \
4658 if (_ha->queue_pair_map[i]) \
4659 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
4660 } \
4661 }
4662
4663 #define QLA_DIS_CONF(_ha) {\
4664 int i;\
4665 _ha->base_qpair->enable_explicit_conf = 0; \
4666 for (i = 0; i < _ha->max_qpairs; i++) { \
4667 if (_ha->queue_pair_map[i]) \
4668 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
4669 } \
4670 }
4671
4672
4673
4674
4675 #define MBS_MASK 0x3fff
4676
4677 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
4678 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
4679 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
4680 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
4681 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
4682 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
4683 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
4684 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
4685 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
4686 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
4687
4688 #define QLA_FUNCTION_TIMEOUT 0x100
4689 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
4690 #define QLA_FUNCTION_FAILED 0x102
4691 #define QLA_MEMORY_ALLOC_FAILED 0x103
4692 #define QLA_LOCK_TIMEOUT 0x104
4693 #define QLA_ABORTED 0x105
4694 #define QLA_SUSPENDED 0x106
4695 #define QLA_BUSY 0x107
4696 #define QLA_ALREADY_REGISTERED 0x109
4697 #define QLA_OS_TIMER_EXPIRED 0x10a
4698
4699 #define NVRAM_DELAY() udelay(10)
4700
4701
4702
4703
4704 #define OPTROM_SIZE_2300 0x20000
4705 #define OPTROM_SIZE_2322 0x100000
4706 #define OPTROM_SIZE_24XX 0x100000
4707 #define OPTROM_SIZE_25XX 0x200000
4708 #define OPTROM_SIZE_81XX 0x400000
4709 #define OPTROM_SIZE_82XX 0x800000
4710 #define OPTROM_SIZE_83XX 0x1000000
4711 #define OPTROM_SIZE_28XX 0x2000000
4712
4713 #define OPTROM_BURST_SIZE 0x1000
4714 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
4715
4716 #define QLA_DSDS_PER_IOCB 37
4717
4718 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
4719
4720 #define QLA_SG_ALL 1024
4721
4722 enum nexus_wait_type {
4723 WAIT_HOST = 0,
4724 WAIT_TARGET,
4725 WAIT_LUN,
4726 };
4727
4728
4729 struct sff_8247_a0 {
4730 u8 txid;
4731 u8 ext_txid;
4732 u8 connector;
4733
4734 u8 eth_infi_cc3;
4735 u8 sonet_cc4[2];
4736 u8 eth_cc6;
4737
4738 #define FC_LL_VL BIT_7
4739 #define FC_LL_S BIT_6
4740 #define FC_LL_I BIT_5
4741 #define FC_LL_L BIT_4
4742 #define FC_LL_M BIT_3
4743 #define FC_LL_SA BIT_2
4744 #define FC_LL_LC BIT_1
4745 #define FC_LL_EL BIT_0
4746 u8 fc_ll_cc7;
4747
4748 #define FC_TEC_EL BIT_7
4749 #define FC_TEC_SN BIT_6
4750 #define FC_TEC_SL BIT_5
4751 #define FC_TEC_LL BIT_4
4752 #define FC_TEC_ACT BIT_3
4753 #define FC_TEC_PAS BIT_2
4754 u8 fc_tec_cc8;
4755
4756 #define FC_MED_TW BIT_7
4757 #define FC_MED_TP BIT_6
4758 #define FC_MED_MI BIT_5
4759 #define FC_MED_TV BIT_4
4760 #define FC_MED_M6 BIT_3
4761 #define FC_MED_M5 BIT_2
4762 #define FC_MED_SM BIT_0
4763 u8 fc_med_cc9;
4764
4765 #define FC_SP_12 BIT_7
4766 #define FC_SP_8 BIT_6
4767 #define FC_SP_16 BIT_5
4768 #define FC_SP_4 BIT_4
4769 #define FC_SP_32 BIT_3
4770 #define FC_SP_2 BIT_2
4771 #define FC_SP_1 BIT_0
4772 u8 fc_sp_cc10;
4773 u8 encode;
4774 u8 bitrate;
4775 u8 rate_id;
4776 u8 length_km;
4777 u8 length_100m;
4778 u8 length_50um_10m;
4779 u8 length_62um_10m;
4780 u8 length_om4_10m;
4781 u8 length_om3_10m;
4782 #define SFF_VEN_NAME_LEN 16
4783 u8 vendor_name[SFF_VEN_NAME_LEN];
4784 u8 tx_compat;
4785 u8 vendor_oui[3];
4786 #define SFF_PART_NAME_LEN 16
4787 u8 vendor_pn[SFF_PART_NAME_LEN];
4788 u8 vendor_rev[4];
4789 u8 wavelength[2];
4790 u8 resv;
4791 u8 cc_base;
4792 u8 options[2];
4793 u8 br_max;
4794 u8 br_min;
4795 u8 vendor_sn[16];
4796 u8 date_code[8];
4797 u8 diag;
4798 u8 enh_options;
4799 u8 sff_revision;
4800 u8 cc_ext;
4801 u8 vendor_specific[32];
4802 u8 resv2[128];
4803 };
4804
4805 #define AUTO_DETECT_SFP_SUPPORT(_vha)\
4806 (ql2xautodetectsfp && !_vha->vp_idx && \
4807 (IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\
4808 IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw) || \
4809 IS_QLA28XX(_vha->hw)))
4810
4811 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
4812
4813 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
4814 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
4815
4816 #define SAVE_TOPO(_ha) { \
4817 if (_ha->current_topology) \
4818 _ha->prev_topology = _ha->current_topology; \
4819 }
4820
4821 #define N2N_TOPO(ha) \
4822 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
4823 ha->current_topology == ISP_CFG_N || \
4824 !ha->current_topology)
4825
4826 #define PRLI_PHASE(_cls) \
4827 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP))
4828
4829 #include "qla_target.h"
4830 #include "qla_gbl.h"
4831 #include "qla_dbg.h"
4832 #include "qla_inline.h"
4833 #endif