This source file includes following definitions.
- ipr_trc_hook
- ipr_lock_and_done
- ipr_reinit_ipr_cmnd
- ipr_init_ipr_cmnd
- __ipr_get_free_ipr_cmnd
- ipr_get_free_ipr_cmnd
- ipr_mask_and_clear_interrupts
- ipr_save_pcix_cmd_reg
- ipr_set_pcix_cmd_reg
- __ipr_sata_eh_done
- ipr_sata_eh_done
- __ipr_scsi_eh_done
- ipr_scsi_eh_done
- ipr_fail_all_ops
- ipr_send_command
- ipr_do_req
- ipr_internal_cmd_done
- ipr_init_ioadl
- ipr_send_blocking_cmd
- ipr_get_hrrq_index
- ipr_send_hcam
- ipr_update_ata_class
- ipr_init_res_entry
- ipr_is_same_device
- __ipr_format_res_path
- ipr_format_res_path
- ipr_update_res_entry
- ipr_clear_res_target
- ipr_handle_config_change
- ipr_process_ccn
- strip_and_pad_whitespace
- ipr_log_vpd_compact
- ipr_log_vpd
- ipr_log_ext_vpd_compact
- ipr_log_ext_vpd
- ipr_log_enhanced_cache_error
- ipr_log_cache_error
- ipr_log_enhanced_config_error
- ipr_log_sis64_config_error
- ipr_log_config_error
- ipr_log_enhanced_array_error
- ipr_log_array_error
- ipr_log_hex_data
- ipr_log_enhanced_dual_ioa_error
- ipr_log_dual_ioa_error
- ipr_log_fabric_path
- ipr_log64_fabric_path
- ipr_log_path_elem
- ipr_log64_path_elem
- ipr_log_fabric_error
- ipr_log_sis64_array_error
- ipr_log_sis64_fabric_error
- ipr_log_sis64_service_required_error
- ipr_log_generic_error
- ipr_log_sis64_device_error
- ipr_get_error
- ipr_handle_log_data
- ipr_get_free_hostrcb
- ipr_process_error
- ipr_timeout
- ipr_oper_timeout
- ipr_find_ses_entry
- ipr_get_max_scsi_speed
- ipr_wait_iodbg_ack
- ipr_get_sis64_dump_data_section
- ipr_get_ldump_data_section
- ipr_sdt_copy
- ipr_init_dump_entry_hdr
- ipr_dump_ioa_type_data
- ipr_dump_version_data
- ipr_dump_trace_data
- ipr_dump_location_data
- ipr_get_ioa_dump
- ipr_release_dump
- ipr_add_remove_thread
- ipr_worker_thread
- ipr_read_trace
- ipr_show_fw_version
- ipr_show_log_level
- ipr_store_log_level
- ipr_store_diagnostics
- ipr_show_adapter_state
- ipr_store_adapter_state
- ipr_store_reset_adapter
- ipr_show_iopoll_weight
- ipr_store_iopoll_weight
- ipr_alloc_ucode_buffer
- ipr_free_ucode_buffer
- ipr_copy_ucode_buffer
- ipr_build_ucode_ioadl64
- ipr_build_ucode_ioadl
- ipr_update_ioa_ucode
- ipr_store_update_fw
- ipr_show_fw_type
- ipr_read_async_err_log
- ipr_next_async_err_log
- ipr_read_dump
- ipr_alloc_dump
- ipr_free_dump
- ipr_write_dump
- ipr_free_dump
- ipr_change_queue_depth
- ipr_show_adapter_handle
- ipr_show_resource_path
- ipr_show_device_id
- ipr_show_resource_type
- ipr_show_raw_mode
- ipr_store_raw_mode
- ipr_biosparam
- ipr_find_starget
- ipr_target_alloc
- ipr_target_destroy
- ipr_find_sdev
- ipr_slave_destroy
- ipr_slave_configure
- ipr_ata_slave_alloc
- ipr_slave_alloc
- ipr_match_lun
- ipr_cmnd_is_free
- ipr_match_res
- ipr_wait_for_ops
- ipr_eh_host_reset
- ipr_device_reset
- ipr_sata_reset
- __ipr_eh_dev_reset
- ipr_eh_dev_reset
- ipr_bus_reset_done
- ipr_abort_timeout
- ipr_cancel_op
- ipr_scan_finished
- ipr_eh_abort
- ipr_handle_other_interrupt
- ipr_isr_eh
- ipr_process_hrrq
- ipr_iopoll
- ipr_isr
- ipr_isr_mhrrq
- ipr_build_ioadl64
- ipr_build_ioadl
- __ipr_erp_done
- ipr_erp_done
- ipr_reinit_ipr_cmnd_for_erp
- __ipr_erp_request_sense
- ipr_erp_request_sense
- ipr_erp_cancel_all
- ipr_dump_ioasa
- ipr_gen_sense
- ipr_get_autosense
- ipr_erp_start
- ipr_scsi_done
- ipr_queuecommand
- ipr_ioctl
- ipr_ioa_info
- ipr_ata_phy_reset
- ipr_ata_post_internal
- ipr_copy_sata_tf
- ipr_sata_done
- ipr_build_ata_ioadl64
- ipr_build_ata_ioadl
- ipr_qc_defer
- ipr_qc_issue
- ipr_qc_fill_rtf
- ipr_invalid_adapter
- ipr_ioa_bringdown_done
- ipr_ioa_reset_done
- ipr_set_sup_dev_dflt
- ipr_set_supported_devs
- ipr_get_mode_page
- ipr_check_term_power
- ipr_scsi_bus_speed_limit
- ipr_modify_ioafp_mode_page_28
- ipr_build_mode_select
- ipr_ioafp_mode_select_page28
- ipr_build_mode_sense
- ipr_reset_cmd_failed
- ipr_reset_mode_sense_failed
- ipr_ioafp_mode_sense_page28
- ipr_ioafp_mode_select_page24
- ipr_reset_mode_sense_page24_failed
- ipr_ioafp_mode_sense_page24
- ipr_init_res_table
- ipr_ioafp_query_ioa_cfg
- ipr_ioa_service_action_failed
- ipr_build_ioa_service_action
- ipr_ioafp_set_caching_parameters
- ipr_ioafp_inquiry
- ipr_inquiry_page_supported
- ipr_ioafp_pageC4_inquiry
- ipr_ioafp_cap_inquiry
- ipr_ioafp_page3_inquiry
- ipr_ioafp_page0_inquiry
- ipr_ioafp_std_inquiry
- ipr_ioafp_identify_hrrq
- ipr_reset_timer_done
- ipr_reset_start_timer
- ipr_init_ioa_mem
- ipr_reset_next_stage
- ipr_reset_enable_ioa
- ipr_reset_wait_for_dump
- ipr_unit_check_no_data
- ipr_get_unit_check_buffer
- ipr_reset_get_unit_check_job
- ipr_dump_mailbox_wait
- ipr_reset_restore_cfg_space
- ipr_reset_bist_done
- ipr_reset_start_bist
- ipr_reset_slot_reset_done
- ipr_reset_reset_work
- ipr_reset_slot_reset
- ipr_reset_block_config_access_wait
- ipr_reset_block_config_access
- ipr_reset_allowed
- ipr_reset_wait_to_start_bist
- ipr_reset_alert
- ipr_reset_quiesce_done
- ipr_reset_cancel_hcam_done
- ipr_reset_cancel_hcam
- ipr_reset_ucode_download_done
- ipr_reset_ucode_download
- ipr_reset_shutdown_ioa
- ipr_reset_ioa_job
- _ipr_initiate_ioa_reset
- ipr_initiate_ioa_reset
- ipr_reset_freeze
- ipr_pci_mmio_enabled
- ipr_pci_frozen
- ipr_pci_slot_reset
- ipr_pci_perm_failure
- ipr_pci_error_detected
- ipr_probe_ioa_part2
- ipr_free_cmd_blks
- ipr_free_mem
- ipr_free_irqs
- ipr_free_all_resources
- ipr_alloc_cmd_blks
- ipr_alloc_mem
- ipr_initialize_bus_attr
- ipr_init_regs
- ipr_init_ioa_cfg
- ipr_get_chip_info
- ipr_wait_for_pci_err_recovery
- name_msi_vectors
- ipr_request_other_msi_irqs
- ipr_test_intr
- ipr_test_msi
- ipr_probe_ioa
- ipr_initiate_ioa_bringdown
- __ipr_remove
- ipr_remove
- ipr_probe
- ipr_shutdown
- ipr_halt_done
- ipr_halt
- ipr_init
- ipr_exit
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43 #include <linux/fs.h>
44 #include <linux/init.h>
45 #include <linux/types.h>
46 #include <linux/errno.h>
47 #include <linux/kernel.h>
48 #include <linux/slab.h>
49 #include <linux/vmalloc.h>
50 #include <linux/ioport.h>
51 #include <linux/delay.h>
52 #include <linux/pci.h>
53 #include <linux/wait.h>
54 #include <linux/spinlock.h>
55 #include <linux/sched.h>
56 #include <linux/interrupt.h>
57 #include <linux/blkdev.h>
58 #include <linux/firmware.h>
59 #include <linux/module.h>
60 #include <linux/moduleparam.h>
61 #include <linux/libata.h>
62 #include <linux/hdreg.h>
63 #include <linux/reboot.h>
64 #include <linux/stringify.h>
65 #include <asm/io.h>
66 #include <asm/irq.h>
67 #include <asm/processor.h>
68 #include <scsi/scsi.h>
69 #include <scsi/scsi_host.h>
70 #include <scsi/scsi_tcq.h>
71 #include <scsi/scsi_eh.h>
72 #include <scsi/scsi_cmnd.h>
73 #include "ipr.h"
74
75
76
77
78 static LIST_HEAD(ipr_ioa_head);
79 static unsigned int ipr_log_level = IPR_DEFAULT_LOG_LEVEL;
80 static unsigned int ipr_max_speed = 1;
81 static int ipr_testmode = 0;
82 static unsigned int ipr_fastfail = 0;
83 static unsigned int ipr_transop_timeout = 0;
84 static unsigned int ipr_debug = 0;
85 static unsigned int ipr_max_devs = IPR_DEFAULT_SIS64_DEVS;
86 static unsigned int ipr_dual_ioa_raid = 1;
87 static unsigned int ipr_number_of_msix = 16;
88 static unsigned int ipr_fast_reboot;
89 static DEFINE_SPINLOCK(ipr_driver_lock);
90
91
92 static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
93 {
94 .mailbox = 0x0042C,
95 .max_cmds = 100,
96 .cache_line_size = 0x20,
97 .clear_isr = 1,
98 .iopoll_weight = 0,
99 {
100 .set_interrupt_mask_reg = 0x0022C,
101 .clr_interrupt_mask_reg = 0x00230,
102 .clr_interrupt_mask_reg32 = 0x00230,
103 .sense_interrupt_mask_reg = 0x0022C,
104 .sense_interrupt_mask_reg32 = 0x0022C,
105 .clr_interrupt_reg = 0x00228,
106 .clr_interrupt_reg32 = 0x00228,
107 .sense_interrupt_reg = 0x00224,
108 .sense_interrupt_reg32 = 0x00224,
109 .ioarrin_reg = 0x00404,
110 .sense_uproc_interrupt_reg = 0x00214,
111 .sense_uproc_interrupt_reg32 = 0x00214,
112 .set_uproc_interrupt_reg = 0x00214,
113 .set_uproc_interrupt_reg32 = 0x00214,
114 .clr_uproc_interrupt_reg = 0x00218,
115 .clr_uproc_interrupt_reg32 = 0x00218
116 }
117 },
118 {
119 .mailbox = 0x0052C,
120 .max_cmds = 100,
121 .cache_line_size = 0x20,
122 .clear_isr = 1,
123 .iopoll_weight = 0,
124 {
125 .set_interrupt_mask_reg = 0x00288,
126 .clr_interrupt_mask_reg = 0x0028C,
127 .clr_interrupt_mask_reg32 = 0x0028C,
128 .sense_interrupt_mask_reg = 0x00288,
129 .sense_interrupt_mask_reg32 = 0x00288,
130 .clr_interrupt_reg = 0x00284,
131 .clr_interrupt_reg32 = 0x00284,
132 .sense_interrupt_reg = 0x00280,
133 .sense_interrupt_reg32 = 0x00280,
134 .ioarrin_reg = 0x00504,
135 .sense_uproc_interrupt_reg = 0x00290,
136 .sense_uproc_interrupt_reg32 = 0x00290,
137 .set_uproc_interrupt_reg = 0x00290,
138 .set_uproc_interrupt_reg32 = 0x00290,
139 .clr_uproc_interrupt_reg = 0x00294,
140 .clr_uproc_interrupt_reg32 = 0x00294
141 }
142 },
143 {
144 .mailbox = 0x00044,
145 .max_cmds = 1000,
146 .cache_line_size = 0x20,
147 .clear_isr = 0,
148 .iopoll_weight = 64,
149 {
150 .set_interrupt_mask_reg = 0x00010,
151 .clr_interrupt_mask_reg = 0x00018,
152 .clr_interrupt_mask_reg32 = 0x0001C,
153 .sense_interrupt_mask_reg = 0x00010,
154 .sense_interrupt_mask_reg32 = 0x00014,
155 .clr_interrupt_reg = 0x00008,
156 .clr_interrupt_reg32 = 0x0000C,
157 .sense_interrupt_reg = 0x00000,
158 .sense_interrupt_reg32 = 0x00004,
159 .ioarrin_reg = 0x00070,
160 .sense_uproc_interrupt_reg = 0x00020,
161 .sense_uproc_interrupt_reg32 = 0x00024,
162 .set_uproc_interrupt_reg = 0x00020,
163 .set_uproc_interrupt_reg32 = 0x00024,
164 .clr_uproc_interrupt_reg = 0x00028,
165 .clr_uproc_interrupt_reg32 = 0x0002C,
166 .init_feedback_reg = 0x0005C,
167 .dump_addr_reg = 0x00064,
168 .dump_data_reg = 0x00068,
169 .endian_swap_reg = 0x00084
170 }
171 },
172 };
173
174 static const struct ipr_chip_t ipr_chip[] = {
175 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
176 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
177 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
178 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
179 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, true, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
180 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
181 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
182 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, true, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },
183 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE, true, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },
184 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_RATTLESNAKE, true, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] }
185 };
186
187 static int ipr_max_bus_speeds[] = {
188 IPR_80MBs_SCSI_RATE, IPR_U160_SCSI_RATE, IPR_U320_SCSI_RATE
189 };
190
191 MODULE_AUTHOR("Brian King <brking@us.ibm.com>");
192 MODULE_DESCRIPTION("IBM Power RAID SCSI Adapter Driver");
193 module_param_named(max_speed, ipr_max_speed, uint, 0);
194 MODULE_PARM_DESC(max_speed, "Maximum bus speed (0-2). Default: 1=U160. Speeds: 0=80 MB/s, 1=U160, 2=U320");
195 module_param_named(log_level, ipr_log_level, uint, 0);
196 MODULE_PARM_DESC(log_level, "Set to 0 - 4 for increasing verbosity of device driver");
197 module_param_named(testmode, ipr_testmode, int, 0);
198 MODULE_PARM_DESC(testmode, "DANGEROUS!!! Allows unsupported configurations");
199 module_param_named(fastfail, ipr_fastfail, int, S_IRUGO | S_IWUSR);
200 MODULE_PARM_DESC(fastfail, "Reduce timeouts and retries");
201 module_param_named(transop_timeout, ipr_transop_timeout, int, 0);
202 MODULE_PARM_DESC(transop_timeout, "Time in seconds to wait for adapter to come operational (default: 300)");
203 module_param_named(debug, ipr_debug, int, S_IRUGO | S_IWUSR);
204 MODULE_PARM_DESC(debug, "Enable device driver debugging logging. Set to 1 to enable. (default: 0)");
205 module_param_named(dual_ioa_raid, ipr_dual_ioa_raid, int, 0);
206 MODULE_PARM_DESC(dual_ioa_raid, "Enable dual adapter RAID support. Set to 1 to enable. (default: 1)");
207 module_param_named(max_devs, ipr_max_devs, int, 0);
208 MODULE_PARM_DESC(max_devs, "Specify the maximum number of physical devices. "
209 "[Default=" __stringify(IPR_DEFAULT_SIS64_DEVS) "]");
210 module_param_named(number_of_msix, ipr_number_of_msix, int, 0);
211 MODULE_PARM_DESC(number_of_msix, "Specify the number of MSIX interrupts to use on capable adapters (1 - 16). (default:16)");
212 module_param_named(fast_reboot, ipr_fast_reboot, int, S_IRUGO | S_IWUSR);
213 MODULE_PARM_DESC(fast_reboot, "Skip adapter shutdown during reboot. Set to 1 to enable. (default: 0)");
214 MODULE_LICENSE("GPL");
215 MODULE_VERSION(IPR_DRIVER_VERSION);
216
217
218 static const
219 struct ipr_error_table_t ipr_error_table[] = {
220 {0x00000000, 1, IPR_DEFAULT_LOG_LEVEL,
221 "8155: An unknown error was received"},
222 {0x00330000, 0, 0,
223 "Soft underlength error"},
224 {0x005A0000, 0, 0,
225 "Command to be cancelled not found"},
226 {0x00808000, 0, 0,
227 "Qualified success"},
228 {0x01080000, 1, IPR_DEFAULT_LOG_LEVEL,
229 "FFFE: Soft device bus error recovered by the IOA"},
230 {0x01088100, 0, IPR_DEFAULT_LOG_LEVEL,
231 "4101: Soft device bus fabric error"},
232 {0x01100100, 0, IPR_DEFAULT_LOG_LEVEL,
233 "FFFC: Logical block guard error recovered by the device"},
234 {0x01100300, 0, IPR_DEFAULT_LOG_LEVEL,
235 "FFFC: Logical block reference tag error recovered by the device"},
236 {0x01108300, 0, IPR_DEFAULT_LOG_LEVEL,
237 "4171: Recovered scatter list tag / sequence number error"},
238 {0x01109000, 0, IPR_DEFAULT_LOG_LEVEL,
239 "FF3D: Recovered logical block CRC error on IOA to Host transfer"},
240 {0x01109200, 0, IPR_DEFAULT_LOG_LEVEL,
241 "4171: Recovered logical block sequence number error on IOA to Host transfer"},
242 {0x0110A000, 0, IPR_DEFAULT_LOG_LEVEL,
243 "FFFD: Recovered logical block reference tag error detected by the IOA"},
244 {0x0110A100, 0, IPR_DEFAULT_LOG_LEVEL,
245 "FFFD: Logical block guard error recovered by the IOA"},
246 {0x01170600, 0, IPR_DEFAULT_LOG_LEVEL,
247 "FFF9: Device sector reassign successful"},
248 {0x01170900, 0, IPR_DEFAULT_LOG_LEVEL,
249 "FFF7: Media error recovered by device rewrite procedures"},
250 {0x01180200, 0, IPR_DEFAULT_LOG_LEVEL,
251 "7001: IOA sector reassignment successful"},
252 {0x01180500, 0, IPR_DEFAULT_LOG_LEVEL,
253 "FFF9: Soft media error. Sector reassignment recommended"},
254 {0x01180600, 0, IPR_DEFAULT_LOG_LEVEL,
255 "FFF7: Media error recovered by IOA rewrite procedures"},
256 {0x01418000, 0, IPR_DEFAULT_LOG_LEVEL,
257 "FF3D: Soft PCI bus error recovered by the IOA"},
258 {0x01440000, 1, IPR_DEFAULT_LOG_LEVEL,
259 "FFF6: Device hardware error recovered by the IOA"},
260 {0x01448100, 0, IPR_DEFAULT_LOG_LEVEL,
261 "FFF6: Device hardware error recovered by the device"},
262 {0x01448200, 1, IPR_DEFAULT_LOG_LEVEL,
263 "FF3D: Soft IOA error recovered by the IOA"},
264 {0x01448300, 0, IPR_DEFAULT_LOG_LEVEL,
265 "FFFA: Undefined device response recovered by the IOA"},
266 {0x014A0000, 1, IPR_DEFAULT_LOG_LEVEL,
267 "FFF6: Device bus error, message or command phase"},
268 {0x014A8000, 0, IPR_DEFAULT_LOG_LEVEL,
269 "FFFE: Task Management Function failed"},
270 {0x015D0000, 0, IPR_DEFAULT_LOG_LEVEL,
271 "FFF6: Failure prediction threshold exceeded"},
272 {0x015D9200, 0, IPR_DEFAULT_LOG_LEVEL,
273 "8009: Impending cache battery pack failure"},
274 {0x02040100, 0, 0,
275 "Logical Unit in process of becoming ready"},
276 {0x02040200, 0, 0,
277 "Initializing command required"},
278 {0x02040400, 0, 0,
279 "34FF: Disk device format in progress"},
280 {0x02040C00, 0, 0,
281 "Logical unit not accessible, target port in unavailable state"},
282 {0x02048000, 0, IPR_DEFAULT_LOG_LEVEL,
283 "9070: IOA requested reset"},
284 {0x023F0000, 0, 0,
285 "Synchronization required"},
286 {0x02408500, 0, 0,
287 "IOA microcode download required"},
288 {0x02408600, 0, 0,
289 "Device bus connection is prohibited by host"},
290 {0x024E0000, 0, 0,
291 "No ready, IOA shutdown"},
292 {0x025A0000, 0, 0,
293 "Not ready, IOA has been shutdown"},
294 {0x02670100, 0, IPR_DEFAULT_LOG_LEVEL,
295 "3020: Storage subsystem configuration error"},
296 {0x03110B00, 0, 0,
297 "FFF5: Medium error, data unreadable, recommend reassign"},
298 {0x03110C00, 0, 0,
299 "7000: Medium error, data unreadable, do not reassign"},
300 {0x03310000, 0, IPR_DEFAULT_LOG_LEVEL,
301 "FFF3: Disk media format bad"},
302 {0x04050000, 0, IPR_DEFAULT_LOG_LEVEL,
303 "3002: Addressed device failed to respond to selection"},
304 {0x04080000, 1, IPR_DEFAULT_LOG_LEVEL,
305 "3100: Device bus error"},
306 {0x04080100, 0, IPR_DEFAULT_LOG_LEVEL,
307 "3109: IOA timed out a device command"},
308 {0x04088000, 0, 0,
309 "3120: SCSI bus is not operational"},
310 {0x04088100, 0, IPR_DEFAULT_LOG_LEVEL,
311 "4100: Hard device bus fabric error"},
312 {0x04100100, 0, IPR_DEFAULT_LOG_LEVEL,
313 "310C: Logical block guard error detected by the device"},
314 {0x04100300, 0, IPR_DEFAULT_LOG_LEVEL,
315 "310C: Logical block reference tag error detected by the device"},
316 {0x04108300, 1, IPR_DEFAULT_LOG_LEVEL,
317 "4170: Scatter list tag / sequence number error"},
318 {0x04109000, 1, IPR_DEFAULT_LOG_LEVEL,
319 "8150: Logical block CRC error on IOA to Host transfer"},
320 {0x04109200, 1, IPR_DEFAULT_LOG_LEVEL,
321 "4170: Logical block sequence number error on IOA to Host transfer"},
322 {0x0410A000, 0, IPR_DEFAULT_LOG_LEVEL,
323 "310D: Logical block reference tag error detected by the IOA"},
324 {0x0410A100, 0, IPR_DEFAULT_LOG_LEVEL,
325 "310D: Logical block guard error detected by the IOA"},
326 {0x04118000, 0, IPR_DEFAULT_LOG_LEVEL,
327 "9000: IOA reserved area data check"},
328 {0x04118100, 0, IPR_DEFAULT_LOG_LEVEL,
329 "9001: IOA reserved area invalid data pattern"},
330 {0x04118200, 0, IPR_DEFAULT_LOG_LEVEL,
331 "9002: IOA reserved area LRC error"},
332 {0x04118300, 1, IPR_DEFAULT_LOG_LEVEL,
333 "Hardware Error, IOA metadata access error"},
334 {0x04320000, 0, IPR_DEFAULT_LOG_LEVEL,
335 "102E: Out of alternate sectors for disk storage"},
336 {0x04330000, 1, IPR_DEFAULT_LOG_LEVEL,
337 "FFF4: Data transfer underlength error"},
338 {0x04338000, 1, IPR_DEFAULT_LOG_LEVEL,
339 "FFF4: Data transfer overlength error"},
340 {0x043E0100, 0, IPR_DEFAULT_LOG_LEVEL,
341 "3400: Logical unit failure"},
342 {0x04408500, 0, IPR_DEFAULT_LOG_LEVEL,
343 "FFF4: Device microcode is corrupt"},
344 {0x04418000, 1, IPR_DEFAULT_LOG_LEVEL,
345 "8150: PCI bus error"},
346 {0x04430000, 1, 0,
347 "Unsupported device bus message received"},
348 {0x04440000, 1, IPR_DEFAULT_LOG_LEVEL,
349 "FFF4: Disk device problem"},
350 {0x04448200, 1, IPR_DEFAULT_LOG_LEVEL,
351 "8150: Permanent IOA failure"},
352 {0x04448300, 0, IPR_DEFAULT_LOG_LEVEL,
353 "3010: Disk device returned wrong response to IOA"},
354 {0x04448400, 0, IPR_DEFAULT_LOG_LEVEL,
355 "8151: IOA microcode error"},
356 {0x04448500, 0, 0,
357 "Device bus status error"},
358 {0x04448600, 0, IPR_DEFAULT_LOG_LEVEL,
359 "8157: IOA error requiring IOA reset to recover"},
360 {0x04448700, 0, 0,
361 "ATA device status error"},
362 {0x04490000, 0, 0,
363 "Message reject received from the device"},
364 {0x04449200, 0, IPR_DEFAULT_LOG_LEVEL,
365 "8008: A permanent cache battery pack failure occurred"},
366 {0x0444A000, 0, IPR_DEFAULT_LOG_LEVEL,
367 "9090: Disk unit has been modified after the last known status"},
368 {0x0444A200, 0, IPR_DEFAULT_LOG_LEVEL,
369 "9081: IOA detected device error"},
370 {0x0444A300, 0, IPR_DEFAULT_LOG_LEVEL,
371 "9082: IOA detected device error"},
372 {0x044A0000, 1, IPR_DEFAULT_LOG_LEVEL,
373 "3110: Device bus error, message or command phase"},
374 {0x044A8000, 1, IPR_DEFAULT_LOG_LEVEL,
375 "3110: SAS Command / Task Management Function failed"},
376 {0x04670400, 0, IPR_DEFAULT_LOG_LEVEL,
377 "9091: Incorrect hardware configuration change has been detected"},
378 {0x04678000, 0, IPR_DEFAULT_LOG_LEVEL,
379 "9073: Invalid multi-adapter configuration"},
380 {0x04678100, 0, IPR_DEFAULT_LOG_LEVEL,
381 "4010: Incorrect connection between cascaded expanders"},
382 {0x04678200, 0, IPR_DEFAULT_LOG_LEVEL,
383 "4020: Connections exceed IOA design limits"},
384 {0x04678300, 0, IPR_DEFAULT_LOG_LEVEL,
385 "4030: Incorrect multipath connection"},
386 {0x04679000, 0, IPR_DEFAULT_LOG_LEVEL,
387 "4110: Unsupported enclosure function"},
388 {0x04679800, 0, IPR_DEFAULT_LOG_LEVEL,
389 "4120: SAS cable VPD cannot be read"},
390 {0x046E0000, 0, IPR_DEFAULT_LOG_LEVEL,
391 "FFF4: Command to logical unit failed"},
392 {0x05240000, 1, 0,
393 "Illegal request, invalid request type or request packet"},
394 {0x05250000, 0, 0,
395 "Illegal request, invalid resource handle"},
396 {0x05258000, 0, 0,
397 "Illegal request, commands not allowed to this device"},
398 {0x05258100, 0, 0,
399 "Illegal request, command not allowed to a secondary adapter"},
400 {0x05258200, 0, 0,
401 "Illegal request, command not allowed to a non-optimized resource"},
402 {0x05260000, 0, 0,
403 "Illegal request, invalid field in parameter list"},
404 {0x05260100, 0, 0,
405 "Illegal request, parameter not supported"},
406 {0x05260200, 0, 0,
407 "Illegal request, parameter value invalid"},
408 {0x052C0000, 0, 0,
409 "Illegal request, command sequence error"},
410 {0x052C8000, 1, 0,
411 "Illegal request, dual adapter support not enabled"},
412 {0x052C8100, 1, 0,
413 "Illegal request, another cable connector was physically disabled"},
414 {0x054E8000, 1, 0,
415 "Illegal request, inconsistent group id/group count"},
416 {0x06040500, 0, IPR_DEFAULT_LOG_LEVEL,
417 "9031: Array protection temporarily suspended, protection resuming"},
418 {0x06040600, 0, IPR_DEFAULT_LOG_LEVEL,
419 "9040: Array protection temporarily suspended, protection resuming"},
420 {0x060B0100, 0, IPR_DEFAULT_LOG_LEVEL,
421 "4080: IOA exceeded maximum operating temperature"},
422 {0x060B8000, 0, IPR_DEFAULT_LOG_LEVEL,
423 "4085: Service required"},
424 {0x060B8100, 0, IPR_DEFAULT_LOG_LEVEL,
425 "4086: SAS Adapter Hardware Configuration Error"},
426 {0x06288000, 0, IPR_DEFAULT_LOG_LEVEL,
427 "3140: Device bus not ready to ready transition"},
428 {0x06290000, 0, IPR_DEFAULT_LOG_LEVEL,
429 "FFFB: SCSI bus was reset"},
430 {0x06290500, 0, 0,
431 "FFFE: SCSI bus transition to single ended"},
432 {0x06290600, 0, 0,
433 "FFFE: SCSI bus transition to LVD"},
434 {0x06298000, 0, IPR_DEFAULT_LOG_LEVEL,
435 "FFFB: SCSI bus was reset by another initiator"},
436 {0x063F0300, 0, IPR_DEFAULT_LOG_LEVEL,
437 "3029: A device replacement has occurred"},
438 {0x063F8300, 0, IPR_DEFAULT_LOG_LEVEL,
439 "4102: Device bus fabric performance degradation"},
440 {0x064C8000, 0, IPR_DEFAULT_LOG_LEVEL,
441 "9051: IOA cache data exists for a missing or failed device"},
442 {0x064C8100, 0, IPR_DEFAULT_LOG_LEVEL,
443 "9055: Auxiliary cache IOA contains cache data needed by the primary IOA"},
444 {0x06670100, 0, IPR_DEFAULT_LOG_LEVEL,
445 "9025: Disk unit is not supported at its physical location"},
446 {0x06670600, 0, IPR_DEFAULT_LOG_LEVEL,
447 "3020: IOA detected a SCSI bus configuration error"},
448 {0x06678000, 0, IPR_DEFAULT_LOG_LEVEL,
449 "3150: SCSI bus configuration error"},
450 {0x06678100, 0, IPR_DEFAULT_LOG_LEVEL,
451 "9074: Asymmetric advanced function disk configuration"},
452 {0x06678300, 0, IPR_DEFAULT_LOG_LEVEL,
453 "4040: Incomplete multipath connection between IOA and enclosure"},
454 {0x06678400, 0, IPR_DEFAULT_LOG_LEVEL,
455 "4041: Incomplete multipath connection between enclosure and device"},
456 {0x06678500, 0, IPR_DEFAULT_LOG_LEVEL,
457 "9075: Incomplete multipath connection between IOA and remote IOA"},
458 {0x06678600, 0, IPR_DEFAULT_LOG_LEVEL,
459 "9076: Configuration error, missing remote IOA"},
460 {0x06679100, 0, IPR_DEFAULT_LOG_LEVEL,
461 "4050: Enclosure does not support a required multipath function"},
462 {0x06679800, 0, IPR_DEFAULT_LOG_LEVEL,
463 "4121: Configuration error, required cable is missing"},
464 {0x06679900, 0, IPR_DEFAULT_LOG_LEVEL,
465 "4122: Cable is not plugged into the correct location on remote IOA"},
466 {0x06679A00, 0, IPR_DEFAULT_LOG_LEVEL,
467 "4123: Configuration error, invalid cable vital product data"},
468 {0x06679B00, 0, IPR_DEFAULT_LOG_LEVEL,
469 "4124: Configuration error, both cable ends are plugged into the same IOA"},
470 {0x06690000, 0, IPR_DEFAULT_LOG_LEVEL,
471 "4070: Logically bad block written on device"},
472 {0x06690200, 0, IPR_DEFAULT_LOG_LEVEL,
473 "9041: Array protection temporarily suspended"},
474 {0x06698200, 0, IPR_DEFAULT_LOG_LEVEL,
475 "9042: Corrupt array parity detected on specified device"},
476 {0x066B0200, 0, IPR_DEFAULT_LOG_LEVEL,
477 "9030: Array no longer protected due to missing or failed disk unit"},
478 {0x066B8000, 0, IPR_DEFAULT_LOG_LEVEL,
479 "9071: Link operational transition"},
480 {0x066B8100, 0, IPR_DEFAULT_LOG_LEVEL,
481 "9072: Link not operational transition"},
482 {0x066B8200, 0, IPR_DEFAULT_LOG_LEVEL,
483 "9032: Array exposed but still protected"},
484 {0x066B8300, 0, IPR_DEBUG_LOG_LEVEL,
485 "70DD: Device forced failed by disrupt device command"},
486 {0x066B9100, 0, IPR_DEFAULT_LOG_LEVEL,
487 "4061: Multipath redundancy level got better"},
488 {0x066B9200, 0, IPR_DEFAULT_LOG_LEVEL,
489 "4060: Multipath redundancy level got worse"},
490 {0x06808100, 0, IPR_DEBUG_LOG_LEVEL,
491 "9083: Device raw mode enabled"},
492 {0x06808200, 0, IPR_DEBUG_LOG_LEVEL,
493 "9084: Device raw mode disabled"},
494 {0x07270000, 0, 0,
495 "Failure due to other device"},
496 {0x07278000, 0, IPR_DEFAULT_LOG_LEVEL,
497 "9008: IOA does not support functions expected by devices"},
498 {0x07278100, 0, IPR_DEFAULT_LOG_LEVEL,
499 "9010: Cache data associated with attached devices cannot be found"},
500 {0x07278200, 0, IPR_DEFAULT_LOG_LEVEL,
501 "9011: Cache data belongs to devices other than those attached"},
502 {0x07278400, 0, IPR_DEFAULT_LOG_LEVEL,
503 "9020: Array missing 2 or more devices with only 1 device present"},
504 {0x07278500, 0, IPR_DEFAULT_LOG_LEVEL,
505 "9021: Array missing 2 or more devices with 2 or more devices present"},
506 {0x07278600, 0, IPR_DEFAULT_LOG_LEVEL,
507 "9022: Exposed array is missing a required device"},
508 {0x07278700, 0, IPR_DEFAULT_LOG_LEVEL,
509 "9023: Array member(s) not at required physical locations"},
510 {0x07278800, 0, IPR_DEFAULT_LOG_LEVEL,
511 "9024: Array not functional due to present hardware configuration"},
512 {0x07278900, 0, IPR_DEFAULT_LOG_LEVEL,
513 "9026: Array not functional due to present hardware configuration"},
514 {0x07278A00, 0, IPR_DEFAULT_LOG_LEVEL,
515 "9027: Array is missing a device and parity is out of sync"},
516 {0x07278B00, 0, IPR_DEFAULT_LOG_LEVEL,
517 "9028: Maximum number of arrays already exist"},
518 {0x07278C00, 0, IPR_DEFAULT_LOG_LEVEL,
519 "9050: Required cache data cannot be located for a disk unit"},
520 {0x07278D00, 0, IPR_DEFAULT_LOG_LEVEL,
521 "9052: Cache data exists for a device that has been modified"},
522 {0x07278F00, 0, IPR_DEFAULT_LOG_LEVEL,
523 "9054: IOA resources not available due to previous problems"},
524 {0x07279100, 0, IPR_DEFAULT_LOG_LEVEL,
525 "9092: Disk unit requires initialization before use"},
526 {0x07279200, 0, IPR_DEFAULT_LOG_LEVEL,
527 "9029: Incorrect hardware configuration change has been detected"},
528 {0x07279600, 0, IPR_DEFAULT_LOG_LEVEL,
529 "9060: One or more disk pairs are missing from an array"},
530 {0x07279700, 0, IPR_DEFAULT_LOG_LEVEL,
531 "9061: One or more disks are missing from an array"},
532 {0x07279800, 0, IPR_DEFAULT_LOG_LEVEL,
533 "9062: One or more disks are missing from an array"},
534 {0x07279900, 0, IPR_DEFAULT_LOG_LEVEL,
535 "9063: Maximum number of functional arrays has been exceeded"},
536 {0x07279A00, 0, 0,
537 "Data protect, other volume set problem"},
538 {0x0B260000, 0, 0,
539 "Aborted command, invalid descriptor"},
540 {0x0B3F9000, 0, 0,
541 "Target operating conditions have changed, dual adapter takeover"},
542 {0x0B530200, 0, 0,
543 "Aborted command, medium removal prevented"},
544 {0x0B5A0000, 0, 0,
545 "Command terminated by host"},
546 {0x0B5B8000, 0, 0,
547 "Aborted command, command terminated by host"}
548 };
549
550 static const struct ipr_ses_table_entry ipr_ses_table[] = {
551 { "2104-DL1 ", "XXXXXXXXXXXXXXXX", 80 },
552 { "2104-TL1 ", "XXXXXXXXXXXXXXXX", 80 },
553 { "HSBP07M P U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
554 { "HSBP05M P U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
555 { "HSBP05M S U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
556 { "HSBP06E ASU2SCSI", "XXXXXXXXXXXXXXXX", 80 },
557 { "2104-DU3 ", "XXXXXXXXXXXXXXXX", 160 },
558 { "2104-TU3 ", "XXXXXXXXXXXXXXXX", 160 },
559 { "HSBP04C RSU2SCSI", "XXXXXXX*XXXXXXXX", 160 },
560 { "HSBP06E RSU2SCSI", "XXXXXXX*XXXXXXXX", 160 },
561 { "St V1S2 ", "XXXXXXXXXXXXXXXX", 160 },
562 { "HSBPD4M PU3SCSI", "XXXXXXX*XXXXXXXX", 160 },
563 { "VSBPD1H U3SCSI", "XXXXXXX*XXXXXXXX", 160 }
564 };
565
566
567
568
569 static int ipr_reset_alert(struct ipr_cmnd *);
570 static void ipr_process_ccn(struct ipr_cmnd *);
571 static void ipr_process_error(struct ipr_cmnd *);
572 static void ipr_reset_ioa_job(struct ipr_cmnd *);
573 static void ipr_initiate_ioa_reset(struct ipr_ioa_cfg *,
574 enum ipr_shutdown_type);
575
576 #ifdef CONFIG_SCSI_IPR_TRACE
577
578
579
580
581
582
583
584
585
586 static void ipr_trc_hook(struct ipr_cmnd *ipr_cmd,
587 u8 type, u32 add_data)
588 {
589 struct ipr_trace_entry *trace_entry;
590 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
591 unsigned int trace_index;
592
593 trace_index = atomic_add_return(1, &ioa_cfg->trace_index) & IPR_TRACE_INDEX_MASK;
594 trace_entry = &ioa_cfg->trace[trace_index];
595 trace_entry->time = jiffies;
596 trace_entry->op_code = ipr_cmd->ioarcb.cmd_pkt.cdb[0];
597 trace_entry->type = type;
598 if (ipr_cmd->ioa_cfg->sis64)
599 trace_entry->ata_op_code = ipr_cmd->i.ata_ioadl.regs.command;
600 else
601 trace_entry->ata_op_code = ipr_cmd->ioarcb.u.add_data.u.regs.command;
602 trace_entry->cmd_index = ipr_cmd->cmd_index & 0xff;
603 trace_entry->res_handle = ipr_cmd->ioarcb.res_handle;
604 trace_entry->u.add_data = add_data;
605 wmb();
606 }
607 #else
608 #define ipr_trc_hook(ipr_cmd, type, add_data) do { } while (0)
609 #endif
610
611
612
613
614
615
616
617
618 static void ipr_lock_and_done(struct ipr_cmnd *ipr_cmd)
619 {
620 unsigned long lock_flags;
621 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
622
623 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
624 ipr_cmd->done(ipr_cmd);
625 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
626 }
627
628
629
630
631
632
633
634
635 static void ipr_reinit_ipr_cmnd(struct ipr_cmnd *ipr_cmd)
636 {
637 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
638 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
639 struct ipr_ioasa64 *ioasa64 = &ipr_cmd->s.ioasa64;
640 dma_addr_t dma_addr = ipr_cmd->dma_addr;
641 int hrrq_id;
642
643 hrrq_id = ioarcb->cmd_pkt.hrrq_id;
644 memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt));
645 ioarcb->cmd_pkt.hrrq_id = hrrq_id;
646 ioarcb->data_transfer_length = 0;
647 ioarcb->read_data_transfer_length = 0;
648 ioarcb->ioadl_len = 0;
649 ioarcb->read_ioadl_len = 0;
650
651 if (ipr_cmd->ioa_cfg->sis64) {
652 ioarcb->u.sis64_addr_data.data_ioadl_addr =
653 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
654 ioasa64->u.gata.status = 0;
655 } else {
656 ioarcb->write_ioadl_addr =
657 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
658 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
659 ioasa->u.gata.status = 0;
660 }
661
662 ioasa->hdr.ioasc = 0;
663 ioasa->hdr.residual_data_len = 0;
664 ipr_cmd->scsi_cmd = NULL;
665 ipr_cmd->qc = NULL;
666 ipr_cmd->sense_buffer[0] = 0;
667 ipr_cmd->dma_use_sg = 0;
668 }
669
670
671
672
673
674
675
676
677 static void ipr_init_ipr_cmnd(struct ipr_cmnd *ipr_cmd,
678 void (*fast_done) (struct ipr_cmnd *))
679 {
680 ipr_reinit_ipr_cmnd(ipr_cmd);
681 ipr_cmd->u.scratch = 0;
682 ipr_cmd->sibling = NULL;
683 ipr_cmd->eh_comp = NULL;
684 ipr_cmd->fast_done = fast_done;
685 timer_setup(&ipr_cmd->timer, NULL, 0);
686 }
687
688
689
690
691
692
693
694
695 static
696 struct ipr_cmnd *__ipr_get_free_ipr_cmnd(struct ipr_hrr_queue *hrrq)
697 {
698 struct ipr_cmnd *ipr_cmd = NULL;
699
700 if (likely(!list_empty(&hrrq->hrrq_free_q))) {
701 ipr_cmd = list_entry(hrrq->hrrq_free_q.next,
702 struct ipr_cmnd, queue);
703 list_del(&ipr_cmd->queue);
704 }
705
706
707 return ipr_cmd;
708 }
709
710
711
712
713
714
715
716
717 static
718 struct ipr_cmnd *ipr_get_free_ipr_cmnd(struct ipr_ioa_cfg *ioa_cfg)
719 {
720 struct ipr_cmnd *ipr_cmd =
721 __ipr_get_free_ipr_cmnd(&ioa_cfg->hrrq[IPR_INIT_HRRQ]);
722 ipr_init_ipr_cmnd(ipr_cmd, ipr_lock_and_done);
723 return ipr_cmd;
724 }
725
726
727
728
729
730
731
732
733
734
735
736
737 static void ipr_mask_and_clear_interrupts(struct ipr_ioa_cfg *ioa_cfg,
738 u32 clr_ints)
739 {
740 volatile u32 int_reg;
741 int i;
742
743
744 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
745 spin_lock(&ioa_cfg->hrrq[i]._lock);
746 ioa_cfg->hrrq[i].allow_interrupts = 0;
747 spin_unlock(&ioa_cfg->hrrq[i]._lock);
748 }
749
750
751 if (ioa_cfg->sis64)
752 writeq(~0, ioa_cfg->regs.set_interrupt_mask_reg);
753 else
754 writel(~0, ioa_cfg->regs.set_interrupt_mask_reg);
755
756
757 if (ioa_cfg->sis64)
758 writel(~0, ioa_cfg->regs.clr_interrupt_reg);
759 writel(clr_ints, ioa_cfg->regs.clr_interrupt_reg32);
760 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
761 }
762
763
764
765
766
767
768
769
770 static int ipr_save_pcix_cmd_reg(struct ipr_ioa_cfg *ioa_cfg)
771 {
772 int pcix_cmd_reg = pci_find_capability(ioa_cfg->pdev, PCI_CAP_ID_PCIX);
773
774 if (pcix_cmd_reg == 0)
775 return 0;
776
777 if (pci_read_config_word(ioa_cfg->pdev, pcix_cmd_reg + PCI_X_CMD,
778 &ioa_cfg->saved_pcix_cmd_reg) != PCIBIOS_SUCCESSFUL) {
779 dev_err(&ioa_cfg->pdev->dev, "Failed to save PCI-X command register\n");
780 return -EIO;
781 }
782
783 ioa_cfg->saved_pcix_cmd_reg |= PCI_X_CMD_DPERR_E | PCI_X_CMD_ERO;
784 return 0;
785 }
786
787
788
789
790
791
792
793
794 static int ipr_set_pcix_cmd_reg(struct ipr_ioa_cfg *ioa_cfg)
795 {
796 int pcix_cmd_reg = pci_find_capability(ioa_cfg->pdev, PCI_CAP_ID_PCIX);
797
798 if (pcix_cmd_reg) {
799 if (pci_write_config_word(ioa_cfg->pdev, pcix_cmd_reg + PCI_X_CMD,
800 ioa_cfg->saved_pcix_cmd_reg) != PCIBIOS_SUCCESSFUL) {
801 dev_err(&ioa_cfg->pdev->dev, "Failed to setup PCI-X command register\n");
802 return -EIO;
803 }
804 }
805
806 return 0;
807 }
808
809
810
811
812
813
814
815
816
817
818
819 static void __ipr_sata_eh_done(struct ipr_cmnd *ipr_cmd)
820 {
821 struct ata_queued_cmd *qc = ipr_cmd->qc;
822 struct ipr_sata_port *sata_port = qc->ap->private_data;
823
824 qc->err_mask |= AC_ERR_OTHER;
825 sata_port->ioasa.status |= ATA_BUSY;
826 ata_qc_complete(qc);
827 if (ipr_cmd->eh_comp)
828 complete(ipr_cmd->eh_comp);
829 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
830 }
831
832
833
834
835
836
837
838
839
840
841
842 static void ipr_sata_eh_done(struct ipr_cmnd *ipr_cmd)
843 {
844 struct ipr_hrr_queue *hrrq = ipr_cmd->hrrq;
845 unsigned long hrrq_flags;
846
847 spin_lock_irqsave(&hrrq->_lock, hrrq_flags);
848 __ipr_sata_eh_done(ipr_cmd);
849 spin_unlock_irqrestore(&hrrq->_lock, hrrq_flags);
850 }
851
852
853
854
855
856
857
858
859
860
861
862 static void __ipr_scsi_eh_done(struct ipr_cmnd *ipr_cmd)
863 {
864 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
865
866 scsi_cmd->result |= (DID_ERROR << 16);
867
868 scsi_dma_unmap(ipr_cmd->scsi_cmd);
869 scsi_cmd->scsi_done(scsi_cmd);
870 if (ipr_cmd->eh_comp)
871 complete(ipr_cmd->eh_comp);
872 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
873 }
874
875
876
877
878
879
880
881
882
883
884
885 static void ipr_scsi_eh_done(struct ipr_cmnd *ipr_cmd)
886 {
887 unsigned long hrrq_flags;
888 struct ipr_hrr_queue *hrrq = ipr_cmd->hrrq;
889
890 spin_lock_irqsave(&hrrq->_lock, hrrq_flags);
891 __ipr_scsi_eh_done(ipr_cmd);
892 spin_unlock_irqrestore(&hrrq->_lock, hrrq_flags);
893 }
894
895
896
897
898
899
900
901
902
903
904 static void ipr_fail_all_ops(struct ipr_ioa_cfg *ioa_cfg)
905 {
906 struct ipr_cmnd *ipr_cmd, *temp;
907 struct ipr_hrr_queue *hrrq;
908
909 ENTER;
910 for_each_hrrq(hrrq, ioa_cfg) {
911 spin_lock(&hrrq->_lock);
912 list_for_each_entry_safe(ipr_cmd,
913 temp, &hrrq->hrrq_pending_q, queue) {
914 list_del(&ipr_cmd->queue);
915
916 ipr_cmd->s.ioasa.hdr.ioasc =
917 cpu_to_be32(IPR_IOASC_IOA_WAS_RESET);
918 ipr_cmd->s.ioasa.hdr.ilid =
919 cpu_to_be32(IPR_DRIVER_ILID);
920
921 if (ipr_cmd->scsi_cmd)
922 ipr_cmd->done = __ipr_scsi_eh_done;
923 else if (ipr_cmd->qc)
924 ipr_cmd->done = __ipr_sata_eh_done;
925
926 ipr_trc_hook(ipr_cmd, IPR_TRACE_FINISH,
927 IPR_IOASC_IOA_WAS_RESET);
928 del_timer(&ipr_cmd->timer);
929 ipr_cmd->done(ipr_cmd);
930 }
931 spin_unlock(&hrrq->_lock);
932 }
933 LEAVE;
934 }
935
936
937
938
939
940
941
942
943
944
945
946
947 static void ipr_send_command(struct ipr_cmnd *ipr_cmd)
948 {
949 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
950 dma_addr_t send_dma_addr = ipr_cmd->dma_addr;
951
952 if (ioa_cfg->sis64) {
953
954 send_dma_addr |= 0x1;
955
956
957
958 if (ipr_cmd->dma_use_sg * sizeof(struct ipr_ioadl64_desc) > 128 )
959 send_dma_addr |= 0x4;
960 writeq(send_dma_addr, ioa_cfg->regs.ioarrin_reg);
961 } else
962 writel(send_dma_addr, ioa_cfg->regs.ioarrin_reg);
963 }
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978 static void ipr_do_req(struct ipr_cmnd *ipr_cmd,
979 void (*done) (struct ipr_cmnd *),
980 void (*timeout_func) (struct timer_list *), u32 timeout)
981 {
982 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
983
984 ipr_cmd->done = done;
985
986 ipr_cmd->timer.expires = jiffies + timeout;
987 ipr_cmd->timer.function = timeout_func;
988
989 add_timer(&ipr_cmd->timer);
990
991 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, 0);
992
993 ipr_send_command(ipr_cmd);
994 }
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006 static void ipr_internal_cmd_done(struct ipr_cmnd *ipr_cmd)
1007 {
1008 if (ipr_cmd->sibling)
1009 ipr_cmd->sibling = NULL;
1010 else
1011 complete(&ipr_cmd->completion);
1012 }
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027 static void ipr_init_ioadl(struct ipr_cmnd *ipr_cmd, dma_addr_t dma_addr,
1028 u32 len, int flags)
1029 {
1030 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
1031 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
1032
1033 ipr_cmd->dma_use_sg = 1;
1034
1035 if (ipr_cmd->ioa_cfg->sis64) {
1036 ioadl64->flags = cpu_to_be32(flags);
1037 ioadl64->data_len = cpu_to_be32(len);
1038 ioadl64->address = cpu_to_be64(dma_addr);
1039
1040 ipr_cmd->ioarcb.ioadl_len =
1041 cpu_to_be32(sizeof(struct ipr_ioadl64_desc));
1042 ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len);
1043 } else {
1044 ioadl->flags_and_data_len = cpu_to_be32(flags | len);
1045 ioadl->address = cpu_to_be32(dma_addr);
1046
1047 if (flags == IPR_IOADL_FLAGS_READ_LAST) {
1048 ipr_cmd->ioarcb.read_ioadl_len =
1049 cpu_to_be32(sizeof(struct ipr_ioadl_desc));
1050 ipr_cmd->ioarcb.read_data_transfer_length = cpu_to_be32(len);
1051 } else {
1052 ipr_cmd->ioarcb.ioadl_len =
1053 cpu_to_be32(sizeof(struct ipr_ioadl_desc));
1054 ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len);
1055 }
1056 }
1057 }
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068 static void ipr_send_blocking_cmd(struct ipr_cmnd *ipr_cmd,
1069 void (*timeout_func) (struct timer_list *),
1070 u32 timeout)
1071 {
1072 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
1073
1074 init_completion(&ipr_cmd->completion);
1075 ipr_do_req(ipr_cmd, ipr_internal_cmd_done, timeout_func, timeout);
1076
1077 spin_unlock_irq(ioa_cfg->host->host_lock);
1078 wait_for_completion(&ipr_cmd->completion);
1079 spin_lock_irq(ioa_cfg->host->host_lock);
1080 }
1081
1082 static int ipr_get_hrrq_index(struct ipr_ioa_cfg *ioa_cfg)
1083 {
1084 unsigned int hrrq;
1085
1086 if (ioa_cfg->hrrq_num == 1)
1087 hrrq = 0;
1088 else {
1089 hrrq = atomic_add_return(1, &ioa_cfg->hrrq_index);
1090 hrrq = (hrrq % (ioa_cfg->hrrq_num - 1)) + 1;
1091 }
1092 return hrrq;
1093 }
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108 static void ipr_send_hcam(struct ipr_ioa_cfg *ioa_cfg, u8 type,
1109 struct ipr_hostrcb *hostrcb)
1110 {
1111 struct ipr_cmnd *ipr_cmd;
1112 struct ipr_ioarcb *ioarcb;
1113
1114 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds) {
1115 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
1116 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
1117 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_pending_q);
1118
1119 ipr_cmd->u.hostrcb = hostrcb;
1120 ioarcb = &ipr_cmd->ioarcb;
1121
1122 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
1123 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_HCAM;
1124 ioarcb->cmd_pkt.cdb[0] = IPR_HOST_CONTROLLED_ASYNC;
1125 ioarcb->cmd_pkt.cdb[1] = type;
1126 ioarcb->cmd_pkt.cdb[7] = (sizeof(hostrcb->hcam) >> 8) & 0xff;
1127 ioarcb->cmd_pkt.cdb[8] = sizeof(hostrcb->hcam) & 0xff;
1128
1129 ipr_init_ioadl(ipr_cmd, hostrcb->hostrcb_dma,
1130 sizeof(hostrcb->hcam), IPR_IOADL_FLAGS_READ_LAST);
1131
1132 if (type == IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE)
1133 ipr_cmd->done = ipr_process_ccn;
1134 else
1135 ipr_cmd->done = ipr_process_error;
1136
1137 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_IOA_RES_ADDR);
1138
1139 ipr_send_command(ipr_cmd);
1140 } else {
1141 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
1142 }
1143 }
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153 static void ipr_update_ata_class(struct ipr_resource_entry *res, unsigned int proto)
1154 {
1155 switch (proto) {
1156 case IPR_PROTO_SATA:
1157 case IPR_PROTO_SAS_STP:
1158 res->ata_class = ATA_DEV_ATA;
1159 break;
1160 case IPR_PROTO_SATA_ATAPI:
1161 case IPR_PROTO_SAS_STP_ATAPI:
1162 res->ata_class = ATA_DEV_ATAPI;
1163 break;
1164 default:
1165 res->ata_class = ATA_DEV_UNKNOWN;
1166 break;
1167 };
1168 }
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178 static void ipr_init_res_entry(struct ipr_resource_entry *res,
1179 struct ipr_config_table_entry_wrapper *cfgtew)
1180 {
1181 int found = 0;
1182 unsigned int proto;
1183 struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg;
1184 struct ipr_resource_entry *gscsi_res = NULL;
1185
1186 res->needs_sync_complete = 0;
1187 res->in_erp = 0;
1188 res->add_to_ml = 0;
1189 res->del_from_ml = 0;
1190 res->resetting_device = 0;
1191 res->reset_occurred = 0;
1192 res->sdev = NULL;
1193 res->sata_port = NULL;
1194
1195 if (ioa_cfg->sis64) {
1196 proto = cfgtew->u.cfgte64->proto;
1197 res->flags = be16_to_cpu(cfgtew->u.cfgte64->flags);
1198 res->res_flags = be16_to_cpu(cfgtew->u.cfgte64->res_flags);
1199 res->qmodel = IPR_QUEUEING_MODEL64(res);
1200 res->type = cfgtew->u.cfgte64->res_type;
1201
1202 memcpy(res->res_path, &cfgtew->u.cfgte64->res_path,
1203 sizeof(res->res_path));
1204
1205 res->bus = 0;
1206 memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1207 sizeof(res->dev_lun.scsi_lun));
1208 res->lun = scsilun_to_int(&res->dev_lun);
1209
1210 if (res->type == IPR_RES_TYPE_GENERIC_SCSI) {
1211 list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue) {
1212 if (gscsi_res->dev_id == cfgtew->u.cfgte64->dev_id) {
1213 found = 1;
1214 res->target = gscsi_res->target;
1215 break;
1216 }
1217 }
1218 if (!found) {
1219 res->target = find_first_zero_bit(ioa_cfg->target_ids,
1220 ioa_cfg->max_devs_supported);
1221 set_bit(res->target, ioa_cfg->target_ids);
1222 }
1223 } else if (res->type == IPR_RES_TYPE_IOAFP) {
1224 res->bus = IPR_IOAFP_VIRTUAL_BUS;
1225 res->target = 0;
1226 } else if (res->type == IPR_RES_TYPE_ARRAY) {
1227 res->bus = IPR_ARRAY_VIRTUAL_BUS;
1228 res->target = find_first_zero_bit(ioa_cfg->array_ids,
1229 ioa_cfg->max_devs_supported);
1230 set_bit(res->target, ioa_cfg->array_ids);
1231 } else if (res->type == IPR_RES_TYPE_VOLUME_SET) {
1232 res->bus = IPR_VSET_VIRTUAL_BUS;
1233 res->target = find_first_zero_bit(ioa_cfg->vset_ids,
1234 ioa_cfg->max_devs_supported);
1235 set_bit(res->target, ioa_cfg->vset_ids);
1236 } else {
1237 res->target = find_first_zero_bit(ioa_cfg->target_ids,
1238 ioa_cfg->max_devs_supported);
1239 set_bit(res->target, ioa_cfg->target_ids);
1240 }
1241 } else {
1242 proto = cfgtew->u.cfgte->proto;
1243 res->qmodel = IPR_QUEUEING_MODEL(res);
1244 res->flags = cfgtew->u.cfgte->flags;
1245 if (res->flags & IPR_IS_IOA_RESOURCE)
1246 res->type = IPR_RES_TYPE_IOAFP;
1247 else
1248 res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f;
1249
1250 res->bus = cfgtew->u.cfgte->res_addr.bus;
1251 res->target = cfgtew->u.cfgte->res_addr.target;
1252 res->lun = cfgtew->u.cfgte->res_addr.lun;
1253 res->lun_wwn = get_unaligned_be64(cfgtew->u.cfgte->lun_wwn);
1254 }
1255
1256 ipr_update_ata_class(res, proto);
1257 }
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267 static int ipr_is_same_device(struct ipr_resource_entry *res,
1268 struct ipr_config_table_entry_wrapper *cfgtew)
1269 {
1270 if (res->ioa_cfg->sis64) {
1271 if (!memcmp(&res->dev_id, &cfgtew->u.cfgte64->dev_id,
1272 sizeof(cfgtew->u.cfgte64->dev_id)) &&
1273 !memcmp(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1274 sizeof(cfgtew->u.cfgte64->lun))) {
1275 return 1;
1276 }
1277 } else {
1278 if (res->bus == cfgtew->u.cfgte->res_addr.bus &&
1279 res->target == cfgtew->u.cfgte->res_addr.target &&
1280 res->lun == cfgtew->u.cfgte->res_addr.lun)
1281 return 1;
1282 }
1283
1284 return 0;
1285 }
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296 static char *__ipr_format_res_path(u8 *res_path, char *buffer, int len)
1297 {
1298 int i;
1299 char *p = buffer;
1300
1301 *p = '\0';
1302 p += snprintf(p, buffer + len - p, "%02X", res_path[0]);
1303 for (i = 1; res_path[i] != 0xff && ((i * 3) < len); i++)
1304 p += snprintf(p, buffer + len - p, "-%02X", res_path[i]);
1305
1306 return buffer;
1307 }
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319 static char *ipr_format_res_path(struct ipr_ioa_cfg *ioa_cfg,
1320 u8 *res_path, char *buffer, int len)
1321 {
1322 char *p = buffer;
1323
1324 *p = '\0';
1325 p += snprintf(p, buffer + len - p, "%d/", ioa_cfg->host->host_no);
1326 __ipr_format_res_path(res_path, p, len - (buffer - p));
1327 return buffer;
1328 }
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338 static void ipr_update_res_entry(struct ipr_resource_entry *res,
1339 struct ipr_config_table_entry_wrapper *cfgtew)
1340 {
1341 char buffer[IPR_MAX_RES_PATH_LENGTH];
1342 unsigned int proto;
1343 int new_path = 0;
1344
1345 if (res->ioa_cfg->sis64) {
1346 res->flags = be16_to_cpu(cfgtew->u.cfgte64->flags);
1347 res->res_flags = be16_to_cpu(cfgtew->u.cfgte64->res_flags);
1348 res->type = cfgtew->u.cfgte64->res_type;
1349
1350 memcpy(&res->std_inq_data, &cfgtew->u.cfgte64->std_inq_data,
1351 sizeof(struct ipr_std_inq_data));
1352
1353 res->qmodel = IPR_QUEUEING_MODEL64(res);
1354 proto = cfgtew->u.cfgte64->proto;
1355 res->res_handle = cfgtew->u.cfgte64->res_handle;
1356 res->dev_id = cfgtew->u.cfgte64->dev_id;
1357
1358 memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1359 sizeof(res->dev_lun.scsi_lun));
1360
1361 if (memcmp(res->res_path, &cfgtew->u.cfgte64->res_path,
1362 sizeof(res->res_path))) {
1363 memcpy(res->res_path, &cfgtew->u.cfgte64->res_path,
1364 sizeof(res->res_path));
1365 new_path = 1;
1366 }
1367
1368 if (res->sdev && new_path)
1369 sdev_printk(KERN_INFO, res->sdev, "Resource path: %s\n",
1370 ipr_format_res_path(res->ioa_cfg,
1371 res->res_path, buffer, sizeof(buffer)));
1372 } else {
1373 res->flags = cfgtew->u.cfgte->flags;
1374 if (res->flags & IPR_IS_IOA_RESOURCE)
1375 res->type = IPR_RES_TYPE_IOAFP;
1376 else
1377 res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f;
1378
1379 memcpy(&res->std_inq_data, &cfgtew->u.cfgte->std_inq_data,
1380 sizeof(struct ipr_std_inq_data));
1381
1382 res->qmodel = IPR_QUEUEING_MODEL(res);
1383 proto = cfgtew->u.cfgte->proto;
1384 res->res_handle = cfgtew->u.cfgte->res_handle;
1385 }
1386
1387 ipr_update_ata_class(res, proto);
1388 }
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399 static void ipr_clear_res_target(struct ipr_resource_entry *res)
1400 {
1401 struct ipr_resource_entry *gscsi_res = NULL;
1402 struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg;
1403
1404 if (!ioa_cfg->sis64)
1405 return;
1406
1407 if (res->bus == IPR_ARRAY_VIRTUAL_BUS)
1408 clear_bit(res->target, ioa_cfg->array_ids);
1409 else if (res->bus == IPR_VSET_VIRTUAL_BUS)
1410 clear_bit(res->target, ioa_cfg->vset_ids);
1411 else if (res->bus == 0 && res->type == IPR_RES_TYPE_GENERIC_SCSI) {
1412 list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue)
1413 if (gscsi_res->dev_id == res->dev_id && gscsi_res != res)
1414 return;
1415 clear_bit(res->target, ioa_cfg->target_ids);
1416
1417 } else if (res->bus == 0)
1418 clear_bit(res->target, ioa_cfg->target_ids);
1419 }
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429 static void ipr_handle_config_change(struct ipr_ioa_cfg *ioa_cfg,
1430 struct ipr_hostrcb *hostrcb)
1431 {
1432 struct ipr_resource_entry *res = NULL;
1433 struct ipr_config_table_entry_wrapper cfgtew;
1434 __be32 cc_res_handle;
1435
1436 u32 is_ndn = 1;
1437
1438 if (ioa_cfg->sis64) {
1439 cfgtew.u.cfgte64 = &hostrcb->hcam.u.ccn.u.cfgte64;
1440 cc_res_handle = cfgtew.u.cfgte64->res_handle;
1441 } else {
1442 cfgtew.u.cfgte = &hostrcb->hcam.u.ccn.u.cfgte;
1443 cc_res_handle = cfgtew.u.cfgte->res_handle;
1444 }
1445
1446 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
1447 if (res->res_handle == cc_res_handle) {
1448 is_ndn = 0;
1449 break;
1450 }
1451 }
1452
1453 if (is_ndn) {
1454 if (list_empty(&ioa_cfg->free_res_q)) {
1455 ipr_send_hcam(ioa_cfg,
1456 IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE,
1457 hostrcb);
1458 return;
1459 }
1460
1461 res = list_entry(ioa_cfg->free_res_q.next,
1462 struct ipr_resource_entry, queue);
1463
1464 list_del(&res->queue);
1465 ipr_init_res_entry(res, &cfgtew);
1466 list_add_tail(&res->queue, &ioa_cfg->used_res_q);
1467 }
1468
1469 ipr_update_res_entry(res, &cfgtew);
1470
1471 if (hostrcb->hcam.notify_type == IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY) {
1472 if (res->sdev) {
1473 res->del_from_ml = 1;
1474 res->res_handle = IPR_INVALID_RES_HANDLE;
1475 schedule_work(&ioa_cfg->work_q);
1476 } else {
1477 ipr_clear_res_target(res);
1478 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
1479 }
1480 } else if (!res->sdev || res->del_from_ml) {
1481 res->add_to_ml = 1;
1482 schedule_work(&ioa_cfg->work_q);
1483 }
1484
1485 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
1486 }
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498 static void ipr_process_ccn(struct ipr_cmnd *ipr_cmd)
1499 {
1500 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
1501 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb;
1502 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
1503
1504 list_del_init(&hostrcb->queue);
1505 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
1506
1507 if (ioasc) {
1508 if (ioasc != IPR_IOASC_IOA_WAS_RESET &&
1509 ioasc != IPR_IOASC_ABORTED_CMD_TERM_BY_HOST)
1510 dev_err(&ioa_cfg->pdev->dev,
1511 "Host RCB failed with IOASC: 0x%08X\n", ioasc);
1512
1513 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
1514 } else {
1515 ipr_handle_config_change(ioa_cfg, hostrcb);
1516 }
1517 }
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530 static int strip_and_pad_whitespace(int i, char *buf)
1531 {
1532 while (i && buf[i] == ' ')
1533 i--;
1534 buf[i+1] = ' ';
1535 buf[i+2] = '\0';
1536 return i + 2;
1537 }
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548 static void ipr_log_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb,
1549 struct ipr_vpd *vpd)
1550 {
1551 char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN + IPR_SERIAL_NUM_LEN + 3];
1552 int i = 0;
1553
1554 memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN);
1555 i = strip_and_pad_whitespace(IPR_VENDOR_ID_LEN - 1, buffer);
1556
1557 memcpy(&buffer[i], vpd->vpids.product_id, IPR_PROD_ID_LEN);
1558 i = strip_and_pad_whitespace(i + IPR_PROD_ID_LEN - 1, buffer);
1559
1560 memcpy(&buffer[i], vpd->sn, IPR_SERIAL_NUM_LEN);
1561 buffer[IPR_SERIAL_NUM_LEN + i] = '\0';
1562
1563 ipr_hcam_err(hostrcb, "%s VPID/SN: %s\n", prefix, buffer);
1564 }
1565
1566
1567
1568
1569
1570
1571
1572
1573 static void ipr_log_vpd(struct ipr_vpd *vpd)
1574 {
1575 char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN
1576 + IPR_SERIAL_NUM_LEN];
1577
1578 memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN);
1579 memcpy(buffer + IPR_VENDOR_ID_LEN, vpd->vpids.product_id,
1580 IPR_PROD_ID_LEN);
1581 buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN] = '\0';
1582 ipr_err("Vendor/Product ID: %s\n", buffer);
1583
1584 memcpy(buffer, vpd->sn, IPR_SERIAL_NUM_LEN);
1585 buffer[IPR_SERIAL_NUM_LEN] = '\0';
1586 ipr_err(" Serial Number: %s\n", buffer);
1587 }
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598 static void ipr_log_ext_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb,
1599 struct ipr_ext_vpd *vpd)
1600 {
1601 ipr_log_vpd_compact(prefix, hostrcb, &vpd->vpd);
1602 ipr_hcam_err(hostrcb, "%s WWN: %08X%08X\n", prefix,
1603 be32_to_cpu(vpd->wwid[0]), be32_to_cpu(vpd->wwid[1]));
1604 }
1605
1606
1607
1608
1609
1610
1611
1612
1613 static void ipr_log_ext_vpd(struct ipr_ext_vpd *vpd)
1614 {
1615 ipr_log_vpd(&vpd->vpd);
1616 ipr_err(" WWN: %08X%08X\n", be32_to_cpu(vpd->wwid[0]),
1617 be32_to_cpu(vpd->wwid[1]));
1618 }
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628 static void ipr_log_enhanced_cache_error(struct ipr_ioa_cfg *ioa_cfg,
1629 struct ipr_hostrcb *hostrcb)
1630 {
1631 struct ipr_hostrcb_type_12_error *error;
1632
1633 if (ioa_cfg->sis64)
1634 error = &hostrcb->hcam.u.error64.u.type_12_error;
1635 else
1636 error = &hostrcb->hcam.u.error.u.type_12_error;
1637
1638 ipr_err("-----Current Configuration-----\n");
1639 ipr_err("Cache Directory Card Information:\n");
1640 ipr_log_ext_vpd(&error->ioa_vpd);
1641 ipr_err("Adapter Card Information:\n");
1642 ipr_log_ext_vpd(&error->cfc_vpd);
1643
1644 ipr_err("-----Expected Configuration-----\n");
1645 ipr_err("Cache Directory Card Information:\n");
1646 ipr_log_ext_vpd(&error->ioa_last_attached_to_cfc_vpd);
1647 ipr_err("Adapter Card Information:\n");
1648 ipr_log_ext_vpd(&error->cfc_last_attached_to_ioa_vpd);
1649
1650 ipr_err("Additional IOA Data: %08X %08X %08X\n",
1651 be32_to_cpu(error->ioa_data[0]),
1652 be32_to_cpu(error->ioa_data[1]),
1653 be32_to_cpu(error->ioa_data[2]));
1654 }
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664 static void ipr_log_cache_error(struct ipr_ioa_cfg *ioa_cfg,
1665 struct ipr_hostrcb *hostrcb)
1666 {
1667 struct ipr_hostrcb_type_02_error *error =
1668 &hostrcb->hcam.u.error.u.type_02_error;
1669
1670 ipr_err("-----Current Configuration-----\n");
1671 ipr_err("Cache Directory Card Information:\n");
1672 ipr_log_vpd(&error->ioa_vpd);
1673 ipr_err("Adapter Card Information:\n");
1674 ipr_log_vpd(&error->cfc_vpd);
1675
1676 ipr_err("-----Expected Configuration-----\n");
1677 ipr_err("Cache Directory Card Information:\n");
1678 ipr_log_vpd(&error->ioa_last_attached_to_cfc_vpd);
1679 ipr_err("Adapter Card Information:\n");
1680 ipr_log_vpd(&error->cfc_last_attached_to_ioa_vpd);
1681
1682 ipr_err("Additional IOA Data: %08X %08X %08X\n",
1683 be32_to_cpu(error->ioa_data[0]),
1684 be32_to_cpu(error->ioa_data[1]),
1685 be32_to_cpu(error->ioa_data[2]));
1686 }
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696 static void ipr_log_enhanced_config_error(struct ipr_ioa_cfg *ioa_cfg,
1697 struct ipr_hostrcb *hostrcb)
1698 {
1699 int errors_logged, i;
1700 struct ipr_hostrcb_device_data_entry_enhanced *dev_entry;
1701 struct ipr_hostrcb_type_13_error *error;
1702
1703 error = &hostrcb->hcam.u.error.u.type_13_error;
1704 errors_logged = be32_to_cpu(error->errors_logged);
1705
1706 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1707 be32_to_cpu(error->errors_detected), errors_logged);
1708
1709 dev_entry = error->dev;
1710
1711 for (i = 0; i < errors_logged; i++, dev_entry++) {
1712 ipr_err_separator;
1713
1714 ipr_phys_res_err(ioa_cfg, dev_entry->dev_res_addr, "Device %d", i + 1);
1715 ipr_log_ext_vpd(&dev_entry->vpd);
1716
1717 ipr_err("-----New Device Information-----\n");
1718 ipr_log_ext_vpd(&dev_entry->new_vpd);
1719
1720 ipr_err("Cache Directory Card Information:\n");
1721 ipr_log_ext_vpd(&dev_entry->ioa_last_with_dev_vpd);
1722
1723 ipr_err("Adapter Card Information:\n");
1724 ipr_log_ext_vpd(&dev_entry->cfc_last_with_dev_vpd);
1725 }
1726 }
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736 static void ipr_log_sis64_config_error(struct ipr_ioa_cfg *ioa_cfg,
1737 struct ipr_hostrcb *hostrcb)
1738 {
1739 int errors_logged, i;
1740 struct ipr_hostrcb64_device_data_entry_enhanced *dev_entry;
1741 struct ipr_hostrcb_type_23_error *error;
1742 char buffer[IPR_MAX_RES_PATH_LENGTH];
1743
1744 error = &hostrcb->hcam.u.error64.u.type_23_error;
1745 errors_logged = be32_to_cpu(error->errors_logged);
1746
1747 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1748 be32_to_cpu(error->errors_detected), errors_logged);
1749
1750 dev_entry = error->dev;
1751
1752 for (i = 0; i < errors_logged; i++, dev_entry++) {
1753 ipr_err_separator;
1754
1755 ipr_err("Device %d : %s", i + 1,
1756 __ipr_format_res_path(dev_entry->res_path,
1757 buffer, sizeof(buffer)));
1758 ipr_log_ext_vpd(&dev_entry->vpd);
1759
1760 ipr_err("-----New Device Information-----\n");
1761 ipr_log_ext_vpd(&dev_entry->new_vpd);
1762
1763 ipr_err("Cache Directory Card Information:\n");
1764 ipr_log_ext_vpd(&dev_entry->ioa_last_with_dev_vpd);
1765
1766 ipr_err("Adapter Card Information:\n");
1767 ipr_log_ext_vpd(&dev_entry->cfc_last_with_dev_vpd);
1768 }
1769 }
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779 static void ipr_log_config_error(struct ipr_ioa_cfg *ioa_cfg,
1780 struct ipr_hostrcb *hostrcb)
1781 {
1782 int errors_logged, i;
1783 struct ipr_hostrcb_device_data_entry *dev_entry;
1784 struct ipr_hostrcb_type_03_error *error;
1785
1786 error = &hostrcb->hcam.u.error.u.type_03_error;
1787 errors_logged = be32_to_cpu(error->errors_logged);
1788
1789 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1790 be32_to_cpu(error->errors_detected), errors_logged);
1791
1792 dev_entry = error->dev;
1793
1794 for (i = 0; i < errors_logged; i++, dev_entry++) {
1795 ipr_err_separator;
1796
1797 ipr_phys_res_err(ioa_cfg, dev_entry->dev_res_addr, "Device %d", i + 1);
1798 ipr_log_vpd(&dev_entry->vpd);
1799
1800 ipr_err("-----New Device Information-----\n");
1801 ipr_log_vpd(&dev_entry->new_vpd);
1802
1803 ipr_err("Cache Directory Card Information:\n");
1804 ipr_log_vpd(&dev_entry->ioa_last_with_dev_vpd);
1805
1806 ipr_err("Adapter Card Information:\n");
1807 ipr_log_vpd(&dev_entry->cfc_last_with_dev_vpd);
1808
1809 ipr_err("Additional IOA Data: %08X %08X %08X %08X %08X\n",
1810 be32_to_cpu(dev_entry->ioa_data[0]),
1811 be32_to_cpu(dev_entry->ioa_data[1]),
1812 be32_to_cpu(dev_entry->ioa_data[2]),
1813 be32_to_cpu(dev_entry->ioa_data[3]),
1814 be32_to_cpu(dev_entry->ioa_data[4]));
1815 }
1816 }
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826 static void ipr_log_enhanced_array_error(struct ipr_ioa_cfg *ioa_cfg,
1827 struct ipr_hostrcb *hostrcb)
1828 {
1829 int i, num_entries;
1830 struct ipr_hostrcb_type_14_error *error;
1831 struct ipr_hostrcb_array_data_entry_enhanced *array_entry;
1832 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
1833
1834 error = &hostrcb->hcam.u.error.u.type_14_error;
1835
1836 ipr_err_separator;
1837
1838 ipr_err("RAID %s Array Configuration: %d:%d:%d:%d\n",
1839 error->protection_level,
1840 ioa_cfg->host->host_no,
1841 error->last_func_vset_res_addr.bus,
1842 error->last_func_vset_res_addr.target,
1843 error->last_func_vset_res_addr.lun);
1844
1845 ipr_err_separator;
1846
1847 array_entry = error->array_member;
1848 num_entries = min_t(u32, be32_to_cpu(error->num_entries),
1849 ARRAY_SIZE(error->array_member));
1850
1851 for (i = 0; i < num_entries; i++, array_entry++) {
1852 if (!memcmp(array_entry->vpd.vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
1853 continue;
1854
1855 if (be32_to_cpu(error->exposed_mode_adn) == i)
1856 ipr_err("Exposed Array Member %d:\n", i);
1857 else
1858 ipr_err("Array Member %d:\n", i);
1859
1860 ipr_log_ext_vpd(&array_entry->vpd);
1861 ipr_phys_res_err(ioa_cfg, array_entry->dev_res_addr, "Current Location");
1862 ipr_phys_res_err(ioa_cfg, array_entry->expected_dev_res_addr,
1863 "Expected Location");
1864
1865 ipr_err_separator;
1866 }
1867 }
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877 static void ipr_log_array_error(struct ipr_ioa_cfg *ioa_cfg,
1878 struct ipr_hostrcb *hostrcb)
1879 {
1880 int i;
1881 struct ipr_hostrcb_type_04_error *error;
1882 struct ipr_hostrcb_array_data_entry *array_entry;
1883 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
1884
1885 error = &hostrcb->hcam.u.error.u.type_04_error;
1886
1887 ipr_err_separator;
1888
1889 ipr_err("RAID %s Array Configuration: %d:%d:%d:%d\n",
1890 error->protection_level,
1891 ioa_cfg->host->host_no,
1892 error->last_func_vset_res_addr.bus,
1893 error->last_func_vset_res_addr.target,
1894 error->last_func_vset_res_addr.lun);
1895
1896 ipr_err_separator;
1897
1898 array_entry = error->array_member;
1899
1900 for (i = 0; i < 18; i++) {
1901 if (!memcmp(array_entry->vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
1902 continue;
1903
1904 if (be32_to_cpu(error->exposed_mode_adn) == i)
1905 ipr_err("Exposed Array Member %d:\n", i);
1906 else
1907 ipr_err("Array Member %d:\n", i);
1908
1909 ipr_log_vpd(&array_entry->vpd);
1910
1911 ipr_phys_res_err(ioa_cfg, array_entry->dev_res_addr, "Current Location");
1912 ipr_phys_res_err(ioa_cfg, array_entry->expected_dev_res_addr,
1913 "Expected Location");
1914
1915 ipr_err_separator;
1916
1917 if (i == 9)
1918 array_entry = error->array_member2;
1919 else
1920 array_entry++;
1921 }
1922 }
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933 static void ipr_log_hex_data(struct ipr_ioa_cfg *ioa_cfg, __be32 *data, int len)
1934 {
1935 int i;
1936
1937 if (len == 0)
1938 return;
1939
1940 if (ioa_cfg->log_level <= IPR_DEFAULT_LOG_LEVEL)
1941 len = min_t(int, len, IPR_DEFAULT_MAX_ERROR_DUMP);
1942
1943 for (i = 0; i < len / 4; i += 4) {
1944 ipr_err("%08X: %08X %08X %08X %08X\n", i*4,
1945 be32_to_cpu(data[i]),
1946 be32_to_cpu(data[i+1]),
1947 be32_to_cpu(data[i+2]),
1948 be32_to_cpu(data[i+3]));
1949 }
1950 }
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960 static void ipr_log_enhanced_dual_ioa_error(struct ipr_ioa_cfg *ioa_cfg,
1961 struct ipr_hostrcb *hostrcb)
1962 {
1963 struct ipr_hostrcb_type_17_error *error;
1964
1965 if (ioa_cfg->sis64)
1966 error = &hostrcb->hcam.u.error64.u.type_17_error;
1967 else
1968 error = &hostrcb->hcam.u.error.u.type_17_error;
1969
1970 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
1971 strim(error->failure_reason);
1972
1973 ipr_hcam_err(hostrcb, "%s [PRC: %08X]\n", error->failure_reason,
1974 be32_to_cpu(hostrcb->hcam.u.error.prc));
1975 ipr_log_ext_vpd_compact("Remote IOA", hostrcb, &error->vpd);
1976 ipr_log_hex_data(ioa_cfg, error->data,
1977 be32_to_cpu(hostrcb->hcam.length) -
1978 (offsetof(struct ipr_hostrcb_error, u) +
1979 offsetof(struct ipr_hostrcb_type_17_error, data)));
1980 }
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990 static void ipr_log_dual_ioa_error(struct ipr_ioa_cfg *ioa_cfg,
1991 struct ipr_hostrcb *hostrcb)
1992 {
1993 struct ipr_hostrcb_type_07_error *error;
1994
1995 error = &hostrcb->hcam.u.error.u.type_07_error;
1996 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
1997 strim(error->failure_reason);
1998
1999 ipr_hcam_err(hostrcb, "%s [PRC: %08X]\n", error->failure_reason,
2000 be32_to_cpu(hostrcb->hcam.u.error.prc));
2001 ipr_log_vpd_compact("Remote IOA", hostrcb, &error->vpd);
2002 ipr_log_hex_data(ioa_cfg, error->data,
2003 be32_to_cpu(hostrcb->hcam.length) -
2004 (offsetof(struct ipr_hostrcb_error, u) +
2005 offsetof(struct ipr_hostrcb_type_07_error, data)));
2006 }
2007
2008 static const struct {
2009 u8 active;
2010 char *desc;
2011 } path_active_desc[] = {
2012 { IPR_PATH_NO_INFO, "Path" },
2013 { IPR_PATH_ACTIVE, "Active path" },
2014 { IPR_PATH_NOT_ACTIVE, "Inactive path" }
2015 };
2016
2017 static const struct {
2018 u8 state;
2019 char *desc;
2020 } path_state_desc[] = {
2021 { IPR_PATH_STATE_NO_INFO, "has no path state information available" },
2022 { IPR_PATH_HEALTHY, "is healthy" },
2023 { IPR_PATH_DEGRADED, "is degraded" },
2024 { IPR_PATH_FAILED, "is failed" }
2025 };
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035 static void ipr_log_fabric_path(struct ipr_hostrcb *hostrcb,
2036 struct ipr_hostrcb_fabric_desc *fabric)
2037 {
2038 int i, j;
2039 u8 path_state = fabric->path_state;
2040 u8 active = path_state & IPR_PATH_ACTIVE_MASK;
2041 u8 state = path_state & IPR_PATH_STATE_MASK;
2042
2043 for (i = 0; i < ARRAY_SIZE(path_active_desc); i++) {
2044 if (path_active_desc[i].active != active)
2045 continue;
2046
2047 for (j = 0; j < ARRAY_SIZE(path_state_desc); j++) {
2048 if (path_state_desc[j].state != state)
2049 continue;
2050
2051 if (fabric->cascaded_expander == 0xff && fabric->phy == 0xff) {
2052 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d\n",
2053 path_active_desc[i].desc, path_state_desc[j].desc,
2054 fabric->ioa_port);
2055 } else if (fabric->cascaded_expander == 0xff) {
2056 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Phy=%d\n",
2057 path_active_desc[i].desc, path_state_desc[j].desc,
2058 fabric->ioa_port, fabric->phy);
2059 } else if (fabric->phy == 0xff) {
2060 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Cascade=%d\n",
2061 path_active_desc[i].desc, path_state_desc[j].desc,
2062 fabric->ioa_port, fabric->cascaded_expander);
2063 } else {
2064 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Cascade=%d, Phy=%d\n",
2065 path_active_desc[i].desc, path_state_desc[j].desc,
2066 fabric->ioa_port, fabric->cascaded_expander, fabric->phy);
2067 }
2068 return;
2069 }
2070 }
2071
2072 ipr_err("Path state=%02X IOA Port=%d Cascade=%d Phy=%d\n", path_state,
2073 fabric->ioa_port, fabric->cascaded_expander, fabric->phy);
2074 }
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084 static void ipr_log64_fabric_path(struct ipr_hostrcb *hostrcb,
2085 struct ipr_hostrcb64_fabric_desc *fabric)
2086 {
2087 int i, j;
2088 u8 path_state = fabric->path_state;
2089 u8 active = path_state & IPR_PATH_ACTIVE_MASK;
2090 u8 state = path_state & IPR_PATH_STATE_MASK;
2091 char buffer[IPR_MAX_RES_PATH_LENGTH];
2092
2093 for (i = 0; i < ARRAY_SIZE(path_active_desc); i++) {
2094 if (path_active_desc[i].active != active)
2095 continue;
2096
2097 for (j = 0; j < ARRAY_SIZE(path_state_desc); j++) {
2098 if (path_state_desc[j].state != state)
2099 continue;
2100
2101 ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s\n",
2102 path_active_desc[i].desc, path_state_desc[j].desc,
2103 ipr_format_res_path(hostrcb->ioa_cfg,
2104 fabric->res_path,
2105 buffer, sizeof(buffer)));
2106 return;
2107 }
2108 }
2109
2110 ipr_err("Path state=%02X Resource Path=%s\n", path_state,
2111 ipr_format_res_path(hostrcb->ioa_cfg, fabric->res_path,
2112 buffer, sizeof(buffer)));
2113 }
2114
2115 static const struct {
2116 u8 type;
2117 char *desc;
2118 } path_type_desc[] = {
2119 { IPR_PATH_CFG_IOA_PORT, "IOA port" },
2120 { IPR_PATH_CFG_EXP_PORT, "Expander port" },
2121 { IPR_PATH_CFG_DEVICE_PORT, "Device port" },
2122 { IPR_PATH_CFG_DEVICE_LUN, "Device LUN" }
2123 };
2124
2125 static const struct {
2126 u8 status;
2127 char *desc;
2128 } path_status_desc[] = {
2129 { IPR_PATH_CFG_NO_PROB, "Functional" },
2130 { IPR_PATH_CFG_DEGRADED, "Degraded" },
2131 { IPR_PATH_CFG_FAILED, "Failed" },
2132 { IPR_PATH_CFG_SUSPECT, "Suspect" },
2133 { IPR_PATH_NOT_DETECTED, "Missing" },
2134 { IPR_PATH_INCORRECT_CONN, "Incorrectly connected" }
2135 };
2136
2137 static const char *link_rate[] = {
2138 "unknown",
2139 "disabled",
2140 "phy reset problem",
2141 "spinup hold",
2142 "port selector",
2143 "unknown",
2144 "unknown",
2145 "unknown",
2146 "1.5Gbps",
2147 "3.0Gbps",
2148 "unknown",
2149 "unknown",
2150 "unknown",
2151 "unknown",
2152 "unknown",
2153 "unknown"
2154 };
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164 static void ipr_log_path_elem(struct ipr_hostrcb *hostrcb,
2165 struct ipr_hostrcb_config_element *cfg)
2166 {
2167 int i, j;
2168 u8 type = cfg->type_status & IPR_PATH_CFG_TYPE_MASK;
2169 u8 status = cfg->type_status & IPR_PATH_CFG_STATUS_MASK;
2170
2171 if (type == IPR_PATH_CFG_NOT_EXIST)
2172 return;
2173
2174 for (i = 0; i < ARRAY_SIZE(path_type_desc); i++) {
2175 if (path_type_desc[i].type != type)
2176 continue;
2177
2178 for (j = 0; j < ARRAY_SIZE(path_status_desc); j++) {
2179 if (path_status_desc[j].status != status)
2180 continue;
2181
2182 if (type == IPR_PATH_CFG_IOA_PORT) {
2183 ipr_hcam_err(hostrcb, "%s %s: Phy=%d, Link rate=%s, WWN=%08X%08X\n",
2184 path_status_desc[j].desc, path_type_desc[i].desc,
2185 cfg->phy, link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2186 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2187 } else {
2188 if (cfg->cascaded_expander == 0xff && cfg->phy == 0xff) {
2189 ipr_hcam_err(hostrcb, "%s %s: Link rate=%s, WWN=%08X%08X\n",
2190 path_status_desc[j].desc, path_type_desc[i].desc,
2191 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2192 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2193 } else if (cfg->cascaded_expander == 0xff) {
2194 ipr_hcam_err(hostrcb, "%s %s: Phy=%d, Link rate=%s, "
2195 "WWN=%08X%08X\n", path_status_desc[j].desc,
2196 path_type_desc[i].desc, cfg->phy,
2197 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2198 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2199 } else if (cfg->phy == 0xff) {
2200 ipr_hcam_err(hostrcb, "%s %s: Cascade=%d, Link rate=%s, "
2201 "WWN=%08X%08X\n", path_status_desc[j].desc,
2202 path_type_desc[i].desc, cfg->cascaded_expander,
2203 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2204 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2205 } else {
2206 ipr_hcam_err(hostrcb, "%s %s: Cascade=%d, Phy=%d, Link rate=%s "
2207 "WWN=%08X%08X\n", path_status_desc[j].desc,
2208 path_type_desc[i].desc, cfg->cascaded_expander, cfg->phy,
2209 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2210 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2211 }
2212 }
2213 return;
2214 }
2215 }
2216
2217 ipr_hcam_err(hostrcb, "Path element=%02X: Cascade=%d Phy=%d Link rate=%s "
2218 "WWN=%08X%08X\n", cfg->type_status, cfg->cascaded_expander, cfg->phy,
2219 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2220 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2221 }
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231 static void ipr_log64_path_elem(struct ipr_hostrcb *hostrcb,
2232 struct ipr_hostrcb64_config_element *cfg)
2233 {
2234 int i, j;
2235 u8 desc_id = cfg->descriptor_id & IPR_DESCRIPTOR_MASK;
2236 u8 type = cfg->type_status & IPR_PATH_CFG_TYPE_MASK;
2237 u8 status = cfg->type_status & IPR_PATH_CFG_STATUS_MASK;
2238 char buffer[IPR_MAX_RES_PATH_LENGTH];
2239
2240 if (type == IPR_PATH_CFG_NOT_EXIST || desc_id != IPR_DESCRIPTOR_SIS64)
2241 return;
2242
2243 for (i = 0; i < ARRAY_SIZE(path_type_desc); i++) {
2244 if (path_type_desc[i].type != type)
2245 continue;
2246
2247 for (j = 0; j < ARRAY_SIZE(path_status_desc); j++) {
2248 if (path_status_desc[j].status != status)
2249 continue;
2250
2251 ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s, Link rate=%s, WWN=%08X%08X\n",
2252 path_status_desc[j].desc, path_type_desc[i].desc,
2253 ipr_format_res_path(hostrcb->ioa_cfg,
2254 cfg->res_path, buffer, sizeof(buffer)),
2255 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2256 be32_to_cpu(cfg->wwid[0]),
2257 be32_to_cpu(cfg->wwid[1]));
2258 return;
2259 }
2260 }
2261 ipr_hcam_err(hostrcb, "Path element=%02X: Resource Path=%s, Link rate=%s "
2262 "WWN=%08X%08X\n", cfg->type_status,
2263 ipr_format_res_path(hostrcb->ioa_cfg,
2264 cfg->res_path, buffer, sizeof(buffer)),
2265 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2266 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2267 }
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277 static void ipr_log_fabric_error(struct ipr_ioa_cfg *ioa_cfg,
2278 struct ipr_hostrcb *hostrcb)
2279 {
2280 struct ipr_hostrcb_type_20_error *error;
2281 struct ipr_hostrcb_fabric_desc *fabric;
2282 struct ipr_hostrcb_config_element *cfg;
2283 int i, add_len;
2284
2285 error = &hostrcb->hcam.u.error.u.type_20_error;
2286 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2287 ipr_hcam_err(hostrcb, "%s\n", error->failure_reason);
2288
2289 add_len = be32_to_cpu(hostrcb->hcam.length) -
2290 (offsetof(struct ipr_hostrcb_error, u) +
2291 offsetof(struct ipr_hostrcb_type_20_error, desc));
2292
2293 for (i = 0, fabric = error->desc; i < error->num_entries; i++) {
2294 ipr_log_fabric_path(hostrcb, fabric);
2295 for_each_fabric_cfg(fabric, cfg)
2296 ipr_log_path_elem(hostrcb, cfg);
2297
2298 add_len -= be16_to_cpu(fabric->length);
2299 fabric = (struct ipr_hostrcb_fabric_desc *)
2300 ((unsigned long)fabric + be16_to_cpu(fabric->length));
2301 }
2302
2303 ipr_log_hex_data(ioa_cfg, (__be32 *)fabric, add_len);
2304 }
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314 static void ipr_log_sis64_array_error(struct ipr_ioa_cfg *ioa_cfg,
2315 struct ipr_hostrcb *hostrcb)
2316 {
2317 int i, num_entries;
2318 struct ipr_hostrcb_type_24_error *error;
2319 struct ipr_hostrcb64_array_data_entry *array_entry;
2320 char buffer[IPR_MAX_RES_PATH_LENGTH];
2321 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
2322
2323 error = &hostrcb->hcam.u.error64.u.type_24_error;
2324
2325 ipr_err_separator;
2326
2327 ipr_err("RAID %s Array Configuration: %s\n",
2328 error->protection_level,
2329 ipr_format_res_path(ioa_cfg, error->last_res_path,
2330 buffer, sizeof(buffer)));
2331
2332 ipr_err_separator;
2333
2334 array_entry = error->array_member;
2335 num_entries = min_t(u32, error->num_entries,
2336 ARRAY_SIZE(error->array_member));
2337
2338 for (i = 0; i < num_entries; i++, array_entry++) {
2339
2340 if (!memcmp(array_entry->vpd.vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
2341 continue;
2342
2343 if (error->exposed_mode_adn == i)
2344 ipr_err("Exposed Array Member %d:\n", i);
2345 else
2346 ipr_err("Array Member %d:\n", i);
2347
2348 ipr_err("Array Member %d:\n", i);
2349 ipr_log_ext_vpd(&array_entry->vpd);
2350 ipr_err("Current Location: %s\n",
2351 ipr_format_res_path(ioa_cfg, array_entry->res_path,
2352 buffer, sizeof(buffer)));
2353 ipr_err("Expected Location: %s\n",
2354 ipr_format_res_path(ioa_cfg,
2355 array_entry->expected_res_path,
2356 buffer, sizeof(buffer)));
2357
2358 ipr_err_separator;
2359 }
2360 }
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370 static void ipr_log_sis64_fabric_error(struct ipr_ioa_cfg *ioa_cfg,
2371 struct ipr_hostrcb *hostrcb)
2372 {
2373 struct ipr_hostrcb_type_30_error *error;
2374 struct ipr_hostrcb64_fabric_desc *fabric;
2375 struct ipr_hostrcb64_config_element *cfg;
2376 int i, add_len;
2377
2378 error = &hostrcb->hcam.u.error64.u.type_30_error;
2379
2380 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2381 ipr_hcam_err(hostrcb, "%s\n", error->failure_reason);
2382
2383 add_len = be32_to_cpu(hostrcb->hcam.length) -
2384 (offsetof(struct ipr_hostrcb64_error, u) +
2385 offsetof(struct ipr_hostrcb_type_30_error, desc));
2386
2387 for (i = 0, fabric = error->desc; i < error->num_entries; i++) {
2388 ipr_log64_fabric_path(hostrcb, fabric);
2389 for_each_fabric_cfg(fabric, cfg)
2390 ipr_log64_path_elem(hostrcb, cfg);
2391
2392 add_len -= be16_to_cpu(fabric->length);
2393 fabric = (struct ipr_hostrcb64_fabric_desc *)
2394 ((unsigned long)fabric + be16_to_cpu(fabric->length));
2395 }
2396
2397 ipr_log_hex_data(ioa_cfg, (__be32 *)fabric, add_len);
2398 }
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408 static void ipr_log_sis64_service_required_error(struct ipr_ioa_cfg *ioa_cfg,
2409 struct ipr_hostrcb *hostrcb)
2410 {
2411 struct ipr_hostrcb_type_41_error *error;
2412
2413 error = &hostrcb->hcam.u.error64.u.type_41_error;
2414
2415 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2416 ipr_err("Primary Failure Reason: %s\n", error->failure_reason);
2417 ipr_log_hex_data(ioa_cfg, error->data,
2418 be32_to_cpu(hostrcb->hcam.length) -
2419 (offsetof(struct ipr_hostrcb_error, u) +
2420 offsetof(struct ipr_hostrcb_type_41_error, data)));
2421 }
2422
2423
2424
2425
2426
2427
2428
2429
2430 static void ipr_log_generic_error(struct ipr_ioa_cfg *ioa_cfg,
2431 struct ipr_hostrcb *hostrcb)
2432 {
2433 ipr_log_hex_data(ioa_cfg, hostrcb->hcam.u.raw.data,
2434 be32_to_cpu(hostrcb->hcam.length));
2435 }
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445 static void ipr_log_sis64_device_error(struct ipr_ioa_cfg *ioa_cfg,
2446 struct ipr_hostrcb *hostrcb)
2447 {
2448 struct ipr_hostrcb_type_21_error *error;
2449 char buffer[IPR_MAX_RES_PATH_LENGTH];
2450
2451 error = &hostrcb->hcam.u.error64.u.type_21_error;
2452
2453 ipr_err("-----Failing Device Information-----\n");
2454 ipr_err("World Wide Unique ID: %08X%08X%08X%08X\n",
2455 be32_to_cpu(error->wwn[0]), be32_to_cpu(error->wwn[1]),
2456 be32_to_cpu(error->wwn[2]), be32_to_cpu(error->wwn[3]));
2457 ipr_err("Device Resource Path: %s\n",
2458 __ipr_format_res_path(error->res_path,
2459 buffer, sizeof(buffer)));
2460 error->primary_problem_desc[sizeof(error->primary_problem_desc) - 1] = '\0';
2461 error->second_problem_desc[sizeof(error->second_problem_desc) - 1] = '\0';
2462 ipr_err("Primary Problem Description: %s\n", error->primary_problem_desc);
2463 ipr_err("Secondary Problem Description: %s\n", error->second_problem_desc);
2464 ipr_err("SCSI Sense Data:\n");
2465 ipr_log_hex_data(ioa_cfg, error->sense_data, sizeof(error->sense_data));
2466 ipr_err("SCSI Command Descriptor Block: \n");
2467 ipr_log_hex_data(ioa_cfg, error->cdb, sizeof(error->cdb));
2468
2469 ipr_err("Additional IOA Data:\n");
2470 ipr_log_hex_data(ioa_cfg, error->ioa_data, be32_to_cpu(error->length_of_error));
2471 }
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484 static u32 ipr_get_error(u32 ioasc)
2485 {
2486 int i;
2487
2488 for (i = 0; i < ARRAY_SIZE(ipr_error_table); i++)
2489 if (ipr_error_table[i].ioasc == (ioasc & IPR_IOASC_IOASC_MASK))
2490 return i;
2491
2492 return 0;
2493 }
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505 static void ipr_handle_log_data(struct ipr_ioa_cfg *ioa_cfg,
2506 struct ipr_hostrcb *hostrcb)
2507 {
2508 u32 ioasc;
2509 int error_index;
2510 struct ipr_hostrcb_type_21_error *error;
2511
2512 if (hostrcb->hcam.notify_type != IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY)
2513 return;
2514
2515 if (hostrcb->hcam.notifications_lost == IPR_HOST_RCB_NOTIFICATIONS_LOST)
2516 dev_err(&ioa_cfg->pdev->dev, "Error notifications lost\n");
2517
2518 if (ioa_cfg->sis64)
2519 ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc);
2520 else
2521 ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
2522
2523 if (!ioa_cfg->sis64 && (ioasc == IPR_IOASC_BUS_WAS_RESET ||
2524 ioasc == IPR_IOASC_BUS_WAS_RESET_BY_OTHER)) {
2525
2526 scsi_report_bus_reset(ioa_cfg->host,
2527 hostrcb->hcam.u.error.fd_res_addr.bus);
2528 }
2529
2530 error_index = ipr_get_error(ioasc);
2531
2532 if (!ipr_error_table[error_index].log_hcam)
2533 return;
2534
2535 if (ioasc == IPR_IOASC_HW_CMD_FAILED &&
2536 hostrcb->hcam.overlay_id == IPR_HOST_RCB_OVERLAY_ID_21) {
2537 error = &hostrcb->hcam.u.error64.u.type_21_error;
2538
2539 if (((be32_to_cpu(error->sense_data[0]) & 0x0000ff00) >> 8) == ILLEGAL_REQUEST &&
2540 ioa_cfg->log_level <= IPR_DEFAULT_LOG_LEVEL)
2541 return;
2542 }
2543
2544 ipr_hcam_err(hostrcb, "%s\n", ipr_error_table[error_index].error);
2545
2546
2547 ioa_cfg->errors_logged++;
2548
2549 if (ioa_cfg->log_level < ipr_error_table[error_index].log_hcam)
2550 return;
2551 if (be32_to_cpu(hostrcb->hcam.length) > sizeof(hostrcb->hcam.u.raw))
2552 hostrcb->hcam.length = cpu_to_be32(sizeof(hostrcb->hcam.u.raw));
2553
2554 switch (hostrcb->hcam.overlay_id) {
2555 case IPR_HOST_RCB_OVERLAY_ID_2:
2556 ipr_log_cache_error(ioa_cfg, hostrcb);
2557 break;
2558 case IPR_HOST_RCB_OVERLAY_ID_3:
2559 ipr_log_config_error(ioa_cfg, hostrcb);
2560 break;
2561 case IPR_HOST_RCB_OVERLAY_ID_4:
2562 case IPR_HOST_RCB_OVERLAY_ID_6:
2563 ipr_log_array_error(ioa_cfg, hostrcb);
2564 break;
2565 case IPR_HOST_RCB_OVERLAY_ID_7:
2566 ipr_log_dual_ioa_error(ioa_cfg, hostrcb);
2567 break;
2568 case IPR_HOST_RCB_OVERLAY_ID_12:
2569 ipr_log_enhanced_cache_error(ioa_cfg, hostrcb);
2570 break;
2571 case IPR_HOST_RCB_OVERLAY_ID_13:
2572 ipr_log_enhanced_config_error(ioa_cfg, hostrcb);
2573 break;
2574 case IPR_HOST_RCB_OVERLAY_ID_14:
2575 case IPR_HOST_RCB_OVERLAY_ID_16:
2576 ipr_log_enhanced_array_error(ioa_cfg, hostrcb);
2577 break;
2578 case IPR_HOST_RCB_OVERLAY_ID_17:
2579 ipr_log_enhanced_dual_ioa_error(ioa_cfg, hostrcb);
2580 break;
2581 case IPR_HOST_RCB_OVERLAY_ID_20:
2582 ipr_log_fabric_error(ioa_cfg, hostrcb);
2583 break;
2584 case IPR_HOST_RCB_OVERLAY_ID_21:
2585 ipr_log_sis64_device_error(ioa_cfg, hostrcb);
2586 break;
2587 case IPR_HOST_RCB_OVERLAY_ID_23:
2588 ipr_log_sis64_config_error(ioa_cfg, hostrcb);
2589 break;
2590 case IPR_HOST_RCB_OVERLAY_ID_24:
2591 case IPR_HOST_RCB_OVERLAY_ID_26:
2592 ipr_log_sis64_array_error(ioa_cfg, hostrcb);
2593 break;
2594 case IPR_HOST_RCB_OVERLAY_ID_30:
2595 ipr_log_sis64_fabric_error(ioa_cfg, hostrcb);
2596 break;
2597 case IPR_HOST_RCB_OVERLAY_ID_41:
2598 ipr_log_sis64_service_required_error(ioa_cfg, hostrcb);
2599 break;
2600 case IPR_HOST_RCB_OVERLAY_ID_1:
2601 case IPR_HOST_RCB_OVERLAY_ID_DEFAULT:
2602 default:
2603 ipr_log_generic_error(ioa_cfg, hostrcb);
2604 break;
2605 }
2606 }
2607
2608 static struct ipr_hostrcb *ipr_get_free_hostrcb(struct ipr_ioa_cfg *ioa)
2609 {
2610 struct ipr_hostrcb *hostrcb;
2611
2612 hostrcb = list_first_entry_or_null(&ioa->hostrcb_free_q,
2613 struct ipr_hostrcb, queue);
2614
2615 if (unlikely(!hostrcb)) {
2616 dev_info(&ioa->pdev->dev, "Reclaiming async error buffers.");
2617 hostrcb = list_first_entry_or_null(&ioa->hostrcb_report_q,
2618 struct ipr_hostrcb, queue);
2619 }
2620
2621 list_del_init(&hostrcb->queue);
2622 return hostrcb;
2623 }
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636 static void ipr_process_error(struct ipr_cmnd *ipr_cmd)
2637 {
2638 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2639 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb;
2640 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
2641 u32 fd_ioasc;
2642
2643 if (ioa_cfg->sis64)
2644 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc);
2645 else
2646 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
2647
2648 list_del_init(&hostrcb->queue);
2649 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
2650
2651 if (!ioasc) {
2652 ipr_handle_log_data(ioa_cfg, hostrcb);
2653 if (fd_ioasc == IPR_IOASC_NR_IOA_RESET_REQUIRED)
2654 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_ABBREV);
2655 } else if (ioasc != IPR_IOASC_IOA_WAS_RESET &&
2656 ioasc != IPR_IOASC_ABORTED_CMD_TERM_BY_HOST) {
2657 dev_err(&ioa_cfg->pdev->dev,
2658 "Host RCB failed with IOASC: 0x%08X\n", ioasc);
2659 }
2660
2661 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_report_q);
2662 schedule_work(&ioa_cfg->work_q);
2663 hostrcb = ipr_get_free_hostrcb(ioa_cfg);
2664
2665 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_LOG_DATA, hostrcb);
2666 }
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678 static void ipr_timeout(struct timer_list *t)
2679 {
2680 struct ipr_cmnd *ipr_cmd = from_timer(ipr_cmd, t, timer);
2681 unsigned long lock_flags = 0;
2682 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2683
2684 ENTER;
2685 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2686
2687 ioa_cfg->errors_logged++;
2688 dev_err(&ioa_cfg->pdev->dev,
2689 "Adapter being reset due to command timeout.\n");
2690
2691 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
2692 ioa_cfg->sdt_state = GET_DUMP;
2693
2694 if (!ioa_cfg->in_reset_reload || ioa_cfg->reset_cmd == ipr_cmd)
2695 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
2696
2697 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2698 LEAVE;
2699 }
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711 static void ipr_oper_timeout(struct timer_list *t)
2712 {
2713 struct ipr_cmnd *ipr_cmd = from_timer(ipr_cmd, t, timer);
2714 unsigned long lock_flags = 0;
2715 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2716
2717 ENTER;
2718 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2719
2720 ioa_cfg->errors_logged++;
2721 dev_err(&ioa_cfg->pdev->dev,
2722 "Adapter timed out transitioning to operational.\n");
2723
2724 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
2725 ioa_cfg->sdt_state = GET_DUMP;
2726
2727 if (!ioa_cfg->in_reset_reload || ioa_cfg->reset_cmd == ipr_cmd) {
2728 if (ipr_fastfail)
2729 ioa_cfg->reset_retries += IPR_NUM_RESET_RELOAD_RETRIES;
2730 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
2731 }
2732
2733 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2734 LEAVE;
2735 }
2736
2737
2738
2739
2740
2741
2742
2743
2744 static const struct ipr_ses_table_entry *
2745 ipr_find_ses_entry(struct ipr_resource_entry *res)
2746 {
2747 int i, j, matches;
2748 struct ipr_std_inq_vpids *vpids;
2749 const struct ipr_ses_table_entry *ste = ipr_ses_table;
2750
2751 for (i = 0; i < ARRAY_SIZE(ipr_ses_table); i++, ste++) {
2752 for (j = 0, matches = 0; j < IPR_PROD_ID_LEN; j++) {
2753 if (ste->compare_product_id_byte[j] == 'X') {
2754 vpids = &res->std_inq_data.vpids;
2755 if (vpids->product_id[j] == ste->product_id[j])
2756 matches++;
2757 else
2758 break;
2759 } else
2760 matches++;
2761 }
2762
2763 if (matches == IPR_PROD_ID_LEN)
2764 return ste;
2765 }
2766
2767 return NULL;
2768 }
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782 static u32 ipr_get_max_scsi_speed(struct ipr_ioa_cfg *ioa_cfg, u8 bus, u8 bus_width)
2783 {
2784 struct ipr_resource_entry *res;
2785 const struct ipr_ses_table_entry *ste;
2786 u32 max_xfer_rate = IPR_MAX_SCSI_RATE(bus_width);
2787
2788
2789 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
2790 if (!(IPR_IS_SES_DEVICE(res->std_inq_data)))
2791 continue;
2792
2793 if (bus != res->bus)
2794 continue;
2795
2796 if (!(ste = ipr_find_ses_entry(res)))
2797 continue;
2798
2799 max_xfer_rate = (ste->max_bus_speed_limit * 10) / (bus_width / 8);
2800 }
2801
2802 return max_xfer_rate;
2803 }
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815 static int ipr_wait_iodbg_ack(struct ipr_ioa_cfg *ioa_cfg, int max_delay)
2816 {
2817 volatile u32 pcii_reg;
2818 int delay = 1;
2819
2820
2821 while (delay < max_delay) {
2822 pcii_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
2823
2824 if (pcii_reg & IPR_PCII_IO_DEBUG_ACKNOWLEDGE)
2825 return 0;
2826
2827
2828 if ((delay / 1000) > MAX_UDELAY_MS)
2829 mdelay(delay / 1000);
2830 else
2831 udelay(delay);
2832
2833 delay += delay;
2834 }
2835 return -EIO;
2836 }
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848 static int ipr_get_sis64_dump_data_section(struct ipr_ioa_cfg *ioa_cfg,
2849 u32 start_addr,
2850 __be32 *dest, u32 length_in_words)
2851 {
2852 int i;
2853
2854 for (i = 0; i < length_in_words; i++) {
2855 writel(start_addr+(i*4), ioa_cfg->regs.dump_addr_reg);
2856 *dest = cpu_to_be32(readl(ioa_cfg->regs.dump_data_reg));
2857 dest++;
2858 }
2859
2860 return 0;
2861 }
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873 static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg,
2874 u32 start_addr,
2875 __be32 *dest, u32 length_in_words)
2876 {
2877 volatile u32 temp_pcii_reg;
2878 int i, delay = 0;
2879
2880 if (ioa_cfg->sis64)
2881 return ipr_get_sis64_dump_data_section(ioa_cfg, start_addr,
2882 dest, length_in_words);
2883
2884
2885 writel((IPR_UPROCI_RESET_ALERT | IPR_UPROCI_IO_DEBUG_ALERT),
2886 ioa_cfg->regs.set_uproc_interrupt_reg32);
2887
2888
2889 if (ipr_wait_iodbg_ack(ioa_cfg,
2890 IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC)) {
2891 dev_err(&ioa_cfg->pdev->dev,
2892 "IOA dump long data transfer timeout\n");
2893 return -EIO;
2894 }
2895
2896
2897 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2898 ioa_cfg->regs.clr_interrupt_reg);
2899
2900
2901 writel(start_addr, ioa_cfg->ioa_mailbox);
2902
2903
2904 writel(IPR_UPROCI_RESET_ALERT,
2905 ioa_cfg->regs.clr_uproc_interrupt_reg32);
2906
2907 for (i = 0; i < length_in_words; i++) {
2908
2909 if (ipr_wait_iodbg_ack(ioa_cfg,
2910 IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC)) {
2911 dev_err(&ioa_cfg->pdev->dev,
2912 "IOA dump short data transfer timeout\n");
2913 return -EIO;
2914 }
2915
2916
2917 *dest = cpu_to_be32(readl(ioa_cfg->ioa_mailbox));
2918 dest++;
2919
2920
2921 if (i < (length_in_words - 1)) {
2922
2923 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2924 ioa_cfg->regs.clr_interrupt_reg);
2925 }
2926 }
2927
2928
2929 writel(IPR_UPROCI_RESET_ALERT,
2930 ioa_cfg->regs.set_uproc_interrupt_reg32);
2931
2932 writel(IPR_UPROCI_IO_DEBUG_ALERT,
2933 ioa_cfg->regs.clr_uproc_interrupt_reg32);
2934
2935
2936 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2937 ioa_cfg->regs.clr_interrupt_reg);
2938
2939
2940 while (delay < IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC) {
2941 temp_pcii_reg =
2942 readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
2943
2944 if (!(temp_pcii_reg & IPR_UPROCI_RESET_ALERT))
2945 return 0;
2946
2947 udelay(10);
2948 delay += 10;
2949 }
2950
2951 return 0;
2952 }
2953
2954 #ifdef CONFIG_SCSI_IPR_DUMP
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966 static int ipr_sdt_copy(struct ipr_ioa_cfg *ioa_cfg,
2967 unsigned long pci_address, u32 length)
2968 {
2969 int bytes_copied = 0;
2970 int cur_len, rc, rem_len, rem_page_len, max_dump_size;
2971 __be32 *page;
2972 unsigned long lock_flags = 0;
2973 struct ipr_ioa_dump *ioa_dump = &ioa_cfg->dump->ioa_dump;
2974
2975 if (ioa_cfg->sis64)
2976 max_dump_size = IPR_FMT3_MAX_IOA_DUMP_SIZE;
2977 else
2978 max_dump_size = IPR_FMT2_MAX_IOA_DUMP_SIZE;
2979
2980 while (bytes_copied < length &&
2981 (ioa_dump->hdr.len + bytes_copied) < max_dump_size) {
2982 if (ioa_dump->page_offset >= PAGE_SIZE ||
2983 ioa_dump->page_offset == 0) {
2984 page = (__be32 *)__get_free_page(GFP_ATOMIC);
2985
2986 if (!page) {
2987 ipr_trace;
2988 return bytes_copied;
2989 }
2990
2991 ioa_dump->page_offset = 0;
2992 ioa_dump->ioa_data[ioa_dump->next_page_index] = page;
2993 ioa_dump->next_page_index++;
2994 } else
2995 page = ioa_dump->ioa_data[ioa_dump->next_page_index - 1];
2996
2997 rem_len = length - bytes_copied;
2998 rem_page_len = PAGE_SIZE - ioa_dump->page_offset;
2999 cur_len = min(rem_len, rem_page_len);
3000
3001 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3002 if (ioa_cfg->sdt_state == ABORT_DUMP) {
3003 rc = -EIO;
3004 } else {
3005 rc = ipr_get_ldump_data_section(ioa_cfg,
3006 pci_address + bytes_copied,
3007 &page[ioa_dump->page_offset / 4],
3008 (cur_len / sizeof(u32)));
3009 }
3010 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3011
3012 if (!rc) {
3013 ioa_dump->page_offset += cur_len;
3014 bytes_copied += cur_len;
3015 } else {
3016 ipr_trace;
3017 break;
3018 }
3019 schedule();
3020 }
3021
3022 return bytes_copied;
3023 }
3024
3025
3026
3027
3028
3029
3030
3031
3032 static void ipr_init_dump_entry_hdr(struct ipr_dump_entry_header *hdr)
3033 {
3034 hdr->eye_catcher = IPR_DUMP_EYE_CATCHER;
3035 hdr->num_elems = 1;
3036 hdr->offset = sizeof(*hdr);
3037 hdr->status = IPR_DUMP_STATUS_SUCCESS;
3038 }
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048 static void ipr_dump_ioa_type_data(struct ipr_ioa_cfg *ioa_cfg,
3049 struct ipr_driver_dump *driver_dump)
3050 {
3051 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
3052
3053 ipr_init_dump_entry_hdr(&driver_dump->ioa_type_entry.hdr);
3054 driver_dump->ioa_type_entry.hdr.len =
3055 sizeof(struct ipr_dump_ioa_type_entry) -
3056 sizeof(struct ipr_dump_entry_header);
3057 driver_dump->ioa_type_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
3058 driver_dump->ioa_type_entry.hdr.id = IPR_DUMP_DRIVER_TYPE_ID;
3059 driver_dump->ioa_type_entry.type = ioa_cfg->type;
3060 driver_dump->ioa_type_entry.fw_version = (ucode_vpd->major_release << 24) |
3061 (ucode_vpd->card_type << 16) | (ucode_vpd->minor_release[0] << 8) |
3062 ucode_vpd->minor_release[1];
3063 driver_dump->hdr.num_entries++;
3064 }
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074 static void ipr_dump_version_data(struct ipr_ioa_cfg *ioa_cfg,
3075 struct ipr_driver_dump *driver_dump)
3076 {
3077 ipr_init_dump_entry_hdr(&driver_dump->version_entry.hdr);
3078 driver_dump->version_entry.hdr.len =
3079 sizeof(struct ipr_dump_version_entry) -
3080 sizeof(struct ipr_dump_entry_header);
3081 driver_dump->version_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_ASCII;
3082 driver_dump->version_entry.hdr.id = IPR_DUMP_DRIVER_VERSION_ID;
3083 strcpy(driver_dump->version_entry.version, IPR_DRIVER_VERSION);
3084 driver_dump->hdr.num_entries++;
3085 }
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095 static void ipr_dump_trace_data(struct ipr_ioa_cfg *ioa_cfg,
3096 struct ipr_driver_dump *driver_dump)
3097 {
3098 ipr_init_dump_entry_hdr(&driver_dump->trace_entry.hdr);
3099 driver_dump->trace_entry.hdr.len =
3100 sizeof(struct ipr_dump_trace_entry) -
3101 sizeof(struct ipr_dump_entry_header);
3102 driver_dump->trace_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
3103 driver_dump->trace_entry.hdr.id = IPR_DUMP_TRACE_ID;
3104 memcpy(driver_dump->trace_entry.trace, ioa_cfg->trace, IPR_TRACE_SIZE);
3105 driver_dump->hdr.num_entries++;
3106 }
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116 static void ipr_dump_location_data(struct ipr_ioa_cfg *ioa_cfg,
3117 struct ipr_driver_dump *driver_dump)
3118 {
3119 ipr_init_dump_entry_hdr(&driver_dump->location_entry.hdr);
3120 driver_dump->location_entry.hdr.len =
3121 sizeof(struct ipr_dump_location_entry) -
3122 sizeof(struct ipr_dump_entry_header);
3123 driver_dump->location_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_ASCII;
3124 driver_dump->location_entry.hdr.id = IPR_DUMP_LOCATION_ID;
3125 strcpy(driver_dump->location_entry.location, dev_name(&ioa_cfg->pdev->dev));
3126 driver_dump->hdr.num_entries++;
3127 }
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137 static void ipr_get_ioa_dump(struct ipr_ioa_cfg *ioa_cfg, struct ipr_dump *dump)
3138 {
3139 unsigned long start_addr, sdt_word;
3140 unsigned long lock_flags = 0;
3141 struct ipr_driver_dump *driver_dump = &dump->driver_dump;
3142 struct ipr_ioa_dump *ioa_dump = &dump->ioa_dump;
3143 u32 num_entries, max_num_entries, start_off, end_off;
3144 u32 max_dump_size, bytes_to_copy, bytes_copied, rc;
3145 struct ipr_sdt *sdt;
3146 int valid = 1;
3147 int i;
3148
3149 ENTER;
3150
3151 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3152
3153 if (ioa_cfg->sdt_state != READ_DUMP) {
3154 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3155 return;
3156 }
3157
3158 if (ioa_cfg->sis64) {
3159 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3160 ssleep(IPR_DUMP_DELAY_SECONDS);
3161 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3162 }
3163
3164 start_addr = readl(ioa_cfg->ioa_mailbox);
3165
3166 if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(start_addr)) {
3167 dev_err(&ioa_cfg->pdev->dev,
3168 "Invalid dump table format: %lx\n", start_addr);
3169 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3170 return;
3171 }
3172
3173 dev_err(&ioa_cfg->pdev->dev, "Dump of IOA initiated\n");
3174
3175 driver_dump->hdr.eye_catcher = IPR_DUMP_EYE_CATCHER;
3176
3177
3178 driver_dump->hdr.len = sizeof(struct ipr_driver_dump);
3179 driver_dump->hdr.num_entries = 1;
3180 driver_dump->hdr.first_entry_offset = sizeof(struct ipr_dump_header);
3181 driver_dump->hdr.status = IPR_DUMP_STATUS_SUCCESS;
3182 driver_dump->hdr.os = IPR_DUMP_OS_LINUX;
3183 driver_dump->hdr.driver_name = IPR_DUMP_DRIVER_NAME;
3184
3185 ipr_dump_version_data(ioa_cfg, driver_dump);
3186 ipr_dump_location_data(ioa_cfg, driver_dump);
3187 ipr_dump_ioa_type_data(ioa_cfg, driver_dump);
3188 ipr_dump_trace_data(ioa_cfg, driver_dump);
3189
3190
3191 driver_dump->hdr.len += sizeof(struct ipr_dump_entry_header);
3192
3193
3194 ipr_init_dump_entry_hdr(&ioa_dump->hdr);
3195 ioa_dump->hdr.len = 0;
3196 ioa_dump->hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
3197 ioa_dump->hdr.id = IPR_DUMP_IOA_DUMP_ID;
3198
3199
3200
3201
3202
3203 sdt = &ioa_dump->sdt;
3204
3205 if (ioa_cfg->sis64) {
3206 max_num_entries = IPR_FMT3_NUM_SDT_ENTRIES;
3207 max_dump_size = IPR_FMT3_MAX_IOA_DUMP_SIZE;
3208 } else {
3209 max_num_entries = IPR_FMT2_NUM_SDT_ENTRIES;
3210 max_dump_size = IPR_FMT2_MAX_IOA_DUMP_SIZE;
3211 }
3212
3213 bytes_to_copy = offsetof(struct ipr_sdt, entry) +
3214 (max_num_entries * sizeof(struct ipr_sdt_entry));
3215 rc = ipr_get_ldump_data_section(ioa_cfg, start_addr, (__be32 *)sdt,
3216 bytes_to_copy / sizeof(__be32));
3217
3218
3219 if (rc || ((be32_to_cpu(sdt->hdr.state) != IPR_FMT3_SDT_READY_TO_USE) &&
3220 (be32_to_cpu(sdt->hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) {
3221 dev_err(&ioa_cfg->pdev->dev,
3222 "Dump of IOA failed. Dump table not valid: %d, %X.\n",
3223 rc, be32_to_cpu(sdt->hdr.state));
3224 driver_dump->hdr.status = IPR_DUMP_STATUS_FAILED;
3225 ioa_cfg->sdt_state = DUMP_OBTAINED;
3226 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3227 return;
3228 }
3229
3230 num_entries = be32_to_cpu(sdt->hdr.num_entries_used);
3231
3232 if (num_entries > max_num_entries)
3233 num_entries = max_num_entries;
3234
3235
3236 dump->driver_dump.hdr.len += sizeof(struct ipr_sdt_header);
3237 if (ioa_cfg->sis64)
3238 dump->driver_dump.hdr.len += num_entries * sizeof(struct ipr_sdt_entry);
3239 else
3240 dump->driver_dump.hdr.len += max_num_entries * sizeof(struct ipr_sdt_entry);
3241
3242 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3243
3244 for (i = 0; i < num_entries; i++) {
3245 if (ioa_dump->hdr.len > max_dump_size) {
3246 driver_dump->hdr.status = IPR_DUMP_STATUS_QUAL_SUCCESS;
3247 break;
3248 }
3249
3250 if (sdt->entry[i].flags & IPR_SDT_VALID_ENTRY) {
3251 sdt_word = be32_to_cpu(sdt->entry[i].start_token);
3252 if (ioa_cfg->sis64)
3253 bytes_to_copy = be32_to_cpu(sdt->entry[i].end_token);
3254 else {
3255 start_off = sdt_word & IPR_FMT2_MBX_ADDR_MASK;
3256 end_off = be32_to_cpu(sdt->entry[i].end_token);
3257
3258 if (ipr_sdt_is_fmt2(sdt_word) && sdt_word)
3259 bytes_to_copy = end_off - start_off;
3260 else
3261 valid = 0;
3262 }
3263 if (valid) {
3264 if (bytes_to_copy > max_dump_size) {
3265 sdt->entry[i].flags &= ~IPR_SDT_VALID_ENTRY;
3266 continue;
3267 }
3268
3269
3270 bytes_copied = ipr_sdt_copy(ioa_cfg, sdt_word,
3271 bytes_to_copy);
3272
3273 ioa_dump->hdr.len += bytes_copied;
3274
3275 if (bytes_copied != bytes_to_copy) {
3276 driver_dump->hdr.status = IPR_DUMP_STATUS_QUAL_SUCCESS;
3277 break;
3278 }
3279 }
3280 }
3281 }
3282
3283 dev_err(&ioa_cfg->pdev->dev, "Dump of IOA completed.\n");
3284
3285
3286 driver_dump->hdr.len += ioa_dump->hdr.len;
3287 wmb();
3288 ioa_cfg->sdt_state = DUMP_OBTAINED;
3289 LEAVE;
3290 }
3291
3292 #else
3293 #define ipr_get_ioa_dump(ioa_cfg, dump) do { } while (0)
3294 #endif
3295
3296
3297
3298
3299
3300
3301
3302
3303 static void ipr_release_dump(struct kref *kref)
3304 {
3305 struct ipr_dump *dump = container_of(kref, struct ipr_dump, kref);
3306 struct ipr_ioa_cfg *ioa_cfg = dump->ioa_cfg;
3307 unsigned long lock_flags = 0;
3308 int i;
3309
3310 ENTER;
3311 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3312 ioa_cfg->dump = NULL;
3313 ioa_cfg->sdt_state = INACTIVE;
3314 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3315
3316 for (i = 0; i < dump->ioa_dump.next_page_index; i++)
3317 free_page((unsigned long) dump->ioa_dump.ioa_data[i]);
3318
3319 vfree(dump->ioa_dump.ioa_data);
3320 kfree(dump);
3321 LEAVE;
3322 }
3323
3324 static void ipr_add_remove_thread(struct work_struct *work)
3325 {
3326 unsigned long lock_flags;
3327 struct ipr_resource_entry *res;
3328 struct scsi_device *sdev;
3329 struct ipr_ioa_cfg *ioa_cfg =
3330 container_of(work, struct ipr_ioa_cfg, scsi_add_work_q);
3331 u8 bus, target, lun;
3332 int did_work;
3333
3334 ENTER;
3335 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3336
3337 restart:
3338 do {
3339 did_work = 0;
3340 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds) {
3341 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3342 return;
3343 }
3344
3345 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
3346 if (res->del_from_ml && res->sdev) {
3347 did_work = 1;
3348 sdev = res->sdev;
3349 if (!scsi_device_get(sdev)) {
3350 if (!res->add_to_ml)
3351 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
3352 else
3353 res->del_from_ml = 0;
3354 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3355 scsi_remove_device(sdev);
3356 scsi_device_put(sdev);
3357 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3358 }
3359 break;
3360 }
3361 }
3362 } while (did_work);
3363
3364 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
3365 if (res->add_to_ml) {
3366 bus = res->bus;
3367 target = res->target;
3368 lun = res->lun;
3369 res->add_to_ml = 0;
3370 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3371 scsi_add_device(ioa_cfg->host, bus, target, lun);
3372 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3373 goto restart;
3374 }
3375 }
3376
3377 ioa_cfg->scan_done = 1;
3378 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3379 kobject_uevent(&ioa_cfg->host->shost_dev.kobj, KOBJ_CHANGE);
3380 LEAVE;
3381 }
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394 static void ipr_worker_thread(struct work_struct *work)
3395 {
3396 unsigned long lock_flags;
3397 struct ipr_dump *dump;
3398 struct ipr_ioa_cfg *ioa_cfg =
3399 container_of(work, struct ipr_ioa_cfg, work_q);
3400
3401 ENTER;
3402 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3403
3404 if (ioa_cfg->sdt_state == READ_DUMP) {
3405 dump = ioa_cfg->dump;
3406 if (!dump) {
3407 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3408 return;
3409 }
3410 kref_get(&dump->kref);
3411 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3412 ipr_get_ioa_dump(ioa_cfg, dump);
3413 kref_put(&dump->kref, ipr_release_dump);
3414
3415 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3416 if (ioa_cfg->sdt_state == DUMP_OBTAINED && !ioa_cfg->dump_timeout)
3417 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
3418 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3419 return;
3420 }
3421
3422 if (ioa_cfg->scsi_unblock) {
3423 ioa_cfg->scsi_unblock = 0;
3424 ioa_cfg->scsi_blocked = 0;
3425 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3426 scsi_unblock_requests(ioa_cfg->host);
3427 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3428 if (ioa_cfg->scsi_blocked)
3429 scsi_block_requests(ioa_cfg->host);
3430 }
3431
3432 if (!ioa_cfg->scan_enabled) {
3433 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3434 return;
3435 }
3436
3437 schedule_work(&ioa_cfg->scsi_add_work_q);
3438
3439 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3440 LEAVE;
3441 }
3442
3443 #ifdef CONFIG_SCSI_IPR_TRACE
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456 static ssize_t ipr_read_trace(struct file *filp, struct kobject *kobj,
3457 struct bin_attribute *bin_attr,
3458 char *buf, loff_t off, size_t count)
3459 {
3460 struct device *dev = container_of(kobj, struct device, kobj);
3461 struct Scsi_Host *shost = class_to_shost(dev);
3462 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3463 unsigned long lock_flags = 0;
3464 ssize_t ret;
3465
3466 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3467 ret = memory_read_from_buffer(buf, count, &off, ioa_cfg->trace,
3468 IPR_TRACE_SIZE);
3469 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3470
3471 return ret;
3472 }
3473
3474 static struct bin_attribute ipr_trace_attr = {
3475 .attr = {
3476 .name = "trace",
3477 .mode = S_IRUGO,
3478 },
3479 .size = 0,
3480 .read = ipr_read_trace,
3481 };
3482 #endif
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492 static ssize_t ipr_show_fw_version(struct device *dev,
3493 struct device_attribute *attr, char *buf)
3494 {
3495 struct Scsi_Host *shost = class_to_shost(dev);
3496 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3497 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
3498 unsigned long lock_flags = 0;
3499 int len;
3500
3501 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3502 len = snprintf(buf, PAGE_SIZE, "%02X%02X%02X%02X\n",
3503 ucode_vpd->major_release, ucode_vpd->card_type,
3504 ucode_vpd->minor_release[0],
3505 ucode_vpd->minor_release[1]);
3506 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3507 return len;
3508 }
3509
3510 static struct device_attribute ipr_fw_version_attr = {
3511 .attr = {
3512 .name = "fw_version",
3513 .mode = S_IRUGO,
3514 },
3515 .show = ipr_show_fw_version,
3516 };
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526 static ssize_t ipr_show_log_level(struct device *dev,
3527 struct device_attribute *attr, char *buf)
3528 {
3529 struct Scsi_Host *shost = class_to_shost(dev);
3530 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3531 unsigned long lock_flags = 0;
3532 int len;
3533
3534 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3535 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->log_level);
3536 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3537 return len;
3538 }
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548 static ssize_t ipr_store_log_level(struct device *dev,
3549 struct device_attribute *attr,
3550 const char *buf, size_t count)
3551 {
3552 struct Scsi_Host *shost = class_to_shost(dev);
3553 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3554 unsigned long lock_flags = 0;
3555
3556 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3557 ioa_cfg->log_level = simple_strtoul(buf, NULL, 10);
3558 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3559 return strlen(buf);
3560 }
3561
3562 static struct device_attribute ipr_log_level_attr = {
3563 .attr = {
3564 .name = "log_level",
3565 .mode = S_IRUGO | S_IWUSR,
3566 },
3567 .show = ipr_show_log_level,
3568 .store = ipr_store_log_level
3569 };
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583 static ssize_t ipr_store_diagnostics(struct device *dev,
3584 struct device_attribute *attr,
3585 const char *buf, size_t count)
3586 {
3587 struct Scsi_Host *shost = class_to_shost(dev);
3588 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3589 unsigned long lock_flags = 0;
3590 int rc = count;
3591
3592 if (!capable(CAP_SYS_ADMIN))
3593 return -EACCES;
3594
3595 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3596 while (ioa_cfg->in_reset_reload) {
3597 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3598 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3599 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3600 }
3601
3602 ioa_cfg->errors_logged = 0;
3603 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3604
3605 if (ioa_cfg->in_reset_reload) {
3606 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3607 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3608
3609
3610 msleep(1000);
3611 } else {
3612 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3613 return -EIO;
3614 }
3615
3616 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3617 if (ioa_cfg->in_reset_reload || ioa_cfg->errors_logged)
3618 rc = -EIO;
3619 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3620
3621 return rc;
3622 }
3623
3624 static struct device_attribute ipr_diagnostics_attr = {
3625 .attr = {
3626 .name = "run_diagnostics",
3627 .mode = S_IWUSR,
3628 },
3629 .store = ipr_store_diagnostics
3630 };
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640 static ssize_t ipr_show_adapter_state(struct device *dev,
3641 struct device_attribute *attr, char *buf)
3642 {
3643 struct Scsi_Host *shost = class_to_shost(dev);
3644 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3645 unsigned long lock_flags = 0;
3646 int len;
3647
3648 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3649 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
3650 len = snprintf(buf, PAGE_SIZE, "offline\n");
3651 else
3652 len = snprintf(buf, PAGE_SIZE, "online\n");
3653 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3654 return len;
3655 }
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668 static ssize_t ipr_store_adapter_state(struct device *dev,
3669 struct device_attribute *attr,
3670 const char *buf, size_t count)
3671 {
3672 struct Scsi_Host *shost = class_to_shost(dev);
3673 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3674 unsigned long lock_flags;
3675 int result = count, i;
3676
3677 if (!capable(CAP_SYS_ADMIN))
3678 return -EACCES;
3679
3680 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3681 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead &&
3682 !strncmp(buf, "online", 6)) {
3683 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
3684 spin_lock(&ioa_cfg->hrrq[i]._lock);
3685 ioa_cfg->hrrq[i].ioa_is_dead = 0;
3686 spin_unlock(&ioa_cfg->hrrq[i]._lock);
3687 }
3688 wmb();
3689 ioa_cfg->reset_retries = 0;
3690 ioa_cfg->in_ioa_bringdown = 0;
3691 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
3692 }
3693 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3694 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3695
3696 return result;
3697 }
3698
3699 static struct device_attribute ipr_ioa_state_attr = {
3700 .attr = {
3701 .name = "online_state",
3702 .mode = S_IRUGO | S_IWUSR,
3703 },
3704 .show = ipr_show_adapter_state,
3705 .store = ipr_store_adapter_state
3706 };
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719 static ssize_t ipr_store_reset_adapter(struct device *dev,
3720 struct device_attribute *attr,
3721 const char *buf, size_t count)
3722 {
3723 struct Scsi_Host *shost = class_to_shost(dev);
3724 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3725 unsigned long lock_flags;
3726 int result = count;
3727
3728 if (!capable(CAP_SYS_ADMIN))
3729 return -EACCES;
3730
3731 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3732 if (!ioa_cfg->in_reset_reload)
3733 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3734 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3735 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3736
3737 return result;
3738 }
3739
3740 static struct device_attribute ipr_ioa_reset_attr = {
3741 .attr = {
3742 .name = "reset_host",
3743 .mode = S_IWUSR,
3744 },
3745 .store = ipr_store_reset_adapter
3746 };
3747
3748 static int ipr_iopoll(struct irq_poll *iop, int budget);
3749
3750
3751
3752
3753
3754
3755
3756
3757 static ssize_t ipr_show_iopoll_weight(struct device *dev,
3758 struct device_attribute *attr, char *buf)
3759 {
3760 struct Scsi_Host *shost = class_to_shost(dev);
3761 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3762 unsigned long lock_flags = 0;
3763 int len;
3764
3765 spin_lock_irqsave(shost->host_lock, lock_flags);
3766 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->iopoll_weight);
3767 spin_unlock_irqrestore(shost->host_lock, lock_flags);
3768
3769 return len;
3770 }
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780 static ssize_t ipr_store_iopoll_weight(struct device *dev,
3781 struct device_attribute *attr,
3782 const char *buf, size_t count)
3783 {
3784 struct Scsi_Host *shost = class_to_shost(dev);
3785 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3786 unsigned long user_iopoll_weight;
3787 unsigned long lock_flags = 0;
3788 int i;
3789
3790 if (!ioa_cfg->sis64) {
3791 dev_info(&ioa_cfg->pdev->dev, "irq_poll not supported on this adapter\n");
3792 return -EINVAL;
3793 }
3794 if (kstrtoul(buf, 10, &user_iopoll_weight))
3795 return -EINVAL;
3796
3797 if (user_iopoll_weight > 256) {
3798 dev_info(&ioa_cfg->pdev->dev, "Invalid irq_poll weight. It must be less than 256\n");
3799 return -EINVAL;
3800 }
3801
3802 if (user_iopoll_weight == ioa_cfg->iopoll_weight) {
3803 dev_info(&ioa_cfg->pdev->dev, "Current irq_poll weight has the same weight\n");
3804 return strlen(buf);
3805 }
3806
3807 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
3808 for (i = 1; i < ioa_cfg->hrrq_num; i++)
3809 irq_poll_disable(&ioa_cfg->hrrq[i].iopoll);
3810 }
3811
3812 spin_lock_irqsave(shost->host_lock, lock_flags);
3813 ioa_cfg->iopoll_weight = user_iopoll_weight;
3814 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
3815 for (i = 1; i < ioa_cfg->hrrq_num; i++) {
3816 irq_poll_init(&ioa_cfg->hrrq[i].iopoll,
3817 ioa_cfg->iopoll_weight, ipr_iopoll);
3818 }
3819 }
3820 spin_unlock_irqrestore(shost->host_lock, lock_flags);
3821
3822 return strlen(buf);
3823 }
3824
3825 static struct device_attribute ipr_iopoll_weight_attr = {
3826 .attr = {
3827 .name = "iopoll_weight",
3828 .mode = S_IRUGO | S_IWUSR,
3829 },
3830 .show = ipr_show_iopoll_weight,
3831 .store = ipr_store_iopoll_weight
3832 };
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844 static struct ipr_sglist *ipr_alloc_ucode_buffer(int buf_len)
3845 {
3846 int sg_size, order;
3847 struct ipr_sglist *sglist;
3848
3849
3850 sg_size = buf_len / (IPR_MAX_SGLIST - 1);
3851
3852
3853 order = get_order(sg_size);
3854
3855
3856 sglist = kzalloc(sizeof(struct ipr_sglist), GFP_KERNEL);
3857 if (sglist == NULL) {
3858 ipr_trace;
3859 return NULL;
3860 }
3861 sglist->order = order;
3862 sglist->scatterlist = sgl_alloc_order(buf_len, order, false, GFP_KERNEL,
3863 &sglist->num_sg);
3864 if (!sglist->scatterlist) {
3865 kfree(sglist);
3866 return NULL;
3867 }
3868
3869 return sglist;
3870 }
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882 static void ipr_free_ucode_buffer(struct ipr_sglist *sglist)
3883 {
3884 sgl_free_order(sglist->scatterlist, sglist->order);
3885 kfree(sglist);
3886 }
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900 static int ipr_copy_ucode_buffer(struct ipr_sglist *sglist,
3901 u8 *buffer, u32 len)
3902 {
3903 int bsize_elem, i, result = 0;
3904 struct scatterlist *sg;
3905 void *kaddr;
3906
3907
3908 bsize_elem = PAGE_SIZE * (1 << sglist->order);
3909
3910 sg = sglist->scatterlist;
3911
3912 for (i = 0; i < (len / bsize_elem); i++, sg = sg_next(sg),
3913 buffer += bsize_elem) {
3914 struct page *page = sg_page(sg);
3915
3916 kaddr = kmap(page);
3917 memcpy(kaddr, buffer, bsize_elem);
3918 kunmap(page);
3919
3920 sg->length = bsize_elem;
3921
3922 if (result != 0) {
3923 ipr_trace;
3924 return result;
3925 }
3926 }
3927
3928 if (len % bsize_elem) {
3929 struct page *page = sg_page(sg);
3930
3931 kaddr = kmap(page);
3932 memcpy(kaddr, buffer, len % bsize_elem);
3933 kunmap(page);
3934
3935 sg->length = len % bsize_elem;
3936 }
3937
3938 sglist->buffer_len = len;
3939 return result;
3940 }
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950 static void ipr_build_ucode_ioadl64(struct ipr_cmnd *ipr_cmd,
3951 struct ipr_sglist *sglist)
3952 {
3953 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
3954 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
3955 struct scatterlist *scatterlist = sglist->scatterlist;
3956 struct scatterlist *sg;
3957 int i;
3958
3959 ipr_cmd->dma_use_sg = sglist->num_dma_sg;
3960 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
3961 ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len);
3962
3963 ioarcb->ioadl_len =
3964 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
3965 for_each_sg(scatterlist, sg, ipr_cmd->dma_use_sg, i) {
3966 ioadl64[i].flags = cpu_to_be32(IPR_IOADL_FLAGS_WRITE);
3967 ioadl64[i].data_len = cpu_to_be32(sg_dma_len(sg));
3968 ioadl64[i].address = cpu_to_be64(sg_dma_address(sg));
3969 }
3970
3971 ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
3972 }
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982 static void ipr_build_ucode_ioadl(struct ipr_cmnd *ipr_cmd,
3983 struct ipr_sglist *sglist)
3984 {
3985 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
3986 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
3987 struct scatterlist *scatterlist = sglist->scatterlist;
3988 struct scatterlist *sg;
3989 int i;
3990
3991 ipr_cmd->dma_use_sg = sglist->num_dma_sg;
3992 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
3993 ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len);
3994
3995 ioarcb->ioadl_len =
3996 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
3997
3998 for_each_sg(scatterlist, sg, ipr_cmd->dma_use_sg, i) {
3999 ioadl[i].flags_and_data_len =
4000 cpu_to_be32(IPR_IOADL_FLAGS_WRITE | sg_dma_len(sg));
4001 ioadl[i].address =
4002 cpu_to_be32(sg_dma_address(sg));
4003 }
4004
4005 ioadl[i-1].flags_and_data_len |=
4006 cpu_to_be32(IPR_IOADL_FLAGS_LAST);
4007 }
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019 static int ipr_update_ioa_ucode(struct ipr_ioa_cfg *ioa_cfg,
4020 struct ipr_sglist *sglist)
4021 {
4022 unsigned long lock_flags;
4023
4024 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4025 while (ioa_cfg->in_reset_reload) {
4026 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4027 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
4028 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4029 }
4030
4031 if (ioa_cfg->ucode_sglist) {
4032 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4033 dev_err(&ioa_cfg->pdev->dev,
4034 "Microcode download already in progress\n");
4035 return -EIO;
4036 }
4037
4038 sglist->num_dma_sg = dma_map_sg(&ioa_cfg->pdev->dev,
4039 sglist->scatterlist, sglist->num_sg,
4040 DMA_TO_DEVICE);
4041
4042 if (!sglist->num_dma_sg) {
4043 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4044 dev_err(&ioa_cfg->pdev->dev,
4045 "Failed to map microcode download buffer!\n");
4046 return -EIO;
4047 }
4048
4049 ioa_cfg->ucode_sglist = sglist;
4050 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
4051 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4052 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
4053
4054 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4055 ioa_cfg->ucode_sglist = NULL;
4056 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4057 return 0;
4058 }
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071 static ssize_t ipr_store_update_fw(struct device *dev,
4072 struct device_attribute *attr,
4073 const char *buf, size_t count)
4074 {
4075 struct Scsi_Host *shost = class_to_shost(dev);
4076 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4077 struct ipr_ucode_image_header *image_hdr;
4078 const struct firmware *fw_entry;
4079 struct ipr_sglist *sglist;
4080 char fname[100];
4081 char *src;
4082 char *endline;
4083 int result, dnld_size;
4084
4085 if (!capable(CAP_SYS_ADMIN))
4086 return -EACCES;
4087
4088 snprintf(fname, sizeof(fname), "%s", buf);
4089
4090 endline = strchr(fname, '\n');
4091 if (endline)
4092 *endline = '\0';
4093
4094 if (request_firmware(&fw_entry, fname, &ioa_cfg->pdev->dev)) {
4095 dev_err(&ioa_cfg->pdev->dev, "Firmware file %s not found\n", fname);
4096 return -EIO;
4097 }
4098
4099 image_hdr = (struct ipr_ucode_image_header *)fw_entry->data;
4100
4101 src = (u8 *)image_hdr + be32_to_cpu(image_hdr->header_length);
4102 dnld_size = fw_entry->size - be32_to_cpu(image_hdr->header_length);
4103 sglist = ipr_alloc_ucode_buffer(dnld_size);
4104
4105 if (!sglist) {
4106 dev_err(&ioa_cfg->pdev->dev, "Microcode buffer allocation failed\n");
4107 release_firmware(fw_entry);
4108 return -ENOMEM;
4109 }
4110
4111 result = ipr_copy_ucode_buffer(sglist, src, dnld_size);
4112
4113 if (result) {
4114 dev_err(&ioa_cfg->pdev->dev,
4115 "Microcode buffer copy to DMA buffer failed\n");
4116 goto out;
4117 }
4118
4119 ipr_info("Updating microcode, please be patient. This may take up to 30 minutes.\n");
4120
4121 result = ipr_update_ioa_ucode(ioa_cfg, sglist);
4122
4123 if (!result)
4124 result = count;
4125 out:
4126 ipr_free_ucode_buffer(sglist);
4127 release_firmware(fw_entry);
4128 return result;
4129 }
4130
4131 static struct device_attribute ipr_update_fw_attr = {
4132 .attr = {
4133 .name = "update_fw",
4134 .mode = S_IWUSR,
4135 },
4136 .store = ipr_store_update_fw
4137 };
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147 static ssize_t ipr_show_fw_type(struct device *dev,
4148 struct device_attribute *attr, char *buf)
4149 {
4150 struct Scsi_Host *shost = class_to_shost(dev);
4151 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4152 unsigned long lock_flags = 0;
4153 int len;
4154
4155 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4156 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->sis64);
4157 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4158 return len;
4159 }
4160
4161 static struct device_attribute ipr_ioa_fw_type_attr = {
4162 .attr = {
4163 .name = "fw_type",
4164 .mode = S_IRUGO,
4165 },
4166 .show = ipr_show_fw_type
4167 };
4168
4169 static ssize_t ipr_read_async_err_log(struct file *filep, struct kobject *kobj,
4170 struct bin_attribute *bin_attr, char *buf,
4171 loff_t off, size_t count)
4172 {
4173 struct device *cdev = container_of(kobj, struct device, kobj);
4174 struct Scsi_Host *shost = class_to_shost(cdev);
4175 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4176 struct ipr_hostrcb *hostrcb;
4177 unsigned long lock_flags = 0;
4178 int ret;
4179
4180 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4181 hostrcb = list_first_entry_or_null(&ioa_cfg->hostrcb_report_q,
4182 struct ipr_hostrcb, queue);
4183 if (!hostrcb) {
4184 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4185 return 0;
4186 }
4187 ret = memory_read_from_buffer(buf, count, &off, &hostrcb->hcam,
4188 sizeof(hostrcb->hcam));
4189 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4190 return ret;
4191 }
4192
4193 static ssize_t ipr_next_async_err_log(struct file *filep, struct kobject *kobj,
4194 struct bin_attribute *bin_attr, char *buf,
4195 loff_t off, size_t count)
4196 {
4197 struct device *cdev = container_of(kobj, struct device, kobj);
4198 struct Scsi_Host *shost = class_to_shost(cdev);
4199 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4200 struct ipr_hostrcb *hostrcb;
4201 unsigned long lock_flags = 0;
4202
4203 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4204 hostrcb = list_first_entry_or_null(&ioa_cfg->hostrcb_report_q,
4205 struct ipr_hostrcb, queue);
4206 if (!hostrcb) {
4207 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4208 return count;
4209 }
4210
4211
4212 list_move_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
4213 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4214 return count;
4215 }
4216
4217 static struct bin_attribute ipr_ioa_async_err_log = {
4218 .attr = {
4219 .name = "async_err_log",
4220 .mode = S_IRUGO | S_IWUSR,
4221 },
4222 .size = 0,
4223 .read = ipr_read_async_err_log,
4224 .write = ipr_next_async_err_log
4225 };
4226
4227 static struct device_attribute *ipr_ioa_attrs[] = {
4228 &ipr_fw_version_attr,
4229 &ipr_log_level_attr,
4230 &ipr_diagnostics_attr,
4231 &ipr_ioa_state_attr,
4232 &ipr_ioa_reset_attr,
4233 &ipr_update_fw_attr,
4234 &ipr_ioa_fw_type_attr,
4235 &ipr_iopoll_weight_attr,
4236 NULL,
4237 };
4238
4239 #ifdef CONFIG_SCSI_IPR_DUMP
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252 static ssize_t ipr_read_dump(struct file *filp, struct kobject *kobj,
4253 struct bin_attribute *bin_attr,
4254 char *buf, loff_t off, size_t count)
4255 {
4256 struct device *cdev = container_of(kobj, struct device, kobj);
4257 struct Scsi_Host *shost = class_to_shost(cdev);
4258 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4259 struct ipr_dump *dump;
4260 unsigned long lock_flags = 0;
4261 char *src;
4262 int len, sdt_end;
4263 size_t rc = count;
4264
4265 if (!capable(CAP_SYS_ADMIN))
4266 return -EACCES;
4267
4268 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4269 dump = ioa_cfg->dump;
4270
4271 if (ioa_cfg->sdt_state != DUMP_OBTAINED || !dump) {
4272 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4273 return 0;
4274 }
4275 kref_get(&dump->kref);
4276 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4277
4278 if (off > dump->driver_dump.hdr.len) {
4279 kref_put(&dump->kref, ipr_release_dump);
4280 return 0;
4281 }
4282
4283 if (off + count > dump->driver_dump.hdr.len) {
4284 count = dump->driver_dump.hdr.len - off;
4285 rc = count;
4286 }
4287
4288 if (count && off < sizeof(dump->driver_dump)) {
4289 if (off + count > sizeof(dump->driver_dump))
4290 len = sizeof(dump->driver_dump) - off;
4291 else
4292 len = count;
4293 src = (u8 *)&dump->driver_dump + off;
4294 memcpy(buf, src, len);
4295 buf += len;
4296 off += len;
4297 count -= len;
4298 }
4299
4300 off -= sizeof(dump->driver_dump);
4301
4302 if (ioa_cfg->sis64)
4303 sdt_end = offsetof(struct ipr_ioa_dump, sdt.entry) +
4304 (be32_to_cpu(dump->ioa_dump.sdt.hdr.num_entries_used) *
4305 sizeof(struct ipr_sdt_entry));
4306 else
4307 sdt_end = offsetof(struct ipr_ioa_dump, sdt.entry) +
4308 (IPR_FMT2_NUM_SDT_ENTRIES * sizeof(struct ipr_sdt_entry));
4309
4310 if (count && off < sdt_end) {
4311 if (off + count > sdt_end)
4312 len = sdt_end - off;
4313 else
4314 len = count;
4315 src = (u8 *)&dump->ioa_dump + off;
4316 memcpy(buf, src, len);
4317 buf += len;
4318 off += len;
4319 count -= len;
4320 }
4321
4322 off -= sdt_end;
4323
4324 while (count) {
4325 if ((off & PAGE_MASK) != ((off + count) & PAGE_MASK))
4326 len = PAGE_ALIGN(off) - off;
4327 else
4328 len = count;
4329 src = (u8 *)dump->ioa_dump.ioa_data[(off & PAGE_MASK) >> PAGE_SHIFT];
4330 src += off & ~PAGE_MASK;
4331 memcpy(buf, src, len);
4332 buf += len;
4333 off += len;
4334 count -= len;
4335 }
4336
4337 kref_put(&dump->kref, ipr_release_dump);
4338 return rc;
4339 }
4340
4341
4342
4343
4344
4345
4346
4347
4348 static int ipr_alloc_dump(struct ipr_ioa_cfg *ioa_cfg)
4349 {
4350 struct ipr_dump *dump;
4351 __be32 **ioa_data;
4352 unsigned long lock_flags = 0;
4353
4354 dump = kzalloc(sizeof(struct ipr_dump), GFP_KERNEL);
4355
4356 if (!dump) {
4357 ipr_err("Dump memory allocation failed\n");
4358 return -ENOMEM;
4359 }
4360
4361 if (ioa_cfg->sis64)
4362 ioa_data = vmalloc(array_size(IPR_FMT3_MAX_NUM_DUMP_PAGES,
4363 sizeof(__be32 *)));
4364 else
4365 ioa_data = vmalloc(array_size(IPR_FMT2_MAX_NUM_DUMP_PAGES,
4366 sizeof(__be32 *)));
4367
4368 if (!ioa_data) {
4369 ipr_err("Dump memory allocation failed\n");
4370 kfree(dump);
4371 return -ENOMEM;
4372 }
4373
4374 dump->ioa_dump.ioa_data = ioa_data;
4375
4376 kref_init(&dump->kref);
4377 dump->ioa_cfg = ioa_cfg;
4378
4379 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4380
4381 if (INACTIVE != ioa_cfg->sdt_state) {
4382 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4383 vfree(dump->ioa_dump.ioa_data);
4384 kfree(dump);
4385 return 0;
4386 }
4387
4388 ioa_cfg->dump = dump;
4389 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
4390 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead && !ioa_cfg->dump_taken) {
4391 ioa_cfg->dump_taken = 1;
4392 schedule_work(&ioa_cfg->work_q);
4393 }
4394 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4395
4396 return 0;
4397 }
4398
4399
4400
4401
4402
4403
4404
4405
4406 static int ipr_free_dump(struct ipr_ioa_cfg *ioa_cfg)
4407 {
4408 struct ipr_dump *dump;
4409 unsigned long lock_flags = 0;
4410
4411 ENTER;
4412
4413 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4414 dump = ioa_cfg->dump;
4415 if (!dump) {
4416 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4417 return 0;
4418 }
4419
4420 ioa_cfg->dump = NULL;
4421 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4422
4423 kref_put(&dump->kref, ipr_release_dump);
4424
4425 LEAVE;
4426 return 0;
4427 }
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441 static ssize_t ipr_write_dump(struct file *filp, struct kobject *kobj,
4442 struct bin_attribute *bin_attr,
4443 char *buf, loff_t off, size_t count)
4444 {
4445 struct device *cdev = container_of(kobj, struct device, kobj);
4446 struct Scsi_Host *shost = class_to_shost(cdev);
4447 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4448 int rc;
4449
4450 if (!capable(CAP_SYS_ADMIN))
4451 return -EACCES;
4452
4453 if (buf[0] == '1')
4454 rc = ipr_alloc_dump(ioa_cfg);
4455 else if (buf[0] == '0')
4456 rc = ipr_free_dump(ioa_cfg);
4457 else
4458 return -EINVAL;
4459
4460 if (rc)
4461 return rc;
4462 else
4463 return count;
4464 }
4465
4466 static struct bin_attribute ipr_dump_attr = {
4467 .attr = {
4468 .name = "dump",
4469 .mode = S_IRUSR | S_IWUSR,
4470 },
4471 .size = 0,
4472 .read = ipr_read_dump,
4473 .write = ipr_write_dump
4474 };
4475 #else
4476 static int ipr_free_dump(struct ipr_ioa_cfg *ioa_cfg) { return 0; };
4477 #endif
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488 static int ipr_change_queue_depth(struct scsi_device *sdev, int qdepth)
4489 {
4490 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4491 struct ipr_resource_entry *res;
4492 unsigned long lock_flags = 0;
4493
4494 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4495 res = (struct ipr_resource_entry *)sdev->hostdata;
4496
4497 if (res && ipr_is_gata(res) && qdepth > IPR_MAX_CMD_PER_ATA_LUN)
4498 qdepth = IPR_MAX_CMD_PER_ATA_LUN;
4499 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4500
4501 scsi_change_queue_depth(sdev, qdepth);
4502 return sdev->queue_depth;
4503 }
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514 static ssize_t ipr_show_adapter_handle(struct device *dev, struct device_attribute *attr, char *buf)
4515 {
4516 struct scsi_device *sdev = to_scsi_device(dev);
4517 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4518 struct ipr_resource_entry *res;
4519 unsigned long lock_flags = 0;
4520 ssize_t len = -ENXIO;
4521
4522 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4523 res = (struct ipr_resource_entry *)sdev->hostdata;
4524 if (res)
4525 len = snprintf(buf, PAGE_SIZE, "%08X\n", res->res_handle);
4526 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4527 return len;
4528 }
4529
4530 static struct device_attribute ipr_adapter_handle_attr = {
4531 .attr = {
4532 .name = "adapter_handle",
4533 .mode = S_IRUSR,
4534 },
4535 .show = ipr_show_adapter_handle
4536 };
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548 static ssize_t ipr_show_resource_path(struct device *dev, struct device_attribute *attr, char *buf)
4549 {
4550 struct scsi_device *sdev = to_scsi_device(dev);
4551 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4552 struct ipr_resource_entry *res;
4553 unsigned long lock_flags = 0;
4554 ssize_t len = -ENXIO;
4555 char buffer[IPR_MAX_RES_PATH_LENGTH];
4556
4557 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4558 res = (struct ipr_resource_entry *)sdev->hostdata;
4559 if (res && ioa_cfg->sis64)
4560 len = snprintf(buf, PAGE_SIZE, "%s\n",
4561 __ipr_format_res_path(res->res_path, buffer,
4562 sizeof(buffer)));
4563 else if (res)
4564 len = snprintf(buf, PAGE_SIZE, "%d:%d:%d:%d\n", ioa_cfg->host->host_no,
4565 res->bus, res->target, res->lun);
4566
4567 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4568 return len;
4569 }
4570
4571 static struct device_attribute ipr_resource_path_attr = {
4572 .attr = {
4573 .name = "resource_path",
4574 .mode = S_IRUGO,
4575 },
4576 .show = ipr_show_resource_path
4577 };
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588 static ssize_t ipr_show_device_id(struct device *dev, struct device_attribute *attr, char *buf)
4589 {
4590 struct scsi_device *sdev = to_scsi_device(dev);
4591 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4592 struct ipr_resource_entry *res;
4593 unsigned long lock_flags = 0;
4594 ssize_t len = -ENXIO;
4595
4596 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4597 res = (struct ipr_resource_entry *)sdev->hostdata;
4598 if (res && ioa_cfg->sis64)
4599 len = snprintf(buf, PAGE_SIZE, "0x%llx\n", be64_to_cpu(res->dev_id));
4600 else if (res)
4601 len = snprintf(buf, PAGE_SIZE, "0x%llx\n", res->lun_wwn);
4602
4603 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4604 return len;
4605 }
4606
4607 static struct device_attribute ipr_device_id_attr = {
4608 .attr = {
4609 .name = "device_id",
4610 .mode = S_IRUGO,
4611 },
4612 .show = ipr_show_device_id
4613 };
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624 static ssize_t ipr_show_resource_type(struct device *dev, struct device_attribute *attr, char *buf)
4625 {
4626 struct scsi_device *sdev = to_scsi_device(dev);
4627 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4628 struct ipr_resource_entry *res;
4629 unsigned long lock_flags = 0;
4630 ssize_t len = -ENXIO;
4631
4632 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4633 res = (struct ipr_resource_entry *)sdev->hostdata;
4634
4635 if (res)
4636 len = snprintf(buf, PAGE_SIZE, "%x\n", res->type);
4637
4638 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4639 return len;
4640 }
4641
4642 static struct device_attribute ipr_resource_type_attr = {
4643 .attr = {
4644 .name = "resource_type",
4645 .mode = S_IRUGO,
4646 },
4647 .show = ipr_show_resource_type
4648 };
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658 static ssize_t ipr_show_raw_mode(struct device *dev,
4659 struct device_attribute *attr, char *buf)
4660 {
4661 struct scsi_device *sdev = to_scsi_device(dev);
4662 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4663 struct ipr_resource_entry *res;
4664 unsigned long lock_flags = 0;
4665 ssize_t len;
4666
4667 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4668 res = (struct ipr_resource_entry *)sdev->hostdata;
4669 if (res)
4670 len = snprintf(buf, PAGE_SIZE, "%d\n", res->raw_mode);
4671 else
4672 len = -ENXIO;
4673 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4674 return len;
4675 }
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685 static ssize_t ipr_store_raw_mode(struct device *dev,
4686 struct device_attribute *attr,
4687 const char *buf, size_t count)
4688 {
4689 struct scsi_device *sdev = to_scsi_device(dev);
4690 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4691 struct ipr_resource_entry *res;
4692 unsigned long lock_flags = 0;
4693 ssize_t len;
4694
4695 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4696 res = (struct ipr_resource_entry *)sdev->hostdata;
4697 if (res) {
4698 if (ipr_is_af_dasd_device(res)) {
4699 res->raw_mode = simple_strtoul(buf, NULL, 10);
4700 len = strlen(buf);
4701 if (res->sdev)
4702 sdev_printk(KERN_INFO, res->sdev, "raw mode is %s\n",
4703 res->raw_mode ? "enabled" : "disabled");
4704 } else
4705 len = -EINVAL;
4706 } else
4707 len = -ENXIO;
4708 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4709 return len;
4710 }
4711
4712 static struct device_attribute ipr_raw_mode_attr = {
4713 .attr = {
4714 .name = "raw_mode",
4715 .mode = S_IRUGO | S_IWUSR,
4716 },
4717 .show = ipr_show_raw_mode,
4718 .store = ipr_store_raw_mode
4719 };
4720
4721 static struct device_attribute *ipr_dev_attrs[] = {
4722 &ipr_adapter_handle_attr,
4723 &ipr_resource_path_attr,
4724 &ipr_device_id_attr,
4725 &ipr_resource_type_attr,
4726 &ipr_raw_mode_attr,
4727 NULL,
4728 };
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744 static int ipr_biosparam(struct scsi_device *sdev,
4745 struct block_device *block_device,
4746 sector_t capacity, int *parm)
4747 {
4748 int heads, sectors;
4749 sector_t cylinders;
4750
4751 heads = 128;
4752 sectors = 32;
4753
4754 cylinders = capacity;
4755 sector_div(cylinders, (128 * 32));
4756
4757
4758 parm[0] = heads;
4759 parm[1] = sectors;
4760 parm[2] = cylinders;
4761
4762 return 0;
4763 }
4764
4765
4766
4767
4768
4769
4770
4771
4772 static struct ipr_resource_entry *ipr_find_starget(struct scsi_target *starget)
4773 {
4774 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4775 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4776 struct ipr_resource_entry *res;
4777
4778 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
4779 if ((res->bus == starget->channel) &&
4780 (res->target == starget->id)) {
4781 return res;
4782 }
4783 }
4784
4785 return NULL;
4786 }
4787
4788 static struct ata_port_info sata_port_info;
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800 static int ipr_target_alloc(struct scsi_target *starget)
4801 {
4802 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4803 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4804 struct ipr_sata_port *sata_port;
4805 struct ata_port *ap;
4806 struct ipr_resource_entry *res;
4807 unsigned long lock_flags;
4808
4809 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4810 res = ipr_find_starget(starget);
4811 starget->hostdata = NULL;
4812
4813 if (res && ipr_is_gata(res)) {
4814 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4815 sata_port = kzalloc(sizeof(*sata_port), GFP_KERNEL);
4816 if (!sata_port)
4817 return -ENOMEM;
4818
4819 ap = ata_sas_port_alloc(&ioa_cfg->ata_host, &sata_port_info, shost);
4820 if (ap) {
4821 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4822 sata_port->ioa_cfg = ioa_cfg;
4823 sata_port->ap = ap;
4824 sata_port->res = res;
4825
4826 res->sata_port = sata_port;
4827 ap->private_data = sata_port;
4828 starget->hostdata = sata_port;
4829 } else {
4830 kfree(sata_port);
4831 return -ENOMEM;
4832 }
4833 }
4834 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4835
4836 return 0;
4837 }
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847 static void ipr_target_destroy(struct scsi_target *starget)
4848 {
4849 struct ipr_sata_port *sata_port = starget->hostdata;
4850 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4851 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4852
4853 if (ioa_cfg->sis64) {
4854 if (!ipr_find_starget(starget)) {
4855 if (starget->channel == IPR_ARRAY_VIRTUAL_BUS)
4856 clear_bit(starget->id, ioa_cfg->array_ids);
4857 else if (starget->channel == IPR_VSET_VIRTUAL_BUS)
4858 clear_bit(starget->id, ioa_cfg->vset_ids);
4859 else if (starget->channel == 0)
4860 clear_bit(starget->id, ioa_cfg->target_ids);
4861 }
4862 }
4863
4864 if (sata_port) {
4865 starget->hostdata = NULL;
4866 ata_sas_port_destroy(sata_port->ap);
4867 kfree(sata_port);
4868 }
4869 }
4870
4871
4872
4873
4874
4875
4876
4877
4878 static struct ipr_resource_entry *ipr_find_sdev(struct scsi_device *sdev)
4879 {
4880 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4881 struct ipr_resource_entry *res;
4882
4883 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
4884 if ((res->bus == sdev->channel) &&
4885 (res->target == sdev->id) &&
4886 (res->lun == sdev->lun))
4887 return res;
4888 }
4889
4890 return NULL;
4891 }
4892
4893
4894
4895
4896
4897
4898
4899
4900 static void ipr_slave_destroy(struct scsi_device *sdev)
4901 {
4902 struct ipr_resource_entry *res;
4903 struct ipr_ioa_cfg *ioa_cfg;
4904 unsigned long lock_flags = 0;
4905
4906 ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4907
4908 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4909 res = (struct ipr_resource_entry *) sdev->hostdata;
4910 if (res) {
4911 if (res->sata_port)
4912 res->sata_port->ap->link.device[0].class = ATA_DEV_NONE;
4913 sdev->hostdata = NULL;
4914 res->sdev = NULL;
4915 res->sata_port = NULL;
4916 }
4917 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4918 }
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929 static int ipr_slave_configure(struct scsi_device *sdev)
4930 {
4931 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4932 struct ipr_resource_entry *res;
4933 struct ata_port *ap = NULL;
4934 unsigned long lock_flags = 0;
4935 char buffer[IPR_MAX_RES_PATH_LENGTH];
4936
4937 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4938 res = sdev->hostdata;
4939 if (res) {
4940 if (ipr_is_af_dasd_device(res))
4941 sdev->type = TYPE_RAID;
4942 if (ipr_is_af_dasd_device(res) || ipr_is_ioa_resource(res)) {
4943 sdev->scsi_level = 4;
4944 sdev->no_uld_attach = 1;
4945 }
4946 if (ipr_is_vset_device(res)) {
4947 sdev->scsi_level = SCSI_SPC_3;
4948 sdev->no_report_opcodes = 1;
4949 blk_queue_rq_timeout(sdev->request_queue,
4950 IPR_VSET_RW_TIMEOUT);
4951 blk_queue_max_hw_sectors(sdev->request_queue, IPR_VSET_MAX_SECTORS);
4952 }
4953 if (ipr_is_gata(res) && res->sata_port)
4954 ap = res->sata_port->ap;
4955 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4956
4957 if (ap) {
4958 scsi_change_queue_depth(sdev, IPR_MAX_CMD_PER_ATA_LUN);
4959 ata_sas_slave_configure(sdev, ap);
4960 }
4961
4962 if (ioa_cfg->sis64)
4963 sdev_printk(KERN_INFO, sdev, "Resource path: %s\n",
4964 ipr_format_res_path(ioa_cfg,
4965 res->res_path, buffer, sizeof(buffer)));
4966 return 0;
4967 }
4968 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4969 return 0;
4970 }
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982 static int ipr_ata_slave_alloc(struct scsi_device *sdev)
4983 {
4984 struct ipr_sata_port *sata_port = NULL;
4985 int rc = -ENXIO;
4986
4987 ENTER;
4988 if (sdev->sdev_target)
4989 sata_port = sdev->sdev_target->hostdata;
4990 if (sata_port) {
4991 rc = ata_sas_port_init(sata_port->ap);
4992 if (rc == 0)
4993 rc = ata_sas_sync_probe(sata_port->ap);
4994 }
4995
4996 if (rc)
4997 ipr_slave_destroy(sdev);
4998
4999 LEAVE;
5000 return rc;
5001 }
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015 static int ipr_slave_alloc(struct scsi_device *sdev)
5016 {
5017 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
5018 struct ipr_resource_entry *res;
5019 unsigned long lock_flags;
5020 int rc = -ENXIO;
5021
5022 sdev->hostdata = NULL;
5023
5024 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5025
5026 res = ipr_find_sdev(sdev);
5027 if (res) {
5028 res->sdev = sdev;
5029 res->add_to_ml = 0;
5030 res->in_erp = 0;
5031 sdev->hostdata = res;
5032 if (!ipr_is_naca_model(res))
5033 res->needs_sync_complete = 1;
5034 rc = 0;
5035 if (ipr_is_gata(res)) {
5036 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5037 return ipr_ata_slave_alloc(sdev);
5038 }
5039 }
5040
5041 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5042
5043 return rc;
5044 }
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054 static int ipr_match_lun(struct ipr_cmnd *ipr_cmd, void *device)
5055 {
5056 if (ipr_cmd->scsi_cmd && ipr_cmd->scsi_cmd->device == device)
5057 return 1;
5058 return 0;
5059 }
5060
5061
5062
5063
5064
5065
5066
5067
5068 static bool ipr_cmnd_is_free(struct ipr_cmnd *ipr_cmd)
5069 {
5070 struct ipr_cmnd *loop_cmd;
5071
5072 list_for_each_entry(loop_cmd, &ipr_cmd->hrrq->hrrq_free_q, queue) {
5073 if (loop_cmd == ipr_cmd)
5074 return true;
5075 }
5076
5077 return false;
5078 }
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088 static int ipr_match_res(struct ipr_cmnd *ipr_cmd, void *resource)
5089 {
5090 struct ipr_resource_entry *res = resource;
5091
5092 if (res && ipr_cmd->ioarcb.res_handle == res->res_handle)
5093 return 1;
5094 return 0;
5095 }
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106 static int ipr_wait_for_ops(struct ipr_ioa_cfg *ioa_cfg, void *device,
5107 int (*match)(struct ipr_cmnd *, void *))
5108 {
5109 struct ipr_cmnd *ipr_cmd;
5110 int wait, i;
5111 unsigned long flags;
5112 struct ipr_hrr_queue *hrrq;
5113 signed long timeout = IPR_ABORT_TASK_TIMEOUT;
5114 DECLARE_COMPLETION_ONSTACK(comp);
5115
5116 ENTER;
5117 do {
5118 wait = 0;
5119
5120 for_each_hrrq(hrrq, ioa_cfg) {
5121 spin_lock_irqsave(hrrq->lock, flags);
5122 for (i = hrrq->min_cmd_id; i <= hrrq->max_cmd_id; i++) {
5123 ipr_cmd = ioa_cfg->ipr_cmnd_list[i];
5124 if (!ipr_cmnd_is_free(ipr_cmd)) {
5125 if (match(ipr_cmd, device)) {
5126 ipr_cmd->eh_comp = ∁
5127 wait++;
5128 }
5129 }
5130 }
5131 spin_unlock_irqrestore(hrrq->lock, flags);
5132 }
5133
5134 if (wait) {
5135 timeout = wait_for_completion_timeout(&comp, timeout);
5136
5137 if (!timeout) {
5138 wait = 0;
5139
5140 for_each_hrrq(hrrq, ioa_cfg) {
5141 spin_lock_irqsave(hrrq->lock, flags);
5142 for (i = hrrq->min_cmd_id; i <= hrrq->max_cmd_id; i++) {
5143 ipr_cmd = ioa_cfg->ipr_cmnd_list[i];
5144 if (!ipr_cmnd_is_free(ipr_cmd)) {
5145 if (match(ipr_cmd, device)) {
5146 ipr_cmd->eh_comp = NULL;
5147 wait++;
5148 }
5149 }
5150 }
5151 spin_unlock_irqrestore(hrrq->lock, flags);
5152 }
5153
5154 if (wait)
5155 dev_err(&ioa_cfg->pdev->dev, "Timed out waiting for aborted commands\n");
5156 LEAVE;
5157 return wait ? FAILED : SUCCESS;
5158 }
5159 }
5160 } while (wait);
5161
5162 LEAVE;
5163 return SUCCESS;
5164 }
5165
5166 static int ipr_eh_host_reset(struct scsi_cmnd *cmd)
5167 {
5168 struct ipr_ioa_cfg *ioa_cfg;
5169 unsigned long lock_flags = 0;
5170 int rc = SUCCESS;
5171
5172 ENTER;
5173 ioa_cfg = (struct ipr_ioa_cfg *) cmd->device->host->hostdata;
5174 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5175
5176 if (!ioa_cfg->in_reset_reload && !ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
5177 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_ABBREV);
5178 dev_err(&ioa_cfg->pdev->dev,
5179 "Adapter being reset as a result of error recovery.\n");
5180
5181 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5182 ioa_cfg->sdt_state = GET_DUMP;
5183 }
5184
5185 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5186 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
5187 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5188
5189
5190
5191 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
5192 ipr_trace;
5193 rc = FAILED;
5194 }
5195
5196 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5197 LEAVE;
5198 return rc;
5199 }
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215 static int ipr_device_reset(struct ipr_ioa_cfg *ioa_cfg,
5216 struct ipr_resource_entry *res)
5217 {
5218 struct ipr_cmnd *ipr_cmd;
5219 struct ipr_ioarcb *ioarcb;
5220 struct ipr_cmd_pkt *cmd_pkt;
5221 struct ipr_ioarcb_ata_regs *regs;
5222 u32 ioasc;
5223
5224 ENTER;
5225 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5226 ioarcb = &ipr_cmd->ioarcb;
5227 cmd_pkt = &ioarcb->cmd_pkt;
5228
5229 if (ipr_cmd->ioa_cfg->sis64) {
5230 regs = &ipr_cmd->i.ata_ioadl.regs;
5231 ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb));
5232 } else
5233 regs = &ioarcb->u.add_data.u.regs;
5234
5235 ioarcb->res_handle = res->res_handle;
5236 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5237 cmd_pkt->cdb[0] = IPR_RESET_DEVICE;
5238 if (ipr_is_gata(res)) {
5239 cmd_pkt->cdb[2] = IPR_ATA_PHY_RESET;
5240 ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(regs->flags));
5241 regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION;
5242 }
5243
5244 ipr_send_blocking_cmd(ipr_cmd, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
5245 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5246 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5247 if (ipr_is_gata(res) && res->sata_port && ioasc != IPR_IOASC_IOA_WAS_RESET) {
5248 if (ipr_cmd->ioa_cfg->sis64)
5249 memcpy(&res->sata_port->ioasa, &ipr_cmd->s.ioasa64.u.gata,
5250 sizeof(struct ipr_ioasa_gata));
5251 else
5252 memcpy(&res->sata_port->ioasa, &ipr_cmd->s.ioasa.u.gata,
5253 sizeof(struct ipr_ioasa_gata));
5254 }
5255
5256 LEAVE;
5257 return IPR_IOASC_SENSE_KEY(ioasc) ? -EIO : 0;
5258 }
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270 static int ipr_sata_reset(struct ata_link *link, unsigned int *classes,
5271 unsigned long deadline)
5272 {
5273 struct ipr_sata_port *sata_port = link->ap->private_data;
5274 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
5275 struct ipr_resource_entry *res;
5276 unsigned long lock_flags = 0;
5277 int rc = -ENXIO, ret;
5278
5279 ENTER;
5280 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5281 while (ioa_cfg->in_reset_reload) {
5282 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5283 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
5284 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5285 }
5286
5287 res = sata_port->res;
5288 if (res) {
5289 rc = ipr_device_reset(ioa_cfg, res);
5290 *classes = res->ata_class;
5291 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5292
5293 ret = ipr_wait_for_ops(ioa_cfg, res, ipr_match_res);
5294 if (ret != SUCCESS) {
5295 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5296 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_ABBREV);
5297 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5298
5299 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
5300 }
5301 } else
5302 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5303
5304 LEAVE;
5305 return rc;
5306 }
5307
5308
5309
5310
5311
5312
5313
5314
5315
5316
5317
5318
5319 static int __ipr_eh_dev_reset(struct scsi_cmnd *scsi_cmd)
5320 {
5321 struct ipr_cmnd *ipr_cmd;
5322 struct ipr_ioa_cfg *ioa_cfg;
5323 struct ipr_resource_entry *res;
5324 struct ata_port *ap;
5325 int rc = 0, i;
5326 struct ipr_hrr_queue *hrrq;
5327
5328 ENTER;
5329 ioa_cfg = (struct ipr_ioa_cfg *) scsi_cmd->device->host->hostdata;
5330 res = scsi_cmd->device->hostdata;
5331
5332
5333
5334
5335
5336
5337 if (ioa_cfg->in_reset_reload)
5338 return FAILED;
5339 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
5340 return FAILED;
5341
5342 for_each_hrrq(hrrq, ioa_cfg) {
5343 spin_lock(&hrrq->_lock);
5344 for (i = hrrq->min_cmd_id; i <= hrrq->max_cmd_id; i++) {
5345 ipr_cmd = ioa_cfg->ipr_cmnd_list[i];
5346
5347 if (ipr_cmd->ioarcb.res_handle == res->res_handle) {
5348 if (!ipr_cmd->qc)
5349 continue;
5350 if (ipr_cmnd_is_free(ipr_cmd))
5351 continue;
5352
5353 ipr_cmd->done = ipr_sata_eh_done;
5354 if (!(ipr_cmd->qc->flags & ATA_QCFLAG_FAILED)) {
5355 ipr_cmd->qc->err_mask |= AC_ERR_TIMEOUT;
5356 ipr_cmd->qc->flags |= ATA_QCFLAG_FAILED;
5357 }
5358 }
5359 }
5360 spin_unlock(&hrrq->_lock);
5361 }
5362 res->resetting_device = 1;
5363 scmd_printk(KERN_ERR, scsi_cmd, "Resetting device\n");
5364
5365 if (ipr_is_gata(res) && res->sata_port) {
5366 ap = res->sata_port->ap;
5367 spin_unlock_irq(scsi_cmd->device->host->host_lock);
5368 ata_std_error_handler(ap);
5369 spin_lock_irq(scsi_cmd->device->host->host_lock);
5370 } else
5371 rc = ipr_device_reset(ioa_cfg, res);
5372 res->resetting_device = 0;
5373 res->reset_occurred = 1;
5374
5375 LEAVE;
5376 return rc ? FAILED : SUCCESS;
5377 }
5378
5379 static int ipr_eh_dev_reset(struct scsi_cmnd *cmd)
5380 {
5381 int rc;
5382 struct ipr_ioa_cfg *ioa_cfg;
5383 struct ipr_resource_entry *res;
5384
5385 ioa_cfg = (struct ipr_ioa_cfg *) cmd->device->host->hostdata;
5386 res = cmd->device->hostdata;
5387
5388 if (!res)
5389 return FAILED;
5390
5391 spin_lock_irq(cmd->device->host->host_lock);
5392 rc = __ipr_eh_dev_reset(cmd);
5393 spin_unlock_irq(cmd->device->host->host_lock);
5394
5395 if (rc == SUCCESS) {
5396 if (ipr_is_gata(res) && res->sata_port)
5397 rc = ipr_wait_for_ops(ioa_cfg, res, ipr_match_res);
5398 else
5399 rc = ipr_wait_for_ops(ioa_cfg, cmd->device, ipr_match_lun);
5400 }
5401
5402 return rc;
5403 }
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414 static void ipr_bus_reset_done(struct ipr_cmnd *ipr_cmd)
5415 {
5416 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
5417 struct ipr_resource_entry *res;
5418
5419 ENTER;
5420 if (!ioa_cfg->sis64)
5421 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
5422 if (res->res_handle == ipr_cmd->ioarcb.res_handle) {
5423 scsi_report_bus_reset(ioa_cfg->host, res->bus);
5424 break;
5425 }
5426 }
5427
5428
5429
5430
5431
5432 if (ipr_cmd->sibling->sibling)
5433 ipr_cmd->sibling->sibling = NULL;
5434 else
5435 ipr_cmd->sibling->done(ipr_cmd->sibling);
5436
5437 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5438 LEAVE;
5439 }
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452 static void ipr_abort_timeout(struct timer_list *t)
5453 {
5454 struct ipr_cmnd *ipr_cmd = from_timer(ipr_cmd, t, timer);
5455 struct ipr_cmnd *reset_cmd;
5456 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
5457 struct ipr_cmd_pkt *cmd_pkt;
5458 unsigned long lock_flags = 0;
5459
5460 ENTER;
5461 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5462 if (ipr_cmd->completion.done || ioa_cfg->in_reset_reload) {
5463 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5464 return;
5465 }
5466
5467 sdev_printk(KERN_ERR, ipr_cmd->u.sdev, "Abort timed out. Resetting bus.\n");
5468 reset_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5469 ipr_cmd->sibling = reset_cmd;
5470 reset_cmd->sibling = ipr_cmd;
5471 reset_cmd->ioarcb.res_handle = ipr_cmd->ioarcb.res_handle;
5472 cmd_pkt = &reset_cmd->ioarcb.cmd_pkt;
5473 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5474 cmd_pkt->cdb[0] = IPR_RESET_DEVICE;
5475 cmd_pkt->cdb[2] = IPR_RESET_TYPE_SELECT | IPR_BUS_RESET;
5476
5477 ipr_do_req(reset_cmd, ipr_bus_reset_done, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
5478 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5479 LEAVE;
5480 }
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491 static int ipr_cancel_op(struct scsi_cmnd *scsi_cmd)
5492 {
5493 struct ipr_cmnd *ipr_cmd;
5494 struct ipr_ioa_cfg *ioa_cfg;
5495 struct ipr_resource_entry *res;
5496 struct ipr_cmd_pkt *cmd_pkt;
5497 u32 ioasc, int_reg;
5498 int i, op_found = 0;
5499 struct ipr_hrr_queue *hrrq;
5500
5501 ENTER;
5502 ioa_cfg = (struct ipr_ioa_cfg *)scsi_cmd->device->host->hostdata;
5503 res = scsi_cmd->device->hostdata;
5504
5505
5506
5507
5508
5509 if (ioa_cfg->in_reset_reload ||
5510 ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
5511 return FAILED;
5512 if (!res)
5513 return FAILED;
5514
5515
5516
5517
5518
5519
5520 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
5521
5522 if (!ipr_is_gscsi(res))
5523 return FAILED;
5524
5525 for_each_hrrq(hrrq, ioa_cfg) {
5526 spin_lock(&hrrq->_lock);
5527 for (i = hrrq->min_cmd_id; i <= hrrq->max_cmd_id; i++) {
5528 if (ioa_cfg->ipr_cmnd_list[i]->scsi_cmd == scsi_cmd) {
5529 if (!ipr_cmnd_is_free(ioa_cfg->ipr_cmnd_list[i])) {
5530 op_found = 1;
5531 break;
5532 }
5533 }
5534 }
5535 spin_unlock(&hrrq->_lock);
5536 }
5537
5538 if (!op_found)
5539 return SUCCESS;
5540
5541 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5542 ipr_cmd->ioarcb.res_handle = res->res_handle;
5543 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
5544 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5545 cmd_pkt->cdb[0] = IPR_CANCEL_ALL_REQUESTS;
5546 ipr_cmd->u.sdev = scsi_cmd->device;
5547
5548 scmd_printk(KERN_ERR, scsi_cmd, "Aborting command: %02X\n",
5549 scsi_cmd->cmnd[0]);
5550 ipr_send_blocking_cmd(ipr_cmd, ipr_abort_timeout, IPR_CANCEL_ALL_TIMEOUT);
5551 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5552
5553
5554
5555
5556
5557 if (ioasc == IPR_IOASC_BUS_WAS_RESET || ioasc == IPR_IOASC_SYNC_REQUIRED) {
5558 ioasc = 0;
5559 ipr_trace;
5560 }
5561
5562 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5563 if (!ipr_is_naca_model(res))
5564 res->needs_sync_complete = 1;
5565
5566 LEAVE;
5567 return IPR_IOASC_SENSE_KEY(ioasc) ? FAILED : SUCCESS;
5568 }
5569
5570
5571
5572
5573
5574
5575
5576
5577 static int ipr_scan_finished(struct Scsi_Host *shost, unsigned long elapsed_time)
5578 {
5579 unsigned long lock_flags;
5580 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
5581 int rc = 0;
5582
5583 spin_lock_irqsave(shost->host_lock, lock_flags);
5584 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead || ioa_cfg->scan_done)
5585 rc = 1;
5586 if ((elapsed_time/HZ) > (ioa_cfg->transop_timeout * 2))
5587 rc = 1;
5588 spin_unlock_irqrestore(shost->host_lock, lock_flags);
5589 return rc;
5590 }
5591
5592
5593
5594
5595
5596
5597
5598
5599 static int ipr_eh_abort(struct scsi_cmnd *scsi_cmd)
5600 {
5601 unsigned long flags;
5602 int rc;
5603 struct ipr_ioa_cfg *ioa_cfg;
5604
5605 ENTER;
5606
5607 ioa_cfg = (struct ipr_ioa_cfg *) scsi_cmd->device->host->hostdata;
5608
5609 spin_lock_irqsave(scsi_cmd->device->host->host_lock, flags);
5610 rc = ipr_cancel_op(scsi_cmd);
5611 spin_unlock_irqrestore(scsi_cmd->device->host->host_lock, flags);
5612
5613 if (rc == SUCCESS)
5614 rc = ipr_wait_for_ops(ioa_cfg, scsi_cmd->device, ipr_match_lun);
5615 LEAVE;
5616 return rc;
5617 }
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627 static irqreturn_t ipr_handle_other_interrupt(struct ipr_ioa_cfg *ioa_cfg,
5628 u32 int_reg)
5629 {
5630 irqreturn_t rc = IRQ_HANDLED;
5631 u32 int_mask_reg;
5632
5633 int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
5634 int_reg &= ~int_mask_reg;
5635
5636
5637
5638
5639 if ((int_reg & IPR_PCII_OPER_INTERRUPTS) == 0) {
5640 if (ioa_cfg->sis64) {
5641 int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
5642 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
5643 if (int_reg & IPR_PCII_IPL_STAGE_CHANGE) {
5644
5645
5646 writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_reg);
5647 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
5648 list_del(&ioa_cfg->reset_cmd->queue);
5649 del_timer(&ioa_cfg->reset_cmd->timer);
5650 ipr_reset_ioa_job(ioa_cfg->reset_cmd);
5651 return IRQ_HANDLED;
5652 }
5653 }
5654
5655 return IRQ_NONE;
5656 }
5657
5658 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
5659
5660 writel(IPR_PCII_IOA_TRANS_TO_OPER, ioa_cfg->regs.set_interrupt_mask_reg);
5661 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
5662
5663 list_del(&ioa_cfg->reset_cmd->queue);
5664 del_timer(&ioa_cfg->reset_cmd->timer);
5665 ipr_reset_ioa_job(ioa_cfg->reset_cmd);
5666 } else if ((int_reg & IPR_PCII_HRRQ_UPDATED) == int_reg) {
5667 if (ioa_cfg->clear_isr) {
5668 if (ipr_debug && printk_ratelimit())
5669 dev_err(&ioa_cfg->pdev->dev,
5670 "Spurious interrupt detected. 0x%08X\n", int_reg);
5671 writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg32);
5672 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5673 return IRQ_NONE;
5674 }
5675 } else {
5676 if (int_reg & IPR_PCII_IOA_UNIT_CHECKED)
5677 ioa_cfg->ioa_unit_checked = 1;
5678 else if (int_reg & IPR_PCII_NO_HOST_RRQ)
5679 dev_err(&ioa_cfg->pdev->dev,
5680 "No Host RRQ. 0x%08X\n", int_reg);
5681 else
5682 dev_err(&ioa_cfg->pdev->dev,
5683 "Permanent IOA failure. 0x%08X\n", int_reg);
5684
5685 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5686 ioa_cfg->sdt_state = GET_DUMP;
5687
5688 ipr_mask_and_clear_interrupts(ioa_cfg, ~0);
5689 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
5690 }
5691
5692 return rc;
5693 }
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703 static void ipr_isr_eh(struct ipr_ioa_cfg *ioa_cfg, char *msg, u16 number)
5704 {
5705 ioa_cfg->errors_logged++;
5706 dev_err(&ioa_cfg->pdev->dev, "%s %d\n", msg, number);
5707
5708 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5709 ioa_cfg->sdt_state = GET_DUMP;
5710
5711 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
5712 }
5713
5714 static int ipr_process_hrrq(struct ipr_hrr_queue *hrr_queue, int budget,
5715 struct list_head *doneq)
5716 {
5717 u32 ioasc;
5718 u16 cmd_index;
5719 struct ipr_cmnd *ipr_cmd;
5720 struct ipr_ioa_cfg *ioa_cfg = hrr_queue->ioa_cfg;
5721 int num_hrrq = 0;
5722
5723
5724 if (!hrr_queue->allow_interrupts)
5725 return 0;
5726
5727 while ((be32_to_cpu(*hrr_queue->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5728 hrr_queue->toggle_bit) {
5729
5730 cmd_index = (be32_to_cpu(*hrr_queue->hrrq_curr) &
5731 IPR_HRRQ_REQ_RESP_HANDLE_MASK) >>
5732 IPR_HRRQ_REQ_RESP_HANDLE_SHIFT;
5733
5734 if (unlikely(cmd_index > hrr_queue->max_cmd_id ||
5735 cmd_index < hrr_queue->min_cmd_id)) {
5736 ipr_isr_eh(ioa_cfg,
5737 "Invalid response handle from IOA: ",
5738 cmd_index);
5739 break;
5740 }
5741
5742 ipr_cmd = ioa_cfg->ipr_cmnd_list[cmd_index];
5743 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5744
5745 ipr_trc_hook(ipr_cmd, IPR_TRACE_FINISH, ioasc);
5746
5747 list_move_tail(&ipr_cmd->queue, doneq);
5748
5749 if (hrr_queue->hrrq_curr < hrr_queue->hrrq_end) {
5750 hrr_queue->hrrq_curr++;
5751 } else {
5752 hrr_queue->hrrq_curr = hrr_queue->hrrq_start;
5753 hrr_queue->toggle_bit ^= 1u;
5754 }
5755 num_hrrq++;
5756 if (budget > 0 && num_hrrq >= budget)
5757 break;
5758 }
5759
5760 return num_hrrq;
5761 }
5762
5763 static int ipr_iopoll(struct irq_poll *iop, int budget)
5764 {
5765 struct ipr_ioa_cfg *ioa_cfg;
5766 struct ipr_hrr_queue *hrrq;
5767 struct ipr_cmnd *ipr_cmd, *temp;
5768 unsigned long hrrq_flags;
5769 int completed_ops;
5770 LIST_HEAD(doneq);
5771
5772 hrrq = container_of(iop, struct ipr_hrr_queue, iopoll);
5773 ioa_cfg = hrrq->ioa_cfg;
5774
5775 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5776 completed_ops = ipr_process_hrrq(hrrq, budget, &doneq);
5777
5778 if (completed_ops < budget)
5779 irq_poll_complete(iop);
5780 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5781
5782 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5783 list_del(&ipr_cmd->queue);
5784 del_timer(&ipr_cmd->timer);
5785 ipr_cmd->fast_done(ipr_cmd);
5786 }
5787
5788 return completed_ops;
5789 }
5790
5791
5792
5793
5794
5795
5796
5797
5798
5799 static irqreturn_t ipr_isr(int irq, void *devp)
5800 {
5801 struct ipr_hrr_queue *hrrq = (struct ipr_hrr_queue *)devp;
5802 struct ipr_ioa_cfg *ioa_cfg = hrrq->ioa_cfg;
5803 unsigned long hrrq_flags = 0;
5804 u32 int_reg = 0;
5805 int num_hrrq = 0;
5806 int irq_none = 0;
5807 struct ipr_cmnd *ipr_cmd, *temp;
5808 irqreturn_t rc = IRQ_NONE;
5809 LIST_HEAD(doneq);
5810
5811 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5812
5813 if (!hrrq->allow_interrupts) {
5814 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5815 return IRQ_NONE;
5816 }
5817
5818 while (1) {
5819 if (ipr_process_hrrq(hrrq, -1, &doneq)) {
5820 rc = IRQ_HANDLED;
5821
5822 if (!ioa_cfg->clear_isr)
5823 break;
5824
5825
5826 num_hrrq = 0;
5827 do {
5828 writel(IPR_PCII_HRRQ_UPDATED,
5829 ioa_cfg->regs.clr_interrupt_reg32);
5830 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5831 } while (int_reg & IPR_PCII_HRRQ_UPDATED &&
5832 num_hrrq++ < IPR_MAX_HRRQ_RETRIES);
5833
5834 } else if (rc == IRQ_NONE && irq_none == 0) {
5835 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5836 irq_none++;
5837 } else if (num_hrrq == IPR_MAX_HRRQ_RETRIES &&
5838 int_reg & IPR_PCII_HRRQ_UPDATED) {
5839 ipr_isr_eh(ioa_cfg,
5840 "Error clearing HRRQ: ", num_hrrq);
5841 rc = IRQ_HANDLED;
5842 break;
5843 } else
5844 break;
5845 }
5846
5847 if (unlikely(rc == IRQ_NONE))
5848 rc = ipr_handle_other_interrupt(ioa_cfg, int_reg);
5849
5850 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5851 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5852 list_del(&ipr_cmd->queue);
5853 del_timer(&ipr_cmd->timer);
5854 ipr_cmd->fast_done(ipr_cmd);
5855 }
5856 return rc;
5857 }
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867 static irqreturn_t ipr_isr_mhrrq(int irq, void *devp)
5868 {
5869 struct ipr_hrr_queue *hrrq = (struct ipr_hrr_queue *)devp;
5870 struct ipr_ioa_cfg *ioa_cfg = hrrq->ioa_cfg;
5871 unsigned long hrrq_flags = 0;
5872 struct ipr_cmnd *ipr_cmd, *temp;
5873 irqreturn_t rc = IRQ_NONE;
5874 LIST_HEAD(doneq);
5875
5876 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5877
5878
5879 if (!hrrq->allow_interrupts) {
5880 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5881 return IRQ_NONE;
5882 }
5883
5884 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
5885 if ((be32_to_cpu(*hrrq->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5886 hrrq->toggle_bit) {
5887 irq_poll_sched(&hrrq->iopoll);
5888 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5889 return IRQ_HANDLED;
5890 }
5891 } else {
5892 if ((be32_to_cpu(*hrrq->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5893 hrrq->toggle_bit)
5894
5895 if (ipr_process_hrrq(hrrq, -1, &doneq))
5896 rc = IRQ_HANDLED;
5897 }
5898
5899 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5900
5901 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5902 list_del(&ipr_cmd->queue);
5903 del_timer(&ipr_cmd->timer);
5904 ipr_cmd->fast_done(ipr_cmd);
5905 }
5906 return rc;
5907 }
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917 static int ipr_build_ioadl64(struct ipr_ioa_cfg *ioa_cfg,
5918 struct ipr_cmnd *ipr_cmd)
5919 {
5920 int i, nseg;
5921 struct scatterlist *sg;
5922 u32 length;
5923 u32 ioadl_flags = 0;
5924 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5925 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5926 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
5927
5928 length = scsi_bufflen(scsi_cmd);
5929 if (!length)
5930 return 0;
5931
5932 nseg = scsi_dma_map(scsi_cmd);
5933 if (nseg < 0) {
5934 if (printk_ratelimit())
5935 dev_err(&ioa_cfg->pdev->dev, "scsi_dma_map failed!\n");
5936 return -1;
5937 }
5938
5939 ipr_cmd->dma_use_sg = nseg;
5940
5941 ioarcb->data_transfer_length = cpu_to_be32(length);
5942 ioarcb->ioadl_len =
5943 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
5944
5945 if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) {
5946 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
5947 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
5948 } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE)
5949 ioadl_flags = IPR_IOADL_FLAGS_READ;
5950
5951 scsi_for_each_sg(scsi_cmd, sg, ipr_cmd->dma_use_sg, i) {
5952 ioadl64[i].flags = cpu_to_be32(ioadl_flags);
5953 ioadl64[i].data_len = cpu_to_be32(sg_dma_len(sg));
5954 ioadl64[i].address = cpu_to_be64(sg_dma_address(sg));
5955 }
5956
5957 ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
5958 return 0;
5959 }
5960
5961
5962
5963
5964
5965
5966
5967
5968
5969 static int ipr_build_ioadl(struct ipr_ioa_cfg *ioa_cfg,
5970 struct ipr_cmnd *ipr_cmd)
5971 {
5972 int i, nseg;
5973 struct scatterlist *sg;
5974 u32 length;
5975 u32 ioadl_flags = 0;
5976 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5977 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5978 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
5979
5980 length = scsi_bufflen(scsi_cmd);
5981 if (!length)
5982 return 0;
5983
5984 nseg = scsi_dma_map(scsi_cmd);
5985 if (nseg < 0) {
5986 dev_err(&ioa_cfg->pdev->dev, "scsi_dma_map failed!\n");
5987 return -1;
5988 }
5989
5990 ipr_cmd->dma_use_sg = nseg;
5991
5992 if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) {
5993 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
5994 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
5995 ioarcb->data_transfer_length = cpu_to_be32(length);
5996 ioarcb->ioadl_len =
5997 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
5998 } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE) {
5999 ioadl_flags = IPR_IOADL_FLAGS_READ;
6000 ioarcb->read_data_transfer_length = cpu_to_be32(length);
6001 ioarcb->read_ioadl_len =
6002 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6003 }
6004
6005 if (ipr_cmd->dma_use_sg <= ARRAY_SIZE(ioarcb->u.add_data.u.ioadl)) {
6006 ioadl = ioarcb->u.add_data.u.ioadl;
6007 ioarcb->write_ioadl_addr = cpu_to_be32((ipr_cmd->dma_addr) +
6008 offsetof(struct ipr_ioarcb, u.add_data));
6009 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
6010 }
6011
6012 scsi_for_each_sg(scsi_cmd, sg, ipr_cmd->dma_use_sg, i) {
6013 ioadl[i].flags_and_data_len =
6014 cpu_to_be32(ioadl_flags | sg_dma_len(sg));
6015 ioadl[i].address = cpu_to_be32(sg_dma_address(sg));
6016 }
6017
6018 ioadl[i-1].flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6019 return 0;
6020 }
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032 static void __ipr_erp_done(struct ipr_cmnd *ipr_cmd)
6033 {
6034 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
6035 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
6036 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6037
6038 if (IPR_IOASC_SENSE_KEY(ioasc) > 0) {
6039 scsi_cmd->result |= (DID_ERROR << 16);
6040 scmd_printk(KERN_ERR, scsi_cmd,
6041 "Request Sense failed with IOASC: 0x%08X\n", ioasc);
6042 } else {
6043 memcpy(scsi_cmd->sense_buffer, ipr_cmd->sense_buffer,
6044 SCSI_SENSE_BUFFERSIZE);
6045 }
6046
6047 if (res) {
6048 if (!ipr_is_naca_model(res))
6049 res->needs_sync_complete = 1;
6050 res->in_erp = 0;
6051 }
6052 scsi_dma_unmap(ipr_cmd->scsi_cmd);
6053 scsi_cmd->scsi_done(scsi_cmd);
6054 if (ipr_cmd->eh_comp)
6055 complete(ipr_cmd->eh_comp);
6056 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6057 }
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069 static void ipr_erp_done(struct ipr_cmnd *ipr_cmd)
6070 {
6071 struct ipr_hrr_queue *hrrq = ipr_cmd->hrrq;
6072 unsigned long hrrq_flags;
6073
6074 spin_lock_irqsave(&hrrq->_lock, hrrq_flags);
6075 __ipr_erp_done(ipr_cmd);
6076 spin_unlock_irqrestore(&hrrq->_lock, hrrq_flags);
6077 }
6078
6079
6080
6081
6082
6083
6084
6085
6086 static void ipr_reinit_ipr_cmnd_for_erp(struct ipr_cmnd *ipr_cmd)
6087 {
6088 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6089 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
6090 dma_addr_t dma_addr = ipr_cmd->dma_addr;
6091
6092 memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt));
6093 ioarcb->data_transfer_length = 0;
6094 ioarcb->read_data_transfer_length = 0;
6095 ioarcb->ioadl_len = 0;
6096 ioarcb->read_ioadl_len = 0;
6097 ioasa->hdr.ioasc = 0;
6098 ioasa->hdr.residual_data_len = 0;
6099
6100 if (ipr_cmd->ioa_cfg->sis64)
6101 ioarcb->u.sis64_addr_data.data_ioadl_addr =
6102 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
6103 else {
6104 ioarcb->write_ioadl_addr =
6105 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
6106 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
6107 }
6108 }
6109
6110
6111
6112
6113
6114
6115
6116
6117
6118
6119
6120 static void __ipr_erp_request_sense(struct ipr_cmnd *ipr_cmd)
6121 {
6122 struct ipr_cmd_pkt *cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
6123 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6124
6125 if (IPR_IOASC_SENSE_KEY(ioasc) > 0) {
6126 __ipr_erp_done(ipr_cmd);
6127 return;
6128 }
6129
6130 ipr_reinit_ipr_cmnd_for_erp(ipr_cmd);
6131
6132 cmd_pkt->request_type = IPR_RQTYPE_SCSICDB;
6133 cmd_pkt->cdb[0] = REQUEST_SENSE;
6134 cmd_pkt->cdb[4] = SCSI_SENSE_BUFFERSIZE;
6135 cmd_pkt->flags_hi |= IPR_FLAGS_HI_SYNC_OVERRIDE;
6136 cmd_pkt->flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6137 cmd_pkt->timeout = cpu_to_be16(IPR_REQUEST_SENSE_TIMEOUT / HZ);
6138
6139 ipr_init_ioadl(ipr_cmd, ipr_cmd->sense_buffer_dma,
6140 SCSI_SENSE_BUFFERSIZE, IPR_IOADL_FLAGS_READ_LAST);
6141
6142 ipr_do_req(ipr_cmd, ipr_erp_done, ipr_timeout,
6143 IPR_REQUEST_SENSE_TIMEOUT * 2);
6144 }
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155
6156 static void ipr_erp_request_sense(struct ipr_cmnd *ipr_cmd)
6157 {
6158 struct ipr_hrr_queue *hrrq = ipr_cmd->hrrq;
6159 unsigned long hrrq_flags;
6160
6161 spin_lock_irqsave(&hrrq->_lock, hrrq_flags);
6162 __ipr_erp_request_sense(ipr_cmd);
6163 spin_unlock_irqrestore(&hrrq->_lock, hrrq_flags);
6164 }
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174
6175
6176
6177
6178 static void ipr_erp_cancel_all(struct ipr_cmnd *ipr_cmd)
6179 {
6180 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
6181 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
6182 struct ipr_cmd_pkt *cmd_pkt;
6183
6184 res->in_erp = 1;
6185
6186 ipr_reinit_ipr_cmnd_for_erp(ipr_cmd);
6187
6188 if (!scsi_cmd->device->simple_tags) {
6189 __ipr_erp_request_sense(ipr_cmd);
6190 return;
6191 }
6192
6193 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
6194 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
6195 cmd_pkt->cdb[0] = IPR_CANCEL_ALL_REQUESTS;
6196
6197 ipr_do_req(ipr_cmd, ipr_erp_request_sense, ipr_timeout,
6198 IPR_CANCEL_ALL_TIMEOUT);
6199 }
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214 static void ipr_dump_ioasa(struct ipr_ioa_cfg *ioa_cfg,
6215 struct ipr_cmnd *ipr_cmd, struct ipr_resource_entry *res)
6216 {
6217 int i;
6218 u16 data_len;
6219 u32 ioasc, fd_ioasc;
6220 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
6221 __be32 *ioasa_data = (__be32 *)ioasa;
6222 int error_index;
6223
6224 ioasc = be32_to_cpu(ioasa->hdr.ioasc) & IPR_IOASC_IOASC_MASK;
6225 fd_ioasc = be32_to_cpu(ioasa->hdr.fd_ioasc) & IPR_IOASC_IOASC_MASK;
6226
6227 if (0 == ioasc)
6228 return;
6229
6230 if (ioa_cfg->log_level < IPR_DEFAULT_LOG_LEVEL)
6231 return;
6232
6233 if (ioasc == IPR_IOASC_BUS_WAS_RESET && fd_ioasc)
6234 error_index = ipr_get_error(fd_ioasc);
6235 else
6236 error_index = ipr_get_error(ioasc);
6237
6238 if (ioa_cfg->log_level < IPR_MAX_LOG_LEVEL) {
6239
6240 if (ioasa->hdr.ilid != 0)
6241 return;
6242
6243 if (!ipr_is_gscsi(res))
6244 return;
6245
6246 if (ipr_error_table[error_index].log_ioasa == 0)
6247 return;
6248 }
6249
6250 ipr_res_err(ioa_cfg, res, "%s\n", ipr_error_table[error_index].error);
6251
6252 data_len = be16_to_cpu(ioasa->hdr.ret_stat_len);
6253 if (ioa_cfg->sis64 && sizeof(struct ipr_ioasa64) < data_len)
6254 data_len = sizeof(struct ipr_ioasa64);
6255 else if (!ioa_cfg->sis64 && sizeof(struct ipr_ioasa) < data_len)
6256 data_len = sizeof(struct ipr_ioasa);
6257
6258 ipr_err("IOASA Dump:\n");
6259
6260 for (i = 0; i < data_len / 4; i += 4) {
6261 ipr_err("%08X: %08X %08X %08X %08X\n", i*4,
6262 be32_to_cpu(ioasa_data[i]),
6263 be32_to_cpu(ioasa_data[i+1]),
6264 be32_to_cpu(ioasa_data[i+2]),
6265 be32_to_cpu(ioasa_data[i+3]));
6266 }
6267 }
6268
6269
6270
6271
6272
6273
6274
6275
6276
6277 static void ipr_gen_sense(struct ipr_cmnd *ipr_cmd)
6278 {
6279 u32 failing_lba;
6280 u8 *sense_buf = ipr_cmd->scsi_cmd->sense_buffer;
6281 struct ipr_resource_entry *res = ipr_cmd->scsi_cmd->device->hostdata;
6282 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
6283 u32 ioasc = be32_to_cpu(ioasa->hdr.ioasc);
6284
6285 memset(sense_buf, 0, SCSI_SENSE_BUFFERSIZE);
6286
6287 if (ioasc >= IPR_FIRST_DRIVER_IOASC)
6288 return;
6289
6290 ipr_cmd->scsi_cmd->result = SAM_STAT_CHECK_CONDITION;
6291
6292 if (ipr_is_vset_device(res) &&
6293 ioasc == IPR_IOASC_MED_DO_NOT_REALLOC &&
6294 ioasa->u.vset.failing_lba_hi != 0) {
6295 sense_buf[0] = 0x72;
6296 sense_buf[1] = IPR_IOASC_SENSE_KEY(ioasc);
6297 sense_buf[2] = IPR_IOASC_SENSE_CODE(ioasc);
6298 sense_buf[3] = IPR_IOASC_SENSE_QUAL(ioasc);
6299
6300 sense_buf[7] = 12;
6301 sense_buf[8] = 0;
6302 sense_buf[9] = 0x0A;
6303 sense_buf[10] = 0x80;
6304
6305 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_hi);
6306
6307 sense_buf[12] = (failing_lba & 0xff000000) >> 24;
6308 sense_buf[13] = (failing_lba & 0x00ff0000) >> 16;
6309 sense_buf[14] = (failing_lba & 0x0000ff00) >> 8;
6310 sense_buf[15] = failing_lba & 0x000000ff;
6311
6312 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_lo);
6313
6314 sense_buf[16] = (failing_lba & 0xff000000) >> 24;
6315 sense_buf[17] = (failing_lba & 0x00ff0000) >> 16;
6316 sense_buf[18] = (failing_lba & 0x0000ff00) >> 8;
6317 sense_buf[19] = failing_lba & 0x000000ff;
6318 } else {
6319 sense_buf[0] = 0x70;
6320 sense_buf[2] = IPR_IOASC_SENSE_KEY(ioasc);
6321 sense_buf[12] = IPR_IOASC_SENSE_CODE(ioasc);
6322 sense_buf[13] = IPR_IOASC_SENSE_QUAL(ioasc);
6323
6324
6325 if ((IPR_IOASC_SENSE_KEY(ioasc) == 0x05) &&
6326 (be32_to_cpu(ioasa->hdr.ioasc_specific) & IPR_FIELD_POINTER_VALID)) {
6327 sense_buf[7] = 10;
6328
6329
6330 if (IPR_IOASC_SENSE_CODE(ioasc) == 0x24)
6331 sense_buf[15] = 0xC0;
6332 else
6333 sense_buf[15] = 0x80;
6334
6335 sense_buf[16] =
6336 ((IPR_FIELD_POINTER_MASK &
6337 be32_to_cpu(ioasa->hdr.ioasc_specific)) >> 8) & 0xff;
6338 sense_buf[17] =
6339 (IPR_FIELD_POINTER_MASK &
6340 be32_to_cpu(ioasa->hdr.ioasc_specific)) & 0xff;
6341 } else {
6342 if (ioasc == IPR_IOASC_MED_DO_NOT_REALLOC) {
6343 if (ipr_is_vset_device(res))
6344 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_lo);
6345 else
6346 failing_lba = be32_to_cpu(ioasa->u.dasd.failing_lba);
6347
6348 sense_buf[0] |= 0x80;
6349 sense_buf[3] = (failing_lba & 0xff000000) >> 24;
6350 sense_buf[4] = (failing_lba & 0x00ff0000) >> 16;
6351 sense_buf[5] = (failing_lba & 0x0000ff00) >> 8;
6352 sense_buf[6] = failing_lba & 0x000000ff;
6353 }
6354
6355 sense_buf[7] = 6;
6356 }
6357 }
6358 }
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370 static int ipr_get_autosense(struct ipr_cmnd *ipr_cmd)
6371 {
6372 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
6373 struct ipr_ioasa64 *ioasa64 = &ipr_cmd->s.ioasa64;
6374
6375 if ((be32_to_cpu(ioasa->hdr.ioasc_specific) & IPR_AUTOSENSE_VALID) == 0)
6376 return 0;
6377
6378 if (ipr_cmd->ioa_cfg->sis64)
6379 memcpy(ipr_cmd->scsi_cmd->sense_buffer, ioasa64->auto_sense.data,
6380 min_t(u16, be16_to_cpu(ioasa64->auto_sense.auto_sense_len),
6381 SCSI_SENSE_BUFFERSIZE));
6382 else
6383 memcpy(ipr_cmd->scsi_cmd->sense_buffer, ioasa->auto_sense.data,
6384 min_t(u16, be16_to_cpu(ioasa->auto_sense.auto_sense_len),
6385 SCSI_SENSE_BUFFERSIZE));
6386 return 1;
6387 }
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400 static void ipr_erp_start(struct ipr_ioa_cfg *ioa_cfg,
6401 struct ipr_cmnd *ipr_cmd)
6402 {
6403 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
6404 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
6405 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6406 u32 masked_ioasc = ioasc & IPR_IOASC_IOASC_MASK;
6407
6408 if (!res) {
6409 __ipr_scsi_eh_done(ipr_cmd);
6410 return;
6411 }
6412
6413 if (!ipr_is_gscsi(res) && masked_ioasc != IPR_IOASC_HW_DEV_BUS_STATUS)
6414 ipr_gen_sense(ipr_cmd);
6415
6416 ipr_dump_ioasa(ioa_cfg, ipr_cmd, res);
6417
6418 switch (masked_ioasc) {
6419 case IPR_IOASC_ABORTED_CMD_TERM_BY_HOST:
6420 if (ipr_is_naca_model(res))
6421 scsi_cmd->result |= (DID_ABORT << 16);
6422 else
6423 scsi_cmd->result |= (DID_IMM_RETRY << 16);
6424 break;
6425 case IPR_IOASC_IR_RESOURCE_HANDLE:
6426 case IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA:
6427 scsi_cmd->result |= (DID_NO_CONNECT << 16);
6428 break;
6429 case IPR_IOASC_HW_SEL_TIMEOUT:
6430 scsi_cmd->result |= (DID_NO_CONNECT << 16);
6431 if (!ipr_is_naca_model(res))
6432 res->needs_sync_complete = 1;
6433 break;
6434 case IPR_IOASC_SYNC_REQUIRED:
6435 if (!res->in_erp)
6436 res->needs_sync_complete = 1;
6437 scsi_cmd->result |= (DID_IMM_RETRY << 16);
6438 break;
6439 case IPR_IOASC_MED_DO_NOT_REALLOC:
6440 case IPR_IOASA_IR_DUAL_IOA_DISABLED:
6441
6442
6443
6444
6445 if (scsi_cmd->result != SAM_STAT_CHECK_CONDITION)
6446 scsi_cmd->result |= (DID_PASSTHROUGH << 16);
6447 break;
6448 case IPR_IOASC_BUS_WAS_RESET:
6449 case IPR_IOASC_BUS_WAS_RESET_BY_OTHER:
6450
6451
6452
6453
6454 if (!res->resetting_device)
6455 scsi_report_bus_reset(ioa_cfg->host, scsi_cmd->device->channel);
6456 scsi_cmd->result |= (DID_ERROR << 16);
6457 if (!ipr_is_naca_model(res))
6458 res->needs_sync_complete = 1;
6459 break;
6460 case IPR_IOASC_HW_DEV_BUS_STATUS:
6461 scsi_cmd->result |= IPR_IOASC_SENSE_STATUS(ioasc);
6462 if (IPR_IOASC_SENSE_STATUS(ioasc) == SAM_STAT_CHECK_CONDITION) {
6463 if (!ipr_get_autosense(ipr_cmd)) {
6464 if (!ipr_is_naca_model(res)) {
6465 ipr_erp_cancel_all(ipr_cmd);
6466 return;
6467 }
6468 }
6469 }
6470 if (!ipr_is_naca_model(res))
6471 res->needs_sync_complete = 1;
6472 break;
6473 case IPR_IOASC_NR_INIT_CMD_REQUIRED:
6474 break;
6475 case IPR_IOASC_IR_NON_OPTIMIZED:
6476 if (res->raw_mode) {
6477 res->raw_mode = 0;
6478 scsi_cmd->result |= (DID_IMM_RETRY << 16);
6479 } else
6480 scsi_cmd->result |= (DID_ERROR << 16);
6481 break;
6482 default:
6483 if (IPR_IOASC_SENSE_KEY(ioasc) > RECOVERED_ERROR)
6484 scsi_cmd->result |= (DID_ERROR << 16);
6485 if (!ipr_is_vset_device(res) && !ipr_is_naca_model(res))
6486 res->needs_sync_complete = 1;
6487 break;
6488 }
6489
6490 scsi_dma_unmap(ipr_cmd->scsi_cmd);
6491 scsi_cmd->scsi_done(scsi_cmd);
6492 if (ipr_cmd->eh_comp)
6493 complete(ipr_cmd->eh_comp);
6494 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6495 }
6496
6497
6498
6499
6500
6501
6502
6503
6504
6505
6506
6507 static void ipr_scsi_done(struct ipr_cmnd *ipr_cmd)
6508 {
6509 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6510 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
6511 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6512 unsigned long lock_flags;
6513
6514 scsi_set_resid(scsi_cmd, be32_to_cpu(ipr_cmd->s.ioasa.hdr.residual_data_len));
6515
6516 if (likely(IPR_IOASC_SENSE_KEY(ioasc) == 0)) {
6517 scsi_dma_unmap(scsi_cmd);
6518
6519 spin_lock_irqsave(ipr_cmd->hrrq->lock, lock_flags);
6520 scsi_cmd->scsi_done(scsi_cmd);
6521 if (ipr_cmd->eh_comp)
6522 complete(ipr_cmd->eh_comp);
6523 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6524 spin_unlock_irqrestore(ipr_cmd->hrrq->lock, lock_flags);
6525 } else {
6526 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
6527 spin_lock(&ipr_cmd->hrrq->_lock);
6528 ipr_erp_start(ioa_cfg, ipr_cmd);
6529 spin_unlock(&ipr_cmd->hrrq->_lock);
6530 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
6531 }
6532 }
6533
6534
6535
6536
6537
6538
6539
6540
6541
6542
6543
6544
6545
6546 static int ipr_queuecommand(struct Scsi_Host *shost,
6547 struct scsi_cmnd *scsi_cmd)
6548 {
6549 struct ipr_ioa_cfg *ioa_cfg;
6550 struct ipr_resource_entry *res;
6551 struct ipr_ioarcb *ioarcb;
6552 struct ipr_cmnd *ipr_cmd;
6553 unsigned long hrrq_flags, lock_flags;
6554 int rc;
6555 struct ipr_hrr_queue *hrrq;
6556 int hrrq_id;
6557
6558 ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
6559
6560 scsi_cmd->result = (DID_OK << 16);
6561 res = scsi_cmd->device->hostdata;
6562
6563 if (ipr_is_gata(res) && res->sata_port) {
6564 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
6565 rc = ata_sas_queuecmd(scsi_cmd, res->sata_port->ap);
6566 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
6567 return rc;
6568 }
6569
6570 hrrq_id = ipr_get_hrrq_index(ioa_cfg);
6571 hrrq = &ioa_cfg->hrrq[hrrq_id];
6572
6573 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6574
6575
6576
6577
6578
6579 if (unlikely(!hrrq->allow_cmds && !hrrq->ioa_is_dead && !hrrq->removing_ioa)) {
6580 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6581 return SCSI_MLQUEUE_HOST_BUSY;
6582 }
6583
6584
6585
6586
6587
6588 if (unlikely(hrrq->ioa_is_dead || hrrq->removing_ioa || !res)) {
6589 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6590 goto err_nodev;
6591 }
6592
6593 ipr_cmd = __ipr_get_free_ipr_cmnd(hrrq);
6594 if (ipr_cmd == NULL) {
6595 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6596 return SCSI_MLQUEUE_HOST_BUSY;
6597 }
6598 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6599
6600 ipr_init_ipr_cmnd(ipr_cmd, ipr_scsi_done);
6601 ioarcb = &ipr_cmd->ioarcb;
6602
6603 memcpy(ioarcb->cmd_pkt.cdb, scsi_cmd->cmnd, scsi_cmd->cmd_len);
6604 ipr_cmd->scsi_cmd = scsi_cmd;
6605 ipr_cmd->done = ipr_scsi_eh_done;
6606
6607 if (ipr_is_gscsi(res)) {
6608 if (scsi_cmd->underflow == 0)
6609 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6610
6611 if (res->reset_occurred) {
6612 res->reset_occurred = 0;
6613 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_DELAY_AFTER_RST;
6614 }
6615 }
6616
6617 if (ipr_is_gscsi(res) || ipr_is_vset_device(res)) {
6618 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC;
6619
6620 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_ALIGNED_BFR;
6621 if (scsi_cmd->flags & SCMD_TAGGED)
6622 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_SIMPLE_TASK;
6623 else
6624 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_UNTAGGED_TASK;
6625 }
6626
6627 if (scsi_cmd->cmnd[0] >= 0xC0 &&
6628 (!ipr_is_gscsi(res) || scsi_cmd->cmnd[0] == IPR_QUERY_RSRC_STATE)) {
6629 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
6630 }
6631 if (res->raw_mode && ipr_is_af_dasd_device(res)) {
6632 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_PIPE;
6633
6634 if (scsi_cmd->underflow == 0)
6635 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6636 }
6637
6638 if (ioa_cfg->sis64)
6639 rc = ipr_build_ioadl64(ioa_cfg, ipr_cmd);
6640 else
6641 rc = ipr_build_ioadl(ioa_cfg, ipr_cmd);
6642
6643 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6644 if (unlikely(rc || (!hrrq->allow_cmds && !hrrq->ioa_is_dead))) {
6645 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_free_q);
6646 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6647 if (!rc)
6648 scsi_dma_unmap(scsi_cmd);
6649 return SCSI_MLQUEUE_HOST_BUSY;
6650 }
6651
6652 if (unlikely(hrrq->ioa_is_dead)) {
6653 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_free_q);
6654 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6655 scsi_dma_unmap(scsi_cmd);
6656 goto err_nodev;
6657 }
6658
6659 ioarcb->res_handle = res->res_handle;
6660 if (res->needs_sync_complete) {
6661 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_SYNC_COMPLETE;
6662 res->needs_sync_complete = 0;
6663 }
6664 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_pending_q);
6665 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res));
6666 ipr_send_command(ipr_cmd);
6667 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6668 return 0;
6669
6670 err_nodev:
6671 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6672 memset(scsi_cmd->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
6673 scsi_cmd->result = (DID_NO_CONNECT << 16);
6674 scsi_cmd->scsi_done(scsi_cmd);
6675 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6676 return 0;
6677 }
6678
6679
6680
6681
6682
6683
6684
6685
6686
6687
6688 static int ipr_ioctl(struct scsi_device *sdev, unsigned int cmd,
6689 void __user *arg)
6690 {
6691 struct ipr_resource_entry *res;
6692
6693 res = (struct ipr_resource_entry *)sdev->hostdata;
6694 if (res && ipr_is_gata(res)) {
6695 if (cmd == HDIO_GET_IDENTITY)
6696 return -ENOTTY;
6697 return ata_sas_scsi_ioctl(res->sata_port->ap, sdev, cmd, arg);
6698 }
6699
6700 return -EINVAL;
6701 }
6702
6703
6704
6705
6706
6707
6708
6709
6710 static const char *ipr_ioa_info(struct Scsi_Host *host)
6711 {
6712 static char buffer[512];
6713 struct ipr_ioa_cfg *ioa_cfg;
6714 unsigned long lock_flags = 0;
6715
6716 ioa_cfg = (struct ipr_ioa_cfg *) host->hostdata;
6717
6718 spin_lock_irqsave(host->host_lock, lock_flags);
6719 sprintf(buffer, "IBM %X Storage Adapter", ioa_cfg->type);
6720 spin_unlock_irqrestore(host->host_lock, lock_flags);
6721
6722 return buffer;
6723 }
6724
6725 static struct scsi_host_template driver_template = {
6726 .module = THIS_MODULE,
6727 .name = "IPR",
6728 .info = ipr_ioa_info,
6729 .ioctl = ipr_ioctl,
6730 .queuecommand = ipr_queuecommand,
6731 .eh_abort_handler = ipr_eh_abort,
6732 .eh_device_reset_handler = ipr_eh_dev_reset,
6733 .eh_host_reset_handler = ipr_eh_host_reset,
6734 .slave_alloc = ipr_slave_alloc,
6735 .slave_configure = ipr_slave_configure,
6736 .slave_destroy = ipr_slave_destroy,
6737 .scan_finished = ipr_scan_finished,
6738 .target_alloc = ipr_target_alloc,
6739 .target_destroy = ipr_target_destroy,
6740 .change_queue_depth = ipr_change_queue_depth,
6741 .bios_param = ipr_biosparam,
6742 .can_queue = IPR_MAX_COMMANDS,
6743 .this_id = -1,
6744 .sg_tablesize = IPR_MAX_SGLIST,
6745 .max_sectors = IPR_IOA_MAX_SECTORS,
6746 .cmd_per_lun = IPR_MAX_CMD_PER_LUN,
6747 .shost_attrs = ipr_ioa_attrs,
6748 .sdev_attrs = ipr_dev_attrs,
6749 .proc_name = IPR_NAME,
6750 };
6751
6752
6753
6754
6755
6756
6757 static void ipr_ata_phy_reset(struct ata_port *ap)
6758 {
6759 unsigned long flags;
6760 struct ipr_sata_port *sata_port = ap->private_data;
6761 struct ipr_resource_entry *res = sata_port->res;
6762 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6763 int rc;
6764
6765 ENTER;
6766 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6767 while (ioa_cfg->in_reset_reload) {
6768 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6769 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
6770 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6771 }
6772
6773 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds)
6774 goto out_unlock;
6775
6776 rc = ipr_device_reset(ioa_cfg, res);
6777
6778 if (rc) {
6779 ap->link.device[0].class = ATA_DEV_NONE;
6780 goto out_unlock;
6781 }
6782
6783 ap->link.device[0].class = res->ata_class;
6784 if (ap->link.device[0].class == ATA_DEV_UNKNOWN)
6785 ap->link.device[0].class = ATA_DEV_NONE;
6786
6787 out_unlock:
6788 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6789 LEAVE;
6790 }
6791
6792
6793
6794
6795
6796
6797
6798
6799 static void ipr_ata_post_internal(struct ata_queued_cmd *qc)
6800 {
6801 struct ipr_sata_port *sata_port = qc->ap->private_data;
6802 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6803 struct ipr_cmnd *ipr_cmd;
6804 struct ipr_hrr_queue *hrrq;
6805 unsigned long flags;
6806
6807 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6808 while (ioa_cfg->in_reset_reload) {
6809 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6810 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
6811 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6812 }
6813
6814 for_each_hrrq(hrrq, ioa_cfg) {
6815 spin_lock(&hrrq->_lock);
6816 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
6817 if (ipr_cmd->qc == qc) {
6818 ipr_device_reset(ioa_cfg, sata_port->res);
6819 break;
6820 }
6821 }
6822 spin_unlock(&hrrq->_lock);
6823 }
6824 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6825 }
6826
6827
6828
6829
6830
6831
6832
6833
6834
6835 static void ipr_copy_sata_tf(struct ipr_ioarcb_ata_regs *regs,
6836 struct ata_taskfile *tf)
6837 {
6838 regs->feature = tf->feature;
6839 regs->nsect = tf->nsect;
6840 regs->lbal = tf->lbal;
6841 regs->lbam = tf->lbam;
6842 regs->lbah = tf->lbah;
6843 regs->device = tf->device;
6844 regs->command = tf->command;
6845 regs->hob_feature = tf->hob_feature;
6846 regs->hob_nsect = tf->hob_nsect;
6847 regs->hob_lbal = tf->hob_lbal;
6848 regs->hob_lbam = tf->hob_lbam;
6849 regs->hob_lbah = tf->hob_lbah;
6850 regs->ctl = tf->ctl;
6851 }
6852
6853
6854
6855
6856
6857
6858
6859
6860
6861
6862
6863 static void ipr_sata_done(struct ipr_cmnd *ipr_cmd)
6864 {
6865 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6866 struct ata_queued_cmd *qc = ipr_cmd->qc;
6867 struct ipr_sata_port *sata_port = qc->ap->private_data;
6868 struct ipr_resource_entry *res = sata_port->res;
6869 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6870
6871 spin_lock(&ipr_cmd->hrrq->_lock);
6872 if (ipr_cmd->ioa_cfg->sis64)
6873 memcpy(&sata_port->ioasa, &ipr_cmd->s.ioasa64.u.gata,
6874 sizeof(struct ipr_ioasa_gata));
6875 else
6876 memcpy(&sata_port->ioasa, &ipr_cmd->s.ioasa.u.gata,
6877 sizeof(struct ipr_ioasa_gata));
6878 ipr_dump_ioasa(ioa_cfg, ipr_cmd, res);
6879
6880 if (be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc_specific) & IPR_ATA_DEVICE_WAS_RESET)
6881 scsi_report_device_reset(ioa_cfg->host, res->bus, res->target);
6882
6883 if (IPR_IOASC_SENSE_KEY(ioasc) > RECOVERED_ERROR)
6884 qc->err_mask |= __ac_err_mask(sata_port->ioasa.status);
6885 else
6886 qc->err_mask |= ac_err_mask(sata_port->ioasa.status);
6887 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6888 spin_unlock(&ipr_cmd->hrrq->_lock);
6889 ata_qc_complete(qc);
6890 }
6891
6892
6893
6894
6895
6896
6897
6898 static void ipr_build_ata_ioadl64(struct ipr_cmnd *ipr_cmd,
6899 struct ata_queued_cmd *qc)
6900 {
6901 u32 ioadl_flags = 0;
6902 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6903 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ata_ioadl.ioadl64;
6904 struct ipr_ioadl64_desc *last_ioadl64 = NULL;
6905 int len = qc->nbytes;
6906 struct scatterlist *sg;
6907 unsigned int si;
6908 dma_addr_t dma_addr = ipr_cmd->dma_addr;
6909
6910 if (len == 0)
6911 return;
6912
6913 if (qc->dma_dir == DMA_TO_DEVICE) {
6914 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
6915 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6916 } else if (qc->dma_dir == DMA_FROM_DEVICE)
6917 ioadl_flags = IPR_IOADL_FLAGS_READ;
6918
6919 ioarcb->data_transfer_length = cpu_to_be32(len);
6920 ioarcb->ioadl_len =
6921 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
6922 ioarcb->u.sis64_addr_data.data_ioadl_addr =
6923 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ata_ioadl.ioadl64));
6924
6925 for_each_sg(qc->sg, sg, qc->n_elem, si) {
6926 ioadl64->flags = cpu_to_be32(ioadl_flags);
6927 ioadl64->data_len = cpu_to_be32(sg_dma_len(sg));
6928 ioadl64->address = cpu_to_be64(sg_dma_address(sg));
6929
6930 last_ioadl64 = ioadl64;
6931 ioadl64++;
6932 }
6933
6934 if (likely(last_ioadl64))
6935 last_ioadl64->flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6936 }
6937
6938
6939
6940
6941
6942
6943
6944 static void ipr_build_ata_ioadl(struct ipr_cmnd *ipr_cmd,
6945 struct ata_queued_cmd *qc)
6946 {
6947 u32 ioadl_flags = 0;
6948 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6949 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
6950 struct ipr_ioadl_desc *last_ioadl = NULL;
6951 int len = qc->nbytes;
6952 struct scatterlist *sg;
6953 unsigned int si;
6954
6955 if (len == 0)
6956 return;
6957
6958 if (qc->dma_dir == DMA_TO_DEVICE) {
6959 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
6960 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6961 ioarcb->data_transfer_length = cpu_to_be32(len);
6962 ioarcb->ioadl_len =
6963 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6964 } else if (qc->dma_dir == DMA_FROM_DEVICE) {
6965 ioadl_flags = IPR_IOADL_FLAGS_READ;
6966 ioarcb->read_data_transfer_length = cpu_to_be32(len);
6967 ioarcb->read_ioadl_len =
6968 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6969 }
6970
6971 for_each_sg(qc->sg, sg, qc->n_elem, si) {
6972 ioadl->flags_and_data_len = cpu_to_be32(ioadl_flags | sg_dma_len(sg));
6973 ioadl->address = cpu_to_be32(sg_dma_address(sg));
6974
6975 last_ioadl = ioadl;
6976 ioadl++;
6977 }
6978
6979 if (likely(last_ioadl))
6980 last_ioadl->flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6981 }
6982
6983
6984
6985
6986
6987
6988
6989
6990 static int ipr_qc_defer(struct ata_queued_cmd *qc)
6991 {
6992 struct ata_port *ap = qc->ap;
6993 struct ipr_sata_port *sata_port = ap->private_data;
6994 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6995 struct ipr_cmnd *ipr_cmd;
6996 struct ipr_hrr_queue *hrrq;
6997 int hrrq_id;
6998
6999 hrrq_id = ipr_get_hrrq_index(ioa_cfg);
7000 hrrq = &ioa_cfg->hrrq[hrrq_id];
7001
7002 qc->lldd_task = NULL;
7003 spin_lock(&hrrq->_lock);
7004 if (unlikely(hrrq->ioa_is_dead)) {
7005 spin_unlock(&hrrq->_lock);
7006 return 0;
7007 }
7008
7009 if (unlikely(!hrrq->allow_cmds)) {
7010 spin_unlock(&hrrq->_lock);
7011 return ATA_DEFER_LINK;
7012 }
7013
7014 ipr_cmd = __ipr_get_free_ipr_cmnd(hrrq);
7015 if (ipr_cmd == NULL) {
7016 spin_unlock(&hrrq->_lock);
7017 return ATA_DEFER_LINK;
7018 }
7019
7020 qc->lldd_task = ipr_cmd;
7021 spin_unlock(&hrrq->_lock);
7022 return 0;
7023 }
7024
7025
7026
7027
7028
7029
7030
7031
7032 static unsigned int ipr_qc_issue(struct ata_queued_cmd *qc)
7033 {
7034 struct ata_port *ap = qc->ap;
7035 struct ipr_sata_port *sata_port = ap->private_data;
7036 struct ipr_resource_entry *res = sata_port->res;
7037 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
7038 struct ipr_cmnd *ipr_cmd;
7039 struct ipr_ioarcb *ioarcb;
7040 struct ipr_ioarcb_ata_regs *regs;
7041
7042 if (qc->lldd_task == NULL)
7043 ipr_qc_defer(qc);
7044
7045 ipr_cmd = qc->lldd_task;
7046 if (ipr_cmd == NULL)
7047 return AC_ERR_SYSTEM;
7048
7049 qc->lldd_task = NULL;
7050 spin_lock(&ipr_cmd->hrrq->_lock);
7051 if (unlikely(!ipr_cmd->hrrq->allow_cmds ||
7052 ipr_cmd->hrrq->ioa_is_dead)) {
7053 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
7054 spin_unlock(&ipr_cmd->hrrq->_lock);
7055 return AC_ERR_SYSTEM;
7056 }
7057
7058 ipr_init_ipr_cmnd(ipr_cmd, ipr_lock_and_done);
7059 ioarcb = &ipr_cmd->ioarcb;
7060
7061 if (ioa_cfg->sis64) {
7062 regs = &ipr_cmd->i.ata_ioadl.regs;
7063 ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb));
7064 } else
7065 regs = &ioarcb->u.add_data.u.regs;
7066
7067 memset(regs, 0, sizeof(*regs));
7068 ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(*regs));
7069
7070 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
7071 ipr_cmd->qc = qc;
7072 ipr_cmd->done = ipr_sata_done;
7073 ipr_cmd->ioarcb.res_handle = res->res_handle;
7074 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_ATA_PASSTHRU;
7075 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC;
7076 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
7077 ipr_cmd->dma_use_sg = qc->n_elem;
7078
7079 if (ioa_cfg->sis64)
7080 ipr_build_ata_ioadl64(ipr_cmd, qc);
7081 else
7082 ipr_build_ata_ioadl(ipr_cmd, qc);
7083
7084 regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION;
7085 ipr_copy_sata_tf(regs, &qc->tf);
7086 memcpy(ioarcb->cmd_pkt.cdb, qc->cdb, IPR_MAX_CDB_LEN);
7087 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res));
7088
7089 switch (qc->tf.protocol) {
7090 case ATA_PROT_NODATA:
7091 case ATA_PROT_PIO:
7092 break;
7093
7094 case ATA_PROT_DMA:
7095 regs->flags |= IPR_ATA_FLAG_XFER_TYPE_DMA;
7096 break;
7097
7098 case ATAPI_PROT_PIO:
7099 case ATAPI_PROT_NODATA:
7100 regs->flags |= IPR_ATA_FLAG_PACKET_CMD;
7101 break;
7102
7103 case ATAPI_PROT_DMA:
7104 regs->flags |= IPR_ATA_FLAG_PACKET_CMD;
7105 regs->flags |= IPR_ATA_FLAG_XFER_TYPE_DMA;
7106 break;
7107
7108 default:
7109 WARN_ON(1);
7110 spin_unlock(&ipr_cmd->hrrq->_lock);
7111 return AC_ERR_INVALID;
7112 }
7113
7114 ipr_send_command(ipr_cmd);
7115 spin_unlock(&ipr_cmd->hrrq->_lock);
7116
7117 return 0;
7118 }
7119
7120
7121
7122
7123
7124
7125
7126
7127 static bool ipr_qc_fill_rtf(struct ata_queued_cmd *qc)
7128 {
7129 struct ipr_sata_port *sata_port = qc->ap->private_data;
7130 struct ipr_ioasa_gata *g = &sata_port->ioasa;
7131 struct ata_taskfile *tf = &qc->result_tf;
7132
7133 tf->feature = g->error;
7134 tf->nsect = g->nsect;
7135 tf->lbal = g->lbal;
7136 tf->lbam = g->lbam;
7137 tf->lbah = g->lbah;
7138 tf->device = g->device;
7139 tf->command = g->status;
7140 tf->hob_nsect = g->hob_nsect;
7141 tf->hob_lbal = g->hob_lbal;
7142 tf->hob_lbam = g->hob_lbam;
7143 tf->hob_lbah = g->hob_lbah;
7144
7145 return true;
7146 }
7147
7148 static struct ata_port_operations ipr_sata_ops = {
7149 .phy_reset = ipr_ata_phy_reset,
7150 .hardreset = ipr_sata_reset,
7151 .post_internal_cmd = ipr_ata_post_internal,
7152 .qc_prep = ata_noop_qc_prep,
7153 .qc_defer = ipr_qc_defer,
7154 .qc_issue = ipr_qc_issue,
7155 .qc_fill_rtf = ipr_qc_fill_rtf,
7156 .port_start = ata_sas_port_start,
7157 .port_stop = ata_sas_port_stop
7158 };
7159
7160 static struct ata_port_info sata_port_info = {
7161 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
7162 ATA_FLAG_SAS_HOST,
7163 .pio_mask = ATA_PIO4_ONLY,
7164 .mwdma_mask = ATA_MWDMA2,
7165 .udma_mask = ATA_UDMA6,
7166 .port_ops = &ipr_sata_ops
7167 };
7168
7169 #ifdef CONFIG_PPC_PSERIES
7170 static const u16 ipr_blocked_processors[] = {
7171 PVR_NORTHSTAR,
7172 PVR_PULSAR,
7173 PVR_POWER4,
7174 PVR_ICESTAR,
7175 PVR_SSTAR,
7176 PVR_POWER4p,
7177 PVR_630,
7178 PVR_630p
7179 };
7180
7181
7182
7183
7184
7185
7186
7187
7188
7189
7190
7191
7192 static int ipr_invalid_adapter(struct ipr_ioa_cfg *ioa_cfg)
7193 {
7194 int i;
7195
7196 if ((ioa_cfg->type == 0x5702) && (ioa_cfg->pdev->revision < 4)) {
7197 for (i = 0; i < ARRAY_SIZE(ipr_blocked_processors); i++) {
7198 if (pvr_version_is(ipr_blocked_processors[i]))
7199 return 1;
7200 }
7201 }
7202 return 0;
7203 }
7204 #else
7205 #define ipr_invalid_adapter(ioa_cfg) 0
7206 #endif
7207
7208
7209
7210
7211
7212
7213
7214
7215
7216
7217
7218 static int ipr_ioa_bringdown_done(struct ipr_cmnd *ipr_cmd)
7219 {
7220 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7221 int i;
7222
7223 ENTER;
7224 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa) {
7225 ipr_trace;
7226 ioa_cfg->scsi_unblock = 1;
7227 schedule_work(&ioa_cfg->work_q);
7228 }
7229
7230 ioa_cfg->in_reset_reload = 0;
7231 ioa_cfg->reset_retries = 0;
7232 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
7233 spin_lock(&ioa_cfg->hrrq[i]._lock);
7234 ioa_cfg->hrrq[i].ioa_is_dead = 1;
7235 spin_unlock(&ioa_cfg->hrrq[i]._lock);
7236 }
7237 wmb();
7238
7239 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
7240 wake_up_all(&ioa_cfg->reset_wait_q);
7241 LEAVE;
7242
7243 return IPR_RC_JOB_RETURN;
7244 }
7245
7246
7247
7248
7249
7250
7251
7252
7253
7254
7255
7256
7257 static int ipr_ioa_reset_done(struct ipr_cmnd *ipr_cmd)
7258 {
7259 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7260 struct ipr_resource_entry *res;
7261 int j;
7262
7263 ENTER;
7264 ioa_cfg->in_reset_reload = 0;
7265 for (j = 0; j < ioa_cfg->hrrq_num; j++) {
7266 spin_lock(&ioa_cfg->hrrq[j]._lock);
7267 ioa_cfg->hrrq[j].allow_cmds = 1;
7268 spin_unlock(&ioa_cfg->hrrq[j]._lock);
7269 }
7270 wmb();
7271 ioa_cfg->reset_cmd = NULL;
7272 ioa_cfg->doorbell |= IPR_RUNTIME_RESET;
7273
7274 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
7275 if (res->add_to_ml || res->del_from_ml) {
7276 ipr_trace;
7277 break;
7278 }
7279 }
7280 schedule_work(&ioa_cfg->work_q);
7281
7282 for (j = 0; j < IPR_NUM_HCAMS; j++) {
7283 list_del_init(&ioa_cfg->hostrcb[j]->queue);
7284 if (j < IPR_NUM_LOG_HCAMS)
7285 ipr_send_hcam(ioa_cfg,
7286 IPR_HCAM_CDB_OP_CODE_LOG_DATA,
7287 ioa_cfg->hostrcb[j]);
7288 else
7289 ipr_send_hcam(ioa_cfg,
7290 IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE,
7291 ioa_cfg->hostrcb[j]);
7292 }
7293
7294 scsi_report_bus_reset(ioa_cfg->host, IPR_VSET_BUS);
7295 dev_info(&ioa_cfg->pdev->dev, "IOA initialized.\n");
7296
7297 ioa_cfg->reset_retries = 0;
7298 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
7299 wake_up_all(&ioa_cfg->reset_wait_q);
7300
7301 ioa_cfg->scsi_unblock = 1;
7302 schedule_work(&ioa_cfg->work_q);
7303 LEAVE;
7304 return IPR_RC_JOB_RETURN;
7305 }
7306
7307
7308
7309
7310
7311
7312
7313
7314
7315 static void ipr_set_sup_dev_dflt(struct ipr_supported_device *supported_dev,
7316 struct ipr_std_inq_vpids *vpids)
7317 {
7318 memset(supported_dev, 0, sizeof(struct ipr_supported_device));
7319 memcpy(&supported_dev->vpids, vpids, sizeof(struct ipr_std_inq_vpids));
7320 supported_dev->num_records = 1;
7321 supported_dev->data_length =
7322 cpu_to_be16(sizeof(struct ipr_supported_device));
7323 supported_dev->reserved = 0;
7324 }
7325
7326
7327
7328
7329
7330
7331
7332
7333
7334
7335 static int ipr_set_supported_devs(struct ipr_cmnd *ipr_cmd)
7336 {
7337 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7338 struct ipr_supported_device *supp_dev = &ioa_cfg->vpd_cbs->supp_dev;
7339 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7340 struct ipr_resource_entry *res = ipr_cmd->u.res;
7341
7342 ipr_cmd->job_step = ipr_ioa_reset_done;
7343
7344 list_for_each_entry_continue(res, &ioa_cfg->used_res_q, queue) {
7345 if (!ipr_is_scsi_disk(res))
7346 continue;
7347
7348 ipr_cmd->u.res = res;
7349 ipr_set_sup_dev_dflt(supp_dev, &res->std_inq_data.vpids);
7350
7351 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7352 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
7353 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7354
7355 ioarcb->cmd_pkt.cdb[0] = IPR_SET_SUPPORTED_DEVICES;
7356 ioarcb->cmd_pkt.cdb[1] = IPR_SET_ALL_SUPPORTED_DEVICES;
7357 ioarcb->cmd_pkt.cdb[7] = (sizeof(struct ipr_supported_device) >> 8) & 0xff;
7358 ioarcb->cmd_pkt.cdb[8] = sizeof(struct ipr_supported_device) & 0xff;
7359
7360 ipr_init_ioadl(ipr_cmd,
7361 ioa_cfg->vpd_cbs_dma +
7362 offsetof(struct ipr_misc_cbs, supp_dev),
7363 sizeof(struct ipr_supported_device),
7364 IPR_IOADL_FLAGS_WRITE_LAST);
7365
7366 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
7367 IPR_SET_SUP_DEVICE_TIMEOUT);
7368
7369 if (!ioa_cfg->sis64)
7370 ipr_cmd->job_step = ipr_set_supported_devs;
7371 LEAVE;
7372 return IPR_RC_JOB_RETURN;
7373 }
7374
7375 LEAVE;
7376 return IPR_RC_JOB_CONTINUE;
7377 }
7378
7379
7380
7381
7382
7383
7384
7385
7386
7387
7388 static void *ipr_get_mode_page(struct ipr_mode_pages *mode_pages,
7389 u32 page_code, u32 len)
7390 {
7391 struct ipr_mode_page_hdr *mode_hdr;
7392 u32 page_length;
7393 u32 length;
7394
7395 if (!mode_pages || (mode_pages->hdr.length == 0))
7396 return NULL;
7397
7398 length = (mode_pages->hdr.length + 1) - 4 - mode_pages->hdr.block_desc_len;
7399 mode_hdr = (struct ipr_mode_page_hdr *)
7400 (mode_pages->data + mode_pages->hdr.block_desc_len);
7401
7402 while (length) {
7403 if (IPR_GET_MODE_PAGE_CODE(mode_hdr) == page_code) {
7404 if (mode_hdr->page_length >= (len - sizeof(struct ipr_mode_page_hdr)))
7405 return mode_hdr;
7406 break;
7407 } else {
7408 page_length = (sizeof(struct ipr_mode_page_hdr) +
7409 mode_hdr->page_length);
7410 length -= page_length;
7411 mode_hdr = (struct ipr_mode_page_hdr *)
7412 ((unsigned long)mode_hdr + page_length);
7413 }
7414 }
7415 return NULL;
7416 }
7417
7418
7419
7420
7421
7422
7423
7424
7425
7426
7427
7428 static void ipr_check_term_power(struct ipr_ioa_cfg *ioa_cfg,
7429 struct ipr_mode_pages *mode_pages)
7430 {
7431 int i;
7432 int entry_length;
7433 struct ipr_dev_bus_entry *bus;
7434 struct ipr_mode_page28 *mode_page;
7435
7436 mode_page = ipr_get_mode_page(mode_pages, 0x28,
7437 sizeof(struct ipr_mode_page28));
7438
7439 entry_length = mode_page->entry_length;
7440
7441 bus = mode_page->bus;
7442
7443 for (i = 0; i < mode_page->num_entries; i++) {
7444 if (bus->flags & IPR_SCSI_ATTR_NO_TERM_PWR) {
7445 dev_err(&ioa_cfg->pdev->dev,
7446 "Term power is absent on scsi bus %d\n",
7447 bus->res_addr.bus);
7448 }
7449
7450 bus = (struct ipr_dev_bus_entry *)((char *)bus + entry_length);
7451 }
7452 }
7453
7454
7455
7456
7457
7458
7459
7460
7461
7462
7463
7464
7465 static void ipr_scsi_bus_speed_limit(struct ipr_ioa_cfg *ioa_cfg)
7466 {
7467 u32 max_xfer_rate;
7468 int i;
7469
7470 for (i = 0; i < IPR_MAX_NUM_BUSES; i++) {
7471 max_xfer_rate = ipr_get_max_scsi_speed(ioa_cfg, i,
7472 ioa_cfg->bus_attr[i].bus_width);
7473
7474 if (max_xfer_rate < ioa_cfg->bus_attr[i].max_xfer_rate)
7475 ioa_cfg->bus_attr[i].max_xfer_rate = max_xfer_rate;
7476 }
7477 }
7478
7479
7480
7481
7482
7483
7484
7485
7486
7487
7488
7489 static void ipr_modify_ioafp_mode_page_28(struct ipr_ioa_cfg *ioa_cfg,
7490 struct ipr_mode_pages *mode_pages)
7491 {
7492 int i, entry_length;
7493 struct ipr_dev_bus_entry *bus;
7494 struct ipr_bus_attributes *bus_attr;
7495 struct ipr_mode_page28 *mode_page;
7496
7497 mode_page = ipr_get_mode_page(mode_pages, 0x28,
7498 sizeof(struct ipr_mode_page28));
7499
7500 entry_length = mode_page->entry_length;
7501
7502
7503 for (i = 0, bus = mode_page->bus;
7504 i < mode_page->num_entries;
7505 i++, bus = (struct ipr_dev_bus_entry *)((u8 *)bus + entry_length)) {
7506 if (bus->res_addr.bus > IPR_MAX_NUM_BUSES) {
7507 dev_err(&ioa_cfg->pdev->dev,
7508 "Invalid resource address reported: 0x%08X\n",
7509 IPR_GET_PHYS_LOC(bus->res_addr));
7510 continue;
7511 }
7512
7513 bus_attr = &ioa_cfg->bus_attr[i];
7514 bus->extended_reset_delay = IPR_EXTENDED_RESET_DELAY;
7515 bus->bus_width = bus_attr->bus_width;
7516 bus->max_xfer_rate = cpu_to_be32(bus_attr->max_xfer_rate);
7517 bus->flags &= ~IPR_SCSI_ATTR_QAS_MASK;
7518 if (bus_attr->qas_enabled)
7519 bus->flags |= IPR_SCSI_ATTR_ENABLE_QAS;
7520 else
7521 bus->flags |= IPR_SCSI_ATTR_DISABLE_QAS;
7522 }
7523 }
7524
7525
7526
7527
7528
7529
7530
7531
7532
7533
7534
7535
7536 static void ipr_build_mode_select(struct ipr_cmnd *ipr_cmd,
7537 __be32 res_handle, u8 parm,
7538 dma_addr_t dma_addr, u8 xfer_len)
7539 {
7540 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7541
7542 ioarcb->res_handle = res_handle;
7543 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7544 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
7545 ioarcb->cmd_pkt.cdb[0] = MODE_SELECT;
7546 ioarcb->cmd_pkt.cdb[1] = parm;
7547 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7548
7549 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_WRITE_LAST);
7550 }
7551
7552
7553
7554
7555
7556
7557
7558
7559
7560
7561
7562 static int ipr_ioafp_mode_select_page28(struct ipr_cmnd *ipr_cmd)
7563 {
7564 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7565 struct ipr_mode_pages *mode_pages = &ioa_cfg->vpd_cbs->mode_pages;
7566 int length;
7567
7568 ENTER;
7569 ipr_scsi_bus_speed_limit(ioa_cfg);
7570 ipr_check_term_power(ioa_cfg, mode_pages);
7571 ipr_modify_ioafp_mode_page_28(ioa_cfg, mode_pages);
7572 length = mode_pages->hdr.length + 1;
7573 mode_pages->hdr.length = 0;
7574
7575 ipr_build_mode_select(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE), 0x11,
7576 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, mode_pages),
7577 length);
7578
7579 ipr_cmd->job_step = ipr_set_supported_devs;
7580 ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next,
7581 struct ipr_resource_entry, queue);
7582 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7583
7584 LEAVE;
7585 return IPR_RC_JOB_RETURN;
7586 }
7587
7588
7589
7590
7591
7592
7593
7594
7595
7596
7597
7598
7599 static void ipr_build_mode_sense(struct ipr_cmnd *ipr_cmd,
7600 __be32 res_handle,
7601 u8 parm, dma_addr_t dma_addr, u8 xfer_len)
7602 {
7603 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7604
7605 ioarcb->res_handle = res_handle;
7606 ioarcb->cmd_pkt.cdb[0] = MODE_SENSE;
7607 ioarcb->cmd_pkt.cdb[2] = parm;
7608 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7609 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7610
7611 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST);
7612 }
7613
7614
7615
7616
7617
7618
7619
7620
7621
7622
7623 static int ipr_reset_cmd_failed(struct ipr_cmnd *ipr_cmd)
7624 {
7625 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7626 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7627
7628 dev_err(&ioa_cfg->pdev->dev,
7629 "0x%02X failed with IOASC: 0x%08X\n",
7630 ipr_cmd->ioarcb.cmd_pkt.cdb[0], ioasc);
7631
7632 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
7633 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
7634 return IPR_RC_JOB_RETURN;
7635 }
7636
7637
7638
7639
7640
7641
7642
7643
7644
7645
7646
7647 static int ipr_reset_mode_sense_failed(struct ipr_cmnd *ipr_cmd)
7648 {
7649 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7650 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7651
7652 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT) {
7653 ipr_cmd->job_step = ipr_set_supported_devs;
7654 ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next,
7655 struct ipr_resource_entry, queue);
7656 return IPR_RC_JOB_CONTINUE;
7657 }
7658
7659 return ipr_reset_cmd_failed(ipr_cmd);
7660 }
7661
7662
7663
7664
7665
7666
7667
7668
7669
7670
7671
7672 static int ipr_ioafp_mode_sense_page28(struct ipr_cmnd *ipr_cmd)
7673 {
7674 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7675
7676 ENTER;
7677 ipr_build_mode_sense(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE),
7678 0x28, ioa_cfg->vpd_cbs_dma +
7679 offsetof(struct ipr_misc_cbs, mode_pages),
7680 sizeof(struct ipr_mode_pages));
7681
7682 ipr_cmd->job_step = ipr_ioafp_mode_select_page28;
7683 ipr_cmd->job_step_failed = ipr_reset_mode_sense_failed;
7684
7685 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7686
7687 LEAVE;
7688 return IPR_RC_JOB_RETURN;
7689 }
7690
7691
7692
7693
7694
7695
7696
7697
7698
7699
7700 static int ipr_ioafp_mode_select_page24(struct ipr_cmnd *ipr_cmd)
7701 {
7702 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7703 struct ipr_mode_pages *mode_pages = &ioa_cfg->vpd_cbs->mode_pages;
7704 struct ipr_mode_page24 *mode_page;
7705 int length;
7706
7707 ENTER;
7708 mode_page = ipr_get_mode_page(mode_pages, 0x24,
7709 sizeof(struct ipr_mode_page24));
7710
7711 if (mode_page)
7712 mode_page->flags |= IPR_ENABLE_DUAL_IOA_AF;
7713
7714 length = mode_pages->hdr.length + 1;
7715 mode_pages->hdr.length = 0;
7716
7717 ipr_build_mode_select(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE), 0x11,
7718 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, mode_pages),
7719 length);
7720
7721 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7722 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7723
7724 LEAVE;
7725 return IPR_RC_JOB_RETURN;
7726 }
7727
7728
7729
7730
7731
7732
7733
7734
7735
7736
7737
7738 static int ipr_reset_mode_sense_page24_failed(struct ipr_cmnd *ipr_cmd)
7739 {
7740 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7741
7742 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT) {
7743 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7744 return IPR_RC_JOB_CONTINUE;
7745 }
7746
7747 return ipr_reset_cmd_failed(ipr_cmd);
7748 }
7749
7750
7751
7752
7753
7754
7755
7756
7757
7758
7759
7760 static int ipr_ioafp_mode_sense_page24(struct ipr_cmnd *ipr_cmd)
7761 {
7762 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7763
7764 ENTER;
7765 ipr_build_mode_sense(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE),
7766 0x24, ioa_cfg->vpd_cbs_dma +
7767 offsetof(struct ipr_misc_cbs, mode_pages),
7768 sizeof(struct ipr_mode_pages));
7769
7770 ipr_cmd->job_step = ipr_ioafp_mode_select_page24;
7771 ipr_cmd->job_step_failed = ipr_reset_mode_sense_page24_failed;
7772
7773 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7774
7775 LEAVE;
7776 return IPR_RC_JOB_RETURN;
7777 }
7778
7779
7780
7781
7782
7783
7784
7785
7786
7787
7788
7789
7790
7791 static int ipr_init_res_table(struct ipr_cmnd *ipr_cmd)
7792 {
7793 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7794 struct ipr_resource_entry *res, *temp;
7795 struct ipr_config_table_entry_wrapper cfgtew;
7796 int entries, found, flag, i;
7797 LIST_HEAD(old_res);
7798
7799 ENTER;
7800 if (ioa_cfg->sis64)
7801 flag = ioa_cfg->u.cfg_table64->hdr64.flags;
7802 else
7803 flag = ioa_cfg->u.cfg_table->hdr.flags;
7804
7805 if (flag & IPR_UCODE_DOWNLOAD_REQ)
7806 dev_err(&ioa_cfg->pdev->dev, "Microcode download required\n");
7807
7808 list_for_each_entry_safe(res, temp, &ioa_cfg->used_res_q, queue)
7809 list_move_tail(&res->queue, &old_res);
7810
7811 if (ioa_cfg->sis64)
7812 entries = be16_to_cpu(ioa_cfg->u.cfg_table64->hdr64.num_entries);
7813 else
7814 entries = ioa_cfg->u.cfg_table->hdr.num_entries;
7815
7816 for (i = 0; i < entries; i++) {
7817 if (ioa_cfg->sis64)
7818 cfgtew.u.cfgte64 = &ioa_cfg->u.cfg_table64->dev[i];
7819 else
7820 cfgtew.u.cfgte = &ioa_cfg->u.cfg_table->dev[i];
7821 found = 0;
7822
7823 list_for_each_entry_safe(res, temp, &old_res, queue) {
7824 if (ipr_is_same_device(res, &cfgtew)) {
7825 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7826 found = 1;
7827 break;
7828 }
7829 }
7830
7831 if (!found) {
7832 if (list_empty(&ioa_cfg->free_res_q)) {
7833 dev_err(&ioa_cfg->pdev->dev, "Too many devices attached\n");
7834 break;
7835 }
7836
7837 found = 1;
7838 res = list_entry(ioa_cfg->free_res_q.next,
7839 struct ipr_resource_entry, queue);
7840 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7841 ipr_init_res_entry(res, &cfgtew);
7842 res->add_to_ml = 1;
7843 } else if (res->sdev && (ipr_is_vset_device(res) || ipr_is_scsi_disk(res)))
7844 res->sdev->allow_restart = 1;
7845
7846 if (found)
7847 ipr_update_res_entry(res, &cfgtew);
7848 }
7849
7850 list_for_each_entry_safe(res, temp, &old_res, queue) {
7851 if (res->sdev) {
7852 res->del_from_ml = 1;
7853 res->res_handle = IPR_INVALID_RES_HANDLE;
7854 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7855 }
7856 }
7857
7858 list_for_each_entry_safe(res, temp, &old_res, queue) {
7859 ipr_clear_res_target(res);
7860 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
7861 }
7862
7863 if (ioa_cfg->dual_raid && ipr_dual_ioa_raid)
7864 ipr_cmd->job_step = ipr_ioafp_mode_sense_page24;
7865 else
7866 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7867
7868 LEAVE;
7869 return IPR_RC_JOB_CONTINUE;
7870 }
7871
7872
7873
7874
7875
7876
7877
7878
7879
7880
7881
7882 static int ipr_ioafp_query_ioa_cfg(struct ipr_cmnd *ipr_cmd)
7883 {
7884 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7885 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7886 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
7887 struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap;
7888
7889 ENTER;
7890 if (cap->cap & IPR_CAP_DUAL_IOA_RAID)
7891 ioa_cfg->dual_raid = 1;
7892 dev_info(&ioa_cfg->pdev->dev, "Adapter firmware version: %02X%02X%02X%02X\n",
7893 ucode_vpd->major_release, ucode_vpd->card_type,
7894 ucode_vpd->minor_release[0], ucode_vpd->minor_release[1]);
7895 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7896 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7897
7898 ioarcb->cmd_pkt.cdb[0] = IPR_QUERY_IOA_CONFIG;
7899 ioarcb->cmd_pkt.cdb[6] = (ioa_cfg->cfg_table_size >> 16) & 0xff;
7900 ioarcb->cmd_pkt.cdb[7] = (ioa_cfg->cfg_table_size >> 8) & 0xff;
7901 ioarcb->cmd_pkt.cdb[8] = ioa_cfg->cfg_table_size & 0xff;
7902
7903 ipr_init_ioadl(ipr_cmd, ioa_cfg->cfg_table_dma, ioa_cfg->cfg_table_size,
7904 IPR_IOADL_FLAGS_READ_LAST);
7905
7906 ipr_cmd->job_step = ipr_init_res_table;
7907
7908 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7909
7910 LEAVE;
7911 return IPR_RC_JOB_RETURN;
7912 }
7913
7914 static int ipr_ioa_service_action_failed(struct ipr_cmnd *ipr_cmd)
7915 {
7916 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7917
7918 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT)
7919 return IPR_RC_JOB_CONTINUE;
7920
7921 return ipr_reset_cmd_failed(ipr_cmd);
7922 }
7923
7924 static void ipr_build_ioa_service_action(struct ipr_cmnd *ipr_cmd,
7925 __be32 res_handle, u8 sa_code)
7926 {
7927 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7928
7929 ioarcb->res_handle = res_handle;
7930 ioarcb->cmd_pkt.cdb[0] = IPR_IOA_SERVICE_ACTION;
7931 ioarcb->cmd_pkt.cdb[1] = sa_code;
7932 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7933 }
7934
7935
7936
7937
7938
7939
7940
7941
7942 static int ipr_ioafp_set_caching_parameters(struct ipr_cmnd *ipr_cmd)
7943 {
7944 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7945 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7946 struct ipr_inquiry_pageC4 *pageC4 = &ioa_cfg->vpd_cbs->pageC4_data;
7947
7948 ENTER;
7949
7950 ipr_cmd->job_step = ipr_ioafp_query_ioa_cfg;
7951
7952 if (pageC4->cache_cap[0] & IPR_CAP_SYNC_CACHE) {
7953 ipr_build_ioa_service_action(ipr_cmd,
7954 cpu_to_be32(IPR_IOA_RES_HANDLE),
7955 IPR_IOA_SA_CHANGE_CACHE_PARAMS);
7956
7957 ioarcb->cmd_pkt.cdb[2] = 0x40;
7958
7959 ipr_cmd->job_step_failed = ipr_ioa_service_action_failed;
7960 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
7961 IPR_SET_SUP_DEVICE_TIMEOUT);
7962
7963 LEAVE;
7964 return IPR_RC_JOB_RETURN;
7965 }
7966
7967 LEAVE;
7968 return IPR_RC_JOB_CONTINUE;
7969 }
7970
7971
7972
7973
7974
7975
7976
7977
7978
7979
7980 static void ipr_ioafp_inquiry(struct ipr_cmnd *ipr_cmd, u8 flags, u8 page,
7981 dma_addr_t dma_addr, u8 xfer_len)
7982 {
7983 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7984
7985 ENTER;
7986 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7987 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7988
7989 ioarcb->cmd_pkt.cdb[0] = INQUIRY;
7990 ioarcb->cmd_pkt.cdb[1] = flags;
7991 ioarcb->cmd_pkt.cdb[2] = page;
7992 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7993
7994 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST);
7995
7996 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7997 LEAVE;
7998 }
7999
8000
8001
8002
8003
8004
8005
8006
8007
8008
8009
8010 static int ipr_inquiry_page_supported(struct ipr_inquiry_page0 *page0, u8 page)
8011 {
8012 int i;
8013
8014 for (i = 0; i < min_t(u8, page0->len, IPR_INQUIRY_PAGE0_ENTRIES); i++)
8015 if (page0->page[i] == page)
8016 return 1;
8017
8018 return 0;
8019 }
8020
8021
8022
8023
8024
8025
8026
8027
8028
8029
8030
8031 static int ipr_ioafp_pageC4_inquiry(struct ipr_cmnd *ipr_cmd)
8032 {
8033 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8034 struct ipr_inquiry_page0 *page0 = &ioa_cfg->vpd_cbs->page0_data;
8035 struct ipr_inquiry_pageC4 *pageC4 = &ioa_cfg->vpd_cbs->pageC4_data;
8036
8037 ENTER;
8038 ipr_cmd->job_step = ipr_ioafp_set_caching_parameters;
8039 memset(pageC4, 0, sizeof(*pageC4));
8040
8041 if (ipr_inquiry_page_supported(page0, 0xC4)) {
8042 ipr_ioafp_inquiry(ipr_cmd, 1, 0xC4,
8043 (ioa_cfg->vpd_cbs_dma
8044 + offsetof(struct ipr_misc_cbs,
8045 pageC4_data)),
8046 sizeof(struct ipr_inquiry_pageC4));
8047 return IPR_RC_JOB_RETURN;
8048 }
8049
8050 LEAVE;
8051 return IPR_RC_JOB_CONTINUE;
8052 }
8053
8054
8055
8056
8057
8058
8059
8060
8061
8062
8063
8064 static int ipr_ioafp_cap_inquiry(struct ipr_cmnd *ipr_cmd)
8065 {
8066 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8067 struct ipr_inquiry_page0 *page0 = &ioa_cfg->vpd_cbs->page0_data;
8068 struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap;
8069
8070 ENTER;
8071 ipr_cmd->job_step = ipr_ioafp_pageC4_inquiry;
8072 memset(cap, 0, sizeof(*cap));
8073
8074 if (ipr_inquiry_page_supported(page0, 0xD0)) {
8075 ipr_ioafp_inquiry(ipr_cmd, 1, 0xD0,
8076 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, cap),
8077 sizeof(struct ipr_inquiry_cap));
8078 return IPR_RC_JOB_RETURN;
8079 }
8080
8081 LEAVE;
8082 return IPR_RC_JOB_CONTINUE;
8083 }
8084
8085
8086
8087
8088
8089
8090
8091
8092
8093
8094
8095 static int ipr_ioafp_page3_inquiry(struct ipr_cmnd *ipr_cmd)
8096 {
8097 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8098
8099 ENTER;
8100
8101 ipr_cmd->job_step = ipr_ioafp_cap_inquiry;
8102
8103 ipr_ioafp_inquiry(ipr_cmd, 1, 3,
8104 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, page3_data),
8105 sizeof(struct ipr_inquiry_page3));
8106
8107 LEAVE;
8108 return IPR_RC_JOB_RETURN;
8109 }
8110
8111
8112
8113
8114
8115
8116
8117
8118
8119
8120
8121 static int ipr_ioafp_page0_inquiry(struct ipr_cmnd *ipr_cmd)
8122 {
8123 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8124 char type[5];
8125
8126 ENTER;
8127
8128
8129 memcpy(type, ioa_cfg->vpd_cbs->ioa_vpd.std_inq_data.vpids.product_id, 4);
8130 type[4] = '\0';
8131 ioa_cfg->type = simple_strtoul((char *)type, NULL, 16);
8132
8133 if (ipr_invalid_adapter(ioa_cfg)) {
8134 dev_err(&ioa_cfg->pdev->dev,
8135 "Adapter not supported in this hardware configuration.\n");
8136
8137 if (!ipr_testmode) {
8138 ioa_cfg->reset_retries += IPR_NUM_RESET_RELOAD_RETRIES;
8139 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
8140 list_add_tail(&ipr_cmd->queue,
8141 &ioa_cfg->hrrq->hrrq_free_q);
8142 return IPR_RC_JOB_RETURN;
8143 }
8144 }
8145
8146 ipr_cmd->job_step = ipr_ioafp_page3_inquiry;
8147
8148 ipr_ioafp_inquiry(ipr_cmd, 1, 0,
8149 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, page0_data),
8150 sizeof(struct ipr_inquiry_page0));
8151
8152 LEAVE;
8153 return IPR_RC_JOB_RETURN;
8154 }
8155
8156
8157
8158
8159
8160
8161
8162
8163
8164
8165 static int ipr_ioafp_std_inquiry(struct ipr_cmnd *ipr_cmd)
8166 {
8167 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8168
8169 ENTER;
8170 ipr_cmd->job_step = ipr_ioafp_page0_inquiry;
8171
8172 ipr_ioafp_inquiry(ipr_cmd, 0, 0,
8173 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, ioa_vpd),
8174 sizeof(struct ipr_ioa_vpd));
8175
8176 LEAVE;
8177 return IPR_RC_JOB_RETURN;
8178 }
8179
8180
8181
8182
8183
8184
8185
8186
8187
8188
8189
8190 static int ipr_ioafp_identify_hrrq(struct ipr_cmnd *ipr_cmd)
8191 {
8192 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8193 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
8194 struct ipr_hrr_queue *hrrq;
8195
8196 ENTER;
8197 ipr_cmd->job_step = ipr_ioafp_std_inquiry;
8198 if (ioa_cfg->identify_hrrq_index == 0)
8199 dev_info(&ioa_cfg->pdev->dev, "Starting IOA initialization sequence.\n");
8200
8201 if (ioa_cfg->identify_hrrq_index < ioa_cfg->hrrq_num) {
8202 hrrq = &ioa_cfg->hrrq[ioa_cfg->identify_hrrq_index];
8203
8204 ioarcb->cmd_pkt.cdb[0] = IPR_ID_HOST_RR_Q;
8205 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
8206
8207 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
8208 if (ioa_cfg->sis64)
8209 ioarcb->cmd_pkt.cdb[1] = 0x1;
8210
8211 if (ioa_cfg->nvectors == 1)
8212 ioarcb->cmd_pkt.cdb[1] &= ~IPR_ID_HRRQ_SELE_ENABLE;
8213 else
8214 ioarcb->cmd_pkt.cdb[1] |= IPR_ID_HRRQ_SELE_ENABLE;
8215
8216 ioarcb->cmd_pkt.cdb[2] =
8217 ((u64) hrrq->host_rrq_dma >> 24) & 0xff;
8218 ioarcb->cmd_pkt.cdb[3] =
8219 ((u64) hrrq->host_rrq_dma >> 16) & 0xff;
8220 ioarcb->cmd_pkt.cdb[4] =
8221 ((u64) hrrq->host_rrq_dma >> 8) & 0xff;
8222 ioarcb->cmd_pkt.cdb[5] =
8223 ((u64) hrrq->host_rrq_dma) & 0xff;
8224 ioarcb->cmd_pkt.cdb[7] =
8225 ((sizeof(u32) * hrrq->size) >> 8) & 0xff;
8226 ioarcb->cmd_pkt.cdb[8] =
8227 (sizeof(u32) * hrrq->size) & 0xff;
8228
8229 if (ioarcb->cmd_pkt.cdb[1] & IPR_ID_HRRQ_SELE_ENABLE)
8230 ioarcb->cmd_pkt.cdb[9] =
8231 ioa_cfg->identify_hrrq_index;
8232
8233 if (ioa_cfg->sis64) {
8234 ioarcb->cmd_pkt.cdb[10] =
8235 ((u64) hrrq->host_rrq_dma >> 56) & 0xff;
8236 ioarcb->cmd_pkt.cdb[11] =
8237 ((u64) hrrq->host_rrq_dma >> 48) & 0xff;
8238 ioarcb->cmd_pkt.cdb[12] =
8239 ((u64) hrrq->host_rrq_dma >> 40) & 0xff;
8240 ioarcb->cmd_pkt.cdb[13] =
8241 ((u64) hrrq->host_rrq_dma >> 32) & 0xff;
8242 }
8243
8244 if (ioarcb->cmd_pkt.cdb[1] & IPR_ID_HRRQ_SELE_ENABLE)
8245 ioarcb->cmd_pkt.cdb[14] =
8246 ioa_cfg->identify_hrrq_index;
8247
8248 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
8249 IPR_INTERNAL_TIMEOUT);
8250
8251 if (++ioa_cfg->identify_hrrq_index < ioa_cfg->hrrq_num)
8252 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
8253
8254 LEAVE;
8255 return IPR_RC_JOB_RETURN;
8256 }
8257
8258 LEAVE;
8259 return IPR_RC_JOB_CONTINUE;
8260 }
8261
8262
8263
8264
8265
8266
8267
8268
8269
8270
8271
8272
8273
8274
8275 static void ipr_reset_timer_done(struct timer_list *t)
8276 {
8277 struct ipr_cmnd *ipr_cmd = from_timer(ipr_cmd, t, timer);
8278 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8279 unsigned long lock_flags = 0;
8280
8281 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
8282
8283 if (ioa_cfg->reset_cmd == ipr_cmd) {
8284 list_del(&ipr_cmd->queue);
8285 ipr_cmd->done(ipr_cmd);
8286 }
8287
8288 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
8289 }
8290
8291
8292
8293
8294
8295
8296
8297
8298
8299
8300
8301
8302
8303
8304
8305 static void ipr_reset_start_timer(struct ipr_cmnd *ipr_cmd,
8306 unsigned long timeout)
8307 {
8308
8309 ENTER;
8310 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
8311 ipr_cmd->done = ipr_reset_ioa_job;
8312
8313 ipr_cmd->timer.expires = jiffies + timeout;
8314 ipr_cmd->timer.function = ipr_reset_timer_done;
8315 add_timer(&ipr_cmd->timer);
8316 }
8317
8318
8319
8320
8321
8322
8323
8324
8325 static void ipr_init_ioa_mem(struct ipr_ioa_cfg *ioa_cfg)
8326 {
8327 struct ipr_hrr_queue *hrrq;
8328
8329 for_each_hrrq(hrrq, ioa_cfg) {
8330 spin_lock(&hrrq->_lock);
8331 memset(hrrq->host_rrq, 0, sizeof(u32) * hrrq->size);
8332
8333
8334 hrrq->hrrq_start = hrrq->host_rrq;
8335 hrrq->hrrq_end = &hrrq->host_rrq[hrrq->size - 1];
8336 hrrq->hrrq_curr = hrrq->hrrq_start;
8337 hrrq->toggle_bit = 1;
8338 spin_unlock(&hrrq->_lock);
8339 }
8340 wmb();
8341
8342 ioa_cfg->identify_hrrq_index = 0;
8343 if (ioa_cfg->hrrq_num == 1)
8344 atomic_set(&ioa_cfg->hrrq_index, 0);
8345 else
8346 atomic_set(&ioa_cfg->hrrq_index, 1);
8347
8348
8349 memset(ioa_cfg->u.cfg_table, 0, ioa_cfg->cfg_table_size);
8350 }
8351
8352
8353
8354
8355
8356
8357
8358
8359 static int ipr_reset_next_stage(struct ipr_cmnd *ipr_cmd)
8360 {
8361 unsigned long stage, stage_time;
8362 u32 feedback;
8363 volatile u32 int_reg;
8364 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8365 u64 maskval = 0;
8366
8367 feedback = readl(ioa_cfg->regs.init_feedback_reg);
8368 stage = feedback & IPR_IPL_INIT_STAGE_MASK;
8369 stage_time = feedback & IPR_IPL_INIT_STAGE_TIME_MASK;
8370
8371 ipr_dbg("IPL stage = 0x%lx, IPL stage time = %ld\n", stage, stage_time);
8372
8373
8374 if (stage_time == 0)
8375 stage_time = IPR_IPL_INIT_DEFAULT_STAGE_TIME;
8376 else if (stage_time < IPR_IPL_INIT_MIN_STAGE_TIME)
8377 stage_time = IPR_IPL_INIT_MIN_STAGE_TIME;
8378 else if (stage_time > IPR_LONG_OPERATIONAL_TIMEOUT)
8379 stage_time = IPR_LONG_OPERATIONAL_TIMEOUT;
8380
8381 if (stage == IPR_IPL_INIT_STAGE_UNKNOWN) {
8382 writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.set_interrupt_mask_reg);
8383 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
8384 stage_time = ioa_cfg->transop_timeout;
8385 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
8386 } else if (stage == IPR_IPL_INIT_STAGE_TRANSOP) {
8387 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
8388 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
8389 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
8390 maskval = IPR_PCII_IPL_STAGE_CHANGE;
8391 maskval = (maskval << 32) | IPR_PCII_IOA_TRANS_TO_OPER;
8392 writeq(maskval, ioa_cfg->regs.set_interrupt_mask_reg);
8393 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
8394 return IPR_RC_JOB_CONTINUE;
8395 }
8396 }
8397
8398 ipr_cmd->timer.expires = jiffies + stage_time * HZ;
8399 ipr_cmd->timer.function = ipr_oper_timeout;
8400 ipr_cmd->done = ipr_reset_ioa_job;
8401 add_timer(&ipr_cmd->timer);
8402
8403 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
8404
8405 return IPR_RC_JOB_RETURN;
8406 }
8407
8408
8409
8410
8411
8412
8413
8414
8415
8416
8417
8418 static int ipr_reset_enable_ioa(struct ipr_cmnd *ipr_cmd)
8419 {
8420 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8421 volatile u32 int_reg;
8422 volatile u64 maskval;
8423 int i;
8424
8425 ENTER;
8426 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
8427 ipr_init_ioa_mem(ioa_cfg);
8428
8429 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
8430 spin_lock(&ioa_cfg->hrrq[i]._lock);
8431 ioa_cfg->hrrq[i].allow_interrupts = 1;
8432 spin_unlock(&ioa_cfg->hrrq[i]._lock);
8433 }
8434 if (ioa_cfg->sis64) {
8435
8436 writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
8437 int_reg = readl(ioa_cfg->regs.endian_swap_reg);
8438 }
8439
8440 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
8441
8442 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
8443 writel((IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED),
8444 ioa_cfg->regs.clr_interrupt_mask_reg32);
8445 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
8446 return IPR_RC_JOB_CONTINUE;
8447 }
8448
8449
8450 writel(ioa_cfg->doorbell, ioa_cfg->regs.set_uproc_interrupt_reg32);
8451
8452 if (ioa_cfg->sis64) {
8453 maskval = IPR_PCII_IPL_STAGE_CHANGE;
8454 maskval = (maskval << 32) | IPR_PCII_OPER_INTERRUPTS;
8455 writeq(maskval, ioa_cfg->regs.clr_interrupt_mask_reg);
8456 } else
8457 writel(IPR_PCII_OPER_INTERRUPTS, ioa_cfg->regs.clr_interrupt_mask_reg32);
8458
8459 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
8460
8461 dev_info(&ioa_cfg->pdev->dev, "Initializing IOA.\n");
8462
8463 if (ioa_cfg->sis64) {
8464 ipr_cmd->job_step = ipr_reset_next_stage;
8465 return IPR_RC_JOB_CONTINUE;
8466 }
8467
8468 ipr_cmd->timer.expires = jiffies + (ioa_cfg->transop_timeout * HZ);
8469 ipr_cmd->timer.function = ipr_oper_timeout;
8470 ipr_cmd->done = ipr_reset_ioa_job;
8471 add_timer(&ipr_cmd->timer);
8472 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
8473
8474 LEAVE;
8475 return IPR_RC_JOB_RETURN;
8476 }
8477
8478
8479
8480
8481
8482
8483
8484
8485
8486
8487
8488 static int ipr_reset_wait_for_dump(struct ipr_cmnd *ipr_cmd)
8489 {
8490 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8491
8492 if (ioa_cfg->sdt_state == GET_DUMP)
8493 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
8494 else if (ioa_cfg->sdt_state == READ_DUMP)
8495 ioa_cfg->sdt_state = ABORT_DUMP;
8496
8497 ioa_cfg->dump_timeout = 1;
8498 ipr_cmd->job_step = ipr_reset_alert;
8499
8500 return IPR_RC_JOB_CONTINUE;
8501 }
8502
8503
8504
8505
8506
8507
8508
8509
8510
8511
8512
8513 static void ipr_unit_check_no_data(struct ipr_ioa_cfg *ioa_cfg)
8514 {
8515 ioa_cfg->errors_logged++;
8516 dev_err(&ioa_cfg->pdev->dev, "IOA unit check with no data\n");
8517 }
8518
8519
8520
8521
8522
8523
8524
8525
8526
8527
8528
8529 static void ipr_get_unit_check_buffer(struct ipr_ioa_cfg *ioa_cfg)
8530 {
8531 unsigned long mailbox;
8532 struct ipr_hostrcb *hostrcb;
8533 struct ipr_uc_sdt sdt;
8534 int rc, length;
8535 u32 ioasc;
8536
8537 mailbox = readl(ioa_cfg->ioa_mailbox);
8538
8539 if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(mailbox)) {
8540 ipr_unit_check_no_data(ioa_cfg);
8541 return;
8542 }
8543
8544 memset(&sdt, 0, sizeof(struct ipr_uc_sdt));
8545 rc = ipr_get_ldump_data_section(ioa_cfg, mailbox, (__be32 *) &sdt,
8546 (sizeof(struct ipr_uc_sdt)) / sizeof(__be32));
8547
8548 if (rc || !(sdt.entry[0].flags & IPR_SDT_VALID_ENTRY) ||
8549 ((be32_to_cpu(sdt.hdr.state) != IPR_FMT3_SDT_READY_TO_USE) &&
8550 (be32_to_cpu(sdt.hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) {
8551 ipr_unit_check_no_data(ioa_cfg);
8552 return;
8553 }
8554
8555
8556 if (be32_to_cpu(sdt.hdr.state) == IPR_FMT3_SDT_READY_TO_USE)
8557 length = be32_to_cpu(sdt.entry[0].end_token);
8558 else
8559 length = (be32_to_cpu(sdt.entry[0].end_token) -
8560 be32_to_cpu(sdt.entry[0].start_token)) &
8561 IPR_FMT2_MBX_ADDR_MASK;
8562
8563 hostrcb = list_entry(ioa_cfg->hostrcb_free_q.next,
8564 struct ipr_hostrcb, queue);
8565 list_del_init(&hostrcb->queue);
8566 memset(&hostrcb->hcam, 0, sizeof(hostrcb->hcam));
8567
8568 rc = ipr_get_ldump_data_section(ioa_cfg,
8569 be32_to_cpu(sdt.entry[0].start_token),
8570 (__be32 *)&hostrcb->hcam,
8571 min(length, (int)sizeof(hostrcb->hcam)) / sizeof(__be32));
8572
8573 if (!rc) {
8574 ipr_handle_log_data(ioa_cfg, hostrcb);
8575 ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
8576 if (ioasc == IPR_IOASC_NR_IOA_RESET_REQUIRED &&
8577 ioa_cfg->sdt_state == GET_DUMP)
8578 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
8579 } else
8580 ipr_unit_check_no_data(ioa_cfg);
8581
8582 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
8583 }
8584
8585
8586
8587
8588
8589
8590
8591
8592
8593
8594 static int ipr_reset_get_unit_check_job(struct ipr_cmnd *ipr_cmd)
8595 {
8596 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8597
8598 ENTER;
8599 ioa_cfg->ioa_unit_checked = 0;
8600 ipr_get_unit_check_buffer(ioa_cfg);
8601 ipr_cmd->job_step = ipr_reset_alert;
8602 ipr_reset_start_timer(ipr_cmd, 0);
8603
8604 LEAVE;
8605 return IPR_RC_JOB_RETURN;
8606 }
8607
8608 static int ipr_dump_mailbox_wait(struct ipr_cmnd *ipr_cmd)
8609 {
8610 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8611
8612 ENTER;
8613
8614 if (ioa_cfg->sdt_state != GET_DUMP)
8615 return IPR_RC_JOB_RETURN;
8616
8617 if (!ioa_cfg->sis64 || !ipr_cmd->u.time_left ||
8618 (readl(ioa_cfg->regs.sense_interrupt_reg) &
8619 IPR_PCII_MAILBOX_STABLE)) {
8620
8621 if (!ipr_cmd->u.time_left)
8622 dev_err(&ioa_cfg->pdev->dev,
8623 "Timed out waiting for Mailbox register.\n");
8624
8625 ioa_cfg->sdt_state = READ_DUMP;
8626 ioa_cfg->dump_timeout = 0;
8627 if (ioa_cfg->sis64)
8628 ipr_reset_start_timer(ipr_cmd, IPR_SIS64_DUMP_TIMEOUT);
8629 else
8630 ipr_reset_start_timer(ipr_cmd, IPR_SIS32_DUMP_TIMEOUT);
8631 ipr_cmd->job_step = ipr_reset_wait_for_dump;
8632 schedule_work(&ioa_cfg->work_q);
8633
8634 } else {
8635 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
8636 ipr_reset_start_timer(ipr_cmd,
8637 IPR_CHECK_FOR_RESET_TIMEOUT);
8638 }
8639
8640 LEAVE;
8641 return IPR_RC_JOB_RETURN;
8642 }
8643
8644
8645
8646
8647
8648
8649
8650
8651
8652
8653
8654
8655 static int ipr_reset_restore_cfg_space(struct ipr_cmnd *ipr_cmd)
8656 {
8657 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8658 u32 int_reg;
8659
8660 ENTER;
8661 ioa_cfg->pdev->state_saved = true;
8662 pci_restore_state(ioa_cfg->pdev);
8663
8664 if (ipr_set_pcix_cmd_reg(ioa_cfg)) {
8665 ipr_cmd->s.ioasa.hdr.ioasc = cpu_to_be32(IPR_IOASC_PCI_ACCESS_ERROR);
8666 return IPR_RC_JOB_CONTINUE;
8667 }
8668
8669 ipr_fail_all_ops(ioa_cfg);
8670
8671 if (ioa_cfg->sis64) {
8672
8673 writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
8674 int_reg = readl(ioa_cfg->regs.endian_swap_reg);
8675 }
8676
8677 if (ioa_cfg->ioa_unit_checked) {
8678 if (ioa_cfg->sis64) {
8679 ipr_cmd->job_step = ipr_reset_get_unit_check_job;
8680 ipr_reset_start_timer(ipr_cmd, IPR_DUMP_DELAY_TIMEOUT);
8681 return IPR_RC_JOB_RETURN;
8682 } else {
8683 ioa_cfg->ioa_unit_checked = 0;
8684 ipr_get_unit_check_buffer(ioa_cfg);
8685 ipr_cmd->job_step = ipr_reset_alert;
8686 ipr_reset_start_timer(ipr_cmd, 0);
8687 return IPR_RC_JOB_RETURN;
8688 }
8689 }
8690
8691 if (ioa_cfg->in_ioa_bringdown) {
8692 ipr_cmd->job_step = ipr_ioa_bringdown_done;
8693 } else if (ioa_cfg->sdt_state == GET_DUMP) {
8694 ipr_cmd->job_step = ipr_dump_mailbox_wait;
8695 ipr_cmd->u.time_left = IPR_WAIT_FOR_MAILBOX;
8696 } else {
8697 ipr_cmd->job_step = ipr_reset_enable_ioa;
8698 }
8699
8700 LEAVE;
8701 return IPR_RC_JOB_CONTINUE;
8702 }
8703
8704
8705
8706
8707
8708
8709
8710
8711
8712
8713 static int ipr_reset_bist_done(struct ipr_cmnd *ipr_cmd)
8714 {
8715 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8716
8717 ENTER;
8718 if (ioa_cfg->cfg_locked)
8719 pci_cfg_access_unlock(ioa_cfg->pdev);
8720 ioa_cfg->cfg_locked = 0;
8721 ipr_cmd->job_step = ipr_reset_restore_cfg_space;
8722 LEAVE;
8723 return IPR_RC_JOB_CONTINUE;
8724 }
8725
8726
8727
8728
8729
8730
8731
8732
8733
8734
8735 static int ipr_reset_start_bist(struct ipr_cmnd *ipr_cmd)
8736 {
8737 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8738 int rc = PCIBIOS_SUCCESSFUL;
8739
8740 ENTER;
8741 if (ioa_cfg->ipr_chip->bist_method == IPR_MMIO)
8742 writel(IPR_UPROCI_SIS64_START_BIST,
8743 ioa_cfg->regs.set_uproc_interrupt_reg32);
8744 else
8745 rc = pci_write_config_byte(ioa_cfg->pdev, PCI_BIST, PCI_BIST_START);
8746
8747 if (rc == PCIBIOS_SUCCESSFUL) {
8748 ipr_cmd->job_step = ipr_reset_bist_done;
8749 ipr_reset_start_timer(ipr_cmd, IPR_WAIT_FOR_BIST_TIMEOUT);
8750 rc = IPR_RC_JOB_RETURN;
8751 } else {
8752 if (ioa_cfg->cfg_locked)
8753 pci_cfg_access_unlock(ipr_cmd->ioa_cfg->pdev);
8754 ioa_cfg->cfg_locked = 0;
8755 ipr_cmd->s.ioasa.hdr.ioasc = cpu_to_be32(IPR_IOASC_PCI_ACCESS_ERROR);
8756 rc = IPR_RC_JOB_CONTINUE;
8757 }
8758
8759 LEAVE;
8760 return rc;
8761 }
8762
8763
8764
8765
8766
8767
8768
8769
8770
8771
8772 static int ipr_reset_slot_reset_done(struct ipr_cmnd *ipr_cmd)
8773 {
8774 ENTER;
8775 ipr_cmd->job_step = ipr_reset_bist_done;
8776 ipr_reset_start_timer(ipr_cmd, IPR_WAIT_FOR_BIST_TIMEOUT);
8777 LEAVE;
8778 return IPR_RC_JOB_RETURN;
8779 }
8780
8781
8782
8783
8784
8785
8786
8787
8788 static void ipr_reset_reset_work(struct work_struct *work)
8789 {
8790 struct ipr_cmnd *ipr_cmd = container_of(work, struct ipr_cmnd, work);
8791 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8792 struct pci_dev *pdev = ioa_cfg->pdev;
8793 unsigned long lock_flags = 0;
8794
8795 ENTER;
8796 pci_set_pcie_reset_state(pdev, pcie_warm_reset);
8797 msleep(jiffies_to_msecs(IPR_PCI_RESET_TIMEOUT));
8798 pci_set_pcie_reset_state(pdev, pcie_deassert_reset);
8799
8800 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
8801 if (ioa_cfg->reset_cmd == ipr_cmd)
8802 ipr_reset_ioa_job(ipr_cmd);
8803 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
8804 LEAVE;
8805 }
8806
8807
8808
8809
8810
8811
8812
8813
8814
8815
8816 static int ipr_reset_slot_reset(struct ipr_cmnd *ipr_cmd)
8817 {
8818 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8819
8820 ENTER;
8821 INIT_WORK(&ipr_cmd->work, ipr_reset_reset_work);
8822 queue_work(ioa_cfg->reset_work_q, &ipr_cmd->work);
8823 ipr_cmd->job_step = ipr_reset_slot_reset_done;
8824 LEAVE;
8825 return IPR_RC_JOB_RETURN;
8826 }
8827
8828
8829
8830
8831
8832
8833
8834
8835
8836
8837 static int ipr_reset_block_config_access_wait(struct ipr_cmnd *ipr_cmd)
8838 {
8839 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8840 int rc = IPR_RC_JOB_CONTINUE;
8841
8842 if (pci_cfg_access_trylock(ioa_cfg->pdev)) {
8843 ioa_cfg->cfg_locked = 1;
8844 ipr_cmd->job_step = ioa_cfg->reset;
8845 } else {
8846 if (ipr_cmd->u.time_left) {
8847 rc = IPR_RC_JOB_RETURN;
8848 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
8849 ipr_reset_start_timer(ipr_cmd,
8850 IPR_CHECK_FOR_RESET_TIMEOUT);
8851 } else {
8852 ipr_cmd->job_step = ioa_cfg->reset;
8853 dev_err(&ioa_cfg->pdev->dev,
8854 "Timed out waiting to lock config access. Resetting anyway.\n");
8855 }
8856 }
8857
8858 return rc;
8859 }
8860
8861
8862
8863
8864
8865
8866
8867
8868
8869
8870 static int ipr_reset_block_config_access(struct ipr_cmnd *ipr_cmd)
8871 {
8872 ipr_cmd->ioa_cfg->cfg_locked = 0;
8873 ipr_cmd->job_step = ipr_reset_block_config_access_wait;
8874 ipr_cmd->u.time_left = IPR_WAIT_FOR_RESET_TIMEOUT;
8875 return IPR_RC_JOB_CONTINUE;
8876 }
8877
8878
8879
8880
8881
8882
8883
8884
8885 static int ipr_reset_allowed(struct ipr_ioa_cfg *ioa_cfg)
8886 {
8887 volatile u32 temp_reg;
8888
8889 temp_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
8890 return ((temp_reg & IPR_PCII_CRITICAL_OPERATION) == 0);
8891 }
8892
8893
8894
8895
8896
8897
8898
8899
8900
8901
8902
8903
8904
8905
8906
8907
8908 static int ipr_reset_wait_to_start_bist(struct ipr_cmnd *ipr_cmd)
8909 {
8910 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8911 int rc = IPR_RC_JOB_RETURN;
8912
8913 if (!ipr_reset_allowed(ioa_cfg) && ipr_cmd->u.time_left) {
8914 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
8915 ipr_reset_start_timer(ipr_cmd, IPR_CHECK_FOR_RESET_TIMEOUT);
8916 } else {
8917 ipr_cmd->job_step = ipr_reset_block_config_access;
8918 rc = IPR_RC_JOB_CONTINUE;
8919 }
8920
8921 return rc;
8922 }
8923
8924
8925
8926
8927
8928
8929
8930
8931
8932
8933
8934
8935
8936 static int ipr_reset_alert(struct ipr_cmnd *ipr_cmd)
8937 {
8938 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8939 u16 cmd_reg;
8940 int rc;
8941
8942 ENTER;
8943 rc = pci_read_config_word(ioa_cfg->pdev, PCI_COMMAND, &cmd_reg);
8944
8945 if ((rc == PCIBIOS_SUCCESSFUL) && (cmd_reg & PCI_COMMAND_MEMORY)) {
8946 ipr_mask_and_clear_interrupts(ioa_cfg, ~0);
8947 writel(IPR_UPROCI_RESET_ALERT, ioa_cfg->regs.set_uproc_interrupt_reg32);
8948 ipr_cmd->job_step = ipr_reset_wait_to_start_bist;
8949 } else {
8950 ipr_cmd->job_step = ipr_reset_block_config_access;
8951 }
8952
8953 ipr_cmd->u.time_left = IPR_WAIT_FOR_RESET_TIMEOUT;
8954 ipr_reset_start_timer(ipr_cmd, IPR_CHECK_FOR_RESET_TIMEOUT);
8955
8956 LEAVE;
8957 return IPR_RC_JOB_RETURN;
8958 }
8959
8960
8961
8962
8963
8964
8965
8966
8967
8968
8969 static int ipr_reset_quiesce_done(struct ipr_cmnd *ipr_cmd)
8970 {
8971 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8972
8973 ENTER;
8974 ipr_cmd->job_step = ipr_ioa_bringdown_done;
8975 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
8976 LEAVE;
8977 return IPR_RC_JOB_CONTINUE;
8978 }
8979
8980
8981
8982
8983
8984
8985
8986
8987
8988
8989
8990 static int ipr_reset_cancel_hcam_done(struct ipr_cmnd *ipr_cmd)
8991 {
8992 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8993 struct ipr_cmnd *loop_cmd;
8994 struct ipr_hrr_queue *hrrq;
8995 int rc = IPR_RC_JOB_CONTINUE;
8996 int count = 0;
8997
8998 ENTER;
8999 ipr_cmd->job_step = ipr_reset_quiesce_done;
9000
9001 for_each_hrrq(hrrq, ioa_cfg) {
9002 spin_lock(&hrrq->_lock);
9003 list_for_each_entry(loop_cmd, &hrrq->hrrq_pending_q, queue) {
9004 count++;
9005 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
9006 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
9007 rc = IPR_RC_JOB_RETURN;
9008 break;
9009 }
9010 spin_unlock(&hrrq->_lock);
9011
9012 if (count)
9013 break;
9014 }
9015
9016 LEAVE;
9017 return rc;
9018 }
9019
9020
9021
9022
9023
9024
9025
9026
9027
9028
9029 static int ipr_reset_cancel_hcam(struct ipr_cmnd *ipr_cmd)
9030 {
9031 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9032 int rc = IPR_RC_JOB_CONTINUE;
9033 struct ipr_cmd_pkt *cmd_pkt;
9034 struct ipr_cmnd *hcam_cmd;
9035 struct ipr_hrr_queue *hrrq = &ioa_cfg->hrrq[IPR_INIT_HRRQ];
9036
9037 ENTER;
9038 ipr_cmd->job_step = ipr_reset_cancel_hcam_done;
9039
9040 if (!hrrq->ioa_is_dead) {
9041 if (!list_empty(&ioa_cfg->hostrcb_pending_q)) {
9042 list_for_each_entry(hcam_cmd, &hrrq->hrrq_pending_q, queue) {
9043 if (hcam_cmd->ioarcb.cmd_pkt.cdb[0] != IPR_HOST_CONTROLLED_ASYNC)
9044 continue;
9045
9046 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
9047 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
9048 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
9049 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
9050 cmd_pkt->cdb[0] = IPR_CANCEL_REQUEST;
9051 cmd_pkt->cdb[1] = IPR_CANCEL_64BIT_IOARCB;
9052 cmd_pkt->cdb[10] = ((u64) hcam_cmd->dma_addr >> 56) & 0xff;
9053 cmd_pkt->cdb[11] = ((u64) hcam_cmd->dma_addr >> 48) & 0xff;
9054 cmd_pkt->cdb[12] = ((u64) hcam_cmd->dma_addr >> 40) & 0xff;
9055 cmd_pkt->cdb[13] = ((u64) hcam_cmd->dma_addr >> 32) & 0xff;
9056 cmd_pkt->cdb[2] = ((u64) hcam_cmd->dma_addr >> 24) & 0xff;
9057 cmd_pkt->cdb[3] = ((u64) hcam_cmd->dma_addr >> 16) & 0xff;
9058 cmd_pkt->cdb[4] = ((u64) hcam_cmd->dma_addr >> 8) & 0xff;
9059 cmd_pkt->cdb[5] = ((u64) hcam_cmd->dma_addr) & 0xff;
9060
9061 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
9062 IPR_CANCEL_TIMEOUT);
9063
9064 rc = IPR_RC_JOB_RETURN;
9065 ipr_cmd->job_step = ipr_reset_cancel_hcam;
9066 break;
9067 }
9068 }
9069 } else
9070 ipr_cmd->job_step = ipr_reset_alert;
9071
9072 LEAVE;
9073 return rc;
9074 }
9075
9076
9077
9078
9079
9080
9081
9082
9083
9084
9085 static int ipr_reset_ucode_download_done(struct ipr_cmnd *ipr_cmd)
9086 {
9087 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9088 struct ipr_sglist *sglist = ioa_cfg->ucode_sglist;
9089
9090 dma_unmap_sg(&ioa_cfg->pdev->dev, sglist->scatterlist,
9091 sglist->num_sg, DMA_TO_DEVICE);
9092
9093 ipr_cmd->job_step = ipr_reset_alert;
9094 return IPR_RC_JOB_CONTINUE;
9095 }
9096
9097
9098
9099
9100
9101
9102
9103
9104
9105
9106
9107 static int ipr_reset_ucode_download(struct ipr_cmnd *ipr_cmd)
9108 {
9109 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9110 struct ipr_sglist *sglist = ioa_cfg->ucode_sglist;
9111
9112 ENTER;
9113 ipr_cmd->job_step = ipr_reset_alert;
9114
9115 if (!sglist)
9116 return IPR_RC_JOB_CONTINUE;
9117
9118 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
9119 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
9120 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = WRITE_BUFFER;
9121 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_WR_BUF_DOWNLOAD_AND_SAVE;
9122 ipr_cmd->ioarcb.cmd_pkt.cdb[6] = (sglist->buffer_len & 0xff0000) >> 16;
9123 ipr_cmd->ioarcb.cmd_pkt.cdb[7] = (sglist->buffer_len & 0x00ff00) >> 8;
9124 ipr_cmd->ioarcb.cmd_pkt.cdb[8] = sglist->buffer_len & 0x0000ff;
9125
9126 if (ioa_cfg->sis64)
9127 ipr_build_ucode_ioadl64(ipr_cmd, sglist);
9128 else
9129 ipr_build_ucode_ioadl(ipr_cmd, sglist);
9130 ipr_cmd->job_step = ipr_reset_ucode_download_done;
9131
9132 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
9133 IPR_WRITE_BUFFER_TIMEOUT);
9134
9135 LEAVE;
9136 return IPR_RC_JOB_RETURN;
9137 }
9138
9139
9140
9141
9142
9143
9144
9145
9146
9147
9148
9149
9150 static int ipr_reset_shutdown_ioa(struct ipr_cmnd *ipr_cmd)
9151 {
9152 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9153 enum ipr_shutdown_type shutdown_type = ipr_cmd->u.shutdown_type;
9154 unsigned long timeout;
9155 int rc = IPR_RC_JOB_CONTINUE;
9156
9157 ENTER;
9158 if (shutdown_type == IPR_SHUTDOWN_QUIESCE)
9159 ipr_cmd->job_step = ipr_reset_cancel_hcam;
9160 else if (shutdown_type != IPR_SHUTDOWN_NONE &&
9161 !ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
9162 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
9163 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
9164 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN;
9165 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = shutdown_type;
9166
9167 if (shutdown_type == IPR_SHUTDOWN_NORMAL)
9168 timeout = IPR_SHUTDOWN_TIMEOUT;
9169 else if (shutdown_type == IPR_SHUTDOWN_PREPARE_FOR_NORMAL)
9170 timeout = IPR_INTERNAL_TIMEOUT;
9171 else if (ioa_cfg->dual_raid && ipr_dual_ioa_raid)
9172 timeout = IPR_DUAL_IOA_ABBR_SHUTDOWN_TO;
9173 else
9174 timeout = IPR_ABBREV_SHUTDOWN_TIMEOUT;
9175
9176 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, timeout);
9177
9178 rc = IPR_RC_JOB_RETURN;
9179 ipr_cmd->job_step = ipr_reset_ucode_download;
9180 } else
9181 ipr_cmd->job_step = ipr_reset_alert;
9182
9183 LEAVE;
9184 return rc;
9185 }
9186
9187
9188
9189
9190
9191
9192
9193
9194
9195
9196 static void ipr_reset_ioa_job(struct ipr_cmnd *ipr_cmd)
9197 {
9198 u32 rc, ioasc;
9199 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9200
9201 do {
9202 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
9203
9204 if (ioa_cfg->reset_cmd != ipr_cmd) {
9205
9206
9207
9208
9209 list_add_tail(&ipr_cmd->queue,
9210 &ipr_cmd->hrrq->hrrq_free_q);
9211 return;
9212 }
9213
9214 if (IPR_IOASC_SENSE_KEY(ioasc)) {
9215 rc = ipr_cmd->job_step_failed(ipr_cmd);
9216 if (rc == IPR_RC_JOB_RETURN)
9217 return;
9218 }
9219
9220 ipr_reinit_ipr_cmnd(ipr_cmd);
9221 ipr_cmd->job_step_failed = ipr_reset_cmd_failed;
9222 rc = ipr_cmd->job_step(ipr_cmd);
9223 } while (rc == IPR_RC_JOB_CONTINUE);
9224 }
9225
9226
9227
9228
9229
9230
9231
9232
9233
9234
9235
9236
9237
9238
9239
9240 static void _ipr_initiate_ioa_reset(struct ipr_ioa_cfg *ioa_cfg,
9241 int (*job_step) (struct ipr_cmnd *),
9242 enum ipr_shutdown_type shutdown_type)
9243 {
9244 struct ipr_cmnd *ipr_cmd;
9245 int i;
9246
9247 ioa_cfg->in_reset_reload = 1;
9248 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9249 spin_lock(&ioa_cfg->hrrq[i]._lock);
9250 ioa_cfg->hrrq[i].allow_cmds = 0;
9251 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9252 }
9253 wmb();
9254 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa) {
9255 ioa_cfg->scsi_unblock = 0;
9256 ioa_cfg->scsi_blocked = 1;
9257 scsi_block_requests(ioa_cfg->host);
9258 }
9259
9260 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
9261 ioa_cfg->reset_cmd = ipr_cmd;
9262 ipr_cmd->job_step = job_step;
9263 ipr_cmd->u.shutdown_type = shutdown_type;
9264
9265 ipr_reset_ioa_job(ipr_cmd);
9266 }
9267
9268
9269
9270
9271
9272
9273
9274
9275
9276
9277
9278
9279
9280 static void ipr_initiate_ioa_reset(struct ipr_ioa_cfg *ioa_cfg,
9281 enum ipr_shutdown_type shutdown_type)
9282 {
9283 int i;
9284
9285 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
9286 return;
9287
9288 if (ioa_cfg->in_reset_reload) {
9289 if (ioa_cfg->sdt_state == GET_DUMP)
9290 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
9291 else if (ioa_cfg->sdt_state == READ_DUMP)
9292 ioa_cfg->sdt_state = ABORT_DUMP;
9293 }
9294
9295 if (ioa_cfg->reset_retries++ >= IPR_NUM_RESET_RELOAD_RETRIES) {
9296 dev_err(&ioa_cfg->pdev->dev,
9297 "IOA taken offline - error recovery failed\n");
9298
9299 ioa_cfg->reset_retries = 0;
9300 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9301 spin_lock(&ioa_cfg->hrrq[i]._lock);
9302 ioa_cfg->hrrq[i].ioa_is_dead = 1;
9303 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9304 }
9305 wmb();
9306
9307 if (ioa_cfg->in_ioa_bringdown) {
9308 ioa_cfg->reset_cmd = NULL;
9309 ioa_cfg->in_reset_reload = 0;
9310 ipr_fail_all_ops(ioa_cfg);
9311 wake_up_all(&ioa_cfg->reset_wait_q);
9312
9313 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa) {
9314 ioa_cfg->scsi_unblock = 1;
9315 schedule_work(&ioa_cfg->work_q);
9316 }
9317 return;
9318 } else {
9319 ioa_cfg->in_ioa_bringdown = 1;
9320 shutdown_type = IPR_SHUTDOWN_NONE;
9321 }
9322 }
9323
9324 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_shutdown_ioa,
9325 shutdown_type);
9326 }
9327
9328
9329
9330
9331
9332
9333
9334
9335
9336 static int ipr_reset_freeze(struct ipr_cmnd *ipr_cmd)
9337 {
9338 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9339 int i;
9340
9341
9342 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9343 spin_lock(&ioa_cfg->hrrq[i]._lock);
9344 ioa_cfg->hrrq[i].allow_interrupts = 0;
9345 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9346 }
9347 wmb();
9348 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
9349 ipr_cmd->done = ipr_reset_ioa_job;
9350 return IPR_RC_JOB_RETURN;
9351 }
9352
9353
9354
9355
9356
9357
9358
9359
9360 static pci_ers_result_t ipr_pci_mmio_enabled(struct pci_dev *pdev)
9361 {
9362 unsigned long flags = 0;
9363 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9364
9365 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
9366 if (!ioa_cfg->probe_done)
9367 pci_save_state(pdev);
9368 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9369 return PCI_ERS_RESULT_NEED_RESET;
9370 }
9371
9372
9373
9374
9375
9376
9377
9378
9379
9380 static void ipr_pci_frozen(struct pci_dev *pdev)
9381 {
9382 unsigned long flags = 0;
9383 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9384
9385 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
9386 if (ioa_cfg->probe_done)
9387 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_freeze, IPR_SHUTDOWN_NONE);
9388 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9389 }
9390
9391
9392
9393
9394
9395
9396
9397
9398
9399 static pci_ers_result_t ipr_pci_slot_reset(struct pci_dev *pdev)
9400 {
9401 unsigned long flags = 0;
9402 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9403
9404 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
9405 if (ioa_cfg->probe_done) {
9406 if (ioa_cfg->needs_warm_reset)
9407 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
9408 else
9409 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_restore_cfg_space,
9410 IPR_SHUTDOWN_NONE);
9411 } else
9412 wake_up_all(&ioa_cfg->eeh_wait_q);
9413 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9414 return PCI_ERS_RESULT_RECOVERED;
9415 }
9416
9417
9418
9419
9420
9421
9422
9423
9424 static void ipr_pci_perm_failure(struct pci_dev *pdev)
9425 {
9426 unsigned long flags = 0;
9427 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9428 int i;
9429
9430 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
9431 if (ioa_cfg->probe_done) {
9432 if (ioa_cfg->sdt_state == WAIT_FOR_DUMP)
9433 ioa_cfg->sdt_state = ABORT_DUMP;
9434 ioa_cfg->reset_retries = IPR_NUM_RESET_RELOAD_RETRIES - 1;
9435 ioa_cfg->in_ioa_bringdown = 1;
9436 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9437 spin_lock(&ioa_cfg->hrrq[i]._lock);
9438 ioa_cfg->hrrq[i].allow_cmds = 0;
9439 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9440 }
9441 wmb();
9442 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
9443 } else
9444 wake_up_all(&ioa_cfg->eeh_wait_q);
9445 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9446 }
9447
9448
9449
9450
9451
9452
9453
9454
9455
9456
9457
9458 static pci_ers_result_t ipr_pci_error_detected(struct pci_dev *pdev,
9459 pci_channel_state_t state)
9460 {
9461 switch (state) {
9462 case pci_channel_io_frozen:
9463 ipr_pci_frozen(pdev);
9464 return PCI_ERS_RESULT_CAN_RECOVER;
9465 case pci_channel_io_perm_failure:
9466 ipr_pci_perm_failure(pdev);
9467 return PCI_ERS_RESULT_DISCONNECT;
9468 break;
9469 default:
9470 break;
9471 }
9472 return PCI_ERS_RESULT_NEED_RESET;
9473 }
9474
9475
9476
9477
9478
9479
9480
9481
9482
9483
9484
9485
9486 static int ipr_probe_ioa_part2(struct ipr_ioa_cfg *ioa_cfg)
9487 {
9488 int rc = 0;
9489 unsigned long host_lock_flags = 0;
9490
9491 ENTER;
9492 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
9493 dev_dbg(&ioa_cfg->pdev->dev, "ioa_cfg adx: 0x%p\n", ioa_cfg);
9494 ioa_cfg->probe_done = 1;
9495 if (ioa_cfg->needs_hard_reset) {
9496 ioa_cfg->needs_hard_reset = 0;
9497 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
9498 } else
9499 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_enable_ioa,
9500 IPR_SHUTDOWN_NONE);
9501 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
9502
9503 LEAVE;
9504 return rc;
9505 }
9506
9507
9508
9509
9510
9511
9512
9513
9514 static void ipr_free_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
9515 {
9516 int i;
9517
9518 if (ioa_cfg->ipr_cmnd_list) {
9519 for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
9520 if (ioa_cfg->ipr_cmnd_list[i])
9521 dma_pool_free(ioa_cfg->ipr_cmd_pool,
9522 ioa_cfg->ipr_cmnd_list[i],
9523 ioa_cfg->ipr_cmnd_list_dma[i]);
9524
9525 ioa_cfg->ipr_cmnd_list[i] = NULL;
9526 }
9527 }
9528
9529 if (ioa_cfg->ipr_cmd_pool)
9530 dma_pool_destroy(ioa_cfg->ipr_cmd_pool);
9531
9532 kfree(ioa_cfg->ipr_cmnd_list);
9533 kfree(ioa_cfg->ipr_cmnd_list_dma);
9534 ioa_cfg->ipr_cmnd_list = NULL;
9535 ioa_cfg->ipr_cmnd_list_dma = NULL;
9536 ioa_cfg->ipr_cmd_pool = NULL;
9537 }
9538
9539
9540
9541
9542
9543
9544
9545
9546 static void ipr_free_mem(struct ipr_ioa_cfg *ioa_cfg)
9547 {
9548 int i;
9549
9550 kfree(ioa_cfg->res_entries);
9551 dma_free_coherent(&ioa_cfg->pdev->dev, sizeof(struct ipr_misc_cbs),
9552 ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
9553 ipr_free_cmd_blks(ioa_cfg);
9554
9555 for (i = 0; i < ioa_cfg->hrrq_num; i++)
9556 dma_free_coherent(&ioa_cfg->pdev->dev,
9557 sizeof(u32) * ioa_cfg->hrrq[i].size,
9558 ioa_cfg->hrrq[i].host_rrq,
9559 ioa_cfg->hrrq[i].host_rrq_dma);
9560
9561 dma_free_coherent(&ioa_cfg->pdev->dev, ioa_cfg->cfg_table_size,
9562 ioa_cfg->u.cfg_table, ioa_cfg->cfg_table_dma);
9563
9564 for (i = 0; i < IPR_MAX_HCAMS; i++) {
9565 dma_free_coherent(&ioa_cfg->pdev->dev,
9566 sizeof(struct ipr_hostrcb),
9567 ioa_cfg->hostrcb[i],
9568 ioa_cfg->hostrcb_dma[i]);
9569 }
9570
9571 ipr_free_dump(ioa_cfg);
9572 kfree(ioa_cfg->trace);
9573 }
9574
9575
9576
9577
9578
9579
9580
9581
9582
9583
9584
9585 static void ipr_free_irqs(struct ipr_ioa_cfg *ioa_cfg)
9586 {
9587 struct pci_dev *pdev = ioa_cfg->pdev;
9588 int i;
9589
9590 for (i = 0; i < ioa_cfg->nvectors; i++)
9591 free_irq(pci_irq_vector(pdev, i), &ioa_cfg->hrrq[i]);
9592 pci_free_irq_vectors(pdev);
9593 }
9594
9595
9596
9597
9598
9599
9600
9601
9602
9603
9604
9605 static void ipr_free_all_resources(struct ipr_ioa_cfg *ioa_cfg)
9606 {
9607 struct pci_dev *pdev = ioa_cfg->pdev;
9608
9609 ENTER;
9610 ipr_free_irqs(ioa_cfg);
9611 if (ioa_cfg->reset_work_q)
9612 destroy_workqueue(ioa_cfg->reset_work_q);
9613 iounmap(ioa_cfg->hdw_dma_regs);
9614 pci_release_regions(pdev);
9615 ipr_free_mem(ioa_cfg);
9616 scsi_host_put(ioa_cfg->host);
9617 pci_disable_device(pdev);
9618 LEAVE;
9619 }
9620
9621
9622
9623
9624
9625
9626
9627
9628 static int ipr_alloc_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
9629 {
9630 struct ipr_cmnd *ipr_cmd;
9631 struct ipr_ioarcb *ioarcb;
9632 dma_addr_t dma_addr;
9633 int i, entries_each_hrrq, hrrq_id = 0;
9634
9635 ioa_cfg->ipr_cmd_pool = dma_pool_create(IPR_NAME, &ioa_cfg->pdev->dev,
9636 sizeof(struct ipr_cmnd), 512, 0);
9637
9638 if (!ioa_cfg->ipr_cmd_pool)
9639 return -ENOMEM;
9640
9641 ioa_cfg->ipr_cmnd_list = kcalloc(IPR_NUM_CMD_BLKS, sizeof(struct ipr_cmnd *), GFP_KERNEL);
9642 ioa_cfg->ipr_cmnd_list_dma = kcalloc(IPR_NUM_CMD_BLKS, sizeof(dma_addr_t), GFP_KERNEL);
9643
9644 if (!ioa_cfg->ipr_cmnd_list || !ioa_cfg->ipr_cmnd_list_dma) {
9645 ipr_free_cmd_blks(ioa_cfg);
9646 return -ENOMEM;
9647 }
9648
9649 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9650 if (ioa_cfg->hrrq_num > 1) {
9651 if (i == 0) {
9652 entries_each_hrrq = IPR_NUM_INTERNAL_CMD_BLKS;
9653 ioa_cfg->hrrq[i].min_cmd_id = 0;
9654 ioa_cfg->hrrq[i].max_cmd_id =
9655 (entries_each_hrrq - 1);
9656 } else {
9657 entries_each_hrrq =
9658 IPR_NUM_BASE_CMD_BLKS/
9659 (ioa_cfg->hrrq_num - 1);
9660 ioa_cfg->hrrq[i].min_cmd_id =
9661 IPR_NUM_INTERNAL_CMD_BLKS +
9662 (i - 1) * entries_each_hrrq;
9663 ioa_cfg->hrrq[i].max_cmd_id =
9664 (IPR_NUM_INTERNAL_CMD_BLKS +
9665 i * entries_each_hrrq - 1);
9666 }
9667 } else {
9668 entries_each_hrrq = IPR_NUM_CMD_BLKS;
9669 ioa_cfg->hrrq[i].min_cmd_id = 0;
9670 ioa_cfg->hrrq[i].max_cmd_id = (entries_each_hrrq - 1);
9671 }
9672 ioa_cfg->hrrq[i].size = entries_each_hrrq;
9673 }
9674
9675 BUG_ON(ioa_cfg->hrrq_num == 0);
9676
9677 i = IPR_NUM_CMD_BLKS -
9678 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].max_cmd_id - 1;
9679 if (i > 0) {
9680 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].size += i;
9681 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].max_cmd_id += i;
9682 }
9683
9684 for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
9685 ipr_cmd = dma_pool_zalloc(ioa_cfg->ipr_cmd_pool,
9686 GFP_KERNEL, &dma_addr);
9687
9688 if (!ipr_cmd) {
9689 ipr_free_cmd_blks(ioa_cfg);
9690 return -ENOMEM;
9691 }
9692
9693 ioa_cfg->ipr_cmnd_list[i] = ipr_cmd;
9694 ioa_cfg->ipr_cmnd_list_dma[i] = dma_addr;
9695
9696 ioarcb = &ipr_cmd->ioarcb;
9697 ipr_cmd->dma_addr = dma_addr;
9698 if (ioa_cfg->sis64)
9699 ioarcb->a.ioarcb_host_pci_addr64 = cpu_to_be64(dma_addr);
9700 else
9701 ioarcb->a.ioarcb_host_pci_addr = cpu_to_be32(dma_addr);
9702
9703 ioarcb->host_response_handle = cpu_to_be32(i << 2);
9704 if (ioa_cfg->sis64) {
9705 ioarcb->u.sis64_addr_data.data_ioadl_addr =
9706 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
9707 ioarcb->u.sis64_addr_data.ioasa_host_pci_addr =
9708 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, s.ioasa64));
9709 } else {
9710 ioarcb->write_ioadl_addr =
9711 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
9712 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
9713 ioarcb->ioasa_host_pci_addr =
9714 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, s.ioasa));
9715 }
9716 ioarcb->ioasa_len = cpu_to_be16(sizeof(struct ipr_ioasa));
9717 ipr_cmd->cmd_index = i;
9718 ipr_cmd->ioa_cfg = ioa_cfg;
9719 ipr_cmd->sense_buffer_dma = dma_addr +
9720 offsetof(struct ipr_cmnd, sense_buffer);
9721
9722 ipr_cmd->ioarcb.cmd_pkt.hrrq_id = hrrq_id;
9723 ipr_cmd->hrrq = &ioa_cfg->hrrq[hrrq_id];
9724 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
9725 if (i >= ioa_cfg->hrrq[hrrq_id].max_cmd_id)
9726 hrrq_id++;
9727 }
9728
9729 return 0;
9730 }
9731
9732
9733
9734
9735
9736
9737
9738
9739 static int ipr_alloc_mem(struct ipr_ioa_cfg *ioa_cfg)
9740 {
9741 struct pci_dev *pdev = ioa_cfg->pdev;
9742 int i, rc = -ENOMEM;
9743
9744 ENTER;
9745 ioa_cfg->res_entries = kcalloc(ioa_cfg->max_devs_supported,
9746 sizeof(struct ipr_resource_entry),
9747 GFP_KERNEL);
9748
9749 if (!ioa_cfg->res_entries)
9750 goto out;
9751
9752 for (i = 0; i < ioa_cfg->max_devs_supported; i++) {
9753 list_add_tail(&ioa_cfg->res_entries[i].queue, &ioa_cfg->free_res_q);
9754 ioa_cfg->res_entries[i].ioa_cfg = ioa_cfg;
9755 }
9756
9757 ioa_cfg->vpd_cbs = dma_alloc_coherent(&pdev->dev,
9758 sizeof(struct ipr_misc_cbs),
9759 &ioa_cfg->vpd_cbs_dma,
9760 GFP_KERNEL);
9761
9762 if (!ioa_cfg->vpd_cbs)
9763 goto out_free_res_entries;
9764
9765 if (ipr_alloc_cmd_blks(ioa_cfg))
9766 goto out_free_vpd_cbs;
9767
9768 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9769 ioa_cfg->hrrq[i].host_rrq = dma_alloc_coherent(&pdev->dev,
9770 sizeof(u32) * ioa_cfg->hrrq[i].size,
9771 &ioa_cfg->hrrq[i].host_rrq_dma,
9772 GFP_KERNEL);
9773
9774 if (!ioa_cfg->hrrq[i].host_rrq) {
9775 while (--i > 0)
9776 dma_free_coherent(&pdev->dev,
9777 sizeof(u32) * ioa_cfg->hrrq[i].size,
9778 ioa_cfg->hrrq[i].host_rrq,
9779 ioa_cfg->hrrq[i].host_rrq_dma);
9780 goto out_ipr_free_cmd_blocks;
9781 }
9782 ioa_cfg->hrrq[i].ioa_cfg = ioa_cfg;
9783 }
9784
9785 ioa_cfg->u.cfg_table = dma_alloc_coherent(&pdev->dev,
9786 ioa_cfg->cfg_table_size,
9787 &ioa_cfg->cfg_table_dma,
9788 GFP_KERNEL);
9789
9790 if (!ioa_cfg->u.cfg_table)
9791 goto out_free_host_rrq;
9792
9793 for (i = 0; i < IPR_MAX_HCAMS; i++) {
9794 ioa_cfg->hostrcb[i] = dma_alloc_coherent(&pdev->dev,
9795 sizeof(struct ipr_hostrcb),
9796 &ioa_cfg->hostrcb_dma[i],
9797 GFP_KERNEL);
9798
9799 if (!ioa_cfg->hostrcb[i])
9800 goto out_free_hostrcb_dma;
9801
9802 ioa_cfg->hostrcb[i]->hostrcb_dma =
9803 ioa_cfg->hostrcb_dma[i] + offsetof(struct ipr_hostrcb, hcam);
9804 ioa_cfg->hostrcb[i]->ioa_cfg = ioa_cfg;
9805 list_add_tail(&ioa_cfg->hostrcb[i]->queue, &ioa_cfg->hostrcb_free_q);
9806 }
9807
9808 ioa_cfg->trace = kcalloc(IPR_NUM_TRACE_ENTRIES,
9809 sizeof(struct ipr_trace_entry),
9810 GFP_KERNEL);
9811
9812 if (!ioa_cfg->trace)
9813 goto out_free_hostrcb_dma;
9814
9815 rc = 0;
9816 out:
9817 LEAVE;
9818 return rc;
9819
9820 out_free_hostrcb_dma:
9821 while (i-- > 0) {
9822 dma_free_coherent(&pdev->dev, sizeof(struct ipr_hostrcb),
9823 ioa_cfg->hostrcb[i],
9824 ioa_cfg->hostrcb_dma[i]);
9825 }
9826 dma_free_coherent(&pdev->dev, ioa_cfg->cfg_table_size,
9827 ioa_cfg->u.cfg_table, ioa_cfg->cfg_table_dma);
9828 out_free_host_rrq:
9829 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9830 dma_free_coherent(&pdev->dev,
9831 sizeof(u32) * ioa_cfg->hrrq[i].size,
9832 ioa_cfg->hrrq[i].host_rrq,
9833 ioa_cfg->hrrq[i].host_rrq_dma);
9834 }
9835 out_ipr_free_cmd_blocks:
9836 ipr_free_cmd_blks(ioa_cfg);
9837 out_free_vpd_cbs:
9838 dma_free_coherent(&pdev->dev, sizeof(struct ipr_misc_cbs),
9839 ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
9840 out_free_res_entries:
9841 kfree(ioa_cfg->res_entries);
9842 goto out;
9843 }
9844
9845
9846
9847
9848
9849
9850
9851
9852 static void ipr_initialize_bus_attr(struct ipr_ioa_cfg *ioa_cfg)
9853 {
9854 int i;
9855
9856 for (i = 0; i < IPR_MAX_NUM_BUSES; i++) {
9857 ioa_cfg->bus_attr[i].bus = i;
9858 ioa_cfg->bus_attr[i].qas_enabled = 0;
9859 ioa_cfg->bus_attr[i].bus_width = IPR_DEFAULT_BUS_WIDTH;
9860 if (ipr_max_speed < ARRAY_SIZE(ipr_max_bus_speeds))
9861 ioa_cfg->bus_attr[i].max_xfer_rate = ipr_max_bus_speeds[ipr_max_speed];
9862 else
9863 ioa_cfg->bus_attr[i].max_xfer_rate = IPR_U160_SCSI_RATE;
9864 }
9865 }
9866
9867
9868
9869
9870
9871
9872
9873
9874 static void ipr_init_regs(struct ipr_ioa_cfg *ioa_cfg)
9875 {
9876 const struct ipr_interrupt_offsets *p;
9877 struct ipr_interrupts *t;
9878 void __iomem *base;
9879
9880 p = &ioa_cfg->chip_cfg->regs;
9881 t = &ioa_cfg->regs;
9882 base = ioa_cfg->hdw_dma_regs;
9883
9884 t->set_interrupt_mask_reg = base + p->set_interrupt_mask_reg;
9885 t->clr_interrupt_mask_reg = base + p->clr_interrupt_mask_reg;
9886 t->clr_interrupt_mask_reg32 = base + p->clr_interrupt_mask_reg32;
9887 t->sense_interrupt_mask_reg = base + p->sense_interrupt_mask_reg;
9888 t->sense_interrupt_mask_reg32 = base + p->sense_interrupt_mask_reg32;
9889 t->clr_interrupt_reg = base + p->clr_interrupt_reg;
9890 t->clr_interrupt_reg32 = base + p->clr_interrupt_reg32;
9891 t->sense_interrupt_reg = base + p->sense_interrupt_reg;
9892 t->sense_interrupt_reg32 = base + p->sense_interrupt_reg32;
9893 t->ioarrin_reg = base + p->ioarrin_reg;
9894 t->sense_uproc_interrupt_reg = base + p->sense_uproc_interrupt_reg;
9895 t->sense_uproc_interrupt_reg32 = base + p->sense_uproc_interrupt_reg32;
9896 t->set_uproc_interrupt_reg = base + p->set_uproc_interrupt_reg;
9897 t->set_uproc_interrupt_reg32 = base + p->set_uproc_interrupt_reg32;
9898 t->clr_uproc_interrupt_reg = base + p->clr_uproc_interrupt_reg;
9899 t->clr_uproc_interrupt_reg32 = base + p->clr_uproc_interrupt_reg32;
9900
9901 if (ioa_cfg->sis64) {
9902 t->init_feedback_reg = base + p->init_feedback_reg;
9903 t->dump_addr_reg = base + p->dump_addr_reg;
9904 t->dump_data_reg = base + p->dump_data_reg;
9905 t->endian_swap_reg = base + p->endian_swap_reg;
9906 }
9907 }
9908
9909
9910
9911
9912
9913
9914
9915
9916
9917
9918 static void ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg,
9919 struct Scsi_Host *host, struct pci_dev *pdev)
9920 {
9921 int i;
9922
9923 ioa_cfg->host = host;
9924 ioa_cfg->pdev = pdev;
9925 ioa_cfg->log_level = ipr_log_level;
9926 ioa_cfg->doorbell = IPR_DOORBELL;
9927 sprintf(ioa_cfg->eye_catcher, IPR_EYECATCHER);
9928 sprintf(ioa_cfg->trace_start, IPR_TRACE_START_LABEL);
9929 sprintf(ioa_cfg->cfg_table_start, IPR_CFG_TBL_START);
9930 sprintf(ioa_cfg->resource_table_label, IPR_RES_TABLE_LABEL);
9931 sprintf(ioa_cfg->ipr_hcam_label, IPR_HCAM_LABEL);
9932 sprintf(ioa_cfg->ipr_cmd_label, IPR_CMD_LABEL);
9933
9934 INIT_LIST_HEAD(&ioa_cfg->hostrcb_free_q);
9935 INIT_LIST_HEAD(&ioa_cfg->hostrcb_pending_q);
9936 INIT_LIST_HEAD(&ioa_cfg->hostrcb_report_q);
9937 INIT_LIST_HEAD(&ioa_cfg->free_res_q);
9938 INIT_LIST_HEAD(&ioa_cfg->used_res_q);
9939 INIT_WORK(&ioa_cfg->work_q, ipr_worker_thread);
9940 INIT_WORK(&ioa_cfg->scsi_add_work_q, ipr_add_remove_thread);
9941 init_waitqueue_head(&ioa_cfg->reset_wait_q);
9942 init_waitqueue_head(&ioa_cfg->msi_wait_q);
9943 init_waitqueue_head(&ioa_cfg->eeh_wait_q);
9944 ioa_cfg->sdt_state = INACTIVE;
9945
9946 ipr_initialize_bus_attr(ioa_cfg);
9947 ioa_cfg->max_devs_supported = ipr_max_devs;
9948
9949 if (ioa_cfg->sis64) {
9950 host->max_channel = IPR_MAX_SIS64_BUSES;
9951 host->max_id = IPR_MAX_SIS64_TARGETS_PER_BUS;
9952 host->max_lun = IPR_MAX_SIS64_LUNS_PER_TARGET;
9953 if (ipr_max_devs > IPR_MAX_SIS64_DEVS)
9954 ioa_cfg->max_devs_supported = IPR_MAX_SIS64_DEVS;
9955 ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr64)
9956 + ((sizeof(struct ipr_config_table_entry64)
9957 * ioa_cfg->max_devs_supported)));
9958 } else {
9959 host->max_channel = IPR_VSET_BUS;
9960 host->max_id = IPR_MAX_NUM_TARGETS_PER_BUS;
9961 host->max_lun = IPR_MAX_NUM_LUNS_PER_TARGET;
9962 if (ipr_max_devs > IPR_MAX_PHYSICAL_DEVS)
9963 ioa_cfg->max_devs_supported = IPR_MAX_PHYSICAL_DEVS;
9964 ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr)
9965 + ((sizeof(struct ipr_config_table_entry)
9966 * ioa_cfg->max_devs_supported)));
9967 }
9968
9969 host->unique_id = host->host_no;
9970 host->max_cmd_len = IPR_MAX_CDB_LEN;
9971 host->can_queue = ioa_cfg->max_cmds;
9972 pci_set_drvdata(pdev, ioa_cfg);
9973
9974 for (i = 0; i < ARRAY_SIZE(ioa_cfg->hrrq); i++) {
9975 INIT_LIST_HEAD(&ioa_cfg->hrrq[i].hrrq_free_q);
9976 INIT_LIST_HEAD(&ioa_cfg->hrrq[i].hrrq_pending_q);
9977 spin_lock_init(&ioa_cfg->hrrq[i]._lock);
9978 if (i == 0)
9979 ioa_cfg->hrrq[i].lock = ioa_cfg->host->host_lock;
9980 else
9981 ioa_cfg->hrrq[i].lock = &ioa_cfg->hrrq[i]._lock;
9982 }
9983 }
9984
9985
9986
9987
9988
9989
9990
9991
9992 static const struct ipr_chip_t *
9993 ipr_get_chip_info(const struct pci_device_id *dev_id)
9994 {
9995 int i;
9996
9997 for (i = 0; i < ARRAY_SIZE(ipr_chip); i++)
9998 if (ipr_chip[i].vendor == dev_id->vendor &&
9999 ipr_chip[i].device == dev_id->device)
10000 return &ipr_chip[i];
10001 return NULL;
10002 }
10003
10004
10005
10006
10007
10008
10009
10010
10011
10012 static void ipr_wait_for_pci_err_recovery(struct ipr_ioa_cfg *ioa_cfg)
10013 {
10014 struct pci_dev *pdev = ioa_cfg->pdev;
10015
10016 if (pci_channel_offline(pdev)) {
10017 wait_event_timeout(ioa_cfg->eeh_wait_q,
10018 !pci_channel_offline(pdev),
10019 IPR_PCI_ERROR_RECOVERY_TIMEOUT);
10020 pci_restore_state(pdev);
10021 }
10022 }
10023
10024 static void name_msi_vectors(struct ipr_ioa_cfg *ioa_cfg)
10025 {
10026 int vec_idx, n = sizeof(ioa_cfg->vectors_info[0].desc) - 1;
10027
10028 for (vec_idx = 0; vec_idx < ioa_cfg->nvectors; vec_idx++) {
10029 snprintf(ioa_cfg->vectors_info[vec_idx].desc, n,
10030 "host%d-%d", ioa_cfg->host->host_no, vec_idx);
10031 ioa_cfg->vectors_info[vec_idx].
10032 desc[strlen(ioa_cfg->vectors_info[vec_idx].desc)] = 0;
10033 }
10034 }
10035
10036 static int ipr_request_other_msi_irqs(struct ipr_ioa_cfg *ioa_cfg,
10037 struct pci_dev *pdev)
10038 {
10039 int i, rc;
10040
10041 for (i = 1; i < ioa_cfg->nvectors; i++) {
10042 rc = request_irq(pci_irq_vector(pdev, i),
10043 ipr_isr_mhrrq,
10044 0,
10045 ioa_cfg->vectors_info[i].desc,
10046 &ioa_cfg->hrrq[i]);
10047 if (rc) {
10048 while (--i >= 0)
10049 free_irq(pci_irq_vector(pdev, i),
10050 &ioa_cfg->hrrq[i]);
10051 return rc;
10052 }
10053 }
10054 return 0;
10055 }
10056
10057
10058
10059
10060
10061
10062
10063
10064
10065
10066
10067 static irqreturn_t ipr_test_intr(int irq, void *devp)
10068 {
10069 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)devp;
10070 unsigned long lock_flags = 0;
10071 irqreturn_t rc = IRQ_HANDLED;
10072
10073 dev_info(&ioa_cfg->pdev->dev, "Received IRQ : %d\n", irq);
10074 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10075
10076 ioa_cfg->msi_received = 1;
10077 wake_up(&ioa_cfg->msi_wait_q);
10078
10079 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10080 return rc;
10081 }
10082
10083
10084
10085
10086
10087
10088
10089
10090
10091
10092
10093
10094 static int ipr_test_msi(struct ipr_ioa_cfg *ioa_cfg, struct pci_dev *pdev)
10095 {
10096 int rc;
10097 volatile u32 int_reg;
10098 unsigned long lock_flags = 0;
10099 int irq = pci_irq_vector(pdev, 0);
10100
10101 ENTER;
10102
10103 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10104 init_waitqueue_head(&ioa_cfg->msi_wait_q);
10105 ioa_cfg->msi_received = 0;
10106 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
10107 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.clr_interrupt_mask_reg32);
10108 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
10109 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10110
10111 rc = request_irq(irq, ipr_test_intr, 0, IPR_NAME, ioa_cfg);
10112 if (rc) {
10113 dev_err(&pdev->dev, "Can not assign irq %d\n", irq);
10114 return rc;
10115 } else if (ipr_debug)
10116 dev_info(&pdev->dev, "IRQ assigned: %d\n", irq);
10117
10118 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.sense_interrupt_reg32);
10119 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
10120 wait_event_timeout(ioa_cfg->msi_wait_q, ioa_cfg->msi_received, HZ);
10121 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10122 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
10123
10124 if (!ioa_cfg->msi_received) {
10125
10126 dev_info(&pdev->dev, "MSI test failed. Falling back to LSI.\n");
10127 rc = -EOPNOTSUPP;
10128 } else if (ipr_debug)
10129 dev_info(&pdev->dev, "MSI test succeeded.\n");
10130
10131 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10132
10133 free_irq(irq, ioa_cfg);
10134
10135 LEAVE;
10136
10137 return rc;
10138 }
10139
10140
10141
10142
10143
10144
10145
10146
10147 static int ipr_probe_ioa(struct pci_dev *pdev,
10148 const struct pci_device_id *dev_id)
10149 {
10150 struct ipr_ioa_cfg *ioa_cfg;
10151 struct Scsi_Host *host;
10152 unsigned long ipr_regs_pci;
10153 void __iomem *ipr_regs;
10154 int rc = PCIBIOS_SUCCESSFUL;
10155 volatile u32 mask, uproc, interrupts;
10156 unsigned long lock_flags, driver_lock_flags;
10157 unsigned int irq_flag;
10158
10159 ENTER;
10160
10161 dev_info(&pdev->dev, "Found IOA with IRQ: %d\n", pdev->irq);
10162 host = scsi_host_alloc(&driver_template, sizeof(*ioa_cfg));
10163
10164 if (!host) {
10165 dev_err(&pdev->dev, "call to scsi_host_alloc failed!\n");
10166 rc = -ENOMEM;
10167 goto out;
10168 }
10169
10170 ioa_cfg = (struct ipr_ioa_cfg *)host->hostdata;
10171 memset(ioa_cfg, 0, sizeof(struct ipr_ioa_cfg));
10172 ata_host_init(&ioa_cfg->ata_host, &pdev->dev, &ipr_sata_ops);
10173
10174 ioa_cfg->ipr_chip = ipr_get_chip_info(dev_id);
10175
10176 if (!ioa_cfg->ipr_chip) {
10177 dev_err(&pdev->dev, "Unknown adapter chipset 0x%04X 0x%04X\n",
10178 dev_id->vendor, dev_id->device);
10179 goto out_scsi_host_put;
10180 }
10181
10182
10183 ioa_cfg->sis64 = ioa_cfg->ipr_chip->sis_type == IPR_SIS64 ? 1 : 0;
10184 ioa_cfg->chip_cfg = ioa_cfg->ipr_chip->cfg;
10185 ioa_cfg->clear_isr = ioa_cfg->chip_cfg->clear_isr;
10186 ioa_cfg->max_cmds = ioa_cfg->chip_cfg->max_cmds;
10187
10188 if (ipr_transop_timeout)
10189 ioa_cfg->transop_timeout = ipr_transop_timeout;
10190 else if (dev_id->driver_data & IPR_USE_LONG_TRANSOP_TIMEOUT)
10191 ioa_cfg->transop_timeout = IPR_LONG_OPERATIONAL_TIMEOUT;
10192 else
10193 ioa_cfg->transop_timeout = IPR_OPERATIONAL_TIMEOUT;
10194
10195 ioa_cfg->revid = pdev->revision;
10196
10197 ipr_init_ioa_cfg(ioa_cfg, host, pdev);
10198
10199 ipr_regs_pci = pci_resource_start(pdev, 0);
10200
10201 rc = pci_request_regions(pdev, IPR_NAME);
10202 if (rc < 0) {
10203 dev_err(&pdev->dev,
10204 "Couldn't register memory range of registers\n");
10205 goto out_scsi_host_put;
10206 }
10207
10208 rc = pci_enable_device(pdev);
10209
10210 if (rc || pci_channel_offline(pdev)) {
10211 if (pci_channel_offline(pdev)) {
10212 ipr_wait_for_pci_err_recovery(ioa_cfg);
10213 rc = pci_enable_device(pdev);
10214 }
10215
10216 if (rc) {
10217 dev_err(&pdev->dev, "Cannot enable adapter\n");
10218 ipr_wait_for_pci_err_recovery(ioa_cfg);
10219 goto out_release_regions;
10220 }
10221 }
10222
10223 ipr_regs = pci_ioremap_bar(pdev, 0);
10224
10225 if (!ipr_regs) {
10226 dev_err(&pdev->dev,
10227 "Couldn't map memory range of registers\n");
10228 rc = -ENOMEM;
10229 goto out_disable;
10230 }
10231
10232 ioa_cfg->hdw_dma_regs = ipr_regs;
10233 ioa_cfg->hdw_dma_regs_pci = ipr_regs_pci;
10234 ioa_cfg->ioa_mailbox = ioa_cfg->chip_cfg->mailbox + ipr_regs;
10235
10236 ipr_init_regs(ioa_cfg);
10237
10238 if (ioa_cfg->sis64) {
10239 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
10240 if (rc < 0) {
10241 dev_dbg(&pdev->dev, "Failed to set 64 bit DMA mask\n");
10242 rc = dma_set_mask_and_coherent(&pdev->dev,
10243 DMA_BIT_MASK(32));
10244 }
10245 } else
10246 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10247
10248 if (rc < 0) {
10249 dev_err(&pdev->dev, "Failed to set DMA mask\n");
10250 goto cleanup_nomem;
10251 }
10252
10253 rc = pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
10254 ioa_cfg->chip_cfg->cache_line_size);
10255
10256 if (rc != PCIBIOS_SUCCESSFUL) {
10257 dev_err(&pdev->dev, "Write of cache line size failed\n");
10258 ipr_wait_for_pci_err_recovery(ioa_cfg);
10259 rc = -EIO;
10260 goto cleanup_nomem;
10261 }
10262
10263
10264 interrupts = readl(ioa_cfg->regs.sense_interrupt_reg);
10265 ipr_wait_for_pci_err_recovery(ioa_cfg);
10266
10267 if (ipr_number_of_msix > IPR_MAX_MSIX_VECTORS) {
10268 dev_err(&pdev->dev, "The max number of MSIX is %d\n",
10269 IPR_MAX_MSIX_VECTORS);
10270 ipr_number_of_msix = IPR_MAX_MSIX_VECTORS;
10271 }
10272
10273 irq_flag = PCI_IRQ_LEGACY;
10274 if (ioa_cfg->ipr_chip->has_msi)
10275 irq_flag |= PCI_IRQ_MSI | PCI_IRQ_MSIX;
10276 rc = pci_alloc_irq_vectors(pdev, 1, ipr_number_of_msix, irq_flag);
10277 if (rc < 0) {
10278 ipr_wait_for_pci_err_recovery(ioa_cfg);
10279 goto cleanup_nomem;
10280 }
10281 ioa_cfg->nvectors = rc;
10282
10283 if (!pdev->msi_enabled && !pdev->msix_enabled)
10284 ioa_cfg->clear_isr = 1;
10285
10286 pci_set_master(pdev);
10287
10288 if (pci_channel_offline(pdev)) {
10289 ipr_wait_for_pci_err_recovery(ioa_cfg);
10290 pci_set_master(pdev);
10291 if (pci_channel_offline(pdev)) {
10292 rc = -EIO;
10293 goto out_msi_disable;
10294 }
10295 }
10296
10297 if (pdev->msi_enabled || pdev->msix_enabled) {
10298 rc = ipr_test_msi(ioa_cfg, pdev);
10299 switch (rc) {
10300 case 0:
10301 dev_info(&pdev->dev,
10302 "Request for %d MSI%ss succeeded.", ioa_cfg->nvectors,
10303 pdev->msix_enabled ? "-X" : "");
10304 break;
10305 case -EOPNOTSUPP:
10306 ipr_wait_for_pci_err_recovery(ioa_cfg);
10307 pci_free_irq_vectors(pdev);
10308
10309 ioa_cfg->nvectors = 1;
10310 ioa_cfg->clear_isr = 1;
10311 break;
10312 default:
10313 goto out_msi_disable;
10314 }
10315 }
10316
10317 ioa_cfg->hrrq_num = min3(ioa_cfg->nvectors,
10318 (unsigned int)num_online_cpus(),
10319 (unsigned int)IPR_MAX_HRRQ_NUM);
10320
10321 if ((rc = ipr_save_pcix_cmd_reg(ioa_cfg)))
10322 goto out_msi_disable;
10323
10324 if ((rc = ipr_set_pcix_cmd_reg(ioa_cfg)))
10325 goto out_msi_disable;
10326
10327 rc = ipr_alloc_mem(ioa_cfg);
10328 if (rc < 0) {
10329 dev_err(&pdev->dev,
10330 "Couldn't allocate enough memory for device driver!\n");
10331 goto out_msi_disable;
10332 }
10333
10334
10335 rc = pci_save_state(pdev);
10336
10337 if (rc != PCIBIOS_SUCCESSFUL) {
10338 dev_err(&pdev->dev, "Failed to save PCI config space\n");
10339 rc = -EIO;
10340 goto cleanup_nolog;
10341 }
10342
10343
10344
10345
10346
10347 mask = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
10348 interrupts = readl(ioa_cfg->regs.sense_interrupt_reg32);
10349 uproc = readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
10350 if ((mask & IPR_PCII_HRRQ_UPDATED) == 0 || (uproc & IPR_UPROCI_RESET_ALERT))
10351 ioa_cfg->needs_hard_reset = 1;
10352 if ((interrupts & IPR_PCII_ERROR_INTERRUPTS) || reset_devices)
10353 ioa_cfg->needs_hard_reset = 1;
10354 if (interrupts & IPR_PCII_IOA_UNIT_CHECKED)
10355 ioa_cfg->ioa_unit_checked = 1;
10356
10357 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10358 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
10359 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10360
10361 if (pdev->msi_enabled || pdev->msix_enabled) {
10362 name_msi_vectors(ioa_cfg);
10363 rc = request_irq(pci_irq_vector(pdev, 0), ipr_isr, 0,
10364 ioa_cfg->vectors_info[0].desc,
10365 &ioa_cfg->hrrq[0]);
10366 if (!rc)
10367 rc = ipr_request_other_msi_irqs(ioa_cfg, pdev);
10368 } else {
10369 rc = request_irq(pdev->irq, ipr_isr,
10370 IRQF_SHARED,
10371 IPR_NAME, &ioa_cfg->hrrq[0]);
10372 }
10373 if (rc) {
10374 dev_err(&pdev->dev, "Couldn't register IRQ %d! rc=%d\n",
10375 pdev->irq, rc);
10376 goto cleanup_nolog;
10377 }
10378
10379 if ((dev_id->driver_data & IPR_USE_PCI_WARM_RESET) ||
10380 (dev_id->device == PCI_DEVICE_ID_IBM_OBSIDIAN_E && !ioa_cfg->revid)) {
10381 ioa_cfg->needs_warm_reset = 1;
10382 ioa_cfg->reset = ipr_reset_slot_reset;
10383
10384 ioa_cfg->reset_work_q = alloc_ordered_workqueue("ipr_reset_%d",
10385 WQ_MEM_RECLAIM, host->host_no);
10386
10387 if (!ioa_cfg->reset_work_q) {
10388 dev_err(&pdev->dev, "Couldn't register reset workqueue\n");
10389 rc = -ENOMEM;
10390 goto out_free_irq;
10391 }
10392 } else
10393 ioa_cfg->reset = ipr_reset_start_bist;
10394
10395 spin_lock_irqsave(&ipr_driver_lock, driver_lock_flags);
10396 list_add_tail(&ioa_cfg->queue, &ipr_ioa_head);
10397 spin_unlock_irqrestore(&ipr_driver_lock, driver_lock_flags);
10398
10399 LEAVE;
10400 out:
10401 return rc;
10402
10403 out_free_irq:
10404 ipr_free_irqs(ioa_cfg);
10405 cleanup_nolog:
10406 ipr_free_mem(ioa_cfg);
10407 out_msi_disable:
10408 ipr_wait_for_pci_err_recovery(ioa_cfg);
10409 pci_free_irq_vectors(pdev);
10410 cleanup_nomem:
10411 iounmap(ipr_regs);
10412 out_disable:
10413 pci_disable_device(pdev);
10414 out_release_regions:
10415 pci_release_regions(pdev);
10416 out_scsi_host_put:
10417 scsi_host_put(host);
10418 goto out;
10419 }
10420
10421
10422
10423
10424
10425
10426
10427
10428
10429
10430
10431
10432
10433
10434
10435 static void ipr_initiate_ioa_bringdown(struct ipr_ioa_cfg *ioa_cfg,
10436 enum ipr_shutdown_type shutdown_type)
10437 {
10438 ENTER;
10439 if (ioa_cfg->sdt_state == WAIT_FOR_DUMP)
10440 ioa_cfg->sdt_state = ABORT_DUMP;
10441 ioa_cfg->reset_retries = 0;
10442 ioa_cfg->in_ioa_bringdown = 1;
10443 ipr_initiate_ioa_reset(ioa_cfg, shutdown_type);
10444 LEAVE;
10445 }
10446
10447
10448
10449
10450
10451
10452
10453
10454
10455
10456 static void __ipr_remove(struct pci_dev *pdev)
10457 {
10458 unsigned long host_lock_flags = 0;
10459 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
10460 int i;
10461 unsigned long driver_lock_flags;
10462 ENTER;
10463
10464 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
10465 while (ioa_cfg->in_reset_reload) {
10466 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
10467 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
10468 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
10469 }
10470
10471 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
10472 spin_lock(&ioa_cfg->hrrq[i]._lock);
10473 ioa_cfg->hrrq[i].removing_ioa = 1;
10474 spin_unlock(&ioa_cfg->hrrq[i]._lock);
10475 }
10476 wmb();
10477 ipr_initiate_ioa_bringdown(ioa_cfg, IPR_SHUTDOWN_NORMAL);
10478
10479 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
10480 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
10481 flush_work(&ioa_cfg->work_q);
10482 if (ioa_cfg->reset_work_q)
10483 flush_workqueue(ioa_cfg->reset_work_q);
10484 INIT_LIST_HEAD(&ioa_cfg->used_res_q);
10485 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
10486
10487 spin_lock_irqsave(&ipr_driver_lock, driver_lock_flags);
10488 list_del(&ioa_cfg->queue);
10489 spin_unlock_irqrestore(&ipr_driver_lock, driver_lock_flags);
10490
10491 if (ioa_cfg->sdt_state == ABORT_DUMP)
10492 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
10493 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
10494
10495 ipr_free_all_resources(ioa_cfg);
10496
10497 LEAVE;
10498 }
10499
10500
10501
10502
10503
10504
10505
10506
10507
10508
10509 static void ipr_remove(struct pci_dev *pdev)
10510 {
10511 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
10512
10513 ENTER;
10514
10515 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
10516 &ipr_trace_attr);
10517 ipr_remove_dump_file(&ioa_cfg->host->shost_dev.kobj,
10518 &ipr_dump_attr);
10519 sysfs_remove_bin_file(&ioa_cfg->host->shost_dev.kobj,
10520 &ipr_ioa_async_err_log);
10521 scsi_remove_host(ioa_cfg->host);
10522
10523 __ipr_remove(pdev);
10524
10525 LEAVE;
10526 }
10527
10528
10529
10530
10531
10532
10533
10534 static int ipr_probe(struct pci_dev *pdev, const struct pci_device_id *dev_id)
10535 {
10536 struct ipr_ioa_cfg *ioa_cfg;
10537 unsigned long flags;
10538 int rc, i;
10539
10540 rc = ipr_probe_ioa(pdev, dev_id);
10541
10542 if (rc)
10543 return rc;
10544
10545 ioa_cfg = pci_get_drvdata(pdev);
10546 rc = ipr_probe_ioa_part2(ioa_cfg);
10547
10548 if (rc) {
10549 __ipr_remove(pdev);
10550 return rc;
10551 }
10552
10553 rc = scsi_add_host(ioa_cfg->host, &pdev->dev);
10554
10555 if (rc) {
10556 __ipr_remove(pdev);
10557 return rc;
10558 }
10559
10560 rc = ipr_create_trace_file(&ioa_cfg->host->shost_dev.kobj,
10561 &ipr_trace_attr);
10562
10563 if (rc) {
10564 scsi_remove_host(ioa_cfg->host);
10565 __ipr_remove(pdev);
10566 return rc;
10567 }
10568
10569 rc = sysfs_create_bin_file(&ioa_cfg->host->shost_dev.kobj,
10570 &ipr_ioa_async_err_log);
10571
10572 if (rc) {
10573 ipr_remove_dump_file(&ioa_cfg->host->shost_dev.kobj,
10574 &ipr_dump_attr);
10575 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
10576 &ipr_trace_attr);
10577 scsi_remove_host(ioa_cfg->host);
10578 __ipr_remove(pdev);
10579 return rc;
10580 }
10581
10582 rc = ipr_create_dump_file(&ioa_cfg->host->shost_dev.kobj,
10583 &ipr_dump_attr);
10584
10585 if (rc) {
10586 sysfs_remove_bin_file(&ioa_cfg->host->shost_dev.kobj,
10587 &ipr_ioa_async_err_log);
10588 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
10589 &ipr_trace_attr);
10590 scsi_remove_host(ioa_cfg->host);
10591 __ipr_remove(pdev);
10592 return rc;
10593 }
10594 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
10595 ioa_cfg->scan_enabled = 1;
10596 schedule_work(&ioa_cfg->work_q);
10597 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
10598
10599 ioa_cfg->iopoll_weight = ioa_cfg->chip_cfg->iopoll_weight;
10600
10601 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
10602 for (i = 1; i < ioa_cfg->hrrq_num; i++) {
10603 irq_poll_init(&ioa_cfg->hrrq[i].iopoll,
10604 ioa_cfg->iopoll_weight, ipr_iopoll);
10605 }
10606 }
10607
10608 scsi_scan_host(ioa_cfg->host);
10609
10610 return 0;
10611 }
10612
10613
10614
10615
10616
10617
10618
10619
10620
10621
10622
10623 static void ipr_shutdown(struct pci_dev *pdev)
10624 {
10625 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
10626 unsigned long lock_flags = 0;
10627 enum ipr_shutdown_type shutdown_type = IPR_SHUTDOWN_NORMAL;
10628 int i;
10629
10630 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10631 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
10632 ioa_cfg->iopoll_weight = 0;
10633 for (i = 1; i < ioa_cfg->hrrq_num; i++)
10634 irq_poll_disable(&ioa_cfg->hrrq[i].iopoll);
10635 }
10636
10637 while (ioa_cfg->in_reset_reload) {
10638 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10639 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
10640 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10641 }
10642
10643 if (ipr_fast_reboot && system_state == SYSTEM_RESTART && ioa_cfg->sis64)
10644 shutdown_type = IPR_SHUTDOWN_QUIESCE;
10645
10646 ipr_initiate_ioa_bringdown(ioa_cfg, shutdown_type);
10647 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10648 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
10649 if (ipr_fast_reboot && system_state == SYSTEM_RESTART && ioa_cfg->sis64) {
10650 ipr_free_irqs(ioa_cfg);
10651 pci_disable_device(ioa_cfg->pdev);
10652 }
10653 }
10654
10655 static struct pci_device_id ipr_pci_table[] = {
10656 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
10657 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_5702, 0, 0, 0 },
10658 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
10659 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_5703, 0, 0, 0 },
10660 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
10661 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_573D, 0, 0, 0 },
10662 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
10663 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_573E, 0, 0, 0 },
10664 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
10665 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571B, 0, 0, 0 },
10666 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
10667 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572E, 0, 0, 0 },
10668 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
10669 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571A, 0, 0, 0 },
10670 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
10671 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575B, 0, 0,
10672 IPR_USE_LONG_TRANSOP_TIMEOUT },
10673 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
10674 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572A, 0, 0, 0 },
10675 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
10676 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572B, 0, 0,
10677 IPR_USE_LONG_TRANSOP_TIMEOUT },
10678 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
10679 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575C, 0, 0,
10680 IPR_USE_LONG_TRANSOP_TIMEOUT },
10681 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
10682 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572A, 0, 0, 0 },
10683 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
10684 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572B, 0, 0,
10685 IPR_USE_LONG_TRANSOP_TIMEOUT},
10686 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
10687 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575C, 0, 0,
10688 IPR_USE_LONG_TRANSOP_TIMEOUT },
10689 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
10690 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574E, 0, 0,
10691 IPR_USE_LONG_TRANSOP_TIMEOUT },
10692 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
10693 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B3, 0, 0, 0 },
10694 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
10695 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CC, 0, 0, 0 },
10696 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
10697 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B7, 0, 0,
10698 IPR_USE_LONG_TRANSOP_TIMEOUT | IPR_USE_PCI_WARM_RESET },
10699 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE,
10700 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2780, 0, 0, 0 },
10701 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
10702 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571E, 0, 0, 0 },
10703 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
10704 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571F, 0, 0,
10705 IPR_USE_LONG_TRANSOP_TIMEOUT },
10706 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
10707 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572F, 0, 0,
10708 IPR_USE_LONG_TRANSOP_TIMEOUT },
10709 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10710 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B5, 0, 0, 0 },
10711 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10712 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574D, 0, 0, 0 },
10713 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10714 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B2, 0, 0, 0 },
10715 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10716 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C0, 0, 0, 0 },
10717 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10718 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C3, 0, 0, 0 },
10719 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10720 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C4, 0, 0, 0 },
10721 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10722 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B4, 0, 0, 0 },
10723 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10724 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B1, 0, 0, 0 },
10725 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10726 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C6, 0, 0, 0 },
10727 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10728 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C8, 0, 0, 0 },
10729 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10730 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CE, 0, 0, 0 },
10731 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10732 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D5, 0, 0, 0 },
10733 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10734 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D6, 0, 0, 0 },
10735 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10736 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D7, 0, 0, 0 },
10737 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10738 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D8, 0, 0, 0 },
10739 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10740 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D9, 0, 0, 0 },
10741 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10742 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57DA, 0, 0, 0 },
10743 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10744 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57EB, 0, 0, 0 },
10745 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10746 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57EC, 0, 0, 0 },
10747 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10748 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57ED, 0, 0, 0 },
10749 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10750 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57EE, 0, 0, 0 },
10751 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10752 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57EF, 0, 0, 0 },
10753 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10754 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57F0, 0, 0, 0 },
10755 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10756 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2CCA, 0, 0, 0 },
10757 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10758 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2CD2, 0, 0, 0 },
10759 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10760 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2CCD, 0, 0, 0 },
10761 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_RATTLESNAKE,
10762 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_580A, 0, 0, 0 },
10763 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_RATTLESNAKE,
10764 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_580B, 0, 0, 0 },
10765 { }
10766 };
10767 MODULE_DEVICE_TABLE(pci, ipr_pci_table);
10768
10769 static const struct pci_error_handlers ipr_err_handler = {
10770 .error_detected = ipr_pci_error_detected,
10771 .mmio_enabled = ipr_pci_mmio_enabled,
10772 .slot_reset = ipr_pci_slot_reset,
10773 };
10774
10775 static struct pci_driver ipr_driver = {
10776 .name = IPR_NAME,
10777 .id_table = ipr_pci_table,
10778 .probe = ipr_probe,
10779 .remove = ipr_remove,
10780 .shutdown = ipr_shutdown,
10781 .err_handler = &ipr_err_handler,
10782 };
10783
10784
10785
10786
10787
10788
10789
10790 static void ipr_halt_done(struct ipr_cmnd *ipr_cmd)
10791 {
10792 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
10793 }
10794
10795
10796
10797
10798
10799
10800
10801 static int ipr_halt(struct notifier_block *nb, ulong event, void *buf)
10802 {
10803 struct ipr_cmnd *ipr_cmd;
10804 struct ipr_ioa_cfg *ioa_cfg;
10805 unsigned long flags = 0, driver_lock_flags;
10806
10807 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
10808 return NOTIFY_DONE;
10809
10810 spin_lock_irqsave(&ipr_driver_lock, driver_lock_flags);
10811
10812 list_for_each_entry(ioa_cfg, &ipr_ioa_head, queue) {
10813 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
10814 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds ||
10815 (ipr_fast_reboot && event == SYS_RESTART && ioa_cfg->sis64)) {
10816 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
10817 continue;
10818 }
10819
10820 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
10821 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
10822 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
10823 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN;
10824 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_SHUTDOWN_PREPARE_FOR_NORMAL;
10825
10826 ipr_do_req(ipr_cmd, ipr_halt_done, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
10827 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
10828 }
10829 spin_unlock_irqrestore(&ipr_driver_lock, driver_lock_flags);
10830
10831 return NOTIFY_OK;
10832 }
10833
10834 static struct notifier_block ipr_notifier = {
10835 ipr_halt, NULL, 0
10836 };
10837
10838
10839
10840
10841
10842
10843
10844 static int __init ipr_init(void)
10845 {
10846 ipr_info("IBM Power RAID SCSI Device Driver version: %s %s\n",
10847 IPR_DRIVER_VERSION, IPR_DRIVER_DATE);
10848
10849 register_reboot_notifier(&ipr_notifier);
10850 return pci_register_driver(&ipr_driver);
10851 }
10852
10853
10854
10855
10856
10857
10858
10859
10860
10861 static void __exit ipr_exit(void)
10862 {
10863 unregister_reboot_notifier(&ipr_notifier);
10864 pci_unregister_driver(&ipr_driver);
10865 }
10866
10867 module_init(ipr_init);
10868 module_exit(ipr_exit);