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15 #ifndef __BFI_REG_H__
16 #define __BFI_REG_H__
17
18 #define HOSTFN0_INT_STATUS 0x00014000
19 #define HOSTFN1_INT_STATUS 0x00014100
20 #define HOSTFN2_INT_STATUS 0x00014300
21 #define HOSTFN3_INT_STATUS 0x00014400
22 #define HOSTFN0_INT_MSK 0x00014004
23 #define HOSTFN1_INT_MSK 0x00014104
24 #define HOSTFN2_INT_MSK 0x00014304
25 #define HOSTFN3_INT_MSK 0x00014404
26
27 #define HOST_PAGE_NUM_FN0 0x00014008
28 #define HOST_PAGE_NUM_FN1 0x00014108
29 #define HOST_PAGE_NUM_FN2 0x00014308
30 #define HOST_PAGE_NUM_FN3 0x00014408
31
32 #define APP_PLL_LCLK_CTL_REG 0x00014204
33 #define __P_LCLK_PLL_LOCK 0x80000000
34 #define __APP_PLL_LCLK_SRAM_USE_100MHZ 0x00100000
35 #define __APP_PLL_LCLK_RESET_TIMER_MK 0x000e0000
36 #define __APP_PLL_LCLK_RESET_TIMER_SH 17
37 #define __APP_PLL_LCLK_RESET_TIMER(_v) ((_v) << __APP_PLL_LCLK_RESET_TIMER_SH)
38 #define __APP_PLL_LCLK_LOGIC_SOFT_RESET 0x00010000
39 #define __APP_PLL_LCLK_CNTLMT0_1_MK 0x0000c000
40 #define __APP_PLL_LCLK_CNTLMT0_1_SH 14
41 #define __APP_PLL_LCLK_CNTLMT0_1(_v) ((_v) << __APP_PLL_LCLK_CNTLMT0_1_SH)
42 #define __APP_PLL_LCLK_JITLMT0_1_MK 0x00003000
43 #define __APP_PLL_LCLK_JITLMT0_1_SH 12
44 #define __APP_PLL_LCLK_JITLMT0_1(_v) ((_v) << __APP_PLL_LCLK_JITLMT0_1_SH)
45 #define __APP_PLL_LCLK_HREF 0x00000800
46 #define __APP_PLL_LCLK_HDIV 0x00000400
47 #define __APP_PLL_LCLK_P0_1_MK 0x00000300
48 #define __APP_PLL_LCLK_P0_1_SH 8
49 #define __APP_PLL_LCLK_P0_1(_v) ((_v) << __APP_PLL_LCLK_P0_1_SH)
50 #define __APP_PLL_LCLK_Z0_2_MK 0x000000e0
51 #define __APP_PLL_LCLK_Z0_2_SH 5
52 #define __APP_PLL_LCLK_Z0_2(_v) ((_v) << __APP_PLL_LCLK_Z0_2_SH)
53 #define __APP_PLL_LCLK_RSEL200500 0x00000010
54 #define __APP_PLL_LCLK_ENARST 0x00000008
55 #define __APP_PLL_LCLK_BYPASS 0x00000004
56 #define __APP_PLL_LCLK_LRESETN 0x00000002
57 #define __APP_PLL_LCLK_ENABLE 0x00000001
58 #define APP_PLL_SCLK_CTL_REG 0x00014208
59 #define __P_SCLK_PLL_LOCK 0x80000000
60 #define __APP_PLL_SCLK_RESET_TIMER_MK 0x000e0000
61 #define __APP_PLL_SCLK_RESET_TIMER_SH 17
62 #define __APP_PLL_SCLK_RESET_TIMER(_v) ((_v) << __APP_PLL_SCLK_RESET_TIMER_SH)
63 #define __APP_PLL_SCLK_LOGIC_SOFT_RESET 0x00010000
64 #define __APP_PLL_SCLK_CNTLMT0_1_MK 0x0000c000
65 #define __APP_PLL_SCLK_CNTLMT0_1_SH 14
66 #define __APP_PLL_SCLK_CNTLMT0_1(_v) ((_v) << __APP_PLL_SCLK_CNTLMT0_1_SH)
67 #define __APP_PLL_SCLK_JITLMT0_1_MK 0x00003000
68 #define __APP_PLL_SCLK_JITLMT0_1_SH 12
69 #define __APP_PLL_SCLK_JITLMT0_1(_v) ((_v) << __APP_PLL_SCLK_JITLMT0_1_SH)
70 #define __APP_PLL_SCLK_HREF 0x00000800
71 #define __APP_PLL_SCLK_HDIV 0x00000400
72 #define __APP_PLL_SCLK_P0_1_MK 0x00000300
73 #define __APP_PLL_SCLK_P0_1_SH 8
74 #define __APP_PLL_SCLK_P0_1(_v) ((_v) << __APP_PLL_SCLK_P0_1_SH)
75 #define __APP_PLL_SCLK_Z0_2_MK 0x000000e0
76 #define __APP_PLL_SCLK_Z0_2_SH 5
77 #define __APP_PLL_SCLK_Z0_2(_v) ((_v) << __APP_PLL_SCLK_Z0_2_SH)
78 #define __APP_PLL_SCLK_RSEL200500 0x00000010
79 #define __APP_PLL_SCLK_ENARST 0x00000008
80 #define __APP_PLL_SCLK_BYPASS 0x00000004
81 #define __APP_PLL_SCLK_LRESETN 0x00000002
82 #define __APP_PLL_SCLK_ENABLE 0x00000001
83 #define __ENABLE_MAC_AHB_1 0x00800000
84 #define __ENABLE_MAC_AHB_0 0x00400000
85 #define __ENABLE_MAC_1 0x00200000
86 #define __ENABLE_MAC_0 0x00100000
87
88 #define HOST_SEM0_REG 0x00014230
89 #define HOST_SEM1_REG 0x00014234
90 #define HOST_SEM2_REG 0x00014238
91 #define HOST_SEM3_REG 0x0001423c
92 #define HOST_SEM4_REG 0x00014610
93 #define HOST_SEM5_REG 0x00014614
94 #define HOST_SEM6_REG 0x00014618
95 #define HOST_SEM7_REG 0x0001461c
96 #define HOST_SEM0_INFO_REG 0x00014240
97 #define HOST_SEM1_INFO_REG 0x00014244
98 #define HOST_SEM2_INFO_REG 0x00014248
99 #define HOST_SEM3_INFO_REG 0x0001424c
100 #define HOST_SEM4_INFO_REG 0x00014620
101 #define HOST_SEM5_INFO_REG 0x00014624
102 #define HOST_SEM6_INFO_REG 0x00014628
103 #define HOST_SEM7_INFO_REG 0x0001462c
104
105 #define HOSTFN0_LPU0_CMD_STAT 0x00019000
106 #define HOSTFN0_LPU1_CMD_STAT 0x00019004
107 #define HOSTFN1_LPU0_CMD_STAT 0x00019010
108 #define HOSTFN1_LPU1_CMD_STAT 0x00019014
109 #define HOSTFN2_LPU0_CMD_STAT 0x00019150
110 #define HOSTFN2_LPU1_CMD_STAT 0x00019154
111 #define HOSTFN3_LPU0_CMD_STAT 0x00019160
112 #define HOSTFN3_LPU1_CMD_STAT 0x00019164
113 #define LPU0_HOSTFN0_CMD_STAT 0x00019008
114 #define LPU1_HOSTFN0_CMD_STAT 0x0001900c
115 #define LPU0_HOSTFN1_CMD_STAT 0x00019018
116 #define LPU1_HOSTFN1_CMD_STAT 0x0001901c
117 #define LPU0_HOSTFN2_CMD_STAT 0x00019158
118 #define LPU1_HOSTFN2_CMD_STAT 0x0001915c
119 #define LPU0_HOSTFN3_CMD_STAT 0x00019168
120 #define LPU1_HOSTFN3_CMD_STAT 0x0001916c
121
122 #define PSS_CTL_REG 0x00018800
123 #define __PSS_I2C_CLK_DIV_MK 0x007f0000
124 #define __PSS_I2C_CLK_DIV_SH 16
125 #define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH)
126 #define __PSS_LMEM_INIT_DONE 0x00001000
127 #define __PSS_LMEM_RESET 0x00000200
128 #define __PSS_LMEM_INIT_EN 0x00000100
129 #define __PSS_LPU1_RESET 0x00000002
130 #define __PSS_LPU0_RESET 0x00000001
131 #define PSS_ERR_STATUS_REG 0x00018810
132 #define ERR_SET_REG 0x00018818
133 #define PSS_GPIO_OUT_REG 0x000188c0
134 #define __PSS_GPIO_OUT_REG 0x00000fff
135 #define PSS_GPIO_OE_REG 0x000188c8
136 #define __PSS_GPIO_OE_REG 0x000000ff
137
138 #define HOSTFN0_LPU_MBOX0_0 0x00019200
139 #define HOSTFN1_LPU_MBOX0_8 0x00019260
140 #define LPU_HOSTFN0_MBOX0_0 0x00019280
141 #define LPU_HOSTFN1_MBOX0_8 0x000192e0
142 #define HOSTFN2_LPU_MBOX0_0 0x00019400
143 #define HOSTFN3_LPU_MBOX0_8 0x00019460
144 #define LPU_HOSTFN2_MBOX0_0 0x00019480
145 #define LPU_HOSTFN3_MBOX0_8 0x000194e0
146
147 #define HOST_MSIX_ERR_INDEX_FN0 0x0001400c
148 #define HOST_MSIX_ERR_INDEX_FN1 0x0001410c
149 #define HOST_MSIX_ERR_INDEX_FN2 0x0001430c
150 #define HOST_MSIX_ERR_INDEX_FN3 0x0001440c
151
152 #define MBIST_CTL_REG 0x00014220
153 #define __EDRAM_BISTR_START 0x00000004
154 #define MBIST_STAT_REG 0x00014224
155 #define ETH_MAC_SER_REG 0x00014288
156 #define __APP_EMS_CKBUFAMPIN 0x00000020
157 #define __APP_EMS_REFCLKSEL 0x00000010
158 #define __APP_EMS_CMLCKSEL 0x00000008
159 #define __APP_EMS_REFCKBUFEN2 0x00000004
160 #define __APP_EMS_REFCKBUFEN1 0x00000002
161 #define __APP_EMS_CHANNEL_SEL 0x00000001
162 #define FNC_PERS_REG 0x00014604
163 #define __F3_FUNCTION_ACTIVE 0x80000000
164 #define __F3_FUNCTION_MODE 0x40000000
165 #define __F3_PORT_MAP_MK 0x30000000
166 #define __F3_PORT_MAP_SH 28
167 #define __F3_PORT_MAP(_v) ((_v) << __F3_PORT_MAP_SH)
168 #define __F3_VM_MODE 0x08000000
169 #define __F3_INTX_STATUS_MK 0x07000000
170 #define __F3_INTX_STATUS_SH 24
171 #define __F3_INTX_STATUS(_v) ((_v) << __F3_INTX_STATUS_SH)
172 #define __F2_FUNCTION_ACTIVE 0x00800000
173 #define __F2_FUNCTION_MODE 0x00400000
174 #define __F2_PORT_MAP_MK 0x00300000
175 #define __F2_PORT_MAP_SH 20
176 #define __F2_PORT_MAP(_v) ((_v) << __F2_PORT_MAP_SH)
177 #define __F2_VM_MODE 0x00080000
178 #define __F2_INTX_STATUS_MK 0x00070000
179 #define __F2_INTX_STATUS_SH 16
180 #define __F2_INTX_STATUS(_v) ((_v) << __F2_INTX_STATUS_SH)
181 #define __F1_FUNCTION_ACTIVE 0x00008000
182 #define __F1_FUNCTION_MODE 0x00004000
183 #define __F1_PORT_MAP_MK 0x00003000
184 #define __F1_PORT_MAP_SH 12
185 #define __F1_PORT_MAP(_v) ((_v) << __F1_PORT_MAP_SH)
186 #define __F1_VM_MODE 0x00000800
187 #define __F1_INTX_STATUS_MK 0x00000700
188 #define __F1_INTX_STATUS_SH 8
189 #define __F1_INTX_STATUS(_v) ((_v) << __F1_INTX_STATUS_SH)
190 #define __F0_FUNCTION_ACTIVE 0x00000080
191 #define __F0_FUNCTION_MODE 0x00000040
192 #define __F0_PORT_MAP_MK 0x00000030
193 #define __F0_PORT_MAP_SH 4
194 #define __F0_PORT_MAP(_v) ((_v) << __F0_PORT_MAP_SH)
195 #define __F0_VM_MODE 0x00000008
196 #define __F0_INTX_STATUS 0x00000007
197 enum {
198 __F0_INTX_STATUS_MSIX = 0x0,
199 __F0_INTX_STATUS_INTA = 0x1,
200 __F0_INTX_STATUS_INTB = 0x2,
201 __F0_INTX_STATUS_INTC = 0x3,
202 __F0_INTX_STATUS_INTD = 0x4,
203 };
204
205 #define OP_MODE 0x0001460c
206 #define __APP_ETH_CLK_LOWSPEED 0x00000004
207 #define __GLOBAL_CORECLK_HALFSPEED 0x00000002
208 #define __GLOBAL_FCOE_MODE 0x00000001
209 #define FW_INIT_HALT_P0 0x000191ac
210 #define __FW_INIT_HALT_P 0x00000001
211 #define FW_INIT_HALT_P1 0x000191bc
212 #define PMM_1T_RESET_REG_P0 0x0002381c
213 #define __PMM_1T_RESET_P 0x00000001
214 #define PMM_1T_RESET_REG_P1 0x00023c1c
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218
219 #define CT2_PCI_CPQ_BASE 0x00030000
220 #define CT2_PCI_APP_BASE 0x00030100
221 #define CT2_PCI_ETH_BASE 0x00030400
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225
226 #define CT2_HOSTFN_INT_STATUS (CT2_PCI_APP_BASE + 0x00)
227 #define CT2_HOSTFN_INTR_MASK (CT2_PCI_APP_BASE + 0x04)
228 #define CT2_HOSTFN_PERSONALITY0 (CT2_PCI_APP_BASE + 0x08)
229 #define __PME_STATUS_ 0x00200000
230 #define __PF_VF_BAR_SIZE_MODE__MK 0x00180000
231 #define __PF_VF_BAR_SIZE_MODE__SH 19
232 #define __PF_VF_BAR_SIZE_MODE_(_v) ((_v) << __PF_VF_BAR_SIZE_MODE__SH)
233 #define __FC_LL_PORT_MAP__MK 0x00060000
234 #define __FC_LL_PORT_MAP__SH 17
235 #define __FC_LL_PORT_MAP_(_v) ((_v) << __FC_LL_PORT_MAP__SH)
236 #define __PF_VF_ACTIVE_ 0x00010000
237 #define __PF_VF_CFG_RDY_ 0x00008000
238 #define __PF_VF_ENABLE_ 0x00004000
239 #define __PF_DRIVER_ACTIVE_ 0x00002000
240 #define __PF_PME_SEND_ENABLE_ 0x00001000
241 #define __PF_EXROM_OFFSET__MK 0x00000ff0
242 #define __PF_EXROM_OFFSET__SH 4
243 #define __PF_EXROM_OFFSET_(_v) ((_v) << __PF_EXROM_OFFSET__SH)
244 #define __FC_LL_MODE_ 0x00000008
245 #define __PF_INTX_PIN_ 0x00000007
246 #define CT2_HOSTFN_PERSONALITY1 (CT2_PCI_APP_BASE + 0x0C)
247 #define __PF_NUM_QUEUES1__MK 0xff000000
248 #define __PF_NUM_QUEUES1__SH 24
249 #define __PF_NUM_QUEUES1_(_v) ((_v) << __PF_NUM_QUEUES1__SH)
250 #define __PF_VF_QUE_OFFSET1__MK 0x00ff0000
251 #define __PF_VF_QUE_OFFSET1__SH 16
252 #define __PF_VF_QUE_OFFSET1_(_v) ((_v) << __PF_VF_QUE_OFFSET1__SH)
253 #define __PF_VF_NUM_QUEUES__MK 0x0000ff00
254 #define __PF_VF_NUM_QUEUES__SH 8
255 #define __PF_VF_NUM_QUEUES_(_v) ((_v) << __PF_VF_NUM_QUEUES__SH)
256 #define __PF_VF_QUE_OFFSET_ 0x000000ff
257 #define CT2_HOSTFN_PAGE_NUM (CT2_PCI_APP_BASE + 0x18)
258 #define CT2_HOSTFN_MSIX_VT_INDEX_MBOX_ERR (CT2_PCI_APP_BASE + 0x38)
259
260
261
262
263 #define CT2_HOSTFN_LPU0_MBOX0 (CT2_PCI_CPQ_BASE + 0x00)
264 #define CT2_HOSTFN_LPU1_MBOX0 (CT2_PCI_CPQ_BASE + 0x20)
265 #define CT2_LPU0_HOSTFN_MBOX0 (CT2_PCI_CPQ_BASE + 0x40)
266 #define CT2_LPU1_HOSTFN_MBOX0 (CT2_PCI_CPQ_BASE + 0x60)
267 #define CT2_HOSTFN_LPU0_CMD_STAT (CT2_PCI_CPQ_BASE + 0x80)
268 #define CT2_HOSTFN_LPU1_CMD_STAT (CT2_PCI_CPQ_BASE + 0x84)
269 #define CT2_LPU0_HOSTFN_CMD_STAT (CT2_PCI_CPQ_BASE + 0x88)
270 #define CT2_LPU1_HOSTFN_CMD_STAT (CT2_PCI_CPQ_BASE + 0x8c)
271 #define CT2_HOSTFN_LPU0_READ_STAT (CT2_PCI_CPQ_BASE + 0x90)
272 #define CT2_HOSTFN_LPU1_READ_STAT (CT2_PCI_CPQ_BASE + 0x94)
273 #define CT2_LPU0_HOSTFN_MBOX0_MSK (CT2_PCI_CPQ_BASE + 0x98)
274 #define CT2_LPU1_HOSTFN_MBOX0_MSK (CT2_PCI_CPQ_BASE + 0x9C)
275 #define CT2_HOST_SEM0_REG 0x000148f0
276 #define CT2_HOST_SEM1_REG 0x000148f4
277 #define CT2_HOST_SEM2_REG 0x000148f8
278 #define CT2_HOST_SEM3_REG 0x000148fc
279 #define CT2_HOST_SEM4_REG 0x00014900
280 #define CT2_HOST_SEM5_REG 0x00014904
281 #define CT2_HOST_SEM6_REG 0x00014908
282 #define CT2_HOST_SEM7_REG 0x0001490c
283 #define CT2_HOST_SEM0_INFO_REG 0x000148b0
284 #define CT2_HOST_SEM1_INFO_REG 0x000148b4
285 #define CT2_HOST_SEM2_INFO_REG 0x000148b8
286 #define CT2_HOST_SEM3_INFO_REG 0x000148bc
287 #define CT2_HOST_SEM4_INFO_REG 0x000148c0
288 #define CT2_HOST_SEM5_INFO_REG 0x000148c4
289 #define CT2_HOST_SEM6_INFO_REG 0x000148c8
290 #define CT2_HOST_SEM7_INFO_REG 0x000148cc
291
292 #define CT2_APP_PLL_LCLK_CTL_REG 0x00014808
293 #define __APP_LPUCLK_HALFSPEED 0x40000000
294 #define __APP_PLL_LCLK_LOAD 0x20000000
295 #define __APP_PLL_LCLK_FBCNT_MK 0x1fe00000
296 #define __APP_PLL_LCLK_FBCNT_SH 21
297 #define __APP_PLL_LCLK_FBCNT(_v) ((_v) << __APP_PLL_SCLK_FBCNT_SH)
298 enum {
299 __APP_PLL_LCLK_FBCNT_425_MHZ = 6,
300 __APP_PLL_LCLK_FBCNT_468_MHZ = 4,
301 };
302 #define __APP_PLL_LCLK_EXTFB 0x00000800
303 #define __APP_PLL_LCLK_ENOUTS 0x00000400
304 #define __APP_PLL_LCLK_RATE 0x00000010
305 #define CT2_APP_PLL_SCLK_CTL_REG 0x0001480c
306 #define __P_SCLK_PLL_LOCK 0x80000000
307 #define __APP_PLL_SCLK_REFCLK_SEL 0x40000000
308 #define __APP_PLL_SCLK_CLK_DIV2 0x20000000
309 #define __APP_PLL_SCLK_LOAD 0x10000000
310 #define __APP_PLL_SCLK_FBCNT_MK 0x0ff00000
311 #define __APP_PLL_SCLK_FBCNT_SH 20
312 #define __APP_PLL_SCLK_FBCNT(_v) ((_v) << __APP_PLL_SCLK_FBCNT_SH)
313 enum {
314 __APP_PLL_SCLK_FBCNT_NORM = 6,
315 __APP_PLL_SCLK_FBCNT_10G_FC = 10,
316 };
317 #define __APP_PLL_SCLK_EXTFB 0x00000800
318 #define __APP_PLL_SCLK_ENOUTS 0x00000400
319 #define __APP_PLL_SCLK_RATE 0x00000010
320 #define CT2_PCIE_MISC_REG 0x00014804
321 #define __ETH_CLK_ENABLE_PORT1 0x00000010
322 #define CT2_CHIP_MISC_PRG 0x000148a4
323 #define __ETH_CLK_ENABLE_PORT0 0x00004000
324 #define __APP_LPU_SPEED 0x00000002
325 #define CT2_MBIST_STAT_REG 0x00014818
326 #define CT2_MBIST_CTL_REG 0x0001481c
327 #define CT2_PMM_1T_CONTROL_REG_P0 0x0002381c
328 #define __PMM_1T_PNDB_P 0x00000002
329 #define CT2_PMM_1T_CONTROL_REG_P1 0x00023c1c
330 #define CT2_WGN_STATUS 0x00014990
331 #define __A2T_AHB_LOAD 0x00000800
332 #define __WGN_READY 0x00000400
333 #define __GLBL_PF_VF_CFG_RDY 0x00000200
334 #define CT2_NFC_STS_REG 0x00027410
335 #define CT2_NFC_CSR_CLR_REG 0x00027420
336 #define CT2_NFC_CSR_SET_REG 0x00027424
337 #define __HALT_NFC_CONTROLLER 0x00000002
338 #define __NFC_CONTROLLER_HALTED 0x00001000
339 #define CT2_RSC_GPR15_REG 0x0002765c
340 #define CT2_CSI_FW_CTL_REG 0x00027080
341 #define CT2_CSI_FW_CTL_SET_REG 0x00027088
342 #define __RESET_AND_START_SCLK_LCLK_PLLS 0x00010000
343
344 #define CT2_CSI_MAC0_CONTROL_REG 0x000270d0
345 #define __CSI_MAC_RESET 0x00000010
346 #define __CSI_MAC_AHB_RESET 0x00000008
347 #define CT2_CSI_MAC1_CONTROL_REG 0x000270d4
348 #define CT2_CSI_MAC_CONTROL_REG(__n) \
349 (CT2_CSI_MAC0_CONTROL_REG + \
350 (__n) * (CT2_CSI_MAC1_CONTROL_REG - CT2_CSI_MAC0_CONTROL_REG))
351
352 #define CT2_NFC_FLASH_STS_REG 0x00014834
353 #define __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS 0x00000020
354
355
356
357 #define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG
358 #define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG
359 #define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG
360 #define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG
361 #define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG
362 #define BFA_IOC_FAIL_SYNC HOST_SEM5_INFO_REG
363
364
365
366
367 #define CT2_BFA_IOC0_HBEAT_REG CT2_HOST_SEM0_INFO_REG
368 #define CT2_BFA_IOC0_STATE_REG CT2_HOST_SEM1_INFO_REG
369 #define CT2_BFA_IOC1_HBEAT_REG CT2_HOST_SEM2_INFO_REG
370 #define CT2_BFA_IOC1_STATE_REG CT2_HOST_SEM3_INFO_REG
371 #define CT2_BFA_FW_USE_COUNT CT2_HOST_SEM4_INFO_REG
372 #define CT2_BFA_IOC_FAIL_SYNC CT2_HOST_SEM5_INFO_REG
373
374 #define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
375 #define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
376
377
378
379
380 #define __HFN_INT_CPE_Q0 0x00000001U
381 #define __HFN_INT_CPE_Q1 0x00000002U
382 #define __HFN_INT_CPE_Q2 0x00000004U
383 #define __HFN_INT_CPE_Q3 0x00000008U
384 #define __HFN_INT_CPE_Q4 0x00000010U
385 #define __HFN_INT_CPE_Q5 0x00000020U
386 #define __HFN_INT_CPE_Q6 0x00000040U
387 #define __HFN_INT_CPE_Q7 0x00000080U
388 #define __HFN_INT_RME_Q0 0x00000100U
389 #define __HFN_INT_RME_Q1 0x00000200U
390 #define __HFN_INT_RME_Q2 0x00000400U
391 #define __HFN_INT_RME_Q3 0x00000800U
392 #define __HFN_INT_RME_Q4 0x00001000U
393 #define __HFN_INT_RME_Q5 0x00002000U
394 #define __HFN_INT_RME_Q6 0x00004000U
395 #define __HFN_INT_RME_Q7 0x00008000U
396 #define __HFN_INT_ERR_EMC 0x00010000U
397 #define __HFN_INT_ERR_LPU0 0x00020000U
398 #define __HFN_INT_ERR_LPU1 0x00040000U
399 #define __HFN_INT_ERR_PSS 0x00080000U
400 #define __HFN_INT_MBOX_LPU0 0x00100000U
401 #define __HFN_INT_MBOX_LPU1 0x00200000U
402 #define __HFN_INT_MBOX1_LPU0 0x00400000U
403 #define __HFN_INT_MBOX1_LPU1 0x00800000U
404 #define __HFN_INT_LL_HALT 0x01000000U
405 #define __HFN_INT_CPE_MASK 0x000000ffU
406 #define __HFN_INT_RME_MASK 0x0000ff00U
407 #define __HFN_INT_ERR_MASK \
408 (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | __HFN_INT_ERR_LPU1 | \
409 __HFN_INT_ERR_PSS | __HFN_INT_LL_HALT)
410 #define __HFN_INT_FN0_MASK \
411 (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \
412 __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \
413 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0)
414 #define __HFN_INT_FN1_MASK \
415 (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \
416 __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \
417 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1)
418
419
420
421
422 #define __HFN_INT_MBOX_LPU0_CT2 0x00010000U
423 #define __HFN_INT_MBOX_LPU1_CT2 0x00020000U
424 #define __HFN_INT_ERR_PSS_CT2 0x00040000U
425 #define __HFN_INT_ERR_LPU0_CT2 0x00080000U
426 #define __HFN_INT_ERR_LPU1_CT2 0x00100000U
427 #define __HFN_INT_CPQ_HALT_CT2 0x00200000U
428 #define __HFN_INT_ERR_WGN_CT2 0x00400000U
429 #define __HFN_INT_ERR_LEHRX_CT2 0x00800000U
430 #define __HFN_INT_ERR_LEHTX_CT2 0x01000000U
431 #define __HFN_INT_ERR_MASK_CT2 \
432 (__HFN_INT_ERR_PSS_CT2 | __HFN_INT_ERR_LPU0_CT2 | \
433 __HFN_INT_ERR_LPU1_CT2 | __HFN_INT_CPQ_HALT_CT2 | \
434 __HFN_INT_ERR_WGN_CT2 | __HFN_INT_ERR_LEHRX_CT2 | \
435 __HFN_INT_ERR_LEHTX_CT2)
436 #define __HFN_INT_FN0_MASK_CT2 \
437 (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \
438 __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \
439 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0_CT2)
440 #define __HFN_INT_FN1_MASK_CT2 \
441 (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \
442 __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \
443 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1_CT2)
444
445
446
447
448 #define PSS_SMEM_PAGE_START 0x8000
449 #define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15))
450 #define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff)
451
452 #endif