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11 #ifndef __BFA_DEFS_H__
12 #define __BFA_DEFS_H__
13
14 #include "bfa_fc.h"
15 #include "bfad_drv.h"
16
17 #define BFA_MFG_SERIALNUM_SIZE 11
18 #define STRSZ(_n) (((_n) + 4) & ~3)
19
20
21
22
23 enum {
24 BFA_MFG_TYPE_CB_MAX = 825,
25 BFA_MFG_TYPE_FC8P2 = 825,
26 BFA_MFG_TYPE_FC8P1 = 815,
27 BFA_MFG_TYPE_FC4P2 = 425,
28 BFA_MFG_TYPE_FC4P1 = 415,
29 BFA_MFG_TYPE_CNA10P2 = 1020,
30 BFA_MFG_TYPE_CNA10P1 = 1010,
31 BFA_MFG_TYPE_JAYHAWK = 804,
32 BFA_MFG_TYPE_WANCHESE = 1007,
33 BFA_MFG_TYPE_ASTRA = 807,
34 BFA_MFG_TYPE_LIGHTNING_P0 = 902,
35 BFA_MFG_TYPE_LIGHTNING = 1741,
36 BFA_MFG_TYPE_PROWLER_F = 1560,
37 BFA_MFG_TYPE_PROWLER_N = 1410,
38 BFA_MFG_TYPE_PROWLER_C = 1710,
39 BFA_MFG_TYPE_PROWLER_D = 1860,
40 BFA_MFG_TYPE_CHINOOK = 1867,
41 BFA_MFG_TYPE_CHINOOK2 = 1869,
42 BFA_MFG_TYPE_INVALID = 0,
43 };
44
45 #pragma pack(1)
46
47
48
49
50 #define bfa_mfg_is_mezz(type) (( \
51 (type) == BFA_MFG_TYPE_JAYHAWK || \
52 (type) == BFA_MFG_TYPE_WANCHESE || \
53 (type) == BFA_MFG_TYPE_ASTRA || \
54 (type) == BFA_MFG_TYPE_LIGHTNING_P0 || \
55 (type) == BFA_MFG_TYPE_LIGHTNING || \
56 (type) == BFA_MFG_TYPE_CHINOOK || \
57 (type) == BFA_MFG_TYPE_CHINOOK2))
58
59
60
61
62 #define bfa_mfg_is_old_wwn_mac_model(type) (( \
63 (type) == BFA_MFG_TYPE_FC8P2 || \
64 (type) == BFA_MFG_TYPE_FC8P1 || \
65 (type) == BFA_MFG_TYPE_FC4P2 || \
66 (type) == BFA_MFG_TYPE_FC4P1 || \
67 (type) == BFA_MFG_TYPE_CNA10P2 || \
68 (type) == BFA_MFG_TYPE_CNA10P1 || \
69 (type) == BFA_MFG_TYPE_JAYHAWK || \
70 (type) == BFA_MFG_TYPE_WANCHESE))
71
72 #define bfa_mfg_increment_wwn_mac(m, i) \
73 do { \
74 u32 t = ((u32)(m)[0] << 16) | ((u32)(m)[1] << 8) | \
75 (u32)(m)[2]; \
76 t += (i); \
77 (m)[0] = (t >> 16) & 0xFF; \
78 (m)[1] = (t >> 8) & 0xFF; \
79 (m)[2] = t & 0xFF; \
80 } while (0)
81
82
83
84
85 #define BFA_MFG_VPD_LEN 512
86
87
88
89
90 enum {
91 BFA_MFG_VPD_UNKNOWN = 0,
92 BFA_MFG_VPD_IBM = 1,
93 BFA_MFG_VPD_HP = 2,
94 BFA_MFG_VPD_DELL = 3,
95 BFA_MFG_VPD_PCI_IBM = 0x08,
96 BFA_MFG_VPD_PCI_HP = 0x10,
97 BFA_MFG_VPD_PCI_DELL = 0x20,
98 BFA_MFG_VPD_PCI_BRCD = 0xf8,
99 };
100
101
102
103
104 struct bfa_mfg_vpd_s {
105 u8 version;
106 u8 vpd_sig[3];
107 u8 chksum;
108 u8 vendor;
109 u8 len;
110 u8 rsv;
111 u8 data[BFA_MFG_VPD_LEN];
112 };
113
114 #pragma pack()
115
116
117
118
119 enum bfa_status {
120 BFA_STATUS_OK = 0,
121 BFA_STATUS_FAILED = 1,
122 BFA_STATUS_EINVAL = 2,
123
124 BFA_STATUS_ENOMEM = 3,
125 BFA_STATUS_ETIMER = 5,
126
127 BFA_STATUS_EPROTOCOL = 6,
128 BFA_STATUS_BADFLASH = 9,
129 BFA_STATUS_SFP_UNSUPP = 10,
130 BFA_STATUS_UNKNOWN_VFID = 11,
131 BFA_STATUS_DATACORRUPTED = 12,
132 BFA_STATUS_DEVBUSY = 13,
133 BFA_STATUS_HDMA_FAILED = 16,
134 BFA_STATUS_FLASH_BAD_LEN = 17,
135 BFA_STATUS_UNKNOWN_LWWN = 18,
136 BFA_STATUS_UNKNOWN_RWWN = 19,
137 BFA_STATUS_VPORT_EXISTS = 21,
138 BFA_STATUS_VPORT_MAX = 22,
139 BFA_STATUS_UNSUPP_SPEED = 23,
140 BFA_STATUS_INVLD_DFSZ = 24,
141 BFA_STATUS_CMD_NOTSUPP = 26,
142 BFA_STATUS_FABRIC_RJT = 29,
143 BFA_STATUS_UNKNOWN_VWWN = 30,
144 BFA_STATUS_PORT_OFFLINE = 34,
145 BFA_STATUS_VPORT_WWN_BP = 46,
146 BFA_STATUS_PORT_NOT_DISABLED = 47,
147 BFA_STATUS_NO_FCPIM_NEXUS = 52,
148 BFA_STATUS_IOC_FAILURE = 56,
149
150 BFA_STATUS_INVALID_WWN = 57,
151 BFA_STATUS_ADAPTER_ENABLED = 60,
152 BFA_STATUS_IOC_NON_OP = 61,
153 BFA_STATUS_VERSION_FAIL = 70,
154 BFA_STATUS_DIAG_BUSY = 71,
155 BFA_STATUS_BEACON_ON = 72,
156 BFA_STATUS_ENOFSAVE = 78,
157 BFA_STATUS_IOC_DISABLED = 82,
158 BFA_STATUS_ERROR_TRL_ENABLED = 87,
159 BFA_STATUS_ERROR_QOS_ENABLED = 88,
160 BFA_STATUS_NO_SFP_DEV = 89,
161 BFA_STATUS_MEMTEST_FAILED = 90,
162 BFA_STATUS_LEDTEST_OP = 109,
163 BFA_STATUS_INVALID_MAC = 134,
164 BFA_STATUS_CMD_NOTSUPP_CNA = 146,
165 BFA_STATUS_PBC = 154,
166
167 BFA_STATUS_BAD_FWCFG = 156,
168 BFA_STATUS_INVALID_VENDOR = 158,
169 BFA_STATUS_SFP_NOT_READY = 159,
170 BFA_STATUS_TRUNK_ENABLED = 164,
171
172 BFA_STATUS_TRUNK_DISABLED = 165,
173
174 BFA_STATUS_IOPROFILE_OFF = 175,
175 BFA_STATUS_PHY_NOT_PRESENT = 183,
176 BFA_STATUS_FEATURE_NOT_SUPPORTED = 192,
177 BFA_STATUS_ENTRY_EXISTS = 193,
178 BFA_STATUS_ENTRY_NOT_EXISTS = 194,
179 BFA_STATUS_NO_CHANGE = 195,
180 BFA_STATUS_FAA_ENABLED = 197,
181 BFA_STATUS_FAA_DISABLED = 198,
182 BFA_STATUS_FAA_ACQUIRED = 199,
183 BFA_STATUS_FAA_ACQ_ADDR = 200,
184 BFA_STATUS_BBCR_FC_ONLY = 201,
185
186 BFA_STATUS_ERROR_TRUNK_ENABLED = 203,
187 BFA_STATUS_MAX_ENTRY_REACHED = 212,
188 BFA_STATUS_TOPOLOGY_LOOP = 230,
189 BFA_STATUS_LOOP_UNSUPP_MEZZ = 231,
190
191 BFA_STATUS_INVALID_BW = 233,
192 BFA_STATUS_QOS_BW_INVALID = 234,
193
194 BFA_STATUS_DPORT_ENABLED = 235,
195 BFA_STATUS_DPORT_DISABLED = 236,
196 BFA_STATUS_CMD_NOTSUPP_MEZZ = 239,
197 BFA_STATUS_FRU_NOT_PRESENT = 240,
198 BFA_STATUS_DPORT_NO_SFP = 243,
199
200
201 BFA_STATUS_DPORT_ERR = 245,
202 BFA_STATUS_DPORT_ENOSYS = 254,
203 BFA_STATUS_DPORT_CANT_PERF = 255,
204
205 BFA_STATUS_DPORT_LOGICALERR = 256,
206 BFA_STATUS_DPORT_SWBUSY = 257,
207 BFA_STATUS_ERR_BBCR_SPEED_UNSUPPORT = 258,
208
209 BFA_STATUS_ERROR_BBCR_ENABLED = 259,
210
211 BFA_STATUS_INVALID_BBSCN = 260,
212
213 BFA_STATUS_DDPORT_ERR = 261,
214
215
216 BFA_STATUS_DPORT_SFPWRAP_ERR = 262,
217
218 BFA_STATUS_BBCR_CFG_NO_CHANGE = 265,
219
220 BFA_STATUS_DPORT_SW_NOTREADY = 268,
221
222
223 BFA_STATUS_DPORT_INV_SFP = 271,
224 BFA_STATUS_DPORT_CMD_NOTSUPP = 273,
225
226 BFA_STATUS_MAX_VAL
227 };
228 #define bfa_status_t enum bfa_status
229
230 enum bfa_eproto_status {
231 BFA_EPROTO_BAD_ACCEPT = 0,
232 BFA_EPROTO_UNKNOWN_RSP = 1
233 };
234 #define bfa_eproto_status_t enum bfa_eproto_status
235
236 enum bfa_boolean {
237 BFA_FALSE = 0,
238 BFA_TRUE = 1
239 };
240 #define bfa_boolean_t enum bfa_boolean
241
242 #define BFA_STRING_32 32
243 #define BFA_VERSION_LEN 64
244
245
246
247
248
249
250
251
252 enum {
253 BFA_ADAPTER_SERIAL_NUM_LEN = STRSZ(BFA_MFG_SERIALNUM_SIZE),
254
255
256
257 BFA_ADAPTER_MODEL_NAME_LEN = 16,
258 BFA_ADAPTER_MODEL_DESCR_LEN = 128,
259 BFA_ADAPTER_MFG_NAME_LEN = 8,
260 BFA_ADAPTER_SYM_NAME_LEN = 64,
261 BFA_ADAPTER_OS_TYPE_LEN = 64,
262 BFA_ADAPTER_UUID_LEN = 16,
263 };
264
265 struct bfa_adapter_attr_s {
266 char manufacturer[BFA_ADAPTER_MFG_NAME_LEN];
267 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
268 u32 card_type;
269 char model[BFA_ADAPTER_MODEL_NAME_LEN];
270 char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN];
271 wwn_t pwwn;
272 char node_symname[FC_SYMNAME_MAX];
273 char hw_ver[BFA_VERSION_LEN];
274 char fw_ver[BFA_VERSION_LEN];
275 char optrom_ver[BFA_VERSION_LEN];
276 char os_type[BFA_ADAPTER_OS_TYPE_LEN];
277 struct bfa_mfg_vpd_s vpd;
278 struct mac_s mac;
279
280 u8 nports;
281 u8 max_speed;
282 u8 prototype;
283 char asic_rev;
284
285 u8 pcie_gen;
286 u8 pcie_lanes_orig;
287 u8 pcie_lanes;
288 u8 cna_capable;
289
290 u8 is_mezz;
291 u8 trunk_capable;
292 u8 mfg_day;
293 u8 mfg_month;
294 u16 mfg_year;
295 u16 rsvd;
296 u8 uuid[BFA_ADAPTER_UUID_LEN];
297 };
298
299
300
301
302
303 enum {
304 BFA_IOC_DRIVER_LEN = 16,
305 BFA_IOC_CHIP_REV_LEN = 8,
306 };
307
308
309
310
311 struct bfa_ioc_driver_attr_s {
312 char driver[BFA_IOC_DRIVER_LEN];
313 char driver_ver[BFA_VERSION_LEN];
314 char fw_ver[BFA_VERSION_LEN];
315 char bios_ver[BFA_VERSION_LEN];
316 char efi_ver[BFA_VERSION_LEN];
317 char ob_ver[BFA_VERSION_LEN];
318 };
319
320
321
322
323 struct bfa_ioc_pci_attr_s {
324 u16 vendor_id;
325 u16 device_id;
326 u16 ssid;
327 u16 ssvid;
328 u32 pcifn;
329 u32 rsvd;
330 char chip_rev[BFA_IOC_CHIP_REV_LEN];
331 };
332
333
334
335
336 enum bfa_ioc_state {
337 BFA_IOC_UNINIT = 1,
338 BFA_IOC_RESET = 2,
339 BFA_IOC_SEMWAIT = 3,
340 BFA_IOC_HWINIT = 4,
341 BFA_IOC_GETATTR = 5,
342 BFA_IOC_OPERATIONAL = 6,
343 BFA_IOC_INITFAIL = 7,
344 BFA_IOC_FAIL = 8,
345 BFA_IOC_DISABLING = 9,
346 BFA_IOC_DISABLED = 10,
347 BFA_IOC_FWMISMATCH = 11,
348 BFA_IOC_ENABLING = 12,
349 BFA_IOC_HWFAIL = 13,
350 BFA_IOC_ACQ_ADDR = 14,
351 };
352
353
354
355
356 struct bfa_fw_ioc_stats_s {
357 u32 enable_reqs;
358 u32 disable_reqs;
359 u32 get_attr_reqs;
360 u32 dbg_sync;
361 u32 dbg_dump;
362 u32 unknown_reqs;
363 };
364
365
366
367
368 struct bfa_ioc_drv_stats_s {
369 u32 ioc_isrs;
370 u32 ioc_enables;
371 u32 ioc_disables;
372 u32 ioc_hbfails;
373 u32 ioc_boots;
374 u32 stats_tmos;
375 u32 hb_count;
376 u32 disable_reqs;
377 u32 enable_reqs;
378 u32 disable_replies;
379 u32 enable_replies;
380 u32 rsvd;
381 };
382
383
384
385
386 struct bfa_ioc_stats_s {
387 struct bfa_ioc_drv_stats_s drv_stats;
388 struct bfa_fw_ioc_stats_s fw_stats;
389 };
390
391 enum bfa_ioc_type_e {
392 BFA_IOC_TYPE_FC = 1,
393 BFA_IOC_TYPE_FCoE = 2,
394 BFA_IOC_TYPE_LL = 3,
395 };
396
397
398
399
400 struct bfa_ioc_attr_s {
401 enum bfa_ioc_type_e ioc_type;
402 enum bfa_ioc_state state;
403 struct bfa_adapter_attr_s adapter_attr;
404 struct bfa_ioc_driver_attr_s driver_attr;
405 struct bfa_ioc_pci_attr_s pci_attr;
406 u8 port_id;
407 u8 port_mode;
408 u8 cap_bm;
409 u8 port_mode_cfg;
410 u8 def_fn;
411 u8 rsvd[3];
412 };
413
414
415
416
417 enum bfa_aen_category {
418 BFA_AEN_CAT_ADAPTER = 1,
419 BFA_AEN_CAT_PORT = 2,
420 BFA_AEN_CAT_LPORT = 3,
421 BFA_AEN_CAT_RPORT = 4,
422 BFA_AEN_CAT_ITNIM = 5,
423 BFA_AEN_CAT_AUDIT = 8,
424 BFA_AEN_CAT_IOC = 9,
425 };
426
427
428 enum bfa_adapter_aen_event {
429 BFA_ADAPTER_AEN_ADD = 1,
430 BFA_ADAPTER_AEN_REMOVE = 2,
431 };
432
433 struct bfa_adapter_aen_data_s {
434 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
435 u32 nports;
436 wwn_t pwwn;
437 };
438
439
440 enum bfa_port_aen_event {
441 BFA_PORT_AEN_ONLINE = 1,
442 BFA_PORT_AEN_OFFLINE = 2,
443 BFA_PORT_AEN_RLIR = 3,
444 BFA_PORT_AEN_SFP_INSERT = 4,
445 BFA_PORT_AEN_SFP_REMOVE = 5,
446 BFA_PORT_AEN_SFP_POM = 6,
447 BFA_PORT_AEN_ENABLE = 7,
448 BFA_PORT_AEN_DISABLE = 8,
449 BFA_PORT_AEN_AUTH_ON = 9,
450 BFA_PORT_AEN_AUTH_OFF = 10,
451 BFA_PORT_AEN_DISCONNECT = 11,
452 BFA_PORT_AEN_QOS_NEG = 12,
453 BFA_PORT_AEN_FABRIC_NAME_CHANGE = 13,
454 BFA_PORT_AEN_SFP_ACCESS_ERROR = 14,
455 BFA_PORT_AEN_SFP_UNSUPPORT = 15,
456 };
457
458 enum bfa_port_aen_sfp_pom {
459 BFA_PORT_AEN_SFP_POM_GREEN = 1,
460 BFA_PORT_AEN_SFP_POM_AMBER = 2,
461 BFA_PORT_AEN_SFP_POM_RED = 3,
462 BFA_PORT_AEN_SFP_POM_MAX = BFA_PORT_AEN_SFP_POM_RED
463 };
464
465 struct bfa_port_aen_data_s {
466 wwn_t pwwn;
467 wwn_t fwwn;
468 u32 phy_port_num;
469 u16 ioc_type;
470 u16 level;
471 mac_t mac;
472 u16 rsvd;
473 };
474
475
476 enum bfa_lport_aen_event {
477 BFA_LPORT_AEN_NEW = 1,
478 BFA_LPORT_AEN_DELETE = 2,
479 BFA_LPORT_AEN_ONLINE = 3,
480 BFA_LPORT_AEN_OFFLINE = 4,
481 BFA_LPORT_AEN_DISCONNECT = 5,
482 BFA_LPORT_AEN_NEW_PROP = 6,
483 BFA_LPORT_AEN_DELETE_PROP = 7,
484 BFA_LPORT_AEN_NEW_STANDARD = 8,
485 BFA_LPORT_AEN_DELETE_STANDARD = 9,
486 BFA_LPORT_AEN_NPIV_DUP_WWN = 10,
487 BFA_LPORT_AEN_NPIV_FABRIC_MAX = 11,
488 BFA_LPORT_AEN_NPIV_UNKNOWN = 12,
489 };
490
491 struct bfa_lport_aen_data_s {
492 u16 vf_id;
493 u16 roles;
494 u32 rsvd;
495 wwn_t ppwwn;
496 wwn_t lpwwn;
497 };
498
499
500 enum bfa_itnim_aen_event {
501 BFA_ITNIM_AEN_ONLINE = 1,
502 BFA_ITNIM_AEN_OFFLINE = 2,
503 BFA_ITNIM_AEN_DISCONNECT = 3,
504 };
505
506 struct bfa_itnim_aen_data_s {
507 u16 vf_id;
508 u16 rsvd[3];
509 wwn_t ppwwn;
510 wwn_t lpwwn;
511 wwn_t rpwwn;
512 };
513
514
515 enum bfa_audit_aen_event {
516 BFA_AUDIT_AEN_AUTH_ENABLE = 1,
517 BFA_AUDIT_AEN_AUTH_DISABLE = 2,
518 BFA_AUDIT_AEN_FLASH_ERASE = 3,
519 BFA_AUDIT_AEN_FLASH_UPDATE = 4,
520 };
521
522 struct bfa_audit_aen_data_s {
523 wwn_t pwwn;
524 int partition_inst;
525 int partition_type;
526 };
527
528
529 enum bfa_ioc_aen_event {
530 BFA_IOC_AEN_HBGOOD = 1,
531 BFA_IOC_AEN_HBFAIL = 2,
532 BFA_IOC_AEN_ENABLE = 3,
533 BFA_IOC_AEN_DISABLE = 4,
534 BFA_IOC_AEN_FWMISMATCH = 5,
535 BFA_IOC_AEN_FWCFG_ERROR = 6,
536 BFA_IOC_AEN_INVALID_VENDOR = 7,
537 BFA_IOC_AEN_INVALID_NWWN = 8,
538 BFA_IOC_AEN_INVALID_PWWN = 9
539 };
540
541 struct bfa_ioc_aen_data_s {
542 wwn_t pwwn;
543 u16 ioc_type;
544 mac_t mac;
545 };
546
547
548
549
550
551
552
553
554 #define BFA_MFG_CHKSUM_SIZE 16
555
556 #define BFA_MFG_PARTNUM_SIZE 14
557 #define BFA_MFG_SUPPLIER_ID_SIZE 10
558 #define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20
559 #define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20
560 #define BFA_MFG_SUPPLIER_REVISION_SIZE 4
561
562
563
564 #define BFA_MFG_IC_FC 0x01
565 #define BFA_MFG_IC_ETH 0x02
566
567
568
569
570 #define BFA_CM_HBA 0x01
571 #define BFA_CM_CNA 0x02
572 #define BFA_CM_NIC 0x04
573 #define BFA_CM_FC16G 0x08
574 #define BFA_CM_SRIOV 0x10
575 #define BFA_CM_MEZZ 0x20
576
577 #pragma pack(1)
578
579
580
581
582 struct bfa_mfg_block_s {
583 u8 version;
584 u8 mfg_sig[3];
585 u16 mfgsize;
586 u16 u16_chksum;
587 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
588 char brcd_partnum[STRSZ(BFA_MFG_PARTNUM_SIZE)];
589 u8 mfg_day;
590 u8 mfg_month;
591 u16 mfg_year;
592 wwn_t mfg_wwn;
593 u8 num_wwn;
594 u8 mfg_speeds;
595 u8 rsv[2];
596 char supplier_id[STRSZ(BFA_MFG_SUPPLIER_ID_SIZE)];
597 char supplier_partnum[STRSZ(BFA_MFG_SUPPLIER_PARTNUM_SIZE)];
598 char supplier_serialnum[STRSZ(BFA_MFG_SUPPLIER_SERIALNUM_SIZE)];
599 char supplier_revision[STRSZ(BFA_MFG_SUPPLIER_REVISION_SIZE)];
600 mac_t mfg_mac;
601 u8 num_mac;
602 u8 rsv2;
603 u32 card_type;
604 char cap_nic;
605 char cap_cna;
606 char cap_hba;
607 char cap_fc16g;
608 char cap_sriov;
609 char cap_mezz;
610 u8 rsv3;
611 u8 mfg_nports;
612 char media[8];
613 char initial_mode[8];
614 u8 rsv4[84];
615 u8 md5_chksum[BFA_MFG_CHKSUM_SIZE];
616 };
617
618 #pragma pack()
619
620
621
622
623
624
625
626
627 enum {
628 BFA_PCI_VENDOR_ID_BROCADE = 0x1657,
629 BFA_PCI_DEVICE_ID_FC_8G2P = 0x13,
630 BFA_PCI_DEVICE_ID_FC_8G1P = 0x17,
631 BFA_PCI_DEVICE_ID_CT = 0x14,
632 BFA_PCI_DEVICE_ID_CT_FC = 0x21,
633 BFA_PCI_DEVICE_ID_CT2 = 0x22,
634 BFA_PCI_DEVICE_ID_CT2_QUAD = 0x23,
635 };
636
637 #define bfa_asic_id_cb(__d) \
638 ((__d) == BFA_PCI_DEVICE_ID_FC_8G2P || \
639 (__d) == BFA_PCI_DEVICE_ID_FC_8G1P)
640 #define bfa_asic_id_ct(__d) \
641 ((__d) == BFA_PCI_DEVICE_ID_CT || \
642 (__d) == BFA_PCI_DEVICE_ID_CT_FC)
643 #define bfa_asic_id_ct2(__d) \
644 ((__d) == BFA_PCI_DEVICE_ID_CT2 || \
645 (__d) == BFA_PCI_DEVICE_ID_CT2_QUAD)
646 #define bfa_asic_id_ctc(__d) \
647 (bfa_asic_id_ct(__d) || bfa_asic_id_ct2(__d))
648
649
650
651
652 enum {
653 BFA_PCI_FCOE_SSDEVICE_ID = 0x14,
654 BFA_PCI_CT2_SSID_FCoE = 0x22,
655 BFA_PCI_CT2_SSID_ETH = 0x23,
656 BFA_PCI_CT2_SSID_FC = 0x24,
657 };
658
659
660
661
662 #define BFA_PCI_ACCESS_RANGES 1
663
664
665
666
667
668 enum bfa_port_speed {
669 BFA_PORT_SPEED_UNKNOWN = 0,
670 BFA_PORT_SPEED_1GBPS = 1,
671 BFA_PORT_SPEED_2GBPS = 2,
672 BFA_PORT_SPEED_4GBPS = 4,
673 BFA_PORT_SPEED_8GBPS = 8,
674 BFA_PORT_SPEED_10GBPS = 10,
675 BFA_PORT_SPEED_16GBPS = 16,
676 BFA_PORT_SPEED_AUTO = 0xf,
677 };
678 #define bfa_port_speed_t enum bfa_port_speed
679
680 enum {
681 BFA_BOOT_BOOTLUN_MAX = 4,
682 BFA_PREBOOT_BOOTLUN_MAX = 8,
683 };
684
685 #define BOOT_CFG_REV1 1
686 #define BOOT_CFG_VLAN 1
687
688
689
690
691
692 enum bfa_boot_bootopt {
693 BFA_BOOT_AUTO_DISCOVER = 0,
694 BFA_BOOT_STORED_BLUN = 1,
695 BFA_BOOT_FIRST_LUN = 2,
696 BFA_BOOT_PBC = 3,
697 };
698
699 #pragma pack(1)
700
701
702
703 struct bfa_boot_bootlun_s {
704 wwn_t pwwn;
705 struct scsi_lun lun;
706 };
707 #pragma pack()
708
709
710
711
712 struct bfa_boot_cfg_s {
713 u8 version;
714 u8 rsvd1;
715 u16 chksum;
716 u8 enable;
717 u8 speed;
718 u8 topology;
719 u8 bootopt;
720 u32 nbluns;
721 u32 rsvd2;
722 struct bfa_boot_bootlun_s blun[BFA_BOOT_BOOTLUN_MAX];
723 struct bfa_boot_bootlun_s blun_disc[BFA_BOOT_BOOTLUN_MAX];
724 };
725
726 struct bfa_boot_pbc_s {
727 u8 enable;
728 u8 speed;
729 u8 topology;
730 u8 rsvd1;
731 u32 nbluns;
732 struct bfa_boot_bootlun_s pblun[BFA_PREBOOT_BOOTLUN_MAX];
733 };
734
735 struct bfa_ethboot_cfg_s {
736 u8 version;
737 u8 rsvd1;
738 u16 chksum;
739 u8 enable;
740 u8 rsvd2;
741 u16 vlan;
742 };
743
744
745
746
747 #define BFA_ABLK_MAX_PORTS 2
748 #define BFA_ABLK_MAX_PFS 16
749 #define BFA_ABLK_MAX 2
750
751 #pragma pack(1)
752 enum bfa_mode_s {
753 BFA_MODE_HBA = 1,
754 BFA_MODE_CNA = 2,
755 BFA_MODE_NIC = 3
756 };
757
758 struct bfa_adapter_cfg_mode_s {
759 u16 max_pf;
760 u16 max_vf;
761 enum bfa_mode_s mode;
762 };
763
764 struct bfa_ablk_cfg_pf_s {
765 u16 pers;
766 u8 port_id;
767 u8 optrom;
768 u8 valid;
769 u8 sriov;
770 u8 max_vfs;
771 u8 rsvd[1];
772 u16 num_qpairs;
773 u16 num_vectors;
774 u16 bw_min;
775 u16 bw_max;
776 };
777
778 struct bfa_ablk_cfg_port_s {
779 u8 mode;
780 u8 type;
781 u8 max_pfs;
782 u8 rsvd[5];
783 };
784
785 struct bfa_ablk_cfg_inst_s {
786 u8 nports;
787 u8 max_pfs;
788 u8 rsvd[6];
789 struct bfa_ablk_cfg_pf_s pf_cfg[BFA_ABLK_MAX_PFS];
790 struct bfa_ablk_cfg_port_s port_cfg[BFA_ABLK_MAX_PORTS];
791 };
792
793 struct bfa_ablk_cfg_s {
794 struct bfa_ablk_cfg_inst_s inst[BFA_ABLK_MAX];
795 };
796
797
798
799
800
801 #define SFP_DIAGMON_SIZE 10
802
803
804 #define BFA_SFP_SCN_REMOVED 0
805 #define BFA_SFP_SCN_INSERTED 1
806 #define BFA_SFP_SCN_POM 2
807 #define BFA_SFP_SCN_FAILED 3
808 #define BFA_SFP_SCN_UNSUPPORT 4
809 #define BFA_SFP_SCN_VALID 5
810
811 enum bfa_defs_sfp_media_e {
812 BFA_SFP_MEDIA_UNKNOWN = 0x00,
813 BFA_SFP_MEDIA_CU = 0x01,
814 BFA_SFP_MEDIA_LW = 0x02,
815 BFA_SFP_MEDIA_SW = 0x03,
816 BFA_SFP_MEDIA_EL = 0x04,
817 BFA_SFP_MEDIA_UNSUPPORT = 0x05,
818 };
819
820
821
822
823 enum {
824 SFP_XMTR_TECH_CU = (1 << 0),
825 SFP_XMTR_TECH_CP = (1 << 1),
826 SFP_XMTR_TECH_CA = (1 << 2),
827 SFP_XMTR_TECH_LL = (1 << 3),
828 SFP_XMTR_TECH_SL = (1 << 4),
829 SFP_XMTR_TECH_SN = (1 << 5),
830 SFP_XMTR_TECH_EL_INTRA = (1 << 6),
831 SFP_XMTR_TECH_EL_INTER = (1 << 7),
832 SFP_XMTR_TECH_LC = (1 << 8),
833 SFP_XMTR_TECH_SA = (1 << 9)
834 };
835
836
837
838
839
840 struct sfp_srlid_base_s {
841 u8 id;
842 u8 extid;
843 u8 connector;
844 u8 xcvr[8];
845 u8 encoding;
846 u8 br_norm;
847 u8 rate_id;
848 u8 len_km;
849 u8 len_100m;
850 u8 len_om2;
851 u8 len_om1;
852 u8 len_cu;
853 u8 len_om3;
854 u8 vendor_name[16];
855 u8 unalloc1;
856 u8 vendor_oui[3];
857 u8 vendor_pn[16];
858 u8 vendor_rev[4];
859 u8 wavelen[2];
860 u8 unalloc2;
861 u8 cc_base;
862 };
863
864
865
866
867
868 struct sfp_srlid_ext_s {
869 u8 options[2];
870 u8 br_max;
871 u8 br_min;
872 u8 vendor_sn[16];
873 u8 date_code[8];
874 u8 diag_mon_type;
875 u8 en_options;
876 u8 sff_8472;
877 u8 cc_ext;
878 };
879
880
881
882
883
884 struct sfp_diag_base_s {
885
886
887
888 u8 temp_high_alarm[2];
889 u8 temp_low_alarm[2];
890 u8 temp_high_warning[2];
891 u8 temp_low_warning[2];
892
893 u8 volt_high_alarm[2];
894 u8 volt_low_alarm[2];
895 u8 volt_high_warning[2];
896 u8 volt_low_warning[2];
897
898 u8 bias_high_alarm[2];
899 u8 bias_low_alarm[2];
900 u8 bias_high_warning[2];
901 u8 bias_low_warning[2];
902
903 u8 tx_pwr_high_alarm[2];
904 u8 tx_pwr_low_alarm[2];
905 u8 tx_pwr_high_warning[2];
906 u8 tx_pwr_low_warning[2];
907
908 u8 rx_pwr_high_alarm[2];
909 u8 rx_pwr_low_alarm[2];
910 u8 rx_pwr_high_warning[2];
911 u8 rx_pwr_low_warning[2];
912
913 u8 unallocate_1[16];
914
915
916
917
918 u8 rx_pwr[20];
919 u8 tx_i[4];
920 u8 tx_pwr[4];
921 u8 temp[4];
922 u8 volt[4];
923 u8 unallocate_2[3];
924 u8 cc_dmi;
925 };
926
927
928
929
930
931 struct sfp_diag_ext_s {
932 u8 diag[SFP_DIAGMON_SIZE];
933 u8 unalloc1[4];
934 u8 status_ctl;
935 u8 rsvd;
936 u8 alarm_flags[2];
937 u8 unalloc2[2];
938 u8 warning_flags[2];
939 u8 ext_status_ctl[2];
940 };
941
942
943
944
945
946
947 struct sfp_usr_eeprom_s {
948 u8 rsvd1[2];
949 u8 ewrap;
950 u8 rsvd2[2];
951 u8 owrap;
952 u8 rsvd3[2];
953 u8 prbs;
954 u8 rsvd4[2];
955 u8 tx_eqz_16;
956 u8 tx_eqz_8;
957 u8 rsvd5[2];
958 u8 rx_emp_16;
959 u8 rx_emp_8;
960 u8 rsvd6[2];
961 u8 tx_eye_adj;
962 u8 rsvd7[3];
963 u8 tx_eye_qctl;
964 u8 tx_eye_qres;
965 u8 rsvd8[2];
966 u8 poh[3];
967 u8 rsvd9[2];
968 };
969
970 struct sfp_mem_s {
971 struct sfp_srlid_base_s srlid_base;
972 struct sfp_srlid_ext_s srlid_ext;
973 struct sfp_diag_base_s diag_base;
974 struct sfp_diag_ext_s diag_ext;
975 struct sfp_usr_eeprom_s usr_eeprom;
976 };
977
978
979
980
981 union sfp_xcvr_e10g_code_u {
982 u8 b;
983 struct {
984 #ifdef __BIG_ENDIAN
985 u8 e10g_unall:1;
986 u8 e10g_lrm:1;
987 u8 e10g_lr:1;
988 u8 e10g_sr:1;
989 u8 ib_sx:1;
990 u8 ib_lx:1;
991 u8 ib_cu_a:1;
992 u8 ib_cu_p:1;
993 #else
994 u8 ib_cu_p:1;
995 u8 ib_cu_a:1;
996 u8 ib_lx:1;
997 u8 ib_sx:1;
998 u8 e10g_sr:1;
999 u8 e10g_lr:1;
1000 u8 e10g_lrm:1;
1001 u8 e10g_unall:1;
1002 #endif
1003 } r;
1004 };
1005
1006 union sfp_xcvr_so1_code_u {
1007 u8 b;
1008 struct {
1009 u8 escon:2;
1010 u8 oc192_reach:1;
1011 u8 so_reach:2;
1012 u8 oc48_reach:3;
1013 } r;
1014 };
1015
1016 union sfp_xcvr_so2_code_u {
1017 u8 b;
1018 struct {
1019 u8 reserved:1;
1020 u8 oc12_reach:3;
1021 u8 reserved1:1;
1022 u8 oc3_reach:3;
1023 } r;
1024 };
1025
1026 union sfp_xcvr_eth_code_u {
1027 u8 b;
1028 struct {
1029 u8 base_px:1;
1030 u8 base_bx10:1;
1031 u8 e100base_fx:1;
1032 u8 e100base_lx:1;
1033 u8 e1000base_t:1;
1034 u8 e1000base_cx:1;
1035 u8 e1000base_lx:1;
1036 u8 e1000base_sx:1;
1037 } r;
1038 };
1039
1040 struct sfp_xcvr_fc1_code_s {
1041 u8 link_len:5;
1042 u8 xmtr_tech2:3;
1043 u8 xmtr_tech1:7;
1044 u8 reserved1:1;
1045 };
1046
1047 union sfp_xcvr_fc2_code_u {
1048 u8 b;
1049 struct {
1050 u8 tw_media:1;
1051 u8 tp_media:1;
1052 u8 mi_media:1;
1053 u8 tv_media:1;
1054 u8 m6_media:1;
1055 u8 m5_media:1;
1056 u8 reserved:1;
1057 u8 sm_media:1;
1058 } r;
1059 };
1060
1061 union sfp_xcvr_fc3_code_u {
1062 u8 b;
1063 struct {
1064 #ifdef __BIG_ENDIAN
1065 u8 rsv4:1;
1066 u8 mb800:1;
1067 u8 mb1600:1;
1068 u8 mb400:1;
1069 u8 rsv2:1;
1070 u8 mb200:1;
1071 u8 rsv1:1;
1072 u8 mb100:1;
1073 #else
1074 u8 mb100:1;
1075 u8 rsv1:1;
1076 u8 mb200:1;
1077 u8 rsv2:1;
1078 u8 mb400:1;
1079 u8 mb1600:1;
1080 u8 mb800:1;
1081 u8 rsv4:1;
1082 #endif
1083 } r;
1084 };
1085
1086 struct sfp_xcvr_s {
1087 union sfp_xcvr_e10g_code_u e10g;
1088 union sfp_xcvr_so1_code_u so1;
1089 union sfp_xcvr_so2_code_u so2;
1090 union sfp_xcvr_eth_code_u eth;
1091 struct sfp_xcvr_fc1_code_s fc1;
1092 union sfp_xcvr_fc2_code_u fc2;
1093 union sfp_xcvr_fc3_code_u fc3;
1094 };
1095
1096
1097
1098
1099 #define BFA_FLASH_PART_ENTRY_SIZE 32
1100 #define BFA_FLASH_PART_MAX 32
1101
1102 enum bfa_flash_part_type {
1103 BFA_FLASH_PART_OPTROM = 1,
1104 BFA_FLASH_PART_FWIMG = 2,
1105 BFA_FLASH_PART_FWCFG = 3,
1106 BFA_FLASH_PART_DRV = 4,
1107 BFA_FLASH_PART_BOOT = 5,
1108 BFA_FLASH_PART_ASIC = 6,
1109 BFA_FLASH_PART_MFG = 7,
1110 BFA_FLASH_PART_OPTROM2 = 8,
1111 BFA_FLASH_PART_VPD = 9,
1112 BFA_FLASH_PART_PBC = 10,
1113 BFA_FLASH_PART_BOOTOVL = 11,
1114 BFA_FLASH_PART_LOG = 12,
1115 BFA_FLASH_PART_PXECFG = 13,
1116 BFA_FLASH_PART_PXEOVL = 14,
1117 BFA_FLASH_PART_PORTCFG = 15,
1118 BFA_FLASH_PART_ASICBK = 16,
1119 };
1120
1121
1122
1123
1124 struct bfa_flash_part_attr_s {
1125 u32 part_type;
1126 u32 part_instance;
1127 u32 part_off;
1128 u32 part_size;
1129 u32 part_len;
1130 u32 part_status;
1131 char rsv[BFA_FLASH_PART_ENTRY_SIZE - 24];
1132 };
1133
1134
1135
1136
1137 struct bfa_flash_attr_s {
1138 u32 status;
1139 u32 npart;
1140 struct bfa_flash_part_attr_s part[BFA_FLASH_PART_MAX];
1141 };
1142
1143
1144
1145
1146 #define LB_PATTERN_DEFAULT 0xB5B5B5B5
1147 #define QTEST_CNT_DEFAULT 10
1148 #define QTEST_PAT_DEFAULT LB_PATTERN_DEFAULT
1149 #define DPORT_ENABLE_LOOPCNT_DEFAULT (1024 * 1024)
1150
1151 struct bfa_diag_memtest_s {
1152 u8 algo;
1153 u8 rsvd[7];
1154 };
1155
1156 struct bfa_diag_memtest_result {
1157 u32 status;
1158 u32 addr;
1159 u32 exp;
1160 u32 act;
1161 u32 err_status;
1162 u32 err_status1;
1163 u32 err_addr;
1164 u8 algo;
1165 u8 rsv[3];
1166 };
1167
1168 struct bfa_diag_loopback_result_s {
1169 u32 numtxmfrm;
1170 u32 numosffrm;
1171 u32 numrcvfrm;
1172 u32 badfrminf;
1173 u32 badfrmnum;
1174 u8 status;
1175 u8 rsvd[3];
1176 };
1177
1178 enum bfa_diag_dport_test_status {
1179 DPORT_TEST_ST_IDLE = 0,
1180 DPORT_TEST_ST_FINAL = 1,
1181 DPORT_TEST_ST_SKIP = 2,
1182 DPORT_TEST_ST_FAIL = 3,
1183 DPORT_TEST_ST_INPRG = 4,
1184 DPORT_TEST_ST_RESPONDER = 5,
1185 DPORT_TEST_ST_STOPPED = 6,
1186 DPORT_TEST_ST_MAX
1187 };
1188
1189 enum bfa_diag_dport_test_type {
1190 DPORT_TEST_ELOOP = 0,
1191 DPORT_TEST_OLOOP = 1,
1192 DPORT_TEST_ROLOOP = 2,
1193 DPORT_TEST_LINK = 3,
1194 DPORT_TEST_MAX
1195 };
1196
1197 enum bfa_diag_dport_test_opmode {
1198 BFA_DPORT_OPMODE_AUTO = 0,
1199 BFA_DPORT_OPMODE_MANU = 1,
1200 };
1201
1202 struct bfa_diag_dport_subtest_result_s {
1203 u8 status;
1204 u8 rsvd[7];
1205 u64 start_time;
1206 };
1207
1208 struct bfa_diag_dport_result_s {
1209 wwn_t rp_pwwn;
1210 wwn_t rp_nwwn;
1211 u64 start_time;
1212 u64 end_time;
1213 u8 status;
1214 u8 mode;
1215 u8 rsvd;
1216 u8 speed;
1217 u16 buffer_required;
1218 u16 frmsz;
1219 u32 lpcnt;
1220 u32 pat;
1221 u32 roundtrip_latency;
1222 u32 est_cable_distance;
1223 struct bfa_diag_dport_subtest_result_s subtest[DPORT_TEST_MAX];
1224 };
1225
1226 struct bfa_diag_ledtest_s {
1227 u32 cmd;
1228 u32 color;
1229 u16 freq;
1230 u8 led;
1231 u8 rsvd[5];
1232 };
1233
1234 struct bfa_diag_loopback_s {
1235 u32 loopcnt;
1236 u32 pattern;
1237 u8 lb_mode;
1238 u8 speed;
1239 u8 rsvd[2];
1240 };
1241
1242
1243
1244
1245 enum bfa_phy_status_e {
1246 BFA_PHY_STATUS_GOOD = 0,
1247 BFA_PHY_STATUS_NOT_PRESENT = 1,
1248 BFA_PHY_STATUS_BAD = 2,
1249 };
1250
1251
1252
1253
1254 struct bfa_phy_attr_s {
1255 u32 status;
1256 u32 length;
1257 u32 fw_ver;
1258 u32 an_status;
1259 u32 pma_pmd_status;
1260 u32 pma_pmd_signal;
1261 u32 pcs_status;
1262 };
1263
1264
1265
1266
1267 struct bfa_phy_stats_s {
1268 u32 status;
1269 u32 link_breaks;
1270 u32 pma_pmd_fault;
1271 u32 pcs_fault;
1272 u32 speed_neg;
1273 u32 tx_eq_training;
1274 u32 tx_eq_timeout;
1275 u32 crc_error;
1276 };
1277
1278 #pragma pack()
1279
1280 #endif