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11 #ifndef _MEGARAID_H_
12 #define _MEGARAID_H_
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15 #include "mega_common.h"
16 #include "mbox_defs.h"
17 #include "megaraid_ioctl.h"
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20 #define MEGARAID_VERSION "2.20.5.1"
21 #define MEGARAID_EXT_VERSION "(Release Date: Thu Nov 16 15:32:35 EST 2006)"
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27 #define PCI_DEVICE_ID_PERC4_DI_DISCOVERY 0x000E
28 #define PCI_SUBSYS_ID_PERC4_DI_DISCOVERY 0x0123
29
30 #define PCI_DEVICE_ID_PERC4_SC 0x1960
31 #define PCI_SUBSYS_ID_PERC4_SC 0x0520
32
33 #define PCI_DEVICE_ID_PERC4_DC 0x1960
34 #define PCI_SUBSYS_ID_PERC4_DC 0x0518
35
36 #define PCI_DEVICE_ID_VERDE 0x0407
37
38 #define PCI_DEVICE_ID_PERC4_DI_EVERGLADES 0x000F
39 #define PCI_SUBSYS_ID_PERC4_DI_EVERGLADES 0x014A
40
41 #define PCI_DEVICE_ID_PERC4E_SI_BIGBEND 0x0013
42 #define PCI_SUBSYS_ID_PERC4E_SI_BIGBEND 0x016c
43
44 #define PCI_DEVICE_ID_PERC4E_DI_KOBUK 0x0013
45 #define PCI_SUBSYS_ID_PERC4E_DI_KOBUK 0x016d
46
47 #define PCI_DEVICE_ID_PERC4E_DI_CORVETTE 0x0013
48 #define PCI_SUBSYS_ID_PERC4E_DI_CORVETTE 0x016e
49
50 #define PCI_DEVICE_ID_PERC4E_DI_EXPEDITION 0x0013
51 #define PCI_SUBSYS_ID_PERC4E_DI_EXPEDITION 0x016f
52
53 #define PCI_DEVICE_ID_PERC4E_DI_GUADALUPE 0x0013
54 #define PCI_SUBSYS_ID_PERC4E_DI_GUADALUPE 0x0170
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56 #define PCI_DEVICE_ID_DOBSON 0x0408
57
58 #define PCI_DEVICE_ID_MEGARAID_SCSI_320_0 0x1960
59 #define PCI_SUBSYS_ID_MEGARAID_SCSI_320_0 0xA520
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61 #define PCI_DEVICE_ID_MEGARAID_SCSI_320_1 0x1960
62 #define PCI_SUBSYS_ID_MEGARAID_SCSI_320_1 0x0520
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64 #define PCI_DEVICE_ID_MEGARAID_SCSI_320_2 0x1960
65 #define PCI_SUBSYS_ID_MEGARAID_SCSI_320_2 0x0518
66
67 #define PCI_DEVICE_ID_MEGARAID_I4_133_RAID 0x1960
68 #define PCI_SUBSYS_ID_MEGARAID_I4_133_RAID 0x0522
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70 #define PCI_DEVICE_ID_MEGARAID_SATA_150_4 0x1960
71 #define PCI_SUBSYS_ID_MEGARAID_SATA_150_4 0x4523
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73 #define PCI_DEVICE_ID_MEGARAID_SATA_150_6 0x1960
74 #define PCI_SUBSYS_ID_MEGARAID_SATA_150_6 0x0523
75
76 #define PCI_DEVICE_ID_LINDSAY 0x0409
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78 #define PCI_DEVICE_ID_INTEL_RAID_SRCS16 0x1960
79 #define PCI_SUBSYS_ID_INTEL_RAID_SRCS16 0x0523
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81 #define PCI_DEVICE_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK 0x1960
82 #define PCI_SUBSYS_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK 0x0520
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84 #define PCI_SUBSYS_ID_PERC3_QC 0x0471
85 #define PCI_SUBSYS_ID_PERC3_DC 0x0493
86 #define PCI_SUBSYS_ID_PERC3_SC 0x0475
87 #define PCI_SUBSYS_ID_CERC_ATA100_4CH 0x0511
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90 #define MBOX_MAX_SCSI_CMDS 128
91 #define MBOX_MAX_USER_CMDS 32
92 #define MBOX_DEF_CMD_PER_LUN 64
93 #define MBOX_DEFAULT_SG_SIZE 26
94 #define MBOX_MAX_SG_SIZE 32
95 #define MBOX_MAX_SECTORS 128
96 #define MBOX_TIMEOUT 30
97 #define MBOX_BUSY_WAIT 10
98 #define MBOX_RESET_WAIT 180
99 #define MBOX_RESET_EXT_WAIT 120
100 #define MBOX_SYNC_WAIT_CNT 0xFFFF
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102 #define MBOX_SYNC_DELAY_200 200
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108 #define MBOX_IBUF_SIZE 4096
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128 typedef struct {
129 uint8_t *raw_mbox;
130 mbox_t *mbox;
131 mbox64_t *mbox64;
132 dma_addr_t mbox_dma_h;
133 mbox_sgl64 *sgl64;
134 mbox_sgl32 *sgl32;
135 dma_addr_t sgl_dma_h;
136 mraid_passthru_t *pthru;
137 dma_addr_t pthru_dma_h;
138 mraid_epassthru_t *epthru;
139 dma_addr_t epthru_dma_h;
140 dma_addr_t buf_dma_h;
141 } mbox_ccb_t;
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183 #define MAX_LD_EXTENDED64 64
184 typedef struct {
185 mbox64_t *una_mbox64;
186 dma_addr_t una_mbox64_dma;
187 mbox_t *mbox;
188 mbox64_t *mbox64;
189 dma_addr_t mbox_dma;
190 spinlock_t mailbox_lock;
191 unsigned long baseport;
192 void __iomem * baseaddr;
193 struct mraid_pci_blk mbox_pool[MBOX_MAX_SCSI_CMDS];
194 struct dma_pool *mbox_pool_handle;
195 struct mraid_pci_blk epthru_pool[MBOX_MAX_SCSI_CMDS];
196 struct dma_pool *epthru_pool_handle;
197 struct mraid_pci_blk sg_pool[MBOX_MAX_SCSI_CMDS];
198 struct dma_pool *sg_pool_handle;
199 mbox_ccb_t ccb_list[MBOX_MAX_SCSI_CMDS];
200 mbox_ccb_t uccb_list[MBOX_MAX_USER_CMDS];
201 mbox64_t umbox64[MBOX_MAX_USER_CMDS];
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203 uint8_t pdrv_state[MBOX_MAX_PHYSICAL_DRIVES];
204 uint32_t last_disp;
205 int hw_error;
206 int fast_load;
207 uint8_t channel_class;
208 struct mutex sysfs_mtx;
209 uioc_t *sysfs_uioc;
210 mbox64_t *sysfs_mbox64;
211 caddr_t sysfs_buffer;
212 dma_addr_t sysfs_buffer_dma;
213 wait_queue_head_t sysfs_wait_q;
214 int random_del_supported;
215 uint16_t curr_ldmap[MAX_LD_EXTENDED64];
216 } mraid_device_t;
217
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219 #define ADAP2RAIDDEV(adp) ((mraid_device_t *)((adp)->raid_device))
220
221 #define MAILBOX_LOCK(rdev) (&(rdev)->mailbox_lock)
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224 #define IS_RAID_CH(rdev, ch) (((rdev)->channel_class >> (ch)) & 0x01)
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227 #define RDINDOOR(rdev) readl((rdev)->baseaddr + 0x20)
228 #define RDOUTDOOR(rdev) readl((rdev)->baseaddr + 0x2C)
229 #define WRINDOOR(rdev, value) writel(value, (rdev)->baseaddr + 0x20)
230 #define WROUTDOOR(rdev, value) writel(value, (rdev)->baseaddr + 0x2C)
231
232 #endif
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