1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
4 * of PCI-SCSI IO processors.
5 *
6 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
7 *
8 * This driver is derived from the Linux sym53c8xx driver.
9 * Copyright (C) 1998-2000 Gerard Roudier
10 *
11 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
12 * a port of the FreeBSD ncr driver to Linux-1.2.13.
13 *
14 * The original ncr driver has been written for 386bsd and FreeBSD by
15 * Wolfgang Stanglmeier <wolf@cologne.de>
16 * Stefan Esser <se@mi.Uni-Koeln.de>
17 * Copyright (C) 1994 Wolfgang Stanglmeier
18 *
19 * Other major contributions:
20 *
21 * NVRAM detection and reading.
22 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
23 *
24 *-----------------------------------------------------------------------------
25 */
26
27 #ifndef SYM_DEFS_H
28 #define SYM_DEFS_H
29
30 #define SYM_VERSION "2.2.3"
31 #define SYM_DRIVER_NAME "sym-" SYM_VERSION
32
33 /*
34 * SYM53C8XX device features descriptor.
35 */
36 struct sym_chip {
37 u_short device_id;
38 u_short revision_id;
39 char *name;
40 u_char burst_max; /* log-base-2 of max burst */
41 u_char offset_max;
42 u_char nr_divisor;
43 u_char lp_probe_bit;
44 u_int features;
45 #define FE_LED0 (1<<0)
46 #define FE_WIDE (1<<1) /* Wide data transfers */
47 #define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
48 #define FE_ULTRA2 (1<<3) /* Ultra 2 - 40 Mtrans/sec */
49 #define FE_DBLR (1<<4) /* Clock doubler present */
50 #define FE_QUAD (1<<5) /* Clock quadrupler present */
51 #define FE_ERL (1<<6) /* Enable read line */
52 #define FE_CLSE (1<<7) /* Cache line size enable */
53 #define FE_WRIE (1<<8) /* Write & Invalidate enable */
54 #define FE_ERMP (1<<9) /* Enable read multiple */
55 #define FE_BOF (1<<10) /* Burst opcode fetch */
56 #define FE_DFS (1<<11) /* DMA fifo size */
57 #define FE_PFEN (1<<12) /* Prefetch enable */
58 #define FE_LDSTR (1<<13) /* Load/Store supported */
59 #define FE_RAM (1<<14) /* On chip RAM present */
60 #define FE_VARCLK (1<<15) /* Clock frequency may vary */
61 #define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
62 #define FE_64BIT (1<<17) /* 64-bit PCI BUS interface */
63 #define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
64 #define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
65 #define FE_LEDC (1<<20) /* Hardware control of LED */
66 #define FE_ULTRA3 (1<<21) /* Ultra 3 - 80 Mtrans/sec DT */
67 #define FE_66MHZ (1<<22) /* 66MHz PCI support */
68 #define FE_CRC (1<<23) /* CRC support */
69 #define FE_DIFF (1<<24) /* SCSI HVD support */
70 #define FE_DFBC (1<<25) /* Have DFBC register */
71 #define FE_LCKFRQ (1<<26) /* Have LCKFRQ */
72 #define FE_C10 (1<<27) /* Various C10 core (mis)features */
73 #define FE_U3EN (1<<28) /* U3EN bit usable */
74 #define FE_DAC (1<<29) /* Support PCI DAC (64 bit addressing) */
75 #define FE_ISTAT1 (1<<30) /* Have ISTAT1, MBOX0, MBOX1 registers */
76
77 #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
78 #define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL)
79 };
80
81 /*
82 * SYM53C8XX IO register data structure.
83 */
84 struct sym_reg {
85 /*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */
86
87 /*01*/ u8 nc_scntl1; /* no reset */
88 #define ISCON 0x10 /* connected to scsi */
89 #define CRST 0x08 /* force reset */
90 #define IARB 0x02 /* immediate arbitration */
91
92 /*02*/ u8 nc_scntl2; /* no disconnect expected */
93 #define SDU 0x80 /* cmd: disconnect will raise error */
94 #define CHM 0x40 /* sta: chained mode */
95 #define WSS 0x08 /* sta: wide scsi send [W]*/
96 #define WSR 0x01 /* sta: wide scsi received [W]*/
97
98 /*03*/ u8 nc_scntl3; /* cnf system clock dependent */
99 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
100 #define ULTRA 0x80 /* cmd: ULTRA enable */
101 /* bits 0-2, 7 rsvd for C1010 */
102
103 /*04*/ u8 nc_scid; /* cnf host adapter scsi address */
104 #define RRE 0x40 /* r/w:e enable response to resel. */
105 #define SRE 0x20 /* r/w:e enable response to select */
106
107 /*05*/ u8 nc_sxfer; /* ### Sync speed and count */
108 /* bits 6-7 rsvd for C1010 */
109
110 /*06*/ u8 nc_sdid; /* ### Destination-ID */
111
112 /*07*/ u8 nc_gpreg; /* ??? IO-Pins */
113
114 /*08*/ u8 nc_sfbr; /* ### First byte received */
115
116 /*09*/ u8 nc_socl;
117 #define CREQ 0x80 /* r/w: SCSI-REQ */
118 #define CACK 0x40 /* r/w: SCSI-ACK */
119 #define CBSY 0x20 /* r/w: SCSI-BSY */
120 #define CSEL 0x10 /* r/w: SCSI-SEL */
121 #define CATN 0x08 /* r/w: SCSI-ATN */
122 #define CMSG 0x04 /* r/w: SCSI-MSG */
123 #define CC_D 0x02 /* r/w: SCSI-C_D */
124 #define CI_O 0x01 /* r/w: SCSI-I_O */
125
126 /*0a*/ u8 nc_ssid;
127
128 /*0b*/ u8 nc_sbcl;
129
130 /*0c*/ u8 nc_dstat;
131 #define DFE 0x80 /* sta: dma fifo empty */
132 #define MDPE 0x40 /* int: master data parity error */
133 #define BF 0x20 /* int: script: bus fault */
134 #define ABRT 0x10 /* int: script: command aborted */
135 #define SSI 0x08 /* int: script: single step */
136 #define SIR 0x04 /* int: script: interrupt instruct. */
137 #define IID 0x01 /* int: script: illegal instruct. */
138
139 /*0d*/ u8 nc_sstat0;
140 #define ILF 0x80 /* sta: data in SIDL register lsb */
141 #define ORF 0x40 /* sta: data in SODR register lsb */
142 #define OLF 0x20 /* sta: data in SODL register lsb */
143 #define AIP 0x10 /* sta: arbitration in progress */
144 #define LOA 0x08 /* sta: arbitration lost */
145 #define WOA 0x04 /* sta: arbitration won */
146 #define IRST 0x02 /* sta: scsi reset signal */
147 #define SDP 0x01 /* sta: scsi parity signal */
148
149 /*0e*/ u8 nc_sstat1;
150 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
151
152 /*0f*/ u8 nc_sstat2;
153 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
154 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
155 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
156 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
157 #define LDSC 0x02 /* sta: disconnect & reconnect */
158
159 /*10*/ u8 nc_dsa; /* --> Base page */
160 /*11*/ u8 nc_dsa1;
161 /*12*/ u8 nc_dsa2;
162 /*13*/ u8 nc_dsa3;
163
164 /*14*/ u8 nc_istat; /* --> Main Command and status */
165 #define CABRT 0x80 /* cmd: abort current operation */
166 #define SRST 0x40 /* mod: reset chip */
167 #define SIGP 0x20 /* r/w: message from host to script */
168 #define SEM 0x10 /* r/w: message between host + script */
169 #define CON 0x08 /* sta: connected to scsi */
170 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
171 #define SIP 0x02 /* sta: scsi-interrupt */
172 #define DIP 0x01 /* sta: host/script interrupt */
173
174 /*15*/ u8 nc_istat1; /* 896 only */
175 #define FLSH 0x04 /* sta: chip is flushing */
176 #define SCRUN 0x02 /* sta: scripts are running */
177 #define SIRQD 0x01 /* r/w: disable INT pin */
178
179 /*16*/ u8 nc_mbox0; /* 896 only */
180 /*17*/ u8 nc_mbox1; /* 896 only */
181
182 /*18*/ u8 nc_ctest0;
183 /*19*/ u8 nc_ctest1;
184
185 /*1a*/ u8 nc_ctest2;
186 #define CSIGP 0x40
187 /* bits 0-2,7 rsvd for C1010 */
188
189 /*1b*/ u8 nc_ctest3;
190 #define FLF 0x08 /* cmd: flush dma fifo */
191 #define CLF 0x04 /* cmd: clear dma fifo */
192 #define FM 0x02 /* mod: fetch pin mode */
193 #define WRIE 0x01 /* mod: write and invalidate enable */
194 /* bits 4-7 rsvd for C1010 */
195
196 /*1c*/ u32 nc_temp; /* ### Temporary stack */
197
198 /*20*/ u8 nc_dfifo;
199 /*21*/ u8 nc_ctest4;
200 #define BDIS 0x80 /* mod: burst disable */
201 #define MPEE 0x08 /* mod: master parity error enable */
202
203 /*22*/ u8 nc_ctest5;
204 #define DFS 0x20 /* mod: dma fifo size */
205 /* bits 0-1, 3-7 rsvd for C1010 */
206
207 /*23*/ u8 nc_ctest6;
208
209 /*24*/ u32 nc_dbc; /* ### Byte count and command */
210 /*28*/ u32 nc_dnad; /* ### Next command register */
211 /*2c*/ u32 nc_dsp; /* --> Script Pointer */
212 /*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
213
214 /*34*/ u8 nc_scratcha; /* Temporary register a */
215 /*35*/ u8 nc_scratcha1;
216 /*36*/ u8 nc_scratcha2;
217 /*37*/ u8 nc_scratcha3;
218
219 /*38*/ u8 nc_dmode;
220 #define BL_2 0x80 /* mod: burst length shift value +2 */
221 #define BL_1 0x40 /* mod: burst length shift value +1 */
222 #define ERL 0x08 /* mod: enable read line */
223 #define ERMP 0x04 /* mod: enable read multiple */
224 #define BOF 0x02 /* mod: burst op code fetch */
225
226 /*39*/ u8 nc_dien;
227 /*3a*/ u8 nc_sbr;
228
229 /*3b*/ u8 nc_dcntl; /* --> Script execution control */
230 #define CLSE 0x80 /* mod: cache line size enable */
231 #define PFF 0x40 /* cmd: pre-fetch flush */
232 #define PFEN 0x20 /* mod: pre-fetch enable */
233 #define SSM 0x10 /* mod: single step mode */
234 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
235 #define STD 0x04 /* cmd: start dma mode */
236 #define IRQD 0x02 /* mod: irq disable */
237 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
238 /* bits 0-1 rsvd for C1010 */
239
240 /*3c*/ u32 nc_adder;
241
242 /*40*/ u16 nc_sien; /* -->: interrupt enable */
243 /*42*/ u16 nc_sist; /* <--: interrupt status */
244 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
245 #define STO 0x0400/* sta: timeout (select) */
246 #define GEN 0x0200/* sta: timeout (general) */
247 #define HTH 0x0100/* sta: timeout (handshake) */
248 #define MA 0x80 /* sta: phase mismatch */
249 #define CMP 0x40 /* sta: arbitration complete */
250 #define SEL 0x20 /* sta: selected by another device */
251 #define RSL 0x10 /* sta: reselected by another device*/
252 #define SGE 0x08 /* sta: gross error (over/underflow)*/
253 #define UDC 0x04 /* sta: unexpected disconnect */
254 #define RST 0x02 /* sta: scsi bus reset detected */
255 #define PAR 0x01 /* sta: scsi parity error */
256
257 /*44*/ u8 nc_slpar;
258 /*45*/ u8 nc_swide;
259 /*46*/ u8 nc_macntl;
260 /*47*/ u8 nc_gpcntl;
261 /*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/
262 /*49*/ u8 nc_stime1; /* cmd: timeout user defined */
263 /*4a*/ u16 nc_respid; /* sta: Reselect-IDs */
264
265 /*4c*/ u8 nc_stest0;
266
267 /*4d*/ u8 nc_stest1;
268 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
269 #define DBLEN 0x08 /* clock doubler running */
270 #define DBLSEL 0x04 /* clock doubler selected */
271
272
273 /*4e*/ u8 nc_stest2;
274 #define ROF 0x40 /* reset scsi offset (after gross error!) */
275 #define EXT 0x02 /* extended filtering */
276
277 /*4f*/ u8 nc_stest3;
278 #define TE 0x80 /* c: tolerAnt enable */
279 #define HSC 0x20 /* c: Halt SCSI Clock */
280 #define CSF 0x02 /* c: clear scsi fifo */
281
282 /*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */
283 /*52*/ u8 nc_stest4;
284 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
285 #define SMODE_HVD 0x40 /* High Voltage Differential */
286 #define SMODE_SE 0x80 /* Single Ended */
287 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
288 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
289 /* bits 0-5 rsvd for C1010 */
290
291 /*53*/ u8 nc_53_;
292 /*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */
293 /*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
294 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
295 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
296 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
297 #define DISFC 0x10 /* Disable Auto FIFO Clear */
298 #define DILS 0x02 /* Disable Internal Load/Store */
299 #define DPR 0x01 /* Disable Pipe Req */
300
301 /*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */
302 #define ZMOD 0x80 /* High Impedance Mode */
303 #define DDAC 0x08 /* Disable Dual Address Cycle */
304 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
305 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
306 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
307
308 /*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */
309 /*5a*/ u16 nc_5a_;
310
311 /*5c*/ u8 nc_scr0; /* Working register B */
312 /*5d*/ u8 nc_scr1;
313 /*5e*/ u8 nc_scr2;
314 /*5f*/ u8 nc_scr3;
315
316 /*60*/ u8 nc_scrx[64]; /* Working register C-R */
317 /*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
318 /*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
319 /*a8*/ u32 nc_sfs; /* Script Fetch Selector */
320 /*ac*/ u32 nc_drs; /* DSA Relative Selector */
321 /*b0*/ u32 nc_sbms; /* Static Block Move Selector */
322 /*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
323 /*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
324 /*bc*/ u16 nc_scntl4; /* C1010 only */
325 #define U3EN 0x80 /* Enable Ultra 3 */
326 #define AIPCKEN 0x40 /* AIP checking enable */
327 /* Also enable AIP generation on C10-33*/
328 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT edge */
329 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST edge */
330 #define XCLKS_DT 0x02 /* Extra clock of data set on DT edge */
331 #define XCLKS_ST 0x01 /* Extra clock of data set on ST edge */
332 /*be*/ u8 nc_aipcntl0; /* AIP Control 0 C1010 only */
333 /*bf*/ u8 nc_aipcntl1; /* AIP Control 1 C1010 only */
334 #define DISAIP 0x08 /* Disable AIP generation C10-66 only */
335 /*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
336 /*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
337 /*c8*/ u8 nc_rbc; /* Remaining Byte Count */
338 /*c9*/ u8 nc_rbc1;
339 /*ca*/ u8 nc_rbc2;
340 /*cb*/ u8 nc_rbc3;
341
342 /*cc*/ u8 nc_ua; /* Updated Address */
343 /*cd*/ u8 nc_ua1;
344 /*ce*/ u8 nc_ua2;
345 /*cf*/ u8 nc_ua3;
346 /*d0*/ u32 nc_esa; /* Entry Storage Address */
347 /*d4*/ u8 nc_ia; /* Instruction Address */
348 /*d5*/ u8 nc_ia1;
349 /*d6*/ u8 nc_ia2;
350 /*d7*/ u8 nc_ia3;
351 /*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
352 /*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
353 /* Following for C1010 only */
354 /*e0*/ u16 nc_crcpad; /* CRC Value */
355 /*e2*/ u8 nc_crccntl0; /* CRC control register */
356 #define SNDCRC 0x10 /* Send CRC Request */
357 /*e3*/ u8 nc_crccntl1; /* CRC control register */
358 /*e4*/ u32 nc_crcdata; /* CRC data register */
359 /*e8*/ u32 nc_e8_;
360 /*ec*/ u32 nc_ec_;
361 /*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */
362 };
363
364 /*-----------------------------------------------------------
365 *
366 * Utility macros for the script.
367 *
368 *-----------------------------------------------------------
369 */
370
371 #define REGJ(p,r) (offsetof(struct sym_reg, p ## r))
372 #define REG(r) REGJ (nc_, r)
373
374 /*-----------------------------------------------------------
375 *
376 * SCSI phases
377 *
378 *-----------------------------------------------------------
379 */
380
381 #define SCR_DATA_OUT 0x00000000
382 #define SCR_DATA_IN 0x01000000
383 #define SCR_COMMAND 0x02000000
384 #define SCR_STATUS 0x03000000
385 #define SCR_DT_DATA_OUT 0x04000000
386 #define SCR_DT_DATA_IN 0x05000000
387 #define SCR_MSG_OUT 0x06000000
388 #define SCR_MSG_IN 0x07000000
389 /* DT phases are illegal for non Ultra3 mode */
390 #define SCR_ILG_OUT 0x04000000
391 #define SCR_ILG_IN 0x05000000
392
393 /*-----------------------------------------------------------
394 *
395 * Data transfer via SCSI.
396 *
397 *-----------------------------------------------------------
398 *
399 * MOVE_ABS (LEN)
400 * <<start address>>
401 *
402 * MOVE_IND (LEN)
403 * <<dnad_offset>>
404 *
405 * MOVE_TBL
406 * <<dnad_offset>>
407 *
408 *-----------------------------------------------------------
409 */
410
411 #define OPC_MOVE 0x08000000
412
413 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
414 /* #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) */
415 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
416
417 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
418 /* #define SCR_CHMOV_IND(l) ((0x20000000) | (l)) */
419 #define SCR_CHMOV_TBL (0x10000000)
420
421 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
422 /* We steal the `indirect addressing' flag for target mode MOVE in scripts */
423
424 #define OPC_TCHMOVE 0x08000000
425
426 #define SCR_TCHMOVE_ABS(l) ((0x20000000 | OPC_TCHMOVE) | (l))
427 #define SCR_TCHMOVE_TBL (0x30000000 | OPC_TCHMOVE)
428
429 #define SCR_TMOV_ABS(l) ((0x20000000) | (l))
430 #define SCR_TMOV_TBL (0x30000000)
431 #endif
432
433 struct sym_tblmove {
434 u32 size;
435 u32 addr;
436 };
437
438 /*-----------------------------------------------------------
439 *
440 * Selection
441 *
442 *-----------------------------------------------------------
443 *
444 * SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
445 * <<alternate_address>>
446 *
447 * SEL_TBL | << dnad_offset>> [ | REL_JMP]
448 * <<alternate_address>>
449 *
450 *-----------------------------------------------------------
451 */
452
453 #define SCR_SEL_ABS 0x40000000
454 #define SCR_SEL_ABS_ATN 0x41000000
455 #define SCR_SEL_TBL 0x42000000
456 #define SCR_SEL_TBL_ATN 0x43000000
457
458 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
459 #define SCR_RESEL_ABS 0x40000000
460 #define SCR_RESEL_ABS_ATN 0x41000000
461 #define SCR_RESEL_TBL 0x42000000
462 #define SCR_RESEL_TBL_ATN 0x43000000
463 #endif
464
465 struct sym_tblsel {
466 u_char sel_scntl4; /* C1010 only */
467 u_char sel_sxfer;
468 u_char sel_id;
469 u_char sel_scntl3;
470 };
471
472 #define SCR_JMP_REL 0x04000000
473 #define SCR_ID(id) (((u32)(id)) << 16)
474
475 /*-----------------------------------------------------------
476 *
477 * Waiting for Disconnect or Reselect
478 *
479 *-----------------------------------------------------------
480 *
481 * WAIT_DISC
482 * dummy: <<alternate_address>>
483 *
484 * WAIT_RESEL
485 * <<alternate_address>>
486 *
487 *-----------------------------------------------------------
488 */
489
490 #define SCR_WAIT_DISC 0x48000000
491 #define SCR_WAIT_RESEL 0x50000000
492
493 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
494 #define SCR_DISCONNECT 0x48000000
495 #endif
496
497 /*-----------------------------------------------------------
498 *
499 * Bit Set / Reset
500 *
501 *-----------------------------------------------------------
502 *
503 * SET (flags {|.. })
504 *
505 * CLR (flags {|.. })
506 *
507 *-----------------------------------------------------------
508 */
509
510 #define SCR_SET(f) (0x58000000 | (f))
511 #define SCR_CLR(f) (0x60000000 | (f))
512
513 #define SCR_CARRY 0x00000400
514 #define SCR_TRG 0x00000200
515 #define SCR_ACK 0x00000040
516 #define SCR_ATN 0x00000008
517
518
519 /*-----------------------------------------------------------
520 *
521 * Memory to memory move
522 *
523 *-----------------------------------------------------------
524 *
525 * COPY (bytecount)
526 * << source_address >>
527 * << destination_address >>
528 *
529 * SCR_COPY sets the NO FLUSH option by default.
530 * SCR_COPY_F does not set this option.
531 *
532 * For chips which do not support this option,
533 * sym_fw_bind_script() will remove this bit.
534 *
535 *-----------------------------------------------------------
536 */
537
538 #define SCR_NO_FLUSH 0x01000000
539
540 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
541 #define SCR_COPY_F(n) (0xc0000000 | (n))
542
543 /*-----------------------------------------------------------
544 *
545 * Register move and binary operations
546 *
547 *-----------------------------------------------------------
548 *
549 * SFBR_REG (reg, op, data) reg = SFBR op data
550 * << 0 >>
551 *
552 * REG_SFBR (reg, op, data) SFBR = reg op data
553 * << 0 >>
554 *
555 * REG_REG (reg, op, data) reg = reg op data
556 * << 0 >>
557 *
558 *-----------------------------------------------------------
559 *
560 * On 825A, 875, 895 and 896 chips the content
561 * of SFBR register can be used as data (SCR_SFBR_DATA).
562 * The 896 has additionnal IO registers starting at
563 * offset 0x80. Bit 7 of register offset is stored in
564 * bit 7 of the SCRIPTS instruction first DWORD.
565 *
566 *-----------------------------------------------------------
567 */
568
569 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
570
571 #define SCR_SFBR_REG(reg,op,data) \
572 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
573
574 #define SCR_REG_SFBR(reg,op,data) \
575 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
576
577 #define SCR_REG_REG(reg,op,data) \
578 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
579
580
581 #define SCR_LOAD 0x00000000
582 #define SCR_SHL 0x01000000
583 #define SCR_OR 0x02000000
584 #define SCR_XOR 0x03000000
585 #define SCR_AND 0x04000000
586 #define SCR_SHR 0x05000000
587 #define SCR_ADD 0x06000000
588 #define SCR_ADDC 0x07000000
589
590 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
591
592 /*-----------------------------------------------------------
593 *
594 * FROM_REG (reg) SFBR = reg
595 * << 0 >>
596 *
597 * TO_REG (reg) reg = SFBR
598 * << 0 >>
599 *
600 * LOAD_REG (reg, data) reg = <data>
601 * << 0 >>
602 *
603 * LOAD_SFBR(data) SFBR = <data>
604 * << 0 >>
605 *
606 *-----------------------------------------------------------
607 */
608
609 #define SCR_FROM_REG(reg) \
610 SCR_REG_SFBR(reg,SCR_OR,0)
611
612 #define SCR_TO_REG(reg) \
613 SCR_SFBR_REG(reg,SCR_OR,0)
614
615 #define SCR_LOAD_REG(reg,data) \
616 SCR_REG_REG(reg,SCR_LOAD,data)
617
618 #define SCR_LOAD_SFBR(data) \
619 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
620
621 /*-----------------------------------------------------------
622 *
623 * LOAD from memory to register.
624 * STORE from register to memory.
625 *
626 * Only supported by 810A, 860, 825A, 875, 895 and 896.
627 *
628 *-----------------------------------------------------------
629 *
630 * LOAD_ABS (LEN)
631 * <<start address>>
632 *
633 * LOAD_REL (LEN) (DSA relative)
634 * <<dsa_offset>>
635 *
636 *-----------------------------------------------------------
637 */
638
639 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
640 #define SCR_NO_FLUSH2 0x02000000
641 #define SCR_DSA_REL2 0x10000000
642
643 #define SCR_LOAD_R(reg, how, n) \
644 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
645
646 #define SCR_STORE_R(reg, how, n) \
647 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
648
649 #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
650 #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
651 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
652 #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
653
654 #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
655 #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
656 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
657 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
658
659
660 /*-----------------------------------------------------------
661 *
662 * Waiting for Disconnect or Reselect
663 *
664 *-----------------------------------------------------------
665 *
666 * JUMP [ | IFTRUE/IFFALSE ( ... ) ]
667 * <<address>>
668 *
669 * JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
670 * <<distance>>
671 *
672 * CALL [ | IFTRUE/IFFALSE ( ... ) ]
673 * <<address>>
674 *
675 * CALLR [ | IFTRUE/IFFALSE ( ... ) ]
676 * <<distance>>
677 *
678 * RETURN [ | IFTRUE/IFFALSE ( ... ) ]
679 * <<dummy>>
680 *
681 * INT [ | IFTRUE/IFFALSE ( ... ) ]
682 * <<ident>>
683 *
684 * INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
685 * <<ident>>
686 *
687 * Conditions:
688 * WHEN (phase)
689 * IF (phase)
690 * CARRYSET
691 * DATA (data, mask)
692 *
693 *-----------------------------------------------------------
694 */
695
696 #define SCR_NO_OP 0x80000000
697 #define SCR_JUMP 0x80080000
698 #define SCR_JUMP64 0x80480000
699 #define SCR_JUMPR 0x80880000
700 #define SCR_CALL 0x88080000
701 #define SCR_CALLR 0x88880000
702 #define SCR_RETURN 0x90080000
703 #define SCR_INT 0x98080000
704 #define SCR_INT_FLY 0x98180000
705
706 #define IFFALSE(arg) (0x00080000 | (arg))
707 #define IFTRUE(arg) (0x00000000 | (arg))
708
709 #define WHEN(phase) (0x00030000 | (phase))
710 #define IF(phase) (0x00020000 | (phase))
711
712 #define DATA(D) (0x00040000 | ((D) & 0xff))
713 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
714
715 #define CARRYSET (0x00200000)
716
717 /*-----------------------------------------------------------
718 *
719 * SCSI constants.
720 *
721 *-----------------------------------------------------------
722 */
723
724 /*
725 * Messages
726 */
727
728 #define M_COMPLETE COMMAND_COMPLETE
729 #define M_EXTENDED EXTENDED_MESSAGE
730 #define M_SAVE_DP SAVE_POINTERS
731 #define M_RESTORE_DP RESTORE_POINTERS
732 #define M_DISCONNECT DISCONNECT
733 #define M_ID_ERROR INITIATOR_ERROR
734 #define M_ABORT ABORT_TASK_SET
735 #define M_REJECT MESSAGE_REJECT
736 #define M_NOOP NOP
737 #define M_PARITY MSG_PARITY_ERROR
738 #define M_LCOMPLETE LINKED_CMD_COMPLETE
739 #define M_FCOMPLETE LINKED_FLG_CMD_COMPLETE
740 #define M_RESET TARGET_RESET
741 #define M_ABORT_TAG ABORT_TASK
742 #define M_CLEAR_QUEUE CLEAR_TASK_SET
743 #define M_INIT_REC INITIATE_RECOVERY
744 #define M_REL_REC RELEASE_RECOVERY
745 #define M_TERMINATE (0x11)
746 #define M_SIMPLE_TAG SIMPLE_QUEUE_TAG
747 #define M_HEAD_TAG HEAD_OF_QUEUE_TAG
748 #define M_ORDERED_TAG ORDERED_QUEUE_TAG
749 #define M_IGN_RESIDUE IGNORE_WIDE_RESIDUE
750
751 #define M_X_MODIFY_DP EXTENDED_MODIFY_DATA_POINTER
752 #define M_X_SYNC_REQ EXTENDED_SDTR
753 #define M_X_WIDE_REQ EXTENDED_WDTR
754 #define M_X_PPR_REQ EXTENDED_PPR
755
756 /*
757 * PPR protocol options
758 */
759 #define PPR_OPT_IU (0x01)
760 #define PPR_OPT_DT (0x02)
761 #define PPR_OPT_QAS (0x04)
762 #define PPR_OPT_MASK (0x07)
763
764 /*
765 * Status
766 */
767
768 #define S_GOOD SAM_STAT_GOOD
769 #define S_CHECK_COND SAM_STAT_CHECK_CONDITION
770 #define S_COND_MET SAM_STAT_CONDITION_MET
771 #define S_BUSY SAM_STAT_BUSY
772 #define S_INT SAM_STAT_INTERMEDIATE
773 #define S_INT_COND_MET SAM_STAT_INTERMEDIATE_CONDITION_MET
774 #define S_CONFLICT SAM_STAT_RESERVATION_CONFLICT
775 #define S_TERMINATED SAM_STAT_COMMAND_TERMINATED
776 #define S_QUEUE_FULL SAM_STAT_TASK_SET_FULL
777 #define S_ILLEGAL (0xff)
778
779 #endif /* defined SYM_DEFS_H */