1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * CXL Flash Device Driver
4 *
5 * Written by: Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
6 * Uma Krishnan <ukrishn@linux.vnet.ibm.com>, IBM Corporation
7 *
8 * Copyright (C) 2018 IBM Corporation
9 */
10
11 #define OCXL_MAX_IRQS 4 /* Max interrupts per process */
12
13 struct ocxlflash_irqs {
14 int hwirq;
15 u32 virq;
16 u64 ptrig;
17 void __iomem *vtrig;
18 };
19
20 /* OCXL hardware AFU associated with the host */
21 struct ocxl_hw_afu {
22 struct ocxlflash_context *ocxl_ctx; /* Host context */
23 struct pci_dev *pdev; /* PCI device */
24 struct device *dev; /* Generic device */
25 bool perst_same_image; /* Same image loaded on perst */
26
27 struct ocxl_fn_config fcfg; /* DVSEC config of the function */
28 struct ocxl_afu_config acfg; /* AFU configuration data */
29
30 int fn_actag_base; /* Function acTag base */
31 int fn_actag_enabled; /* Function acTag number enabled */
32 int afu_actag_base; /* AFU acTag base */
33 int afu_actag_enabled; /* AFU acTag number enabled */
34
35 phys_addr_t ppmmio_phys; /* Per process MMIO space */
36 phys_addr_t gmmio_phys; /* Global AFU MMIO space */
37 void __iomem *gmmio_virt; /* Global MMIO map */
38
39 void *link_token; /* Link token for the SPA */
40 struct idr idr; /* IDR to manage contexts */
41 int max_pasid; /* Maximum number of contexts */
42 bool is_present; /* Function has AFUs defined */
43 };
44
45 enum ocxlflash_ctx_state {
46 CLOSED,
47 OPENED,
48 STARTED
49 };
50
51 struct ocxlflash_context {
52 struct ocxl_hw_afu *hw_afu; /* HW AFU back pointer */
53 struct address_space *mapping; /* Mapping for pseudo filesystem */
54 bool master; /* Whether this is a master context */
55 int pe; /* Process element */
56
57 phys_addr_t psn_phys; /* Process mapping */
58 u64 psn_size; /* Process mapping size */
59
60 spinlock_t slock; /* Protects irq/fault/event updates */
61 wait_queue_head_t wq; /* Wait queue for poll and interrupts */
62 struct mutex state_mutex; /* Mutex to update context state */
63 enum ocxlflash_ctx_state state; /* Context state */
64
65 struct ocxlflash_irqs *irqs; /* Pointer to array of structures */
66 int num_irqs; /* Number of interrupts */
67 bool pending_irq; /* Pending interrupt on the context */
68 ulong irq_bitmap; /* Bits indicating pending irq num */
69
70 u64 fault_addr; /* Address that triggered the fault */
71 u64 fault_dsisr; /* Value of dsisr register at fault */
72 bool pending_fault; /* Pending translation fault */
73 };