1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * mesh.h: definitions for the driver for the MESH SCSI bus adaptor
4 * (Macintosh Enhanced SCSI Hardware) found on Power Macintosh computers.
5 *
6 * Copyright (C) 1996 Paul Mackerras.
7 */
8 #ifndef _MESH_H
9 #define _MESH_H
10
11 /*
12 * Registers in the MESH controller.
13 */
14
15 struct mesh_regs {
16 unsigned char count_lo;
17 char pad0[15];
18 unsigned char count_hi;
19 char pad1[15];
20 unsigned char fifo;
21 char pad2[15];
22 unsigned char sequence;
23 char pad3[15];
24 unsigned char bus_status0;
25 char pad4[15];
26 unsigned char bus_status1;
27 char pad5[15];
28 unsigned char fifo_count;
29 char pad6[15];
30 unsigned char exception;
31 char pad7[15];
32 unsigned char error;
33 char pad8[15];
34 unsigned char intr_mask;
35 char pad9[15];
36 unsigned char interrupt;
37 char pad10[15];
38 unsigned char source_id;
39 char pad11[15];
40 unsigned char dest_id;
41 char pad12[15];
42 unsigned char sync_params;
43 char pad13[15];
44 unsigned char mesh_id;
45 char pad14[15];
46 unsigned char sel_timeout;
47 char pad15[15];
48 };
49
50 /* Bits in the sequence register. */
51 #define SEQ_DMA_MODE 0x80 /* use DMA for data transfer */
52 #define SEQ_TARGET 0x40 /* put the controller into target mode */
53 #define SEQ_ATN 0x20 /* assert ATN signal */
54 #define SEQ_ACTIVE_NEG 0x10 /* use active negation on REQ/ACK */
55 #define SEQ_CMD 0x0f /* command bits: */
56 #define SEQ_ARBITRATE 1 /* get the bus */
57 #define SEQ_SELECT 2 /* select a target */
58 #define SEQ_COMMAND 3 /* send a command */
59 #define SEQ_STATUS 4 /* receive status */
60 #define SEQ_DATAOUT 5 /* send data */
61 #define SEQ_DATAIN 6 /* receive data */
62 #define SEQ_MSGOUT 7 /* send a message */
63 #define SEQ_MSGIN 8 /* receive a message */
64 #define SEQ_BUSFREE 9 /* look for bus free */
65 #define SEQ_ENBPARITY 0x0a /* enable parity checking */
66 #define SEQ_DISPARITY 0x0b /* disable parity checking */
67 #define SEQ_ENBRESEL 0x0c /* enable reselection */
68 #define SEQ_DISRESEL 0x0d /* disable reselection */
69 #define SEQ_RESETMESH 0x0e /* reset the controller */
70 #define SEQ_FLUSHFIFO 0x0f /* clear out the FIFO */
71
72 /* Bits in the bus_status0 and bus_status1 registers:
73 these correspond directly to the SCSI bus control signals. */
74 #define BS0_REQ 0x20
75 #define BS0_ACK 0x10
76 #define BS0_ATN 0x08
77 #define BS0_MSG 0x04
78 #define BS0_CD 0x02
79 #define BS0_IO 0x01
80 #define BS1_RST 0x80
81 #define BS1_BSY 0x40
82 #define BS1_SEL 0x20
83
84 /* Bus phases defined by the bits in bus_status0 */
85 #define BS0_PHASE (BS0_MSG+BS0_CD+BS0_IO)
86 #define BP_DATAOUT 0
87 #define BP_DATAIN BS0_IO
88 #define BP_COMMAND BS0_CD
89 #define BP_STATUS (BS0_CD+BS0_IO)
90 #define BP_MSGOUT (BS0_MSG+BS0_CD)
91 #define BP_MSGIN (BS0_MSG+BS0_CD+BS0_IO)
92
93 /* Bits in the exception register. */
94 #define EXC_SELWATN 0x20 /* (as target) we were selected with ATN */
95 #define EXC_SELECTED 0x10 /* (as target) we were selected w/o ATN */
96 #define EXC_RESELECTED 0x08 /* (as initiator) we were reselected */
97 #define EXC_ARBLOST 0x04 /* we lost arbitration */
98 #define EXC_PHASEMM 0x02 /* SCSI phase mismatch */
99 #define EXC_SELTO 0x01 /* selection timeout */
100
101 /* Bits in the error register */
102 #define ERR_UNEXPDISC 0x40 /* target unexpectedly disconnected */
103 #define ERR_SCSIRESET 0x20 /* SCSI bus got reset on us */
104 #define ERR_SEQERR 0x10 /* we did something the chip didn't like */
105 #define ERR_PARITY 0x01 /* parity error was detected */
106
107 /* Bits in the interrupt and intr_mask registers */
108 #define INT_ERROR 0x04 /* error interrupt */
109 #define INT_EXCEPTION 0x02 /* exception interrupt */
110 #define INT_CMDDONE 0x01 /* command done interrupt */
111
112 /* Fields in the sync_params register */
113 #define SYNC_OFF(x) ((x) >> 4) /* offset field */
114 #define SYNC_PER(x) ((x) & 0xf) /* period field */
115 #define SYNC_PARAMS(o, p) (((o) << 4) | (p))
116 #define ASYNC_PARAMS 2 /* sync_params value for async xfers */
117
118 /*
119 * Assuming a clock frequency of 50MHz:
120 *
121 * The transfer period with SYNC_PER(sync_params) == x
122 * is (x + 2) * 40ns, except that x == 0 gives 100ns.
123 *
124 * The units of the sel_timeout register are 10ms.
125 */
126
127
128 #endif /* _MESH_H */