arch/ia64/mm/tlb.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
mmu_context_init
wrap_mmu_context
spinaphore_init
down_spin
up_spin
set_nptcg
setup_ptcg_sem
ia64_global_tlb_purge
local_flush_tlb_all
__flush_tlb_range
flush_tlb_range
ia64_tlb_init
is_tr_overlap
ia64_itr_entry
ia64_ptr_entry
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * TLB support routines.
   4  *
   5  * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  *
   8  * 08/02/00 A. Mallick <asit.k.mallick@intel.com>
   9  *              Modified RID allocation for SMP
  10  *          Goutham Rao <goutham.rao@intel.com>
  11  *              IPI based ptc implementation and A-step IPI implementation.
  12  * Rohit Seth <rohit.seth@intel.com>
  13  * Ken Chen <kenneth.w.chen@intel.com>
  14  * Christophe de Dinechin <ddd@hp.com>: Avoid ptc.e on memory allocation
  15  * Copyright (C) 2007 Intel Corp
  16  *      Fenghua Yu <fenghua.yu@intel.com>
  17  *      Add multiple ptc.g/ptc.ga instruction support in global tlb purge.
  18  */
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/sched.h>
  23 #include <linux/smp.h>
  24 #include <linux/mm.h>
  25 #include <linux/memblock.h>
  26 #include <linux/slab.h>
  27 
  28 #include <asm/delay.h>
  29 #include <asm/mmu_context.h>
  30 #include <asm/pgalloc.h>
  31 #include <asm/pal.h>
  32 #include <asm/tlbflush.h>
  33 #include <asm/dma.h>
  34 #include <asm/processor.h>
  35 #include <asm/sal.h>
  36 #include <asm/tlb.h>
  37 
  38 static struct {
  39         u64 mask;               /* mask of supported purge page-sizes */
  40         unsigned long max_bits; /* log2 of largest supported purge page-size */
  41 } purge;
  42 
  43 struct ia64_ctx ia64_ctx = {
  44         .lock = __SPIN_LOCK_UNLOCKED(ia64_ctx.lock),
  45         .next = 1,
  46         .max_ctx = ~0U
  47 };
  48 
  49 DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
  50 DEFINE_PER_CPU(u8, ia64_tr_num);  /*Number of TR slots in current processor*/
  51 DEFINE_PER_CPU(u8, ia64_tr_used); /*Max Slot number used by kernel*/
  52 
  53 struct ia64_tr_entry *ia64_idtrs[NR_CPUS];
  54 
  55 /*
  56  * Initializes the ia64_ctx.bitmap array based on max_ctx+1.
  57  * Called after cpu_init() has setup ia64_ctx.max_ctx based on
  58  * maximum RID that is supported by boot CPU.
  59  */
  60 void __init
  61 mmu_context_init (void)
  62 {
  63         ia64_ctx.bitmap = memblock_alloc((ia64_ctx.max_ctx + 1) >> 3,
  64                                          SMP_CACHE_BYTES);
  65         if (!ia64_ctx.bitmap)
  66                 panic("%s: Failed to allocate %u bytes\n", __func__,
  67                       (ia64_ctx.max_ctx + 1) >> 3);
  68         ia64_ctx.flushmap = memblock_alloc((ia64_ctx.max_ctx + 1) >> 3,
  69                                            SMP_CACHE_BYTES);
  70         if (!ia64_ctx.flushmap)
  71                 panic("%s: Failed to allocate %u bytes\n", __func__,
  72                       (ia64_ctx.max_ctx + 1) >> 3);
  73 }
  74 
  75 /*
  76  * Acquire the ia64_ctx.lock before calling this function!
  77  */
  78 void
  79 wrap_mmu_context (struct mm_struct *mm)
  80 {
  81         int i, cpu;
  82         unsigned long flush_bit;
  83 
  84         for (i=0; i <= ia64_ctx.max_ctx / BITS_PER_LONG; i++) {
  85                 flush_bit = xchg(&ia64_ctx.flushmap[i], 0);
  86                 ia64_ctx.bitmap[i] ^= flush_bit;
  87         }
  88  
  89         /* use offset at 300 to skip daemons */
  90         ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
  91                                 ia64_ctx.max_ctx, 300);
  92         ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
  93                                 ia64_ctx.max_ctx, ia64_ctx.next);
  94 
  95         /*
  96          * can't call flush_tlb_all() here because of race condition
  97          * with O(1) scheduler [EF]
  98          */
  99         cpu = get_cpu(); /* prevent preemption/migration */
 100         for_each_online_cpu(i)
 101                 if (i != cpu)
 102                         per_cpu(ia64_need_tlb_flush, i) = 1;
 103         put_cpu();
 104         local_flush_tlb_all();
 105 }
 106 
 107 /*
 108  * Implement "spinaphores" ... like counting semaphores, but they
 109  * spin instead of sleeping.  If there are ever any other users for
 110  * this primitive it can be moved up to a spinaphore.h header.
 111  */
 112 struct spinaphore {
 113         unsigned long   ticket;
 114         unsigned long   serve;
 115 };
 116 
 117 static inline void spinaphore_init(struct spinaphore *ss, int val)
 118 {
 119         ss->ticket = 0;
 120         ss->serve = val;
 121 }
 122 
 123 static inline void down_spin(struct spinaphore *ss)
 124 {
 125         unsigned long t = ia64_fetchadd(1, &ss->ticket, acq), serve;
 126 
 127         if (time_before(t, ss->serve))
 128                 return;
 129 
 130         ia64_invala();
 131 
 132         for (;;) {
 133                 asm volatile ("ld8.c.nc %0=[%1]" : "=r"(serve) : "r"(&ss->serve) : "memory");
 134                 if (time_before(t, serve))
 135                         return;
 136                 cpu_relax();
 137         }
 138 }
 139 
 140 static inline void up_spin(struct spinaphore *ss)
 141 {
 142         ia64_fetchadd(1, &ss->serve, rel);
 143 }
 144 
 145 static struct spinaphore ptcg_sem;
 146 static u16 nptcg = 1;
 147 static int need_ptcg_sem = 1;
 148 static int toolatetochangeptcgsem = 0;
 149 
 150 /*
 151  * Kernel parameter "nptcg=" overrides max number of concurrent global TLB
 152  * purges which is reported from either PAL or SAL PALO.
 153  *
 154  * We don't have sanity checking for nptcg value. It's the user's responsibility
 155  * for valid nptcg value on the platform. Otherwise, kernel may hang in some
 156  * cases.
 157  */
 158 static int __init
 159 set_nptcg(char *str)
 160 {
 161         int value = 0;
 162 
 163         get_option(&str, &value);
 164         setup_ptcg_sem(value, NPTCG_FROM_KERNEL_PARAMETER);
 165 
 166         return 1;
 167 }
 168 
 169 __setup("nptcg=", set_nptcg);
 170 
 171 /*
 172  * Maximum number of simultaneous ptc.g purges in the system can
 173  * be defined by PAL_VM_SUMMARY (in which case we should take
 174  * the smallest value for any cpu in the system) or by the PAL
 175  * override table (in which case we should ignore the value from
 176  * PAL_VM_SUMMARY).
 177  *
 178  * Kernel parameter "nptcg=" overrides maximum number of simultanesous ptc.g
 179  * purges defined in either PAL_VM_SUMMARY or PAL override table. In this case,
 180  * we should ignore the value from either PAL_VM_SUMMARY or PAL override table.
 181  *
 182  * Complicating the logic here is the fact that num_possible_cpus()
 183  * isn't fully setup until we start bringing cpus online.
 184  */
 185 void
 186 setup_ptcg_sem(int max_purges, int nptcg_from)
 187 {
 188         static int kp_override;
 189         static int palo_override;
 190         static int firstcpu = 1;
 191 
 192         if (toolatetochangeptcgsem) {
 193                 if (nptcg_from == NPTCG_FROM_PAL && max_purges == 0)
 194                         BUG_ON(1 < nptcg);
 195                 else
 196                         BUG_ON(max_purges < nptcg);
 197                 return;
 198         }
 199 
 200         if (nptcg_from == NPTCG_FROM_KERNEL_PARAMETER) {
 201                 kp_override = 1;
 202                 nptcg = max_purges;
 203                 goto resetsema;
 204         }
 205         if (kp_override) {
 206                 need_ptcg_sem = num_possible_cpus() > nptcg;
 207                 return;
 208         }
 209 
 210         if (nptcg_from == NPTCG_FROM_PALO) {
 211                 palo_override = 1;
 212 
 213                 /* In PALO max_purges == 0 really means it! */
 214                 if (max_purges == 0)
 215                         panic("Whoa! Platform does not support global TLB purges.\n");
 216                 nptcg = max_purges;
 217                 if (nptcg == PALO_MAX_TLB_PURGES) {
 218                         need_ptcg_sem = 0;
 219                         return;
 220                 }
 221                 goto resetsema;
 222         }
 223         if (palo_override) {
 224                 if (nptcg != PALO_MAX_TLB_PURGES)
 225                         need_ptcg_sem = (num_possible_cpus() > nptcg);
 226                 return;
 227         }
 228 
 229         /* In PAL_VM_SUMMARY max_purges == 0 actually means 1 */
 230         if (max_purges == 0) max_purges = 1;
 231 
 232         if (firstcpu) {
 233                 nptcg = max_purges;
 234                 firstcpu = 0;
 235         }
 236         if (max_purges < nptcg)
 237                 nptcg = max_purges;
 238         if (nptcg == PAL_MAX_PURGES) {
 239                 need_ptcg_sem = 0;
 240                 return;
 241         } else
 242                 need_ptcg_sem = (num_possible_cpus() > nptcg);
 243 
 244 resetsema:
 245         spinaphore_init(&ptcg_sem, max_purges);
 246 }
 247 
 248 #ifdef CONFIG_SMP
 249 static void
 250 ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
 251                        unsigned long end, unsigned long nbits)
 252 {
 253         struct mm_struct *active_mm = current->active_mm;
 254 
 255         toolatetochangeptcgsem = 1;
 256 
 257         if (mm != active_mm) {
 258                 /* Restore region IDs for mm */
 259                 if (mm && active_mm) {
 260                         activate_context(mm);
 261                 } else {
 262                         flush_tlb_all();
 263                         return;
 264                 }
 265         }
 266 
 267         if (need_ptcg_sem)
 268                 down_spin(&ptcg_sem);
 269 
 270         do {
 271                 /*
 272                  * Flush ALAT entries also.
 273                  */
 274                 ia64_ptcga(start, (nbits << 2));
 275                 ia64_srlz_i();
 276                 start += (1UL << nbits);
 277         } while (start < end);
 278 
 279         if (need_ptcg_sem)
 280                 up_spin(&ptcg_sem);
 281 
 282         if (mm != active_mm) {
 283                 activate_context(active_mm);
 284         }
 285 }
 286 #endif /* CONFIG_SMP */
 287 
 288 void
 289 local_flush_tlb_all (void)
 290 {
 291         unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
 292 
 293         addr    = local_cpu_data->ptce_base;
 294         count0  = local_cpu_data->ptce_count[0];
 295         count1  = local_cpu_data->ptce_count[1];
 296         stride0 = local_cpu_data->ptce_stride[0];
 297         stride1 = local_cpu_data->ptce_stride[1];
 298 
 299         local_irq_save(flags);
 300         for (i = 0; i < count0; ++i) {
 301                 for (j = 0; j < count1; ++j) {
 302                         ia64_ptce(addr);
 303                         addr += stride1;
 304                 }
 305                 addr += stride0;
 306         }
 307         local_irq_restore(flags);
 308         ia64_srlz_i();                  /* srlz.i implies srlz.d */
 309 }
 310 
 311 static void
 312 __flush_tlb_range (struct vm_area_struct *vma, unsigned long start,
 313                  unsigned long end)
 314 {
 315         struct mm_struct *mm = vma->vm_mm;
 316         unsigned long size = end - start;
 317         unsigned long nbits;
 318 
 319 #ifndef CONFIG_SMP
 320         if (mm != current->active_mm) {
 321                 mm->context = 0;
 322                 return;
 323         }
 324 #endif
 325 
 326         nbits = ia64_fls(size + 0xfff);
 327         while (unlikely (((1UL << nbits) & purge.mask) == 0) &&
 328                         (nbits < purge.max_bits))
 329                 ++nbits;
 330         if (nbits > purge.max_bits)
 331                 nbits = purge.max_bits;
 332         start &= ~((1UL << nbits) - 1);
 333 
 334         preempt_disable();
 335 #ifdef CONFIG_SMP
 336         if (mm != current->active_mm || cpumask_weight(mm_cpumask(mm)) != 1) {
 337                 ia64_global_tlb_purge(mm, start, end, nbits);
 338                 preempt_enable();
 339                 return;
 340         }
 341 #endif
 342         do {
 343                 ia64_ptcl(start, (nbits<<2));
 344                 start += (1UL << nbits);
 345         } while (start < end);
 346         preempt_enable();
 347         ia64_srlz_i();                  /* srlz.i implies srlz.d */
 348 }
 349 
 350 void flush_tlb_range(struct vm_area_struct *vma,
 351                 unsigned long start, unsigned long end)
 352 {
 353         if (unlikely(end - start >= 1024*1024*1024*1024UL
 354                         || REGION_NUMBER(start) != REGION_NUMBER(end - 1))) {
 355                 /*
 356                  * If we flush more than a tera-byte or across regions, we're
 357                  * probably better off just flushing the entire TLB(s).  This
 358                  * should be very rare and is not worth optimizing for.
 359                  */
 360                 flush_tlb_all();
 361         } else {
 362                 /* flush the address range from the tlb */
 363                 __flush_tlb_range(vma, start, end);
 364                 /* flush the virt. page-table area mapping the addr range */
 365                 __flush_tlb_range(vma, ia64_thash(start), ia64_thash(end));
 366         }
 367 }
 368 EXPORT_SYMBOL(flush_tlb_range);
 369 
 370 void ia64_tlb_init(void)
 371 {
 372         ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */
 373         u64 tr_pgbits;
 374         long status;
 375         pal_vm_info_1_u_t vm_info_1;
 376         pal_vm_info_2_u_t vm_info_2;
 377         int cpu = smp_processor_id();
 378 
 379         if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
 380                 printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld; "
 381                        "defaulting to architected purge page-sizes.\n", status);
 382                 purge.mask = 0x115557000UL;
 383         }
 384         purge.max_bits = ia64_fls(purge.mask);
 385 
 386         ia64_get_ptce(&ptce_info);
 387         local_cpu_data->ptce_base = ptce_info.base;
 388         local_cpu_data->ptce_count[0] = ptce_info.count[0];
 389         local_cpu_data->ptce_count[1] = ptce_info.count[1];
 390         local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
 391         local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
 392 
 393         local_flush_tlb_all();  /* nuke left overs from bootstrapping... */
 394         status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2);
 395 
 396         if (status) {
 397                 printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
 398                 per_cpu(ia64_tr_num, cpu) = 8;
 399                 return;
 400         }
 401         per_cpu(ia64_tr_num, cpu) = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
 402         if (per_cpu(ia64_tr_num, cpu) >
 403                                 (vm_info_1.pal_vm_info_1_s.max_dtr_entry+1))
 404                 per_cpu(ia64_tr_num, cpu) =
 405                                 vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
 406         if (per_cpu(ia64_tr_num, cpu) > IA64_TR_ALLOC_MAX) {
 407                 static int justonce = 1;
 408                 per_cpu(ia64_tr_num, cpu) = IA64_TR_ALLOC_MAX;
 409                 if (justonce) {
 410                         justonce = 0;
 411                         printk(KERN_DEBUG "TR register number exceeds "
 412                                "IA64_TR_ALLOC_MAX!\n");
 413                 }
 414         }
 415 }
 416 
 417 /*
 418  * is_tr_overlap
 419  *
 420  * Check overlap with inserted TRs.
 421  */
 422 static int is_tr_overlap(struct ia64_tr_entry *p, u64 va, u64 log_size)
 423 {
 424         u64 tr_log_size;
 425         u64 tr_end;
 426         u64 va_rr = ia64_get_rr(va);
 427         u64 va_rid = RR_TO_RID(va_rr);
 428         u64 va_end = va + (1<<log_size) - 1;
 429 
 430         if (va_rid != RR_TO_RID(p->rr))
 431                 return 0;
 432         tr_log_size = (p->itir & 0xff) >> 2;
 433         tr_end = p->ifa + (1<<tr_log_size) - 1;
 434 
 435         if (va > tr_end || p->ifa > va_end)
 436                 return 0;
 437         return 1;
 438 
 439 }
 440 
 441 /*
 442  * ia64_insert_tr in virtual mode. Allocate a TR slot
 443  *
 444  * target_mask : 0x1 : itr, 0x2 : dtr, 0x3 : idtr
 445  *
 446  * va   : virtual address.
 447  * pte  : pte entries inserted.
 448  * log_size: range to be covered.
 449  *
 450  * Return value:  <0 :  error No.
 451  *
 452  *                >=0 : slot number allocated for TR.
 453  * Must be called with preemption disabled.
 454  */
 455 int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size)
 456 {
 457         int i, r;
 458         unsigned long psr;
 459         struct ia64_tr_entry *p;
 460         int cpu = smp_processor_id();
 461 
 462         if (!ia64_idtrs[cpu]) {
 463                 ia64_idtrs[cpu] = kmalloc_array(2 * IA64_TR_ALLOC_MAX,
 464                                                 sizeof(struct ia64_tr_entry),
 465                                                 GFP_KERNEL);
 466                 if (!ia64_idtrs[cpu])
 467                         return -ENOMEM;
 468         }
 469         r = -EINVAL;
 470         /*Check overlap with existing TR entries*/
 471         if (target_mask & 0x1) {
 472                 p = ia64_idtrs[cpu];
 473                 for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
 474                                                                 i++, p++) {
 475                         if (p->pte & 0x1)
 476                                 if (is_tr_overlap(p, va, log_size)) {
 477                                         printk(KERN_DEBUG "Overlapped Entry"
 478                                                 "Inserted for TR Register!!\n");
 479                                         goto out;
 480                         }
 481                 }
 482         }
 483         if (target_mask & 0x2) {
 484                 p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX;
 485                 for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
 486                                                                 i++, p++) {
 487                         if (p->pte & 0x1)
 488                                 if (is_tr_overlap(p, va, log_size)) {
 489                                         printk(KERN_DEBUG "Overlapped Entry"
 490                                                 "Inserted for TR Register!!\n");
 491                                         goto out;
 492                                 }
 493                 }
 494         }
 495 
 496         for (i = IA64_TR_ALLOC_BASE; i < per_cpu(ia64_tr_num, cpu); i++) {
 497                 switch (target_mask & 0x3) {
 498                 case 1:
 499                         if (!((ia64_idtrs[cpu] + i)->pte & 0x1))
 500                                 goto found;
 501                         continue;
 502                 case 2:
 503                         if (!((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
 504                                 goto found;
 505                         continue;
 506                 case 3:
 507                         if (!((ia64_idtrs[cpu] + i)->pte & 0x1) &&
 508                             !((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
 509                                 goto found;
 510                         continue;
 511                 default:
 512                         r = -EINVAL;
 513                         goto out;
 514                 }
 515         }
 516 found:
 517         if (i >= per_cpu(ia64_tr_num, cpu))
 518                 return -EBUSY;
 519 
 520         /*Record tr info for mca hander use!*/
 521         if (i > per_cpu(ia64_tr_used, cpu))
 522                 per_cpu(ia64_tr_used, cpu) = i;
 523 
 524         psr = ia64_clear_ic();
 525         if (target_mask & 0x1) {
 526                 ia64_itr(0x1, i, va, pte, log_size);
 527                 ia64_srlz_i();
 528                 p = ia64_idtrs[cpu] + i;
 529                 p->ifa = va;
 530                 p->pte = pte;
 531                 p->itir = log_size << 2;
 532                 p->rr = ia64_get_rr(va);
 533         }
 534         if (target_mask & 0x2) {
 535                 ia64_itr(0x2, i, va, pte, log_size);
 536                 ia64_srlz_i();
 537                 p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i;
 538                 p->ifa = va;
 539                 p->pte = pte;
 540                 p->itir = log_size << 2;
 541                 p->rr = ia64_get_rr(va);
 542         }
 543         ia64_set_psr(psr);
 544         r = i;
 545 out:
 546         return r;
 547 }
 548 EXPORT_SYMBOL_GPL(ia64_itr_entry);
 549 
 550 /*
 551  * ia64_purge_tr
 552  *
 553  * target_mask: 0x1: purge itr, 0x2 : purge dtr, 0x3 purge idtr.
 554  * slot: slot number to be freed.
 555  *
 556  * Must be called with preemption disabled.
 557  */
 558 void ia64_ptr_entry(u64 target_mask, int slot)
 559 {
 560         int cpu = smp_processor_id();
 561         int i;
 562         struct ia64_tr_entry *p;
 563 
 564         if (slot < IA64_TR_ALLOC_BASE || slot >= per_cpu(ia64_tr_num, cpu))
 565                 return;
 566 
 567         if (target_mask & 0x1) {
 568                 p = ia64_idtrs[cpu] + slot;
 569                 if ((p->pte&0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
 570                         p->pte = 0;
 571                         ia64_ptr(0x1, p->ifa, p->itir>>2);
 572                         ia64_srlz_i();
 573                 }
 574         }
 575 
 576         if (target_mask & 0x2) {
 577                 p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + slot;
 578                 if ((p->pte & 0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
 579                         p->pte = 0;
 580                         ia64_ptr(0x2, p->ifa, p->itir>>2);
 581                         ia64_srlz_i();
 582                 }
 583         }
 584 
 585         for (i = per_cpu(ia64_tr_used, cpu); i >= IA64_TR_ALLOC_BASE; i--) {
 586                 if (((ia64_idtrs[cpu] + i)->pte & 0x1) ||
 587                     ((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
 588                         break;
 589         }
 590         per_cpu(ia64_tr_used, cpu) = i;
 591 }
 592 EXPORT_SYMBOL_GPL(ia64_ptr_entry);
/* [<][>][^][v][top][bottom][index][help] */
root/arch/ia64/mm/tlb.c

DEFINITIONS
