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9 #ifndef __EMIF_H
10 #define __EMIF_H
11
12
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14
15
16
17 #define EMIF_MAX_NUM_FREQUENCIES 6
18
19
20 #define DDR_VOLTAGE_STABLE 0
21 #define DDR_VOLTAGE_RAMPING 1
22
23
24 #define EMIF_NORMAL_TIMINGS 0
25 #define EMIF_DERATED_TIMINGS 1
26
27
28 #define EMIF_READ_IDLE_LEN_VAL 5
29
30
31
32
33
34 #define READ_IDLE_INTERVAL_DVFS (1*1000000)
35
36
37
38
39
40 #define READ_IDLE_INTERVAL_NORMAL (50*1000000)
41
42
43 #define DLL_CALIB_INTERVAL_DVFS (1*1000000)
44
45 #define DLL_CALIB_ACK_WAIT_VAL 5
46
47
48 #define EMIF_ZQCS_INTERVAL_US (50*1000)
49
50 #define ZQ_SFEXITEN_ENABLE 1
51
52
53
54
55 #define ZQ_DUALCALEN_DISABLE 0
56 #define ZQ_DUALCALEN_ENABLE 1
57
58 #define T_ZQCS_DEFAULT_NS 90
59 #define T_ZQCL_DEFAULT_NS 360
60 #define T_ZQINIT_DEFAULT_NS 1000
61
62
63 #define DPD_DISABLE 0
64 #define DPD_ENABLE 1
65
66
67
68
69
70
71 #define EMIF_LP_MODE_TIMEOUT_PERFORMANCE 2048
72 #define EMIF_LP_MODE_TIMEOUT_POWER 512
73 #define EMIF_LP_MODE_FREQ_THRESHOLD 400000000
74
75
76 #define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000
77 #define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x41
78 #define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x80
79 #define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF
80
81
82 #define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E084200
83 #define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS 10000
84
85
86 #define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS 360
87
88 #define EMIF_T_CSTA 3
89 #define EMIF_T_PDLL_UL 128
90
91
92 #define EMIF_EXT_PHY_CTRL_1_VAL 0x04020080
93 #define EMIF_EXT_PHY_CTRL_5_VAL 0x04010040
94 #define EMIF_EXT_PHY_CTRL_6_VAL 0x01004010
95 #define EMIF_EXT_PHY_CTRL_7_VAL 0x00001004
96 #define EMIF_EXT_PHY_CTRL_8_VAL 0x04010040
97 #define EMIF_EXT_PHY_CTRL_9_VAL 0x01004010
98 #define EMIF_EXT_PHY_CTRL_10_VAL 0x00001004
99 #define EMIF_EXT_PHY_CTRL_11_VAL 0x00000000
100 #define EMIF_EXT_PHY_CTRL_12_VAL 0x00000000
101 #define EMIF_EXT_PHY_CTRL_13_VAL 0x00000000
102 #define EMIF_EXT_PHY_CTRL_14_VAL 0x80080080
103 #define EMIF_EXT_PHY_CTRL_15_VAL 0x00800800
104 #define EMIF_EXT_PHY_CTRL_16_VAL 0x08102040
105 #define EMIF_EXT_PHY_CTRL_17_VAL 0x00000001
106 #define EMIF_EXT_PHY_CTRL_18_VAL 0x540A8150
107 #define EMIF_EXT_PHY_CTRL_19_VAL 0xA81502A0
108 #define EMIF_EXT_PHY_CTRL_20_VAL 0x002A0540
109 #define EMIF_EXT_PHY_CTRL_21_VAL 0x00000000
110 #define EMIF_EXT_PHY_CTRL_22_VAL 0x00000000
111 #define EMIF_EXT_PHY_CTRL_23_VAL 0x00000000
112 #define EMIF_EXT_PHY_CTRL_24_VAL 0x00000077
113
114 #define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS 1200
115
116
117 #define EMIF_MODULE_ID_AND_REVISION 0x0000
118 #define EMIF_STATUS 0x0004
119 #define EMIF_SDRAM_CONFIG 0x0008
120 #define EMIF_SDRAM_CONFIG_2 0x000c
121 #define EMIF_SDRAM_REFRESH_CONTROL 0x0010
122 #define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014
123 #define EMIF_SDRAM_TIMING_1 0x0018
124 #define EMIF_SDRAM_TIMING_1_SHDW 0x001c
125 #define EMIF_SDRAM_TIMING_2 0x0020
126 #define EMIF_SDRAM_TIMING_2_SHDW 0x0024
127 #define EMIF_SDRAM_TIMING_3 0x0028
128 #define EMIF_SDRAM_TIMING_3_SHDW 0x002c
129 #define EMIF_LPDDR2_NVM_TIMING 0x0030
130 #define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034
131 #define EMIF_POWER_MANAGEMENT_CONTROL 0x0038
132 #define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c
133 #define EMIF_LPDDR2_MODE_REG_DATA 0x0040
134 #define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050
135 #define EMIF_OCP_CONFIG 0x0054
136 #define EMIF_OCP_CONFIG_VALUE_1 0x0058
137 #define EMIF_OCP_CONFIG_VALUE_2 0x005c
138 #define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL 0x0060
139 #define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT 0x0064
140 #define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT 0x0068
141 #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 0x006c
142 #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 0x0070
143 #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 0x0074
144 #define EMIF_PERFORMANCE_COUNTER_1 0x0080
145 #define EMIF_PERFORMANCE_COUNTER_2 0x0084
146 #define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088
147 #define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c
148 #define EMIF_PERFORMANCE_COUNTER_TIME 0x0090
149 #define EMIF_MISC_REG 0x0094
150 #define EMIF_DLL_CALIB_CTRL 0x0098
151 #define EMIF_DLL_CALIB_CTRL_SHDW 0x009c
152 #define EMIF_END_OF_INTERRUPT 0x00a0
153 #define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4
154 #define EMIF_LL_OCP_INTERRUPT_RAW_STATUS 0x00a8
155 #define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac
156 #define EMIF_LL_OCP_INTERRUPT_STATUS 0x00b0
157 #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4
158 #define EMIF_LL_OCP_INTERRUPT_ENABLE_SET 0x00b8
159 #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc
160 #define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR 0x00c0
161 #define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8
162 #define EMIF_TEMPERATURE_ALERT_CONFIG 0x00cc
163 #define EMIF_OCP_ERROR_LOG 0x00d0
164 #define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4
165 #define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8
166 #define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc
167 #define EMIF_DDR_PHY_CTRL_1 0x00e4
168 #define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8
169 #define EMIF_DDR_PHY_CTRL_2 0x00ec
170 #define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING 0x0100
171 #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104
172 #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108
173 #define EMIF_READ_WRITE_EXECUTION_THRESHOLD 0x0120
174 #define EMIF_COS_CONFIG 0x0124
175 #define EMIF_PHY_STATUS_1 0x0140
176 #define EMIF_PHY_STATUS_2 0x0144
177 #define EMIF_PHY_STATUS_3 0x0148
178 #define EMIF_PHY_STATUS_4 0x014c
179 #define EMIF_PHY_STATUS_5 0x0150
180 #define EMIF_PHY_STATUS_6 0x0154
181 #define EMIF_PHY_STATUS_7 0x0158
182 #define EMIF_PHY_STATUS_8 0x015c
183 #define EMIF_PHY_STATUS_9 0x0160
184 #define EMIF_PHY_STATUS_10 0x0164
185 #define EMIF_PHY_STATUS_11 0x0168
186 #define EMIF_PHY_STATUS_12 0x016c
187 #define EMIF_PHY_STATUS_13 0x0170
188 #define EMIF_PHY_STATUS_14 0x0174
189 #define EMIF_PHY_STATUS_15 0x0178
190 #define EMIF_PHY_STATUS_16 0x017c
191 #define EMIF_PHY_STATUS_17 0x0180
192 #define EMIF_PHY_STATUS_18 0x0184
193 #define EMIF_PHY_STATUS_19 0x0188
194 #define EMIF_PHY_STATUS_20 0x018c
195 #define EMIF_PHY_STATUS_21 0x0190
196 #define EMIF_EXT_PHY_CTRL_1 0x0200
197 #define EMIF_EXT_PHY_CTRL_1_SHDW 0x0204
198 #define EMIF_EXT_PHY_CTRL_2 0x0208
199 #define EMIF_EXT_PHY_CTRL_2_SHDW 0x020c
200 #define EMIF_EXT_PHY_CTRL_3 0x0210
201 #define EMIF_EXT_PHY_CTRL_3_SHDW 0x0214
202 #define EMIF_EXT_PHY_CTRL_4 0x0218
203 #define EMIF_EXT_PHY_CTRL_4_SHDW 0x021c
204 #define EMIF_EXT_PHY_CTRL_5 0x0220
205 #define EMIF_EXT_PHY_CTRL_5_SHDW 0x0224
206 #define EMIF_EXT_PHY_CTRL_6 0x0228
207 #define EMIF_EXT_PHY_CTRL_6_SHDW 0x022c
208 #define EMIF_EXT_PHY_CTRL_7 0x0230
209 #define EMIF_EXT_PHY_CTRL_7_SHDW 0x0234
210 #define EMIF_EXT_PHY_CTRL_8 0x0238
211 #define EMIF_EXT_PHY_CTRL_8_SHDW 0x023c
212 #define EMIF_EXT_PHY_CTRL_9 0x0240
213 #define EMIF_EXT_PHY_CTRL_9_SHDW 0x0244
214 #define EMIF_EXT_PHY_CTRL_10 0x0248
215 #define EMIF_EXT_PHY_CTRL_10_SHDW 0x024c
216 #define EMIF_EXT_PHY_CTRL_11 0x0250
217 #define EMIF_EXT_PHY_CTRL_11_SHDW 0x0254
218 #define EMIF_EXT_PHY_CTRL_12 0x0258
219 #define EMIF_EXT_PHY_CTRL_12_SHDW 0x025c
220 #define EMIF_EXT_PHY_CTRL_13 0x0260
221 #define EMIF_EXT_PHY_CTRL_13_SHDW 0x0264
222 #define EMIF_EXT_PHY_CTRL_14 0x0268
223 #define EMIF_EXT_PHY_CTRL_14_SHDW 0x026c
224 #define EMIF_EXT_PHY_CTRL_15 0x0270
225 #define EMIF_EXT_PHY_CTRL_15_SHDW 0x0274
226 #define EMIF_EXT_PHY_CTRL_16 0x0278
227 #define EMIF_EXT_PHY_CTRL_16_SHDW 0x027c
228 #define EMIF_EXT_PHY_CTRL_17 0x0280
229 #define EMIF_EXT_PHY_CTRL_17_SHDW 0x0284
230 #define EMIF_EXT_PHY_CTRL_18 0x0288
231 #define EMIF_EXT_PHY_CTRL_18_SHDW 0x028c
232 #define EMIF_EXT_PHY_CTRL_19 0x0290
233 #define EMIF_EXT_PHY_CTRL_19_SHDW 0x0294
234 #define EMIF_EXT_PHY_CTRL_20 0x0298
235 #define EMIF_EXT_PHY_CTRL_20_SHDW 0x029c
236 #define EMIF_EXT_PHY_CTRL_21 0x02a0
237 #define EMIF_EXT_PHY_CTRL_21_SHDW 0x02a4
238 #define EMIF_EXT_PHY_CTRL_22 0x02a8
239 #define EMIF_EXT_PHY_CTRL_22_SHDW 0x02ac
240 #define EMIF_EXT_PHY_CTRL_23 0x02b0
241 #define EMIF_EXT_PHY_CTRL_23_SHDW 0x02b4
242 #define EMIF_EXT_PHY_CTRL_24 0x02b8
243 #define EMIF_EXT_PHY_CTRL_24_SHDW 0x02bc
244 #define EMIF_EXT_PHY_CTRL_25 0x02c0
245 #define EMIF_EXT_PHY_CTRL_25_SHDW 0x02c4
246 #define EMIF_EXT_PHY_CTRL_26 0x02c8
247 #define EMIF_EXT_PHY_CTRL_26_SHDW 0x02cc
248 #define EMIF_EXT_PHY_CTRL_27 0x02d0
249 #define EMIF_EXT_PHY_CTRL_27_SHDW 0x02d4
250 #define EMIF_EXT_PHY_CTRL_28 0x02d8
251 #define EMIF_EXT_PHY_CTRL_28_SHDW 0x02dc
252 #define EMIF_EXT_PHY_CTRL_29 0x02e0
253 #define EMIF_EXT_PHY_CTRL_29_SHDW 0x02e4
254 #define EMIF_EXT_PHY_CTRL_30 0x02e8
255 #define EMIF_EXT_PHY_CTRL_30_SHDW 0x02ec
256
257
258
259
260 #define SCHEME_SHIFT 30
261 #define SCHEME_MASK (0x3 << 30)
262 #define MODULE_ID_SHIFT 16
263 #define MODULE_ID_MASK (0xfff << 16)
264 #define RTL_VERSION_SHIFT 11
265 #define RTL_VERSION_MASK (0x1f << 11)
266 #define MAJOR_REVISION_SHIFT 8
267 #define MAJOR_REVISION_MASK (0x7 << 8)
268 #define MINOR_REVISION_SHIFT 0
269 #define MINOR_REVISION_MASK (0x3f << 0)
270
271
272 #define BE_SHIFT 31
273 #define BE_MASK (1 << 31)
274 #define DUAL_CLK_MODE_SHIFT 30
275 #define DUAL_CLK_MODE_MASK (1 << 30)
276 #define FAST_INIT_SHIFT 29
277 #define FAST_INIT_MASK (1 << 29)
278 #define RDLVLGATETO_SHIFT 6
279 #define RDLVLGATETO_MASK (1 << 6)
280 #define RDLVLTO_SHIFT 5
281 #define RDLVLTO_MASK (1 << 5)
282 #define WRLVLTO_SHIFT 4
283 #define WRLVLTO_MASK (1 << 4)
284 #define PHY_DLL_READY_SHIFT 2
285 #define PHY_DLL_READY_MASK (1 << 2)
286
287
288 #define SDRAM_TYPE_SHIFT 29
289 #define SDRAM_TYPE_MASK (0x7 << 29)
290 #define IBANK_POS_SHIFT 27
291 #define IBANK_POS_MASK (0x3 << 27)
292 #define DDR_TERM_SHIFT 24
293 #define DDR_TERM_MASK (0x7 << 24)
294 #define DDR2_DDQS_SHIFT 23
295 #define DDR2_DDQS_MASK (1 << 23)
296 #define DYN_ODT_SHIFT 21
297 #define DYN_ODT_MASK (0x3 << 21)
298 #define DDR_DISABLE_DLL_SHIFT 20
299 #define DDR_DISABLE_DLL_MASK (1 << 20)
300 #define SDRAM_DRIVE_SHIFT 18
301 #define SDRAM_DRIVE_MASK (0x3 << 18)
302 #define CWL_SHIFT 16
303 #define CWL_MASK (0x3 << 16)
304 #define NARROW_MODE_SHIFT 14
305 #define NARROW_MODE_MASK (0x3 << 14)
306 #define CL_SHIFT 10
307 #define CL_MASK (0xf << 10)
308 #define ROWSIZE_SHIFT 7
309 #define ROWSIZE_MASK (0x7 << 7)
310 #define IBANK_SHIFT 4
311 #define IBANK_MASK (0x7 << 4)
312 #define EBANK_SHIFT 3
313 #define EBANK_MASK (1 << 3)
314 #define PAGESIZE_SHIFT 0
315 #define PAGESIZE_MASK (0x7 << 0)
316
317
318 #define CS1NVMEN_SHIFT 30
319 #define CS1NVMEN_MASK (1 << 30)
320 #define EBANK_POS_SHIFT 27
321 #define EBANK_POS_MASK (1 << 27)
322 #define RDBNUM_SHIFT 4
323 #define RDBNUM_MASK (0x3 << 4)
324 #define RDBSIZE_SHIFT 0
325 #define RDBSIZE_MASK (0x7 << 0)
326
327
328 #define INITREF_DIS_SHIFT 31
329 #define INITREF_DIS_MASK (1 << 31)
330 #define SRT_SHIFT 29
331 #define SRT_MASK (1 << 29)
332 #define ASR_SHIFT 28
333 #define ASR_MASK (1 << 28)
334 #define PASR_SHIFT 24
335 #define PASR_MASK (0x7 << 24)
336 #define REFRESH_RATE_SHIFT 0
337 #define REFRESH_RATE_MASK (0xffff << 0)
338
339
340 #define T_RTW_SHIFT 29
341 #define T_RTW_MASK (0x7 << 29)
342 #define T_RP_SHIFT 25
343 #define T_RP_MASK (0xf << 25)
344 #define T_RCD_SHIFT 21
345 #define T_RCD_MASK (0xf << 21)
346 #define T_WR_SHIFT 17
347 #define T_WR_MASK (0xf << 17)
348 #define T_RAS_SHIFT 12
349 #define T_RAS_MASK (0x1f << 12)
350 #define T_RC_SHIFT 6
351 #define T_RC_MASK (0x3f << 6)
352 #define T_RRD_SHIFT 3
353 #define T_RRD_MASK (0x7 << 3)
354 #define T_WTR_SHIFT 0
355 #define T_WTR_MASK (0x7 << 0)
356
357
358 #define T_XP_SHIFT 28
359 #define T_XP_MASK (0x7 << 28)
360 #define T_ODT_SHIFT 25
361 #define T_ODT_MASK (0x7 << 25)
362 #define T_XSNR_SHIFT 16
363 #define T_XSNR_MASK (0x1ff << 16)
364 #define T_XSRD_SHIFT 6
365 #define T_XSRD_MASK (0x3ff << 6)
366 #define T_RTP_SHIFT 3
367 #define T_RTP_MASK (0x7 << 3)
368 #define T_CKE_SHIFT 0
369 #define T_CKE_MASK (0x7 << 0)
370
371
372 #define T_PDLL_UL_SHIFT 28
373 #define T_PDLL_UL_MASK (0xf << 28)
374 #define T_CSTA_SHIFT 24
375 #define T_CSTA_MASK (0xf << 24)
376 #define T_CKESR_SHIFT 21
377 #define T_CKESR_MASK (0x7 << 21)
378 #define ZQ_ZQCS_SHIFT 15
379 #define ZQ_ZQCS_MASK (0x3f << 15)
380 #define T_TDQSCKMAX_SHIFT 13
381 #define T_TDQSCKMAX_MASK (0x3 << 13)
382 #define T_RFC_SHIFT 4
383 #define T_RFC_MASK (0x1ff << 4)
384 #define T_RAS_MAX_SHIFT 0
385 #define T_RAS_MAX_MASK (0xf << 0)
386
387
388 #define PD_TIM_SHIFT 12
389 #define PD_TIM_MASK (0xf << 12)
390 #define DPD_EN_SHIFT 11
391 #define DPD_EN_MASK (1 << 11)
392 #define LP_MODE_SHIFT 8
393 #define LP_MODE_MASK (0x7 << 8)
394 #define SR_TIM_SHIFT 4
395 #define SR_TIM_MASK (0xf << 4)
396 #define CS_TIM_SHIFT 0
397 #define CS_TIM_MASK (0xf << 0)
398
399
400 #define VALUE_0_SHIFT 0
401 #define VALUE_0_MASK (0x7f << 0)
402
403
404 #define CS_SHIFT 31
405 #define CS_MASK (1 << 31)
406 #define REFRESH_EN_SHIFT 30
407 #define REFRESH_EN_MASK (1 << 30)
408 #define ADDRESS_SHIFT 0
409 #define ADDRESS_MASK (0xff << 0)
410
411
412 #define SYS_THRESH_MAX_SHIFT 24
413 #define SYS_THRESH_MAX_MASK (0xf << 24)
414 #define MPU_THRESH_MAX_SHIFT 20
415 #define MPU_THRESH_MAX_MASK (0xf << 20)
416 #define LL_THRESH_MAX_SHIFT 16
417 #define LL_THRESH_MAX_MASK (0xf << 16)
418
419
420 #define COUNTER1_SHIFT 0
421 #define COUNTER1_MASK (0xffffffff << 0)
422
423
424 #define COUNTER2_SHIFT 0
425 #define COUNTER2_MASK (0xffffffff << 0)
426
427
428 #define CNTR2_MCONNID_EN_SHIFT 31
429 #define CNTR2_MCONNID_EN_MASK (1 << 31)
430 #define CNTR2_REGION_EN_SHIFT 30
431 #define CNTR2_REGION_EN_MASK (1 << 30)
432 #define CNTR2_CFG_SHIFT 16
433 #define CNTR2_CFG_MASK (0xf << 16)
434 #define CNTR1_MCONNID_EN_SHIFT 15
435 #define CNTR1_MCONNID_EN_MASK (1 << 15)
436 #define CNTR1_REGION_EN_SHIFT 14
437 #define CNTR1_REGION_EN_MASK (1 << 14)
438 #define CNTR1_CFG_SHIFT 0
439 #define CNTR1_CFG_MASK (0xf << 0)
440
441
442 #define MCONNID2_SHIFT 24
443 #define MCONNID2_MASK (0xff << 24)
444 #define REGION_SEL2_SHIFT 16
445 #define REGION_SEL2_MASK (0x3 << 16)
446 #define MCONNID1_SHIFT 8
447 #define MCONNID1_MASK (0xff << 8)
448 #define REGION_SEL1_SHIFT 0
449 #define REGION_SEL1_MASK (0x3 << 0)
450
451
452 #define TOTAL_TIME_SHIFT 0
453 #define TOTAL_TIME_MASK (0xffffffff << 0)
454
455
456 #define ACK_WAIT_SHIFT 16
457 #define ACK_WAIT_MASK (0xf << 16)
458 #define DLL_CALIB_INTERVAL_SHIFT 0
459 #define DLL_CALIB_INTERVAL_MASK (0x1ff << 0)
460
461
462 #define EOI_SHIFT 0
463 #define EOI_MASK (1 << 0)
464
465
466 #define DNV_SYS_SHIFT 2
467 #define DNV_SYS_MASK (1 << 2)
468 #define TA_SYS_SHIFT 1
469 #define TA_SYS_MASK (1 << 1)
470 #define ERR_SYS_SHIFT 0
471 #define ERR_SYS_MASK (1 << 0)
472
473
474 #define DNV_LL_SHIFT 2
475 #define DNV_LL_MASK (1 << 2)
476 #define TA_LL_SHIFT 1
477 #define TA_LL_MASK (1 << 1)
478 #define ERR_LL_SHIFT 0
479 #define ERR_LL_MASK (1 << 0)
480
481
482 #define EN_DNV_SYS_SHIFT 2
483 #define EN_DNV_SYS_MASK (1 << 2)
484 #define EN_TA_SYS_SHIFT 1
485 #define EN_TA_SYS_MASK (1 << 1)
486 #define EN_ERR_SYS_SHIFT 0
487 #define EN_ERR_SYS_MASK (1 << 0)
488
489
490 #define EN_DNV_LL_SHIFT 2
491 #define EN_DNV_LL_MASK (1 << 2)
492 #define EN_TA_LL_SHIFT 1
493 #define EN_TA_LL_MASK (1 << 1)
494 #define EN_ERR_LL_SHIFT 0
495 #define EN_ERR_LL_MASK (1 << 0)
496
497
498 #define ZQ_CS1EN_SHIFT 31
499 #define ZQ_CS1EN_MASK (1 << 31)
500 #define ZQ_CS0EN_SHIFT 30
501 #define ZQ_CS0EN_MASK (1 << 30)
502 #define ZQ_DUALCALEN_SHIFT 29
503 #define ZQ_DUALCALEN_MASK (1 << 29)
504 #define ZQ_SFEXITEN_SHIFT 28
505 #define ZQ_SFEXITEN_MASK (1 << 28)
506 #define ZQ_ZQINIT_MULT_SHIFT 18
507 #define ZQ_ZQINIT_MULT_MASK (0x3 << 18)
508 #define ZQ_ZQCL_MULT_SHIFT 16
509 #define ZQ_ZQCL_MULT_MASK (0x3 << 16)
510 #define ZQ_REFINTERVAL_SHIFT 0
511 #define ZQ_REFINTERVAL_MASK (0xffff << 0)
512
513
514 #define TA_CS1EN_SHIFT 31
515 #define TA_CS1EN_MASK (1 << 31)
516 #define TA_CS0EN_SHIFT 30
517 #define TA_CS0EN_MASK (1 << 30)
518 #define TA_SFEXITEN_SHIFT 28
519 #define TA_SFEXITEN_MASK (1 << 28)
520 #define TA_DEVWDT_SHIFT 26
521 #define TA_DEVWDT_MASK (0x3 << 26)
522 #define TA_DEVCNT_SHIFT 24
523 #define TA_DEVCNT_MASK (0x3 << 24)
524 #define TA_REFINTERVAL_SHIFT 0
525 #define TA_REFINTERVAL_MASK (0x3fffff << 0)
526
527
528 #define MADDRSPACE_SHIFT 14
529 #define MADDRSPACE_MASK (0x3 << 14)
530 #define MBURSTSEQ_SHIFT 11
531 #define MBURSTSEQ_MASK (0x7 << 11)
532 #define MCMD_SHIFT 8
533 #define MCMD_MASK (0x7 << 8)
534 #define MCONNID_SHIFT 0
535 #define MCONNID_MASK (0xff << 0)
536
537
538 #define RDWRLVLFULL_START 0x80000000
539
540
541 #define DLL_SLAVE_DLY_CTRL_SHIFT_4D 4
542 #define DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4)
543 #define READ_LATENCY_SHIFT_4D 0
544 #define READ_LATENCY_MASK_4D (0xf << 0)
545
546
547 #define DLL_HALF_DELAY_SHIFT_4D5 21
548 #define DLL_HALF_DELAY_MASK_4D5 (1 << 21)
549 #define READ_LATENCY_SHIFT_4D5 0
550 #define READ_LATENCY_MASK_4D5 (0x1f << 0)
551
552
553 #define DDR_PHY_CTRL_1_SHDW_SHIFT 5
554 #define DDR_PHY_CTRL_1_SHDW_MASK (0x7ffffff << 5)
555 #define READ_LATENCY_SHDW_SHIFT 0
556 #define READ_LATENCY_SHDW_MASK (0x1f << 0)
557
558 #define EMIF_SRAM_AM33_REG_LAYOUT 0x00000000
559 #define EMIF_SRAM_AM43_REG_LAYOUT 0x00000001
560
561 #ifndef __ASSEMBLY__
562
563
564
565
566
567 struct emif_regs {
568 u32 freq;
569 u32 ref_ctrl_shdw;
570 u32 ref_ctrl_shdw_derated;
571 u32 sdram_tim1_shdw;
572 u32 sdram_tim1_shdw_derated;
573 u32 sdram_tim2_shdw;
574 u32 sdram_tim3_shdw;
575 u32 sdram_tim3_shdw_derated;
576 u32 pwr_mgmt_ctrl_shdw;
577 union {
578 u32 read_idle_ctrl_shdw_normal;
579 u32 dll_calib_ctrl_shdw_normal;
580 };
581 union {
582 u32 read_idle_ctrl_shdw_volt_ramp;
583 u32 dll_calib_ctrl_shdw_volt_ramp;
584 };
585
586 u32 phy_ctrl_1_shdw;
587 u32 ext_phy_ctrl_2_shdw;
588 u32 ext_phy_ctrl_3_shdw;
589 u32 ext_phy_ctrl_4_shdw;
590 };
591
592 struct ti_emif_pm_functions;
593
594 extern unsigned int ti_emif_sram;
595 extern unsigned int ti_emif_sram_sz;
596 extern struct ti_emif_pm_data ti_emif_pm_sram_data;
597 extern struct emif_regs_amx3 ti_emif_regs_amx3;
598
599 void ti_emif_save_context(void);
600 void ti_emif_restore_context(void);
601 void ti_emif_run_hw_leveling(void);
602 void ti_emif_enter_sr(void);
603 void ti_emif_exit_sr(void);
604 void ti_emif_abort_sr(void);
605
606 #endif
607 #endif