drivers/rtc/rtc-sun6i.c

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This source file includes following definitions.
sun6i_rtc_osc_recalc_rate
sun6i_rtc_osc_get_parent
sun6i_rtc_osc_set_parent
sun6i_rtc_clk_init
sun6i_a31_rtc_clk_init
sun8i_a23_rtc_clk_init
sun8i_h3_rtc_clk_init
sun50i_h6_rtc_clk_init
sun8i_r40_rtc_clk_init
sun8i_v3_rtc_clk_init
sun6i_rtc_alarmirq
sun6i_rtc_setaie
sun6i_rtc_gettime
sun6i_rtc_getalarm
sun6i_rtc_setalarm
sun6i_rtc_wait
sun6i_rtc_settime
sun6i_rtc_alarm_irq_enable
sun6i_rtc_suspend
sun6i_rtc_resume
sun6i_rtc_probe
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * An RTC driver for Allwinner A31/A23
   4  *
   5  * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
   6  *
   7  * based on rtc-sunxi.c
   8  *
   9  * An RTC driver for Allwinner A10/A20
  10  *
  11  * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
  12  */
  13 
  14 #include <linux/clk.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18 #include <linux/fs.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/rtc.h>
  29 #include <linux/slab.h>
  30 #include <linux/types.h>
  31 
  32 /* Control register */
  33 #define SUN6I_LOSC_CTRL                         0x0000
  34 #define SUN6I_LOSC_CTRL_KEY                     (0x16aa << 16)
  35 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS         BIT(15)
  36 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC            BIT(9)
  37 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC             BIT(8)
  38 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC             BIT(7)
  39 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN             BIT(4)
  40 #define SUN6I_LOSC_CTRL_EXT_OSC                 BIT(0)
  41 #define SUN6I_LOSC_CTRL_ACC_MASK                GENMASK(9, 7)
  42 
  43 #define SUN6I_LOSC_CLK_PRESCAL                  0x0008
  44 
  45 /* RTC */
  46 #define SUN6I_RTC_YMD                           0x0010
  47 #define SUN6I_RTC_HMS                           0x0014
  48 
  49 /* Alarm 0 (counter) */
  50 #define SUN6I_ALRM_COUNTER                      0x0020
  51 #define SUN6I_ALRM_CUR_VAL                      0x0024
  52 #define SUN6I_ALRM_EN                           0x0028
  53 #define SUN6I_ALRM_EN_CNT_EN                    BIT(0)
  54 #define SUN6I_ALRM_IRQ_EN                       0x002c
  55 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN            BIT(0)
  56 #define SUN6I_ALRM_IRQ_STA                      0x0030
  57 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND         BIT(0)
  58 
  59 /* Alarm 1 (wall clock) */
  60 #define SUN6I_ALRM1_EN                          0x0044
  61 #define SUN6I_ALRM1_IRQ_EN                      0x0048
  62 #define SUN6I_ALRM1_IRQ_STA                     0x004c
  63 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND       BIT(0)
  64 
  65 /* Alarm config */
  66 #define SUN6I_ALARM_CONFIG                      0x0050
  67 #define SUN6I_ALARM_CONFIG_WAKEUP               BIT(0)
  68 
  69 #define SUN6I_LOSC_OUT_GATING                   0x0060
  70 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET         0
  71 
  72 /*
  73  * Get date values
  74  */
  75 #define SUN6I_DATE_GET_DAY_VALUE(x)             ((x)  & 0x0000001f)
  76 #define SUN6I_DATE_GET_MON_VALUE(x)             (((x) & 0x00000f00) >> 8)
  77 #define SUN6I_DATE_GET_YEAR_VALUE(x)            (((x) & 0x003f0000) >> 16)
  78 #define SUN6I_LEAP_GET_VALUE(x)                 (((x) & 0x00400000) >> 22)
  79 
  80 /*
  81  * Get time values
  82  */
  83 #define SUN6I_TIME_GET_SEC_VALUE(x)             ((x)  & 0x0000003f)
  84 #define SUN6I_TIME_GET_MIN_VALUE(x)             (((x) & 0x00003f00) >> 8)
  85 #define SUN6I_TIME_GET_HOUR_VALUE(x)            (((x) & 0x001f0000) >> 16)
  86 
  87 /*
  88  * Set date values
  89  */
  90 #define SUN6I_DATE_SET_DAY_VALUE(x)             ((x)       & 0x0000001f)
  91 #define SUN6I_DATE_SET_MON_VALUE(x)             ((x) <<  8 & 0x00000f00)
  92 #define SUN6I_DATE_SET_YEAR_VALUE(x)            ((x) << 16 & 0x003f0000)
  93 #define SUN6I_LEAP_SET_VALUE(x)                 ((x) << 22 & 0x00400000)
  94 
  95 /*
  96  * Set time values
  97  */
  98 #define SUN6I_TIME_SET_SEC_VALUE(x)             ((x)       & 0x0000003f)
  99 #define SUN6I_TIME_SET_MIN_VALUE(x)             ((x) <<  8 & 0x00003f00)
 100 #define SUN6I_TIME_SET_HOUR_VALUE(x)            ((x) << 16 & 0x001f0000)
 101 
 102 /*
 103  * The year parameter passed to the driver is usually an offset relative to
 104  * the year 1900. This macro is used to convert this offset to another one
 105  * relative to the minimum year allowed by the hardware.
 106  *
 107  * The year range is 1970 - 2033. This range is selected to match Allwinner's
 108  * driver, even though it is somewhat limited.
 109  */
 110 #define SUN6I_YEAR_MIN                          1970
 111 #define SUN6I_YEAR_MAX                          2033
 112 #define SUN6I_YEAR_OFF                          (SUN6I_YEAR_MIN - 1900)
 113 
 114 /*
 115  * There are other differences between models, including:
 116  *
 117  *   - number of GPIO pins that can be configured to hold a certain level
 118  *   - crypto-key related registers (H5, H6)
 119  *   - boot process related (super standby, secondary processor entry address)
 120  *     registers (R40, H6)
 121  *   - SYS power domain controls (R40)
 122  *   - DCXO controls (H6)
 123  *   - RC oscillator calibration (H6)
 124  *
 125  * These functions are not covered by this driver.
 126  */
 127 struct sun6i_rtc_clk_data {
 128         unsigned long rc_osc_rate;
 129         unsigned int fixed_prescaler : 16;
 130         unsigned int has_prescaler : 1;
 131         unsigned int has_out_clk : 1;
 132         unsigned int export_iosc : 1;
 133         unsigned int has_losc_en : 1;
 134         unsigned int has_auto_swt : 1;
 135 };
 136 
 137 struct sun6i_rtc_dev {
 138         struct rtc_device *rtc;
 139         struct device *dev;
 140         const struct sun6i_rtc_clk_data *data;
 141         void __iomem *base;
 142         int irq;
 143         unsigned long alarm;
 144 
 145         struct clk_hw hw;
 146         struct clk_hw *int_osc;
 147         struct clk *losc;
 148         struct clk *ext_losc;
 149 
 150         spinlock_t lock;
 151 };
 152 
 153 static struct sun6i_rtc_dev *sun6i_rtc;
 154 
 155 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
 156                                                unsigned long parent_rate)
 157 {
 158         struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
 159         u32 val = 0;
 160 
 161         val = readl(rtc->base + SUN6I_LOSC_CTRL);
 162         if (val & SUN6I_LOSC_CTRL_EXT_OSC)
 163                 return parent_rate;
 164 
 165         if (rtc->data->fixed_prescaler)
 166                 parent_rate /= rtc->data->fixed_prescaler;
 167 
 168         if (rtc->data->has_prescaler) {
 169                 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
 170                 val &= GENMASK(4, 0);
 171         }
 172 
 173         return parent_rate / (val + 1);
 174 }
 175 
 176 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
 177 {
 178         struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
 179 
 180         return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
 181 }
 182 
 183 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
 184 {
 185         struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
 186         unsigned long flags;
 187         u32 val;
 188 
 189         if (index > 1)
 190                 return -EINVAL;
 191 
 192         spin_lock_irqsave(&rtc->lock, flags);
 193         val = readl(rtc->base + SUN6I_LOSC_CTRL);
 194         val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
 195         val |= SUN6I_LOSC_CTRL_KEY;
 196         val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
 197         if (rtc->data->has_losc_en) {
 198                 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN;
 199                 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0;
 200         }
 201         writel(val, rtc->base + SUN6I_LOSC_CTRL);
 202         spin_unlock_irqrestore(&rtc->lock, flags);
 203 
 204         return 0;
 205 }
 206 
 207 static const struct clk_ops sun6i_rtc_osc_ops = {
 208         .recalc_rate    = sun6i_rtc_osc_recalc_rate,
 209 
 210         .get_parent     = sun6i_rtc_osc_get_parent,
 211         .set_parent     = sun6i_rtc_osc_set_parent,
 212 };
 213 
 214 static void __init sun6i_rtc_clk_init(struct device_node *node,
 215                                       const struct sun6i_rtc_clk_data *data)
 216 {
 217         struct clk_hw_onecell_data *clk_data;
 218         struct sun6i_rtc_dev *rtc;
 219         struct clk_init_data init = {
 220                 .ops            = &sun6i_rtc_osc_ops,
 221                 .name           = "losc",
 222         };
 223         const char *iosc_name = "rtc-int-osc";
 224         const char *clkout_name = "osc32k-out";
 225         const char *parents[2];
 226         u32 reg;
 227 
 228         rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
 229         if (!rtc)
 230                 return;
 231 
 232         rtc->data = data;
 233         clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL);
 234         if (!clk_data) {
 235                 kfree(rtc);
 236                 return;
 237         }
 238 
 239         spin_lock_init(&rtc->lock);
 240 
 241         rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
 242         if (IS_ERR(rtc->base)) {
 243                 pr_crit("Can't map RTC registers");
 244                 goto err;
 245         }
 246 
 247         reg = SUN6I_LOSC_CTRL_KEY;
 248         if (rtc->data->has_auto_swt) {
 249                 /* Bypass auto-switch to int osc, on ext losc failure */
 250                 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS;
 251                 writel(reg, rtc->base + SUN6I_LOSC_CTRL);
 252         }
 253 
 254         /* Switch to the external, more precise, oscillator */
 255         reg |= SUN6I_LOSC_CTRL_EXT_OSC;
 256         if (rtc->data->has_losc_en)
 257                 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
 258         writel(reg, rtc->base + SUN6I_LOSC_CTRL);
 259 
 260         /* Yes, I know, this is ugly. */
 261         sun6i_rtc = rtc;
 262 
 263         /* Deal with old DTs */
 264         if (!of_get_property(node, "clocks", NULL))
 265                 goto err;
 266 
 267         /* Only read IOSC name from device tree if it is exported */
 268         if (rtc->data->export_iosc)
 269                 of_property_read_string_index(node, "clock-output-names", 2,
 270                                               &iosc_name);
 271 
 272         rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
 273                                                                 iosc_name,
 274                                                                 NULL, 0,
 275                                                                 rtc->data->rc_osc_rate,
 276                                                                 300000000);
 277         if (IS_ERR(rtc->int_osc)) {
 278                 pr_crit("Couldn't register the internal oscillator\n");
 279                 return;
 280         }
 281 
 282         parents[0] = clk_hw_get_name(rtc->int_osc);
 283         parents[1] = of_clk_get_parent_name(node, 0);
 284 
 285         rtc->hw.init = &init;
 286 
 287         init.parent_names = parents;
 288         init.num_parents = of_clk_get_parent_count(node) + 1;
 289         of_property_read_string_index(node, "clock-output-names", 0,
 290                                       &init.name);
 291 
 292         rtc->losc = clk_register(NULL, &rtc->hw);
 293         if (IS_ERR(rtc->losc)) {
 294                 pr_crit("Couldn't register the LOSC clock\n");
 295                 return;
 296         }
 297 
 298         of_property_read_string_index(node, "clock-output-names", 1,
 299                                       &clkout_name);
 300         rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
 301                                           0, rtc->base + SUN6I_LOSC_OUT_GATING,
 302                                           SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
 303                                           &rtc->lock);
 304         if (IS_ERR(rtc->ext_losc)) {
 305                 pr_crit("Couldn't register the LOSC external gate\n");
 306                 return;
 307         }
 308 
 309         clk_data->num = 2;
 310         clk_data->hws[0] = &rtc->hw;
 311         clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
 312         if (rtc->data->export_iosc) {
 313                 clk_data->hws[2] = rtc->int_osc;
 314                 clk_data->num = 3;
 315         }
 316         of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 317         return;
 318 
 319 err:
 320         kfree(clk_data);
 321 }
 322 
 323 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {
 324         .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
 325         .has_prescaler = 1,
 326 };
 327 
 328 static void __init sun6i_a31_rtc_clk_init(struct device_node *node)
 329 {
 330         sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);
 331 }
 332 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",
 333                       sun6i_a31_rtc_clk_init);
 334 
 335 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {
 336         .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
 337         .has_prescaler = 1,
 338         .has_out_clk = 1,
 339 };
 340 
 341 static void __init sun8i_a23_rtc_clk_init(struct device_node *node)
 342 {
 343         sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);
 344 }
 345 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",
 346                       sun8i_a23_rtc_clk_init);
 347 
 348 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {
 349         .rc_osc_rate = 16000000,
 350         .fixed_prescaler = 32,
 351         .has_prescaler = 1,
 352         .has_out_clk = 1,
 353         .export_iosc = 1,
 354 };
 355 
 356 static void __init sun8i_h3_rtc_clk_init(struct device_node *node)
 357 {
 358         sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);
 359 }
 360 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
 361                       sun8i_h3_rtc_clk_init);
 362 /* As far as we are concerned, clocks for H5 are the same as H3 */
 363 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
 364                       sun8i_h3_rtc_clk_init);
 365 
 366 static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {
 367         .rc_osc_rate = 16000000,
 368         .fixed_prescaler = 32,
 369         .has_prescaler = 1,
 370         .has_out_clk = 1,
 371         .export_iosc = 1,
 372         .has_losc_en = 1,
 373         .has_auto_swt = 1,
 374 };
 375 
 376 static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
 377 {
 378         sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);
 379 }
 380 CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
 381                       sun50i_h6_rtc_clk_init);
 382 
 383 /*
 384  * The R40 user manual is self-conflicting on whether the prescaler is
 385  * fixed or configurable. The clock diagram shows it as fixed, but there
 386  * is also a configurable divider in the RTC block.
 387  */
 388 static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = {
 389         .rc_osc_rate = 16000000,
 390         .fixed_prescaler = 512,
 391 };
 392 static void __init sun8i_r40_rtc_clk_init(struct device_node *node)
 393 {
 394         sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data);
 395 }
 396 CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc",
 397                       sun8i_r40_rtc_clk_init);
 398 
 399 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
 400         .rc_osc_rate = 32000,
 401         .has_out_clk = 1,
 402 };
 403 
 404 static void __init sun8i_v3_rtc_clk_init(struct device_node *node)
 405 {
 406         sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);
 407 }
 408 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",
 409                       sun8i_v3_rtc_clk_init);
 410 
 411 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
 412 {
 413         struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
 414         irqreturn_t ret = IRQ_NONE;
 415         u32 val;
 416 
 417         spin_lock(&chip->lock);
 418         val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
 419 
 420         if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
 421                 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
 422                 writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
 423 
 424                 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
 425 
 426                 ret = IRQ_HANDLED;
 427         }
 428         spin_unlock(&chip->lock);
 429 
 430         return ret;
 431 }
 432 
 433 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
 434 {
 435         u32 alrm_val = 0;
 436         u32 alrm_irq_val = 0;
 437         u32 alrm_wake_val = 0;
 438         unsigned long flags;
 439 
 440         if (to) {
 441                 alrm_val = SUN6I_ALRM_EN_CNT_EN;
 442                 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
 443                 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
 444         } else {
 445                 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
 446                        chip->base + SUN6I_ALRM_IRQ_STA);
 447         }
 448 
 449         spin_lock_irqsave(&chip->lock, flags);
 450         writel(alrm_val, chip->base + SUN6I_ALRM_EN);
 451         writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
 452         writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
 453         spin_unlock_irqrestore(&chip->lock, flags);
 454 }
 455 
 456 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
 457 {
 458         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 459         u32 date, time;
 460 
 461         /*
 462          * read again in case it changes
 463          */
 464         do {
 465                 date = readl(chip->base + SUN6I_RTC_YMD);
 466                 time = readl(chip->base + SUN6I_RTC_HMS);
 467         } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
 468                  (time != readl(chip->base + SUN6I_RTC_HMS)));
 469 
 470         rtc_tm->tm_sec  = SUN6I_TIME_GET_SEC_VALUE(time);
 471         rtc_tm->tm_min  = SUN6I_TIME_GET_MIN_VALUE(time);
 472         rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
 473 
 474         rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
 475         rtc_tm->tm_mon  = SUN6I_DATE_GET_MON_VALUE(date);
 476         rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
 477 
 478         rtc_tm->tm_mon  -= 1;
 479 
 480         /*
 481          * switch from (data_year->min)-relative offset to
 482          * a (1900)-relative one
 483          */
 484         rtc_tm->tm_year += SUN6I_YEAR_OFF;
 485 
 486         return 0;
 487 }
 488 
 489 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
 490 {
 491         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 492         unsigned long flags;
 493         u32 alrm_st;
 494         u32 alrm_en;
 495 
 496         spin_lock_irqsave(&chip->lock, flags);
 497         alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
 498         alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
 499         spin_unlock_irqrestore(&chip->lock, flags);
 500 
 501         wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
 502         wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
 503         rtc_time_to_tm(chip->alarm, &wkalrm->time);
 504 
 505         return 0;
 506 }
 507 
 508 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
 509 {
 510         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 511         struct rtc_time *alrm_tm = &wkalrm->time;
 512         struct rtc_time tm_now;
 513         unsigned long time_now = 0;
 514         unsigned long time_set = 0;
 515         unsigned long time_gap = 0;
 516         int ret = 0;
 517 
 518         ret = sun6i_rtc_gettime(dev, &tm_now);
 519         if (ret < 0) {
 520                 dev_err(dev, "Error in getting time\n");
 521                 return -EINVAL;
 522         }
 523 
 524         rtc_tm_to_time(alrm_tm, &time_set);
 525         rtc_tm_to_time(&tm_now, &time_now);
 526         if (time_set <= time_now) {
 527                 dev_err(dev, "Date to set in the past\n");
 528                 return -EINVAL;
 529         }
 530 
 531         time_gap = time_set - time_now;
 532 
 533         if (time_gap > U32_MAX) {
 534                 dev_err(dev, "Date too far in the future\n");
 535                 return -EINVAL;
 536         }
 537 
 538         sun6i_rtc_setaie(0, chip);
 539         writel(0, chip->base + SUN6I_ALRM_COUNTER);
 540         usleep_range(100, 300);
 541 
 542         writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
 543         chip->alarm = time_set;
 544 
 545         sun6i_rtc_setaie(wkalrm->enabled, chip);
 546 
 547         return 0;
 548 }
 549 
 550 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
 551                           unsigned int mask, unsigned int ms_timeout)
 552 {
 553         const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
 554         u32 reg;
 555 
 556         do {
 557                 reg = readl(chip->base + offset);
 558                 reg &= mask;
 559 
 560                 if (!reg)
 561                         return 0;
 562 
 563         } while (time_before(jiffies, timeout));
 564 
 565         return -ETIMEDOUT;
 566 }
 567 
 568 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
 569 {
 570         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 571         u32 date = 0;
 572         u32 time = 0;
 573         int year;
 574 
 575         year = rtc_tm->tm_year + 1900;
 576         if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) {
 577                 dev_err(dev, "rtc only supports year in range %d - %d\n",
 578                         SUN6I_YEAR_MIN, SUN6I_YEAR_MAX);
 579                 return -EINVAL;
 580         }
 581 
 582         rtc_tm->tm_year -= SUN6I_YEAR_OFF;
 583         rtc_tm->tm_mon += 1;
 584 
 585         date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
 586                 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon)  |
 587                 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
 588 
 589         if (is_leap_year(year))
 590                 date |= SUN6I_LEAP_SET_VALUE(1);
 591 
 592         time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec)  |
 593                 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min)  |
 594                 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
 595 
 596         /* Check whether registers are writable */
 597         if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
 598                            SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
 599                 dev_err(dev, "rtc is still busy.\n");
 600                 return -EBUSY;
 601         }
 602 
 603         writel(time, chip->base + SUN6I_RTC_HMS);
 604 
 605         /*
 606          * After writing the RTC HH-MM-SS register, the
 607          * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
 608          * be cleared until the real writing operation is finished
 609          */
 610 
 611         if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
 612                            SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
 613                 dev_err(dev, "Failed to set rtc time.\n");
 614                 return -ETIMEDOUT;
 615         }
 616 
 617         writel(date, chip->base + SUN6I_RTC_YMD);
 618 
 619         /*
 620          * After writing the RTC YY-MM-DD register, the
 621          * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
 622          * be cleared until the real writing operation is finished
 623          */
 624 
 625         if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
 626                            SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
 627                 dev_err(dev, "Failed to set rtc time.\n");
 628                 return -ETIMEDOUT;
 629         }
 630 
 631         return 0;
 632 }
 633 
 634 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 635 {
 636         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 637 
 638         if (!enabled)
 639                 sun6i_rtc_setaie(enabled, chip);
 640 
 641         return 0;
 642 }
 643 
 644 static const struct rtc_class_ops sun6i_rtc_ops = {
 645         .read_time              = sun6i_rtc_gettime,
 646         .set_time               = sun6i_rtc_settime,
 647         .read_alarm             = sun6i_rtc_getalarm,
 648         .set_alarm              = sun6i_rtc_setalarm,
 649         .alarm_irq_enable       = sun6i_rtc_alarm_irq_enable
 650 };
 651 
 652 #ifdef CONFIG_PM_SLEEP
 653 /* Enable IRQ wake on suspend, to wake up from RTC. */
 654 static int sun6i_rtc_suspend(struct device *dev)
 655 {
 656         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 657 
 658         if (device_may_wakeup(dev))
 659                 enable_irq_wake(chip->irq);
 660 
 661         return 0;
 662 }
 663 
 664 /* Disable IRQ wake on resume. */
 665 static int sun6i_rtc_resume(struct device *dev)
 666 {
 667         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 668 
 669         if (device_may_wakeup(dev))
 670                 disable_irq_wake(chip->irq);
 671 
 672         return 0;
 673 }
 674 #endif
 675 
 676 static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
 677         sun6i_rtc_suspend, sun6i_rtc_resume);
 678 
 679 static int sun6i_rtc_probe(struct platform_device *pdev)
 680 {
 681         struct sun6i_rtc_dev *chip = sun6i_rtc;
 682         int ret;
 683 
 684         if (!chip)
 685                 return -ENODEV;
 686 
 687         platform_set_drvdata(pdev, chip);
 688         chip->dev = &pdev->dev;
 689 
 690         chip->irq = platform_get_irq(pdev, 0);
 691         if (chip->irq < 0)
 692                 return chip->irq;
 693 
 694         ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
 695                                0, dev_name(&pdev->dev), chip);
 696         if (ret) {
 697                 dev_err(&pdev->dev, "Could not request IRQ\n");
 698                 return ret;
 699         }
 700 
 701         /* clear the alarm counter value */
 702         writel(0, chip->base + SUN6I_ALRM_COUNTER);
 703 
 704         /* disable counter alarm */
 705         writel(0, chip->base + SUN6I_ALRM_EN);
 706 
 707         /* disable counter alarm interrupt */
 708         writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
 709 
 710         /* disable week alarm */
 711         writel(0, chip->base + SUN6I_ALRM1_EN);
 712 
 713         /* disable week alarm interrupt */
 714         writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
 715 
 716         /* clear counter alarm pending interrupts */
 717         writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
 718                chip->base + SUN6I_ALRM_IRQ_STA);
 719 
 720         /* clear week alarm pending interrupts */
 721         writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
 722                chip->base + SUN6I_ALRM1_IRQ_STA);
 723 
 724         /* disable alarm wakeup */
 725         writel(0, chip->base + SUN6I_ALARM_CONFIG);
 726 
 727         clk_prepare_enable(chip->losc);
 728 
 729         device_init_wakeup(&pdev->dev, 1);
 730 
 731         chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-sun6i",
 732                                              &sun6i_rtc_ops, THIS_MODULE);
 733         if (IS_ERR(chip->rtc)) {
 734                 dev_err(&pdev->dev, "unable to register device\n");
 735                 return PTR_ERR(chip->rtc);
 736         }
 737 
 738         dev_info(&pdev->dev, "RTC enabled\n");
 739 
 740         return 0;
 741 }
 742 
 743 /*
 744  * As far as RTC functionality goes, all models are the same. The
 745  * datasheets claim that different models have different number of
 746  * registers available for non-volatile storage, but experiments show
 747  * that all SoCs have 16 registers available for this purpose.
 748  */
 749 static const struct of_device_id sun6i_rtc_dt_ids[] = {
 750         { .compatible = "allwinner,sun6i-a31-rtc" },
 751         { .compatible = "allwinner,sun8i-a23-rtc" },
 752         { .compatible = "allwinner,sun8i-h3-rtc" },
 753         { .compatible = "allwinner,sun8i-r40-rtc" },
 754         { .compatible = "allwinner,sun8i-v3-rtc" },
 755         { .compatible = "allwinner,sun50i-h5-rtc" },
 756         { .compatible = "allwinner,sun50i-h6-rtc" },
 757         { /* sentinel */ },
 758 };
 759 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
 760 
 761 static struct platform_driver sun6i_rtc_driver = {
 762         .probe          = sun6i_rtc_probe,
 763         .driver         = {
 764                 .name           = "sun6i-rtc",
 765                 .of_match_table = sun6i_rtc_dt_ids,
 766                 .pm = &sun6i_rtc_pm_ops,
 767         },
 768 };
 769 builtin_platform_driver(sun6i_rtc_driver);
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root/drivers/rtc/rtc-sun6i.c

DEFINITIONS
