drivers/rtc/rtc-rp5c01.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
rp5c01_read
rp5c01_write
rp5c01_lock
rp5c01_unlock
rp5c01_read_time
rp5c01_set_time
rp5c01_nvram_read
rp5c01_nvram_write
rp5c01_rtc_probe
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Ricoh RP5C01 RTC Driver
   4  *
   5  *  Copyright 2009 Geert Uytterhoeven
   6  *
   7  *  Based on the A3000 TOD code in arch/m68k/amiga/config.c
   8  *  Copyright (C) 1993 Hamish Macdonald
   9  */
  10 
  11 #include <linux/io.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/rtc.h>
  16 #include <linux/slab.h>
  17 
  18 
  19 enum {
  20         RP5C01_1_SECOND         = 0x0,  /* MODE 00 */
  21         RP5C01_10_SECOND        = 0x1,  /* MODE 00 */
  22         RP5C01_1_MINUTE         = 0x2,  /* MODE 00 and MODE 01 */
  23         RP5C01_10_MINUTE        = 0x3,  /* MODE 00 and MODE 01 */
  24         RP5C01_1_HOUR           = 0x4,  /* MODE 00 and MODE 01 */
  25         RP5C01_10_HOUR          = 0x5,  /* MODE 00 and MODE 01 */
  26         RP5C01_DAY_OF_WEEK      = 0x6,  /* MODE 00 and MODE 01 */
  27         RP5C01_1_DAY            = 0x7,  /* MODE 00 and MODE 01 */
  28         RP5C01_10_DAY           = 0x8,  /* MODE 00 and MODE 01 */
  29         RP5C01_1_MONTH          = 0x9,  /* MODE 00 */
  30         RP5C01_10_MONTH         = 0xa,  /* MODE 00 */
  31         RP5C01_1_YEAR           = 0xb,  /* MODE 00 */
  32         RP5C01_10_YEAR          = 0xc,  /* MODE 00 */
  33 
  34         RP5C01_12_24_SELECT     = 0xa,  /* MODE 01 */
  35         RP5C01_LEAP_YEAR        = 0xb,  /* MODE 01 */
  36 
  37         RP5C01_MODE             = 0xd,  /* all modes */
  38         RP5C01_TEST             = 0xe,  /* all modes */
  39         RP5C01_RESET            = 0xf,  /* all modes */
  40 };
  41 
  42 #define RP5C01_12_24_SELECT_12  (0 << 0)
  43 #define RP5C01_12_24_SELECT_24  (1 << 0)
  44 
  45 #define RP5C01_10_HOUR_AM       (0 << 1)
  46 #define RP5C01_10_HOUR_PM       (1 << 1)
  47 
  48 #define RP5C01_MODE_TIMER_EN    (1 << 3)        /* timer enable */
  49 #define RP5C01_MODE_ALARM_EN    (1 << 2)        /* alarm enable */
  50 
  51 #define RP5C01_MODE_MODE_MASK   (3 << 0)
  52 #define RP5C01_MODE_MODE00      (0 << 0)        /* time */
  53 #define RP5C01_MODE_MODE01      (1 << 0)        /* alarm, 12h/24h, leap year */
  54 #define RP5C01_MODE_RAM_BLOCK10 (2 << 0)        /* RAM 4 bits x 13 */
  55 #define RP5C01_MODE_RAM_BLOCK11 (3 << 0)        /* RAM 4 bits x 13 */
  56 
  57 #define RP5C01_RESET_1HZ_PULSE  (1 << 3)
  58 #define RP5C01_RESET_16HZ_PULSE (1 << 2)
  59 #define RP5C01_RESET_SECOND     (1 << 1)        /* reset divider stages for */
  60                                                 /* seconds or smaller units */
  61 #define RP5C01_RESET_ALARM      (1 << 0)        /* reset all alarm registers */
  62 
  63 
  64 struct rp5c01_priv {
  65         u32 __iomem *regs;
  66         struct rtc_device *rtc;
  67         spinlock_t lock;        /* against concurrent RTC/NVRAM access */
  68 };
  69 
  70 static inline unsigned int rp5c01_read(struct rp5c01_priv *priv,
  71                                        unsigned int reg)
  72 {
  73         return __raw_readl(&priv->regs[reg]) & 0xf;
  74 }
  75 
  76 static inline void rp5c01_write(struct rp5c01_priv *priv, unsigned int val,
  77                                 unsigned int reg)
  78 {
  79         __raw_writel(val, &priv->regs[reg]);
  80 }
  81 
  82 static void rp5c01_lock(struct rp5c01_priv *priv)
  83 {
  84         rp5c01_write(priv, RP5C01_MODE_MODE00, RP5C01_MODE);
  85 }
  86 
  87 static void rp5c01_unlock(struct rp5c01_priv *priv)
  88 {
  89         rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
  90                      RP5C01_MODE);
  91 }
  92 
  93 static int rp5c01_read_time(struct device *dev, struct rtc_time *tm)
  94 {
  95         struct rp5c01_priv *priv = dev_get_drvdata(dev);
  96 
  97         spin_lock_irq(&priv->lock);
  98         rp5c01_lock(priv);
  99 
 100         tm->tm_sec  = rp5c01_read(priv, RP5C01_10_SECOND) * 10 +
 101                       rp5c01_read(priv, RP5C01_1_SECOND);
 102         tm->tm_min  = rp5c01_read(priv, RP5C01_10_MINUTE) * 10 +
 103                       rp5c01_read(priv, RP5C01_1_MINUTE);
 104         tm->tm_hour = rp5c01_read(priv, RP5C01_10_HOUR) * 10 +
 105                       rp5c01_read(priv, RP5C01_1_HOUR);
 106         tm->tm_mday = rp5c01_read(priv, RP5C01_10_DAY) * 10 +
 107                       rp5c01_read(priv, RP5C01_1_DAY);
 108         tm->tm_wday = rp5c01_read(priv, RP5C01_DAY_OF_WEEK);
 109         tm->tm_mon  = rp5c01_read(priv, RP5C01_10_MONTH) * 10 +
 110                       rp5c01_read(priv, RP5C01_1_MONTH) - 1;
 111         tm->tm_year = rp5c01_read(priv, RP5C01_10_YEAR) * 10 +
 112                       rp5c01_read(priv, RP5C01_1_YEAR);
 113         if (tm->tm_year <= 69)
 114                 tm->tm_year += 100;
 115 
 116         rp5c01_unlock(priv);
 117         spin_unlock_irq(&priv->lock);
 118 
 119         return 0;
 120 }
 121 
 122 static int rp5c01_set_time(struct device *dev, struct rtc_time *tm)
 123 {
 124         struct rp5c01_priv *priv = dev_get_drvdata(dev);
 125 
 126         spin_lock_irq(&priv->lock);
 127         rp5c01_lock(priv);
 128 
 129         rp5c01_write(priv, tm->tm_sec / 10, RP5C01_10_SECOND);
 130         rp5c01_write(priv, tm->tm_sec % 10, RP5C01_1_SECOND);
 131         rp5c01_write(priv, tm->tm_min / 10, RP5C01_10_MINUTE);
 132         rp5c01_write(priv, tm->tm_min % 10, RP5C01_1_MINUTE);
 133         rp5c01_write(priv, tm->tm_hour / 10, RP5C01_10_HOUR);
 134         rp5c01_write(priv, tm->tm_hour % 10, RP5C01_1_HOUR);
 135         rp5c01_write(priv, tm->tm_mday / 10, RP5C01_10_DAY);
 136         rp5c01_write(priv, tm->tm_mday % 10, RP5C01_1_DAY);
 137         if (tm->tm_wday != -1)
 138                 rp5c01_write(priv, tm->tm_wday, RP5C01_DAY_OF_WEEK);
 139         rp5c01_write(priv, (tm->tm_mon + 1) / 10, RP5C01_10_MONTH);
 140         rp5c01_write(priv, (tm->tm_mon + 1) % 10, RP5C01_1_MONTH);
 141         if (tm->tm_year >= 100)
 142                 tm->tm_year -= 100;
 143         rp5c01_write(priv, tm->tm_year / 10, RP5C01_10_YEAR);
 144         rp5c01_write(priv, tm->tm_year % 10, RP5C01_1_YEAR);
 145 
 146         rp5c01_unlock(priv);
 147         spin_unlock_irq(&priv->lock);
 148         return 0;
 149 }
 150 
 151 static const struct rtc_class_ops rp5c01_rtc_ops = {
 152         .read_time      = rp5c01_read_time,
 153         .set_time       = rp5c01_set_time,
 154 };
 155 
 156 
 157 /*
 158  * The NVRAM is organized as 2 blocks of 13 nibbles of 4 bits.
 159  * We provide access to them like AmigaOS does: the high nibble of each 8-bit
 160  * byte is stored in BLOCK10, the low nibble in BLOCK11.
 161  */
 162 
 163 static int rp5c01_nvram_read(void *_priv, unsigned int pos, void *val,
 164                              size_t bytes)
 165 {
 166         struct rp5c01_priv *priv = _priv;
 167         u8 *buf = val;
 168 
 169         spin_lock_irq(&priv->lock);
 170 
 171         for (; bytes; bytes--) {
 172                 u8 data;
 173 
 174                 rp5c01_write(priv,
 175                              RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK10,
 176                              RP5C01_MODE);
 177                 data = rp5c01_read(priv, pos) << 4;
 178                 rp5c01_write(priv,
 179                              RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK11,
 180                              RP5C01_MODE);
 181                 data |= rp5c01_read(priv, pos++);
 182                 rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
 183                              RP5C01_MODE);
 184                 *buf++ = data;
 185         }
 186 
 187         spin_unlock_irq(&priv->lock);
 188         return 0;
 189 }
 190 
 191 static int rp5c01_nvram_write(void *_priv, unsigned int pos, void *val,
 192                               size_t bytes)
 193 {
 194         struct rp5c01_priv *priv = _priv;
 195         u8 *buf = val;
 196 
 197         spin_lock_irq(&priv->lock);
 198 
 199         for (; bytes; bytes--) {
 200                 u8 data = *buf++;
 201 
 202                 rp5c01_write(priv,
 203                              RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK10,
 204                              RP5C01_MODE);
 205                 rp5c01_write(priv, data >> 4, pos);
 206                 rp5c01_write(priv,
 207                              RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK11,
 208                              RP5C01_MODE);
 209                 rp5c01_write(priv, data & 0xf, pos++);
 210                 rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
 211                              RP5C01_MODE);
 212         }
 213 
 214         spin_unlock_irq(&priv->lock);
 215         return 0;
 216 }
 217 
 218 static int __init rp5c01_rtc_probe(struct platform_device *dev)
 219 {
 220         struct resource *res;
 221         struct rp5c01_priv *priv;
 222         struct rtc_device *rtc;
 223         int error;
 224         struct nvmem_config nvmem_cfg = {
 225                 .name = "rp5c01_nvram",
 226                 .word_size = 1,
 227                 .stride = 1,
 228                 .size = RP5C01_MODE,
 229                 .reg_read = rp5c01_nvram_read,
 230                 .reg_write = rp5c01_nvram_write,
 231         };
 232 
 233         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 234         if (!res)
 235                 return -ENODEV;
 236 
 237         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
 238         if (!priv)
 239                 return -ENOMEM;
 240 
 241         priv->regs = devm_ioremap(&dev->dev, res->start, resource_size(res));
 242         if (!priv->regs)
 243                 return -ENOMEM;
 244 
 245         spin_lock_init(&priv->lock);
 246 
 247         platform_set_drvdata(dev, priv);
 248 
 249         rtc = devm_rtc_allocate_device(&dev->dev);
 250         if (IS_ERR(rtc))
 251                 return PTR_ERR(rtc);
 252 
 253         rtc->ops = &rp5c01_rtc_ops;
 254         rtc->nvram_old_abi = true;
 255 
 256         priv->rtc = rtc;
 257 
 258         nvmem_cfg.priv = priv;
 259         error = rtc_nvmem_register(rtc, &nvmem_cfg);
 260         if (error)
 261                 return error;
 262 
 263         return rtc_register_device(rtc);
 264 }
 265 
 266 static struct platform_driver rp5c01_rtc_driver = {
 267         .driver = {
 268                 .name   = "rtc-rp5c01",
 269         },
 270 };
 271 
 272 module_platform_driver_probe(rp5c01_rtc_driver, rp5c01_rtc_probe);
 273 
 274 MODULE_AUTHOR("Geert Uytterhoeven <geert@linux-m68k.org>");
 275 MODULE_LICENSE("GPL");
 276 MODULE_DESCRIPTION("Ricoh RP5C01 RTC driver");
 277 MODULE_ALIAS("platform:rtc-rp5c01");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/rtc/rtc-rp5c01.c

DEFINITIONS
