drivers/i2c/busses/i2c-stu300.c

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This source file includes following definitions.
stu300_wr8
stu300_r8
stu300_irq_enable
stu300_irq_disable
stu300_event_occurred
stu300_irh
stu300_start_and_await_event
stu300_await_event
stu300_wait_while_busy
stu300_set_clk
stu300_init_hw
stu300_send_address
stu300_xfer_msg
stu300_xfer
stu300_xfer_todo
stu300_func
stu300_probe
stu300_suspend
stu300_resume
stu300_remove
stu300_init
stu300_exit
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2007-2012 ST-Ericsson AB
   4  * ST DDC I2C master mode driver, used in e.g. U300 series platforms.
   5  * Author: Linus Walleij <linus.walleij@stericsson.com>
   6  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
   7  */
   8 #include <linux/init.h>
   9 #include <linux/module.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/delay.h>
  12 #include <linux/i2c.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/completion.h>
  15 #include <linux/err.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/clk.h>
  18 #include <linux/io.h>
  19 #include <linux/slab.h>
  20 
  21 /* the name of this kernel module */
  22 #define NAME "stu300"
  23 
  24 /* CR (Control Register) 8bit (R/W) */
  25 #define I2C_CR                                  (0x00000000)
  26 #define I2C_CR_RESET_VALUE                      (0x00)
  27 #define I2C_CR_RESET_UMASK                      (0x00)
  28 #define I2C_CR_DDC1_ENABLE                      (0x80)
  29 #define I2C_CR_TRANS_ENABLE                     (0x40)
  30 #define I2C_CR_PERIPHERAL_ENABLE                (0x20)
  31 #define I2C_CR_DDC2B_ENABLE                     (0x10)
  32 #define I2C_CR_START_ENABLE                     (0x08)
  33 #define I2C_CR_ACK_ENABLE                       (0x04)
  34 #define I2C_CR_STOP_ENABLE                      (0x02)
  35 #define I2C_CR_INTERRUPT_ENABLE                 (0x01)
  36 /* SR1 (Status Register 1) 8bit (R/-) */
  37 #define I2C_SR1                                 (0x00000004)
  38 #define I2C_SR1_RESET_VALUE                     (0x00)
  39 #define I2C_SR1_RESET_UMASK                     (0x00)
  40 #define I2C_SR1_EVF_IND                         (0x80)
  41 #define I2C_SR1_ADD10_IND                       (0x40)
  42 #define I2C_SR1_TRA_IND                         (0x20)
  43 #define I2C_SR1_BUSY_IND                        (0x10)
  44 #define I2C_SR1_BTF_IND                         (0x08)
  45 #define I2C_SR1_ADSL_IND                        (0x04)
  46 #define I2C_SR1_MSL_IND                         (0x02)
  47 #define I2C_SR1_SB_IND                          (0x01)
  48 /* SR2 (Status Register 2) 8bit (R/-) */
  49 #define I2C_SR2                                 (0x00000008)
  50 #define I2C_SR2_RESET_VALUE                     (0x00)
  51 #define I2C_SR2_RESET_UMASK                     (0x40)
  52 #define I2C_SR2_MASK                            (0xBF)
  53 #define I2C_SR2_SCLFAL_IND                      (0x80)
  54 #define I2C_SR2_ENDAD_IND                       (0x20)
  55 #define I2C_SR2_AF_IND                          (0x10)
  56 #define I2C_SR2_STOPF_IND                       (0x08)
  57 #define I2C_SR2_ARLO_IND                        (0x04)
  58 #define I2C_SR2_BERR_IND                        (0x02)
  59 #define I2C_SR2_DDC2BF_IND                      (0x01)
  60 /* CCR (Clock Control Register) 8bit (R/W) */
  61 #define I2C_CCR                                 (0x0000000C)
  62 #define I2C_CCR_RESET_VALUE                     (0x00)
  63 #define I2C_CCR_RESET_UMASK                     (0x00)
  64 #define I2C_CCR_MASK                            (0xFF)
  65 #define I2C_CCR_FMSM                            (0x80)
  66 #define I2C_CCR_CC_MASK                         (0x7F)
  67 /* OAR1 (Own Address Register 1) 8bit (R/W) */
  68 #define I2C_OAR1                                (0x00000010)
  69 #define I2C_OAR1_RESET_VALUE                    (0x00)
  70 #define I2C_OAR1_RESET_UMASK                    (0x00)
  71 #define I2C_OAR1_ADD_MASK                       (0xFF)
  72 /* OAR2 (Own Address Register 2) 8bit (R/W) */
  73 #define I2C_OAR2                                (0x00000014)
  74 #define I2C_OAR2_RESET_VALUE                    (0x40)
  75 #define I2C_OAR2_RESET_UMASK                    (0x19)
  76 #define I2C_OAR2_MASK                           (0xE6)
  77 #define I2C_OAR2_FR_25_10MHZ                    (0x00)
  78 #define I2C_OAR2_FR_10_1667MHZ                  (0x20)
  79 #define I2C_OAR2_FR_1667_2667MHZ                (0x40)
  80 #define I2C_OAR2_FR_2667_40MHZ                  (0x60)
  81 #define I2C_OAR2_FR_40_5333MHZ                  (0x80)
  82 #define I2C_OAR2_FR_5333_66MHZ                  (0xA0)
  83 #define I2C_OAR2_FR_66_80MHZ                    (0xC0)
  84 #define I2C_OAR2_FR_80_100MHZ                   (0xE0)
  85 #define I2C_OAR2_FR_MASK                        (0xE0)
  86 #define I2C_OAR2_ADD_MASK                       (0x06)
  87 /* DR (Data Register) 8bit (R/W) */
  88 #define I2C_DR                                  (0x00000018)
  89 #define I2C_DR_RESET_VALUE                      (0x00)
  90 #define I2C_DR_RESET_UMASK                      (0xFF)
  91 #define I2C_DR_D_MASK                           (0xFF)
  92 /* ECCR (Extended Clock Control Register) 8bit (R/W) */
  93 #define I2C_ECCR                                (0x0000001C)
  94 #define I2C_ECCR_RESET_VALUE                    (0x00)
  95 #define I2C_ECCR_RESET_UMASK                    (0xE0)
  96 #define I2C_ECCR_MASK                           (0x1F)
  97 #define I2C_ECCR_CC_MASK                        (0x1F)
  98 
  99 /*
 100  * These events are more or less responses to commands
 101  * sent into the hardware, presumably reflecting the state
 102  * of an internal state machine.
 103  */
 104 enum stu300_event {
 105         STU300_EVENT_NONE = 0,
 106         STU300_EVENT_1,
 107         STU300_EVENT_2,
 108         STU300_EVENT_3,
 109         STU300_EVENT_4,
 110         STU300_EVENT_5,
 111         STU300_EVENT_6,
 112         STU300_EVENT_7,
 113         STU300_EVENT_8,
 114         STU300_EVENT_9
 115 };
 116 
 117 enum stu300_error {
 118         STU300_ERROR_NONE = 0,
 119         STU300_ERROR_ACKNOWLEDGE_FAILURE,
 120         STU300_ERROR_BUS_ERROR,
 121         STU300_ERROR_ARBITRATION_LOST,
 122         STU300_ERROR_UNKNOWN
 123 };
 124 
 125 /* timeout waiting for the controller to respond */
 126 #define STU300_TIMEOUT (msecs_to_jiffies(1000))
 127 
 128 /*
 129  * The number of address send athemps tried before giving up.
 130  * If the first one fails it seems like 5 to 8 attempts are required.
 131  */
 132 #define NUM_ADDR_RESEND_ATTEMPTS 12
 133 
 134 /* I2C clock speed, in Hz 0-400kHz*/
 135 static unsigned int scl_frequency = 100000;
 136 module_param(scl_frequency, uint,  0644);
 137 
 138 /**
 139  * struct stu300_dev - the stu300 driver state holder
 140  * @pdev: parent platform device
 141  * @adapter: corresponding I2C adapter
 142  * @clk: hardware block clock
 143  * @irq: assigned interrupt line
 144  * @cmd_issue_lock: this locks the following cmd_ variables
 145  * @cmd_complete: acknowledge completion for an I2C command
 146  * @cmd_event: expected event coming in as a response to a command
 147  * @cmd_err: error code as response to a command
 148  * @speed: current bus speed in Hz
 149  * @msg_index: index of current message
 150  * @msg_len: length of current message
 151  */
 152 
 153 struct stu300_dev {
 154         struct platform_device  *pdev;
 155         struct i2c_adapter      adapter;
 156         void __iomem            *virtbase;
 157         struct clk              *clk;
 158         int                     irq;
 159         spinlock_t              cmd_issue_lock;
 160         struct completion       cmd_complete;
 161         enum stu300_event       cmd_event;
 162         enum stu300_error       cmd_err;
 163         unsigned int            speed;
 164         int                     msg_index;
 165         int                     msg_len;
 166 };
 167 
 168 /* Local forward function declarations */
 169 static int stu300_init_hw(struct stu300_dev *dev);
 170 
 171 /*
 172  * The block needs writes in both MSW and LSW in order
 173  * for all data lines to reach their destination.
 174  */
 175 static inline void stu300_wr8(u32 value, void __iomem *address)
 176 {
 177         writel((value << 16) | value, address);
 178 }
 179 
 180 /*
 181  * This merely masks off the duplicates which appear
 182  * in bytes 1-3. You _MUST_ use 32-bit bus access on this
 183  * device, else it will not work.
 184  */
 185 static inline u32 stu300_r8(void __iomem *address)
 186 {
 187         return readl(address) & 0x000000FFU;
 188 }
 189 
 190 static void stu300_irq_enable(struct stu300_dev *dev)
 191 {
 192         u32 val;
 193         val = stu300_r8(dev->virtbase + I2C_CR);
 194         val |= I2C_CR_INTERRUPT_ENABLE;
 195         /* Twice paranoia (possible HW glitch) */
 196         stu300_wr8(val, dev->virtbase + I2C_CR);
 197         stu300_wr8(val, dev->virtbase + I2C_CR);
 198 }
 199 
 200 static void stu300_irq_disable(struct stu300_dev *dev)
 201 {
 202         u32 val;
 203         val = stu300_r8(dev->virtbase + I2C_CR);
 204         val &= ~I2C_CR_INTERRUPT_ENABLE;
 205         /* Twice paranoia (possible HW glitch) */
 206         stu300_wr8(val, dev->virtbase + I2C_CR);
 207         stu300_wr8(val, dev->virtbase + I2C_CR);
 208 }
 209 
 210 
 211 /*
 212  * Tells whether a certain event or events occurred in
 213  * response to a command. The events represent states in
 214  * the internal state machine of the hardware. The events
 215  * are not very well described in the hardware
 216  * documentation and can only be treated as abstract state
 217  * machine states.
 218  *
 219  * @ret 0 = event has not occurred or unknown error, any
 220  * other value means the correct event occurred or an error.
 221  */
 222 
 223 static int stu300_event_occurred(struct stu300_dev *dev,
 224                                    enum stu300_event mr_event) {
 225         u32 status1;
 226         u32 status2;
 227 
 228         /* What event happened? */
 229         status1 = stu300_r8(dev->virtbase + I2C_SR1);
 230 
 231         if (!(status1 & I2C_SR1_EVF_IND))
 232                 /* No event at all */
 233                 return 0;
 234 
 235         status2 = stu300_r8(dev->virtbase + I2C_SR2);
 236 
 237         /* Block any multiple interrupts */
 238         stu300_irq_disable(dev);
 239 
 240         /* Check for errors first */
 241         if (status2 & I2C_SR2_AF_IND) {
 242                 dev->cmd_err = STU300_ERROR_ACKNOWLEDGE_FAILURE;
 243                 return 1;
 244         } else if (status2 & I2C_SR2_BERR_IND) {
 245                 dev->cmd_err = STU300_ERROR_BUS_ERROR;
 246                 return 1;
 247         } else if (status2 & I2C_SR2_ARLO_IND) {
 248                 dev->cmd_err = STU300_ERROR_ARBITRATION_LOST;
 249                 return 1;
 250         }
 251 
 252         switch (mr_event) {
 253         case STU300_EVENT_1:
 254                 if (status1 & I2C_SR1_ADSL_IND)
 255                         return 1;
 256                 break;
 257         case STU300_EVENT_2:
 258         case STU300_EVENT_3:
 259         case STU300_EVENT_7:
 260         case STU300_EVENT_8:
 261                 if (status1 & I2C_SR1_BTF_IND) {
 262                         return 1;
 263                 }
 264                 break;
 265         case STU300_EVENT_4:
 266                 if (status2 & I2C_SR2_STOPF_IND)
 267                         return 1;
 268                 break;
 269         case STU300_EVENT_5:
 270                 if (status1 & I2C_SR1_SB_IND)
 271                         /* Clear start bit */
 272                         return 1;
 273                 break;
 274         case STU300_EVENT_6:
 275                 if (status2 & I2C_SR2_ENDAD_IND) {
 276                         /* First check for any errors */
 277                         return 1;
 278                 }
 279                 break;
 280         case STU300_EVENT_9:
 281                 if (status1 & I2C_SR1_ADD10_IND)
 282                         return 1;
 283                 break;
 284         default:
 285                 break;
 286         }
 287         /* If we get here, we're on thin ice.
 288          * Here we are in a status where we have
 289          * gotten a response that does not match
 290          * what we requested.
 291          */
 292         dev->cmd_err = STU300_ERROR_UNKNOWN;
 293         dev_err(&dev->pdev->dev,
 294                 "Unhandled interrupt! %d sr1: 0x%x sr2: 0x%x\n",
 295                 mr_event, status1, status2);
 296         return 0;
 297 }
 298 
 299 static irqreturn_t stu300_irh(int irq, void *data)
 300 {
 301         struct stu300_dev *dev = data;
 302         int res;
 303 
 304         /* Just make sure that the block is clocked */
 305         clk_enable(dev->clk);
 306 
 307         /* See if this was what we were waiting for */
 308         spin_lock(&dev->cmd_issue_lock);
 309 
 310         res = stu300_event_occurred(dev, dev->cmd_event);
 311         if (res || dev->cmd_err != STU300_ERROR_NONE)
 312                 complete(&dev->cmd_complete);
 313 
 314         spin_unlock(&dev->cmd_issue_lock);
 315 
 316         clk_disable(dev->clk);
 317 
 318         return IRQ_HANDLED;
 319 }
 320 
 321 /*
 322  * Sends a command and then waits for the bits masked by *flagmask*
 323  * to go high or low by IRQ awaiting.
 324  */
 325 static int stu300_start_and_await_event(struct stu300_dev *dev,
 326                                           u8 cr_value,
 327                                           enum stu300_event mr_event)
 328 {
 329         int ret;
 330 
 331         /* Lock command issue, fill in an event we wait for */
 332         spin_lock_irq(&dev->cmd_issue_lock);
 333         init_completion(&dev->cmd_complete);
 334         dev->cmd_err = STU300_ERROR_NONE;
 335         dev->cmd_event = mr_event;
 336         spin_unlock_irq(&dev->cmd_issue_lock);
 337 
 338         /* Turn on interrupt, send command and wait. */
 339         cr_value |= I2C_CR_INTERRUPT_ENABLE;
 340         stu300_wr8(cr_value, dev->virtbase + I2C_CR);
 341         ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
 342                                                         STU300_TIMEOUT);
 343         if (ret < 0) {
 344                 dev_err(&dev->pdev->dev,
 345                        "wait_for_completion_interruptible_timeout() "
 346                        "returned %d waiting for event %04x\n", ret, mr_event);
 347                 return ret;
 348         }
 349 
 350         if (ret == 0) {
 351                 dev_err(&dev->pdev->dev, "controller timed out "
 352                        "waiting for event %d, reinit hardware\n", mr_event);
 353                 (void) stu300_init_hw(dev);
 354                 return -ETIMEDOUT;
 355         }
 356 
 357         if (dev->cmd_err != STU300_ERROR_NONE) {
 358                 dev_err(&dev->pdev->dev, "controller (start) "
 359                        "error %d waiting for event %d, reinit hardware\n",
 360                        dev->cmd_err, mr_event);
 361                 (void) stu300_init_hw(dev);
 362                 return -EIO;
 363         }
 364 
 365         return 0;
 366 }
 367 
 368 /*
 369  * This waits for a flag to be set, if it is not set on entry, an interrupt is
 370  * configured to wait for the flag using a completion.
 371  */
 372 static int stu300_await_event(struct stu300_dev *dev,
 373                                 enum stu300_event mr_event)
 374 {
 375         int ret;
 376 
 377         /* Is it already here? */
 378         spin_lock_irq(&dev->cmd_issue_lock);
 379         dev->cmd_err = STU300_ERROR_NONE;
 380         dev->cmd_event = mr_event;
 381 
 382         init_completion(&dev->cmd_complete);
 383 
 384         /* Turn on the I2C interrupt for current operation */
 385         stu300_irq_enable(dev);
 386 
 387         /* Unlock the command block and wait for the event to occur */
 388         spin_unlock_irq(&dev->cmd_issue_lock);
 389 
 390         ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
 391                                                         STU300_TIMEOUT);
 392         if (ret < 0) {
 393                 dev_err(&dev->pdev->dev,
 394                        "wait_for_completion_interruptible_timeout()"
 395                        "returned %d waiting for event %04x\n", ret, mr_event);
 396                 return ret;
 397         }
 398 
 399         if (ret == 0) {
 400                 if (mr_event != STU300_EVENT_6) {
 401                         dev_err(&dev->pdev->dev, "controller "
 402                                 "timed out waiting for event %d, reinit "
 403                                 "hardware\n", mr_event);
 404                         (void) stu300_init_hw(dev);
 405                 }
 406                 return -ETIMEDOUT;
 407         }
 408 
 409         if (dev->cmd_err != STU300_ERROR_NONE) {
 410                 if (mr_event != STU300_EVENT_6) {
 411                         dev_err(&dev->pdev->dev, "controller "
 412                                 "error (await_event) %d waiting for event %d, "
 413                                "reinit hardware\n", dev->cmd_err, mr_event);
 414                         (void) stu300_init_hw(dev);
 415                 }
 416                 return -EIO;
 417         }
 418 
 419         return 0;
 420 }
 421 
 422 /*
 423  * Waits for the busy bit to go low by repeated polling.
 424  */
 425 #define BUSY_RELEASE_ATTEMPTS 10
 426 static int stu300_wait_while_busy(struct stu300_dev *dev)
 427 {
 428         unsigned long timeout;
 429         int i;
 430 
 431         for (i = 0; i < BUSY_RELEASE_ATTEMPTS; i++) {
 432                 timeout = jiffies + STU300_TIMEOUT;
 433 
 434                 while (!time_after(jiffies, timeout)) {
 435                         /* Is not busy? */
 436                         if ((stu300_r8(dev->virtbase + I2C_SR1) &
 437                              I2C_SR1_BUSY_IND) == 0)
 438                                 return 0;
 439                         msleep(1);
 440                 }
 441 
 442                 dev_err(&dev->pdev->dev, "transaction timed out "
 443                         "waiting for device to be free (not busy). "
 444                        "Attempt: %d\n", i+1);
 445 
 446                 dev_err(&dev->pdev->dev, "base address = "
 447                         "0x%08x, reinit hardware\n", (u32) dev->virtbase);
 448 
 449                 (void) stu300_init_hw(dev);
 450         }
 451 
 452         dev_err(&dev->pdev->dev, "giving up after %d attempts "
 453                 "to reset the bus.\n",  BUSY_RELEASE_ATTEMPTS);
 454 
 455         return -ETIMEDOUT;
 456 }
 457 
 458 struct stu300_clkset {
 459         unsigned long rate;
 460         u32 setting;
 461 };
 462 
 463 static const struct stu300_clkset stu300_clktable[] = {
 464         { 0,         0xFFU },
 465         { 2500000,   I2C_OAR2_FR_25_10MHZ },
 466         { 10000000,  I2C_OAR2_FR_10_1667MHZ },
 467         { 16670000,  I2C_OAR2_FR_1667_2667MHZ },
 468         { 26670000,  I2C_OAR2_FR_2667_40MHZ },
 469         { 40000000,  I2C_OAR2_FR_40_5333MHZ },
 470         { 53330000,  I2C_OAR2_FR_5333_66MHZ },
 471         { 66000000,  I2C_OAR2_FR_66_80MHZ },
 472         { 80000000,  I2C_OAR2_FR_80_100MHZ },
 473         { 100000000, 0xFFU },
 474 };
 475 
 476 
 477 static int stu300_set_clk(struct stu300_dev *dev, unsigned long clkrate)
 478 {
 479 
 480         u32 val;
 481         int i = 0;
 482 
 483         /* Locate the appropriate clock setting */
 484         while (i < ARRAY_SIZE(stu300_clktable) - 1 &&
 485                stu300_clktable[i].rate < clkrate)
 486                 i++;
 487 
 488         if (stu300_clktable[i].setting == 0xFFU) {
 489                 dev_err(&dev->pdev->dev, "too %s clock rate requested "
 490                         "(%lu Hz).\n", i ? "high" : "low", clkrate);
 491                 return -EINVAL;
 492         }
 493 
 494         stu300_wr8(stu300_clktable[i].setting,
 495                    dev->virtbase + I2C_OAR2);
 496 
 497         dev_dbg(&dev->pdev->dev, "Clock rate %lu Hz, I2C bus speed %d Hz "
 498                 "virtbase %p\n", clkrate, dev->speed, dev->virtbase);
 499 
 500         if (dev->speed > 100000)
 501                 /* Fast Mode I2C */
 502                 val = ((clkrate/dev->speed) - 9)/3 + 1;
 503         else
 504                 /* Standard Mode I2C */
 505                 val = ((clkrate/dev->speed) - 7)/2 + 1;
 506 
 507         /* According to spec the divider must be > 2 */
 508         if (val < 0x002) {
 509                 dev_err(&dev->pdev->dev, "too low clock rate (%lu Hz).\n",
 510                         clkrate);
 511                 return -EINVAL;
 512         }
 513 
 514         /* We have 12 bits clock divider only! */
 515         if (val & 0xFFFFF000U) {
 516                 dev_err(&dev->pdev->dev, "too high clock rate (%lu Hz).\n",
 517                         clkrate);
 518                 return -EINVAL;
 519         }
 520 
 521         if (dev->speed > 100000) {
 522                 /* CC6..CC0 */
 523                 stu300_wr8((val & I2C_CCR_CC_MASK) | I2C_CCR_FMSM,
 524                            dev->virtbase + I2C_CCR);
 525                 dev_dbg(&dev->pdev->dev, "set clock divider to 0x%08x, "
 526                         "Fast Mode I2C\n", val);
 527         } else {
 528                 /* CC6..CC0 */
 529                 stu300_wr8((val & I2C_CCR_CC_MASK),
 530                            dev->virtbase + I2C_CCR);
 531                 dev_dbg(&dev->pdev->dev, "set clock divider to "
 532                         "0x%08x, Standard Mode I2C\n", val);
 533         }
 534 
 535         /* CC11..CC7 */
 536         stu300_wr8(((val >> 7) & 0x1F),
 537                    dev->virtbase + I2C_ECCR);
 538 
 539         return 0;
 540 }
 541 
 542 
 543 static int stu300_init_hw(struct stu300_dev *dev)
 544 {
 545         u32 dummy;
 546         unsigned long clkrate;
 547         int ret;
 548 
 549         /* Disable controller */
 550         stu300_wr8(0x00, dev->virtbase + I2C_CR);
 551         /*
 552          * Set own address to some default value (0x00).
 553          * We do not support slave mode anyway.
 554          */
 555         stu300_wr8(0x00, dev->virtbase + I2C_OAR1);
 556         /*
 557          * The I2C controller only operates properly in 26 MHz but we
 558          * program this driver as if we didn't know. This will also set the two
 559          * high bits of the own address to zero as well.
 560          * There is no known hardware issue with running in 13 MHz
 561          * However, speeds over 200 kHz are not used.
 562          */
 563         clkrate = clk_get_rate(dev->clk);
 564         ret = stu300_set_clk(dev, clkrate);
 565 
 566         if (ret)
 567                 return ret;
 568         /*
 569          * Enable block, do it TWICE (hardware glitch)
 570          * Setting bit 7 can enable DDC mode. (Not used currently.)
 571          */
 572         stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
 573                                   dev->virtbase + I2C_CR);
 574         stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
 575                                   dev->virtbase + I2C_CR);
 576         /* Make a dummy read of the status register SR1 & SR2 */
 577         dummy = stu300_r8(dev->virtbase + I2C_SR2);
 578         dummy = stu300_r8(dev->virtbase + I2C_SR1);
 579 
 580         return 0;
 581 }
 582 
 583 
 584 
 585 /* Send slave address. */
 586 static int stu300_send_address(struct stu300_dev *dev,
 587                                  struct i2c_msg *msg, int resend)
 588 {
 589         u32 val;
 590         int ret;
 591 
 592         if (msg->flags & I2C_M_TEN) {
 593                 /* This is probably how 10 bit addresses look */
 594                 val = (0xf0 | (((u32) msg->addr & 0x300) >> 7)) &
 595                         I2C_DR_D_MASK;
 596                 if (msg->flags & I2C_M_RD)
 597                         /* This is the direction bit */
 598                         val |= 0x01;
 599         } else {
 600                 val = i2c_8bit_addr_from_msg(msg);
 601         }
 602 
 603         if (resend) {
 604                 if (msg->flags & I2C_M_RD)
 605                         dev_dbg(&dev->pdev->dev, "read resend\n");
 606                 else
 607                         dev_dbg(&dev->pdev->dev, "write resend\n");
 608         }
 609 
 610         stu300_wr8(val, dev->virtbase + I2C_DR);
 611 
 612         /* For 10bit addressing, await 10bit request (EVENT 9) */
 613         if (msg->flags & I2C_M_TEN) {
 614                 ret = stu300_await_event(dev, STU300_EVENT_9);
 615                 /*
 616                  * The slave device wants a 10bit address, send the rest
 617                  * of the bits (the LSBits)
 618                  */
 619                 val = msg->addr & I2C_DR_D_MASK;
 620                 /* This clears "event 9" */
 621                 stu300_wr8(val, dev->virtbase + I2C_DR);
 622                 if (ret != 0)
 623                         return ret;
 624         }
 625         /* FIXME: Why no else here? two events for 10bit?
 626          * Await event 6 (normal) or event 9 (10bit)
 627          */
 628 
 629         if (resend)
 630                 dev_dbg(&dev->pdev->dev, "await event 6\n");
 631         ret = stu300_await_event(dev, STU300_EVENT_6);
 632 
 633         /*
 634          * Clear any pending EVENT 6 no matter what happened during
 635          * await_event.
 636          */
 637         val = stu300_r8(dev->virtbase + I2C_CR);
 638         val |= I2C_CR_PERIPHERAL_ENABLE;
 639         stu300_wr8(val, dev->virtbase + I2C_CR);
 640 
 641         return ret;
 642 }
 643 
 644 static int stu300_xfer_msg(struct i2c_adapter *adap,
 645                              struct i2c_msg *msg, int stop)
 646 {
 647         u32 cr;
 648         u32 val;
 649         u32 i;
 650         int ret;
 651         int attempts = 0;
 652         struct stu300_dev *dev = i2c_get_adapdata(adap);
 653 
 654         clk_enable(dev->clk);
 655 
 656         /* Remove this if (0) to trace each and every message. */
 657         if (0) {
 658                 dev_dbg(&dev->pdev->dev, "I2C message to: 0x%04x, len: %d, "
 659                         "flags: 0x%04x, stop: %d\n",
 660                         msg->addr, msg->len, msg->flags, stop);
 661         }
 662 
 663         /*
 664          * For some reason, sending the address sometimes fails when running
 665          * on  the 13 MHz clock. No interrupt arrives. This is a work around,
 666          * which tries to restart and send the address up to 10 times before
 667          * really giving up. Usually 5 to 8 attempts are enough.
 668          */
 669         do {
 670                 if (attempts)
 671                         dev_dbg(&dev->pdev->dev, "wait while busy\n");
 672                 /* Check that the bus is free, or wait until some timeout */
 673                 ret = stu300_wait_while_busy(dev);
 674                 if (ret != 0)
 675                         goto exit_disable;
 676 
 677                 if (attempts)
 678                         dev_dbg(&dev->pdev->dev, "re-int hw\n");
 679                 /*
 680                  * According to ST, there is no problem if the clock is
 681                  * changed between 13 and 26 MHz during a transfer.
 682                  */
 683                 ret = stu300_init_hw(dev);
 684                 if (ret)
 685                         goto exit_disable;
 686 
 687                 /* Send a start condition */
 688                 cr = I2C_CR_PERIPHERAL_ENABLE;
 689                 /* Setting the START bit puts the block in master mode */
 690                 if (!(msg->flags & I2C_M_NOSTART))
 691                         cr |= I2C_CR_START_ENABLE;
 692                 if ((msg->flags & I2C_M_RD) && (msg->len > 1))
 693                         /* On read more than 1 byte, we need ack. */
 694                         cr |= I2C_CR_ACK_ENABLE;
 695                 /* Check that it gets through */
 696                 if (!(msg->flags & I2C_M_NOSTART)) {
 697                         if (attempts)
 698                                 dev_dbg(&dev->pdev->dev, "send start event\n");
 699                         ret = stu300_start_and_await_event(dev, cr,
 700                                                              STU300_EVENT_5);
 701                 }
 702 
 703                 if (attempts)
 704                         dev_dbg(&dev->pdev->dev, "send address\n");
 705 
 706                 if (ret == 0)
 707                         /* Send address */
 708                         ret = stu300_send_address(dev, msg, attempts != 0);
 709 
 710                 if (ret != 0) {
 711                         attempts++;
 712                         dev_dbg(&dev->pdev->dev, "failed sending address, "
 713                                 "retrying. Attempt: %d msg_index: %d/%d\n",
 714                                attempts, dev->msg_index, dev->msg_len);
 715                 }
 716 
 717         } while (ret != 0 && attempts < NUM_ADDR_RESEND_ATTEMPTS);
 718 
 719         if (attempts < NUM_ADDR_RESEND_ATTEMPTS && attempts > 0) {
 720                 dev_dbg(&dev->pdev->dev, "managed to get address "
 721                         "through after %d attempts\n", attempts);
 722         } else if (attempts == NUM_ADDR_RESEND_ATTEMPTS) {
 723                 dev_dbg(&dev->pdev->dev, "I give up, tried %d times "
 724                         "to resend address.\n",
 725                         NUM_ADDR_RESEND_ATTEMPTS);
 726                 goto exit_disable;
 727         }
 728 
 729 
 730         if (msg->flags & I2C_M_RD) {
 731                 /* READ: we read the actual bytes one at a time */
 732                 for (i = 0; i < msg->len; i++) {
 733                         if (i == msg->len-1) {
 734                                 /*
 735                                  * Disable ACK and set STOP condition before
 736                                  * reading last byte
 737                                  */
 738                                 val = I2C_CR_PERIPHERAL_ENABLE;
 739 
 740                                 if (stop)
 741                                         val |= I2C_CR_STOP_ENABLE;
 742 
 743                                 stu300_wr8(val,
 744                                            dev->virtbase + I2C_CR);
 745                         }
 746                         /* Wait for this byte... */
 747                         ret = stu300_await_event(dev, STU300_EVENT_7);
 748                         if (ret != 0)
 749                                 goto exit_disable;
 750                         /* This clears event 7 */
 751                         msg->buf[i] = (u8) stu300_r8(dev->virtbase + I2C_DR);
 752                 }
 753         } else {
 754                 /* WRITE: we send the actual bytes one at a time */
 755                 for (i = 0; i < msg->len; i++) {
 756                         /* Write the byte */
 757                         stu300_wr8(msg->buf[i],
 758                                    dev->virtbase + I2C_DR);
 759                         /* Check status */
 760                         ret = stu300_await_event(dev, STU300_EVENT_8);
 761                         /* Next write to DR will clear event 8 */
 762                         if (ret != 0) {
 763                                 dev_err(&dev->pdev->dev, "error awaiting "
 764                                        "event 8 (%d)\n", ret);
 765                                 goto exit_disable;
 766                         }
 767                 }
 768                 /* Check NAK */
 769                 if (!(msg->flags & I2C_M_IGNORE_NAK)) {
 770                         if (stu300_r8(dev->virtbase + I2C_SR2) &
 771                             I2C_SR2_AF_IND) {
 772                                 dev_err(&dev->pdev->dev, "I2C payload "
 773                                        "send returned NAK!\n");
 774                                 ret = -EIO;
 775                                 goto exit_disable;
 776                         }
 777                 }
 778                 if (stop) {
 779                         /* Send stop condition */
 780                         val = I2C_CR_PERIPHERAL_ENABLE;
 781                         val |= I2C_CR_STOP_ENABLE;
 782                         stu300_wr8(val, dev->virtbase + I2C_CR);
 783                 }
 784         }
 785 
 786         /* Check that the bus is free, or wait until some timeout occurs */
 787         ret = stu300_wait_while_busy(dev);
 788         if (ret != 0) {
 789                 dev_err(&dev->pdev->dev, "timeout waiting for transfer "
 790                        "to commence.\n");
 791                 goto exit_disable;
 792         }
 793 
 794         /* Dummy read status registers */
 795         val = stu300_r8(dev->virtbase + I2C_SR2);
 796         val = stu300_r8(dev->virtbase + I2C_SR1);
 797         ret = 0;
 798 
 799  exit_disable:
 800         /* Disable controller */
 801         stu300_wr8(0x00, dev->virtbase + I2C_CR);
 802         clk_disable(dev->clk);
 803         return ret;
 804 }
 805 
 806 static int stu300_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 807                          int num)
 808 {
 809         int ret = -1;
 810         int i;
 811 
 812         struct stu300_dev *dev = i2c_get_adapdata(adap);
 813         dev->msg_len = num;
 814 
 815         for (i = 0; i < num; i++) {
 816                 /*
 817                  * Another driver appears to send stop for each message,
 818                  * here we only do that for the last message. Possibly some
 819                  * peripherals require this behaviour, then their drivers
 820                  * have to send single messages in order to get "stop" for
 821                  * each message.
 822                  */
 823                 dev->msg_index = i;
 824 
 825                 ret = stu300_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 826 
 827                 if (ret != 0) {
 828                         num = ret;
 829                         break;
 830                 }
 831         }
 832 
 833         return num;
 834 }
 835 
 836 static int stu300_xfer_todo(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 837 {
 838         /* TODO: implement polling for this case if need be. */
 839         WARN(1, "%s: atomic transfers not implemented\n", dev_name(&adap->dev));
 840         return -EOPNOTSUPP;
 841 }
 842 
 843 static u32 stu300_func(struct i2c_adapter *adap)
 844 {
 845         /* This is the simplest thing you can think of... */
 846         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
 847 }
 848 
 849 static const struct i2c_algorithm stu300_algo = {
 850         .master_xfer = stu300_xfer,
 851         .master_xfer_atomic = stu300_xfer_todo,
 852         .functionality = stu300_func,
 853 };
 854 
 855 static const struct i2c_adapter_quirks stu300_quirks = {
 856         .flags = I2C_AQ_NO_ZERO_LEN,
 857 };
 858 
 859 static int stu300_probe(struct platform_device *pdev)
 860 {
 861         struct stu300_dev *dev;
 862         struct i2c_adapter *adap;
 863         struct resource *res;
 864         int bus_nr;
 865         int ret = 0;
 866 
 867         dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL);
 868         if (!dev)
 869                 return -ENOMEM;
 870 
 871         bus_nr = pdev->id;
 872         dev->clk = devm_clk_get(&pdev->dev, NULL);
 873         if (IS_ERR(dev->clk)) {
 874                 dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
 875                 return PTR_ERR(dev->clk);
 876         }
 877 
 878         dev->pdev = pdev;
 879         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 880         dev->virtbase = devm_ioremap_resource(&pdev->dev, res);
 881         dev_dbg(&pdev->dev, "initialize bus device I2C%d on virtual "
 882                 "base %p\n", bus_nr, dev->virtbase);
 883         if (IS_ERR(dev->virtbase))
 884                 return PTR_ERR(dev->virtbase);
 885 
 886         dev->irq = platform_get_irq(pdev, 0);
 887         ret = devm_request_irq(&pdev->dev, dev->irq, stu300_irh, 0, NAME, dev);
 888         if (ret < 0)
 889                 return ret;
 890 
 891         dev->speed = scl_frequency;
 892 
 893         clk_prepare_enable(dev->clk);
 894         ret = stu300_init_hw(dev);
 895         clk_disable(dev->clk);
 896         if (ret != 0) {
 897                 dev_err(&dev->pdev->dev, "error initializing hardware.\n");
 898                 return -EIO;
 899         }
 900 
 901         /* IRQ event handling initialization */
 902         spin_lock_init(&dev->cmd_issue_lock);
 903         dev->cmd_event = STU300_EVENT_NONE;
 904         dev->cmd_err = STU300_ERROR_NONE;
 905 
 906         adap = &dev->adapter;
 907         adap->owner = THIS_MODULE;
 908         /* DDC class but actually often used for more generic I2C */
 909         adap->class = I2C_CLASS_DEPRECATED;
 910         strlcpy(adap->name, "ST Microelectronics DDC I2C adapter",
 911                 sizeof(adap->name));
 912         adap->nr = bus_nr;
 913         adap->algo = &stu300_algo;
 914         adap->dev.parent = &pdev->dev;
 915         adap->dev.of_node = pdev->dev.of_node;
 916         adap->quirks = &stu300_quirks;
 917 
 918         i2c_set_adapdata(adap, dev);
 919 
 920         /* i2c device drivers may be active on return from add_adapter() */
 921         ret = i2c_add_numbered_adapter(adap);
 922         if (ret)
 923                 return ret;
 924 
 925         platform_set_drvdata(pdev, dev);
 926         dev_info(&pdev->dev, "ST DDC I2C @ %p, irq %d\n",
 927                  dev->virtbase, dev->irq);
 928 
 929         return 0;
 930 }
 931 
 932 #ifdef CONFIG_PM_SLEEP
 933 static int stu300_suspend(struct device *device)
 934 {
 935         struct stu300_dev *dev = dev_get_drvdata(device);
 936 
 937         /* Turn off everything */
 938         stu300_wr8(0x00, dev->virtbase + I2C_CR);
 939         return 0;
 940 }
 941 
 942 static int stu300_resume(struct device *device)
 943 {
 944         int ret = 0;
 945         struct stu300_dev *dev = dev_get_drvdata(device);
 946 
 947         clk_enable(dev->clk);
 948         ret = stu300_init_hw(dev);
 949         clk_disable(dev->clk);
 950 
 951         if (ret != 0)
 952                 dev_err(device, "error re-initializing hardware.\n");
 953         return ret;
 954 }
 955 
 956 static SIMPLE_DEV_PM_OPS(stu300_pm, stu300_suspend, stu300_resume);
 957 #define STU300_I2C_PM   (&stu300_pm)
 958 #else
 959 #define STU300_I2C_PM   NULL
 960 #endif
 961 
 962 static int stu300_remove(struct platform_device *pdev)
 963 {
 964         struct stu300_dev *dev = platform_get_drvdata(pdev);
 965 
 966         i2c_del_adapter(&dev->adapter);
 967         /* Turn off everything */
 968         stu300_wr8(0x00, dev->virtbase + I2C_CR);
 969         return 0;
 970 }
 971 
 972 static const struct of_device_id stu300_dt_match[] = {
 973         { .compatible = "st,ddci2c" },
 974         {},
 975 };
 976 MODULE_DEVICE_TABLE(of, stu300_dt_match);
 977 
 978 static struct platform_driver stu300_i2c_driver = {
 979         .driver = {
 980                 .name   = NAME,
 981                 .pm     = STU300_I2C_PM,
 982                 .of_match_table = stu300_dt_match,
 983         },
 984         .probe = stu300_probe,
 985         .remove = stu300_remove,
 986 
 987 };
 988 
 989 static int __init stu300_init(void)
 990 {
 991         return platform_driver_register(&stu300_i2c_driver);
 992 }
 993 
 994 static void __exit stu300_exit(void)
 995 {
 996         platform_driver_unregister(&stu300_i2c_driver);
 997 }
 998 
 999 /*
1000  * The systems using this bus often have very basic devices such
1001  * as regulators on the I2C bus, so this needs to be loaded early.
1002  * Therefore it is registered in the subsys_initcall().
1003  */
1004 subsys_initcall(stu300_init);
1005 module_exit(stu300_exit);
1006 
1007 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
1008 MODULE_DESCRIPTION("ST Micro DDC I2C adapter (" NAME ")");
1009 MODULE_LICENSE("GPL");
1010 MODULE_ALIAS("platform:" NAME);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/i2c/busses/i2c-stu300.c

DEFINITIONS
