root/drivers/i2c/busses/i2c-i801.c

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DEFINITIONS

This source file includes following definitions.
  1. i801_check_pre
  2. i801_check_post
  3. i801_wait_intr
  4. i801_wait_byte_done
  5. i801_transaction
  6. i801_block_transaction_by_block
  7. i801_isr_byte_done
  8. i801_host_notify_isr
  9. i801_isr
  10. i801_block_transaction_byte_by_byte
  11. i801_set_block_buffer_mode
  12. i801_block_transaction
  13. i801_access
  14. i801_func
  15. i801_enable_host_notify
  16. i801_disable_host_notify
  17. bios_signature
  18. input_apanel_init
  19. dmi_check_onboard_device
  20. dmi_check_onboard_devices
  21. check_acpi_smo88xx_device
  22. is_dell_system_with_lis3lv02d
  23. register_dell_lis3lv02d_i2c_device
  24. i801_probe_optional_slaves
  25. input_apanel_init
  26. i801_probe_optional_slaves
  27. i801_add_mux
  28. i801_del_mux
  29. i801_get_adapter_class
  30. i801_add_mux
  31. i801_del_mux
  32. i801_get_adapter_class
  33. i801_add_tco_spt
  34. i801_add_tco_cnl
  35. i801_add_tco
  36. i801_acpi_is_smbus_ioport
  37. i801_acpi_io_handler
  38. i801_acpi_probe
  39. i801_acpi_remove
  40. i801_acpi_probe
  41. i801_acpi_remove
  42. i801_probe
  43. i801_remove
  44. i801_shutdown
  45. i801_suspend
  46. i801_resume
  47. i2c_i801_init
  48. i2c_i801_exit

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   4     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   5     <mdsxyz123@yahoo.com>
   6     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   7     Copyright (C) 2010         Intel Corporation,
   8                                David Woodhouse <dwmw2@infradead.org>
   9 
  10 */
  11 
  12 /*
  13  * Supports the following Intel I/O Controller Hubs (ICH):
  14  *
  15  *                                      I/O                     Block   I2C
  16  *                                      region  SMBus   Block   proc.   block
  17  * Chip name                    PCI ID  size    PEC     buffer  call    read
  18  * ---------------------------------------------------------------------------
  19  * 82801AA (ICH)                0x2413  16      no      no      no      no
  20  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  21  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  22  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  23  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  24  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  25  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  26  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  27  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  28  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  29  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  30  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  31  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  32  * ICH10                        0x3a30  32      hard    yes     yes     yes
  33  * ICH10                        0x3a60  32      hard    yes     yes     yes
  34  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  35  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  36  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  37  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  38  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  39  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  40  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  41  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  42  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  43  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  44  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  45  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  46  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  47  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  48  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  49  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  50  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  51  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  52  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  53  * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  54  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  55  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  56  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  57  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  58  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  59  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  60  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  61  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  62  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  63  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  64  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  65  * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  66  * Comet Lake (PCH)             0x02a3  32      hard    yes     yes     yes
  67  * Elkhart Lake (PCH)           0x4b23  32      hard    yes     yes     yes
  68  * Tiger Lake-LP (PCH)          0xa0a3  32      hard    yes     yes     yes
  69  *
  70  * Features supported by this driver:
  71  * Software PEC                         no
  72  * Hardware PEC                         yes
  73  * Block buffer                         yes
  74  * Block process call transaction       yes
  75  * I2C block read transaction           yes (doesn't use the block buffer)
  76  * Slave mode                           no
  77  * SMBus Host Notify                    yes
  78  * Interrupt processing                 yes
  79  *
  80  * See the file Documentation/i2c/busses/i2c-i801.rst for details.
  81  */
  82 
  83 #include <linux/interrupt.h>
  84 #include <linux/module.h>
  85 #include <linux/pci.h>
  86 #include <linux/kernel.h>
  87 #include <linux/stddef.h>
  88 #include <linux/delay.h>
  89 #include <linux/ioport.h>
  90 #include <linux/init.h>
  91 #include <linux/i2c.h>
  92 #include <linux/i2c-smbus.h>
  93 #include <linux/acpi.h>
  94 #include <linux/io.h>
  95 #include <linux/dmi.h>
  96 #include <linux/slab.h>
  97 #include <linux/string.h>
  98 #include <linux/wait.h>
  99 #include <linux/err.h>
 100 #include <linux/platform_device.h>
 101 #include <linux/platform_data/itco_wdt.h>
 102 #include <linux/pm_runtime.h>
 103 
 104 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 105 #include <linux/gpio/machine.h>
 106 #include <linux/platform_data/i2c-mux-gpio.h>
 107 #endif
 108 
 109 /* I801 SMBus address offsets */
 110 #define SMBHSTSTS(p)    (0 + (p)->smba)
 111 #define SMBHSTCNT(p)    (2 + (p)->smba)
 112 #define SMBHSTCMD(p)    (3 + (p)->smba)
 113 #define SMBHSTADD(p)    (4 + (p)->smba)
 114 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 115 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 116 #define SMBBLKDAT(p)    (7 + (p)->smba)
 117 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 118 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 119 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 120 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 121 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 122 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 123 
 124 /* PCI Address Constants */
 125 #define SMBBAR          4
 126 #define SMBPCICTL       0x004
 127 #define SMBPCISTS       0x006
 128 #define SMBHSTCFG       0x040
 129 #define TCOBASE         0x050
 130 #define TCOCTL          0x054
 131 
 132 #define SBREG_BAR               0x10
 133 #define SBREG_SMBCTRL           0xc6000c
 134 #define SBREG_SMBCTRL_DNV       0xcf000c
 135 
 136 /* Host status bits for SMBPCISTS */
 137 #define SMBPCISTS_INTS          BIT(3)
 138 
 139 /* Control bits for SMBPCICTL */
 140 #define SMBPCICTL_INTDIS        BIT(10)
 141 
 142 /* Host configuration bits for SMBHSTCFG */
 143 #define SMBHSTCFG_HST_EN        BIT(0)
 144 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 145 #define SMBHSTCFG_I2C_EN        BIT(2)
 146 #define SMBHSTCFG_SPD_WD        BIT(4)
 147 
 148 /* TCO configuration bits for TCOCTL */
 149 #define TCOCTL_EN               BIT(8)
 150 
 151 /* Auxiliary status register bits, ICH4+ only */
 152 #define SMBAUXSTS_CRCE          BIT(0)
 153 #define SMBAUXSTS_STCO          BIT(1)
 154 
 155 /* Auxiliary control register bits, ICH4+ only */
 156 #define SMBAUXCTL_CRC           BIT(0)
 157 #define SMBAUXCTL_E32B          BIT(1)
 158 
 159 /* Other settings */
 160 #define MAX_RETRIES             400
 161 
 162 /* I801 command constants */
 163 #define I801_QUICK              0x00
 164 #define I801_BYTE               0x04
 165 #define I801_BYTE_DATA          0x08
 166 #define I801_WORD_DATA          0x0C
 167 #define I801_PROC_CALL          0x10    /* unimplemented */
 168 #define I801_BLOCK_DATA         0x14
 169 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 170 #define I801_BLOCK_PROC_CALL    0x1C
 171 
 172 /* I801 Host Control register bits */
 173 #define SMBHSTCNT_INTREN        BIT(0)
 174 #define SMBHSTCNT_KILL          BIT(1)
 175 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 176 #define SMBHSTCNT_START         BIT(6)
 177 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 178 
 179 /* I801 Hosts Status register bits */
 180 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 181 #define SMBHSTSTS_INUSE_STS     BIT(6)
 182 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 183 #define SMBHSTSTS_FAILED        BIT(4)
 184 #define SMBHSTSTS_BUS_ERR       BIT(3)
 185 #define SMBHSTSTS_DEV_ERR       BIT(2)
 186 #define SMBHSTSTS_INTR          BIT(1)
 187 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 188 
 189 /* Host Notify Status register bits */
 190 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 191 
 192 /* Host Notify Command register bits */
 193 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 194 
 195 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 196                                  SMBHSTSTS_DEV_ERR)
 197 
 198 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 199                                  STATUS_ERROR_FLAGS)
 200 
 201 /* Older devices have their ID defined in <linux/pci_ids.h> */
 202 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS             0x02a3
 203 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 204 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 205 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 206 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 207 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 208 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 209 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 210 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 212 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 213 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 214 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 215 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 216 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 217 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 218 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 219 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 220 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS          0x4b23
 221 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 222 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 223 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 224 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 225 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 226 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 227 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 228 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 229 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 230 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 231 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 232 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS          0xa0a3
 233 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 234 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 235 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 236 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 237 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 238 
 239 struct i801_mux_config {
 240         char *gpio_chip;
 241         unsigned values[3];
 242         int n_values;
 243         unsigned classes[3];
 244         unsigned gpios[2];              /* Relative to gpio_chip->base */
 245         int n_gpios;
 246 };
 247 
 248 struct i801_priv {
 249         struct i2c_adapter adapter;
 250         unsigned long smba;
 251         unsigned char original_hstcfg;
 252         unsigned char original_slvcmd;
 253         struct pci_dev *pci_dev;
 254         unsigned int features;
 255 
 256         /* isr processing */
 257         wait_queue_head_t waitq;
 258         u8 status;
 259 
 260         /* Command state used by isr for byte-by-byte block transactions */
 261         u8 cmd;
 262         bool is_read;
 263         int count;
 264         int len;
 265         u8 *data;
 266 
 267 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 268         const struct i801_mux_config *mux_drvdata;
 269         struct platform_device *mux_pdev;
 270         struct gpiod_lookup_table *lookup;
 271 #endif
 272         struct platform_device *tco_pdev;
 273 
 274         /*
 275          * If set to true the host controller registers are reserved for
 276          * ACPI AML use. Protected by acpi_lock.
 277          */
 278         bool acpi_reserved;
 279         struct mutex acpi_lock;
 280 };
 281 
 282 #define FEATURE_SMBUS_PEC       BIT(0)
 283 #define FEATURE_BLOCK_BUFFER    BIT(1)
 284 #define FEATURE_BLOCK_PROC      BIT(2)
 285 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 286 #define FEATURE_IRQ             BIT(4)
 287 #define FEATURE_HOST_NOTIFY     BIT(5)
 288 /* Not really a feature, but it's convenient to handle it as such */
 289 #define FEATURE_IDF             BIT(15)
 290 #define FEATURE_TCO_SPT         BIT(16)
 291 #define FEATURE_TCO_CNL         BIT(17)
 292 
 293 static const char *i801_feature_names[] = {
 294         "SMBus PEC",
 295         "Block buffer",
 296         "Block process call",
 297         "I2C block read",
 298         "Interrupt",
 299         "SMBus Host Notify",
 300 };
 301 
 302 static unsigned int disable_features;
 303 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 304 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 305         "\t\t  0x01  disable SMBus PEC\n"
 306         "\t\t  0x02  disable the block buffer\n"
 307         "\t\t  0x08  disable the I2C block read functionality\n"
 308         "\t\t  0x10  don't use interrupts\n"
 309         "\t\t  0x20  disable SMBus Host Notify ");
 310 
 311 /* Make sure the SMBus host is ready to start transmitting.
 312    Return 0 if it is, -EBUSY if it is not. */
 313 static int i801_check_pre(struct i801_priv *priv)
 314 {
 315         int status;
 316 
 317         status = inb_p(SMBHSTSTS(priv));
 318         if (status & SMBHSTSTS_HOST_BUSY) {
 319                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 320                 return -EBUSY;
 321         }
 322 
 323         status &= STATUS_FLAGS;
 324         if (status) {
 325                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 326                         status);
 327                 outb_p(status, SMBHSTSTS(priv));
 328                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 329                 if (status) {
 330                         dev_err(&priv->pci_dev->dev,
 331                                 "Failed clearing status flags (%02x)\n",
 332                                 status);
 333                         return -EBUSY;
 334                 }
 335         }
 336 
 337         /*
 338          * Clear CRC status if needed.
 339          * During normal operation, i801_check_post() takes care
 340          * of it after every operation.  We do it here only in case
 341          * the hardware was already in this state when the driver
 342          * started.
 343          */
 344         if (priv->features & FEATURE_SMBUS_PEC) {
 345                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 346                 if (status) {
 347                         dev_dbg(&priv->pci_dev->dev,
 348                                 "Clearing aux status flags (%02x)\n", status);
 349                         outb_p(status, SMBAUXSTS(priv));
 350                         status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 351                         if (status) {
 352                                 dev_err(&priv->pci_dev->dev,
 353                                         "Failed clearing aux status flags (%02x)\n",
 354                                         status);
 355                                 return -EBUSY;
 356                         }
 357                 }
 358         }
 359 
 360         return 0;
 361 }
 362 
 363 /*
 364  * Convert the status register to an error code, and clear it.
 365  * Note that status only contains the bits we want to clear, not the
 366  * actual register value.
 367  */
 368 static int i801_check_post(struct i801_priv *priv, int status)
 369 {
 370         int result = 0;
 371 
 372         /*
 373          * If the SMBus is still busy, we give up
 374          * Note: This timeout condition only happens when using polling
 375          * transactions.  For interrupt operation, NAK/timeout is indicated by
 376          * DEV_ERR.
 377          */
 378         if (unlikely(status < 0)) {
 379                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 380                 /* try to stop the current command */
 381                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 382                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 383                        SMBHSTCNT(priv));
 384                 usleep_range(1000, 2000);
 385                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 386                        SMBHSTCNT(priv));
 387 
 388                 /* Check if it worked */
 389                 status = inb_p(SMBHSTSTS(priv));
 390                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 391                     !(status & SMBHSTSTS_FAILED))
 392                         dev_err(&priv->pci_dev->dev,
 393                                 "Failed terminating the transaction\n");
 394                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 395                 return -ETIMEDOUT;
 396         }
 397 
 398         if (status & SMBHSTSTS_FAILED) {
 399                 result = -EIO;
 400                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 401         }
 402         if (status & SMBHSTSTS_DEV_ERR) {
 403                 /*
 404                  * This may be a PEC error, check and clear it.
 405                  *
 406                  * AUXSTS is handled differently from HSTSTS.
 407                  * For HSTSTS, i801_isr() or i801_wait_intr()
 408                  * has already cleared the error bits in hardware,
 409                  * and we are passed a copy of the original value
 410                  * in "status".
 411                  * For AUXSTS, the hardware register is left
 412                  * for us to handle here.
 413                  * This is asymmetric, slightly iffy, but safe,
 414                  * since all this code is serialized and the CRCE
 415                  * bit is harmless as long as it's cleared before
 416                  * the next operation.
 417                  */
 418                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 419                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 420                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 421                         result = -EBADMSG;
 422                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 423                 } else {
 424                         result = -ENXIO;
 425                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 426                 }
 427         }
 428         if (status & SMBHSTSTS_BUS_ERR) {
 429                 result = -EAGAIN;
 430                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 431         }
 432 
 433         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 434         outb_p(status, SMBHSTSTS(priv));
 435 
 436         return result;
 437 }
 438 
 439 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 440 static int i801_wait_intr(struct i801_priv *priv)
 441 {
 442         int timeout = 0;
 443         int status;
 444 
 445         /* We will always wait for a fraction of a second! */
 446         do {
 447                 usleep_range(250, 500);
 448                 status = inb_p(SMBHSTSTS(priv));
 449         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 450                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 451                  (timeout++ < MAX_RETRIES));
 452 
 453         if (timeout > MAX_RETRIES) {
 454                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 455                 return -ETIMEDOUT;
 456         }
 457         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 458 }
 459 
 460 /* Wait for either BYTE_DONE or an error flag being set */
 461 static int i801_wait_byte_done(struct i801_priv *priv)
 462 {
 463         int timeout = 0;
 464         int status;
 465 
 466         /* We will always wait for a fraction of a second! */
 467         do {
 468                 usleep_range(250, 500);
 469                 status = inb_p(SMBHSTSTS(priv));
 470         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 471                  (timeout++ < MAX_RETRIES));
 472 
 473         if (timeout > MAX_RETRIES) {
 474                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 475                 return -ETIMEDOUT;
 476         }
 477         return status & STATUS_ERROR_FLAGS;
 478 }
 479 
 480 static int i801_transaction(struct i801_priv *priv, int xact)
 481 {
 482         int status;
 483         int result;
 484         const struct i2c_adapter *adap = &priv->adapter;
 485 
 486         result = i801_check_pre(priv);
 487         if (result < 0)
 488                 return result;
 489 
 490         if (priv->features & FEATURE_IRQ) {
 491                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 492                        SMBHSTCNT(priv));
 493                 result = wait_event_timeout(priv->waitq,
 494                                             (status = priv->status),
 495                                             adap->timeout);
 496                 if (!result) {
 497                         status = -ETIMEDOUT;
 498                         dev_warn(&priv->pci_dev->dev,
 499                                  "Timeout waiting for interrupt!\n");
 500                 }
 501                 priv->status = 0;
 502                 return i801_check_post(priv, status);
 503         }
 504 
 505         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 506          * SMBSCMD are passed in xact */
 507         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 508 
 509         status = i801_wait_intr(priv);
 510         return i801_check_post(priv, status);
 511 }
 512 
 513 static int i801_block_transaction_by_block(struct i801_priv *priv,
 514                                            union i2c_smbus_data *data,
 515                                            char read_write, int command,
 516                                            int hwpec)
 517 {
 518         int i, len;
 519         int status;
 520         int xact = hwpec ? SMBHSTCNT_PEC_EN : 0;
 521 
 522         switch (command) {
 523         case I2C_SMBUS_BLOCK_PROC_CALL:
 524                 xact |= I801_BLOCK_PROC_CALL;
 525                 break;
 526         case I2C_SMBUS_BLOCK_DATA:
 527                 xact |= I801_BLOCK_DATA;
 528                 break;
 529         default:
 530                 return -EOPNOTSUPP;
 531         }
 532 
 533         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 534 
 535         /* Use 32-byte buffer to process this transaction */
 536         if (read_write == I2C_SMBUS_WRITE) {
 537                 len = data->block[0];
 538                 outb_p(len, SMBHSTDAT0(priv));
 539                 for (i = 0; i < len; i++)
 540                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 541         }
 542 
 543         status = i801_transaction(priv, xact);
 544         if (status)
 545                 return status;
 546 
 547         if (read_write == I2C_SMBUS_READ ||
 548             command == I2C_SMBUS_BLOCK_PROC_CALL) {
 549                 len = inb_p(SMBHSTDAT0(priv));
 550                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 551                         return -EPROTO;
 552 
 553                 data->block[0] = len;
 554                 for (i = 0; i < len; i++)
 555                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 556         }
 557         return 0;
 558 }
 559 
 560 static void i801_isr_byte_done(struct i801_priv *priv)
 561 {
 562         if (priv->is_read) {
 563                 /* For SMBus block reads, length is received with first byte */
 564                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 565                     (priv->count == 0)) {
 566                         priv->len = inb_p(SMBHSTDAT0(priv));
 567                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 568                                 dev_err(&priv->pci_dev->dev,
 569                                         "Illegal SMBus block read size %d\n",
 570                                         priv->len);
 571                                 /* FIXME: Recover */
 572                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 573                         } else {
 574                                 dev_dbg(&priv->pci_dev->dev,
 575                                         "SMBus block read size is %d\n",
 576                                         priv->len);
 577                         }
 578                         priv->data[-1] = priv->len;
 579                 }
 580 
 581                 /* Read next byte */
 582                 if (priv->count < priv->len)
 583                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 584                 else
 585                         dev_dbg(&priv->pci_dev->dev,
 586                                 "Discarding extra byte on block read\n");
 587 
 588                 /* Set LAST_BYTE for last byte of read transaction */
 589                 if (priv->count == priv->len - 1)
 590                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 591                                SMBHSTCNT(priv));
 592         } else if (priv->count < priv->len - 1) {
 593                 /* Write next byte, except for IRQ after last byte */
 594                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 595         }
 596 
 597         /* Clear BYTE_DONE to continue with next byte */
 598         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 599 }
 600 
 601 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 602 {
 603         unsigned short addr;
 604 
 605         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 606 
 607         /*
 608          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 609          * always returns 0. Our current implementation doesn't provide
 610          * data, so we just ignore it.
 611          */
 612         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 613 
 614         /* clear Host Notify bit and return */
 615         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 616         return IRQ_HANDLED;
 617 }
 618 
 619 /*
 620  * There are three kinds of interrupts:
 621  *
 622  * 1) i801 signals transaction completion with one of these interrupts:
 623  *      INTR - Success
 624  *      DEV_ERR - Invalid command, NAK or communication timeout
 625  *      BUS_ERR - SMI# transaction collision
 626  *      FAILED - transaction was canceled due to a KILL request
 627  *    When any of these occur, update ->status and wake up the waitq.
 628  *    ->status must be cleared before kicking off the next transaction.
 629  *
 630  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 631  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 632  *
 633  * 3) Host Notify interrupts
 634  */
 635 static irqreturn_t i801_isr(int irq, void *dev_id)
 636 {
 637         struct i801_priv *priv = dev_id;
 638         u16 pcists;
 639         u8 status;
 640 
 641         /* Confirm this is our interrupt */
 642         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 643         if (!(pcists & SMBPCISTS_INTS))
 644                 return IRQ_NONE;
 645 
 646         if (priv->features & FEATURE_HOST_NOTIFY) {
 647                 status = inb_p(SMBSLVSTS(priv));
 648                 if (status & SMBSLVSTS_HST_NTFY_STS)
 649                         return i801_host_notify_isr(priv);
 650         }
 651 
 652         status = inb_p(SMBHSTSTS(priv));
 653         if (status & SMBHSTSTS_BYTE_DONE)
 654                 i801_isr_byte_done(priv);
 655 
 656         /*
 657          * Clear irq sources and report transaction result.
 658          * ->status must be cleared before the next transaction is started.
 659          */
 660         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 661         if (status) {
 662                 outb_p(status, SMBHSTSTS(priv));
 663                 priv->status = status;
 664                 wake_up(&priv->waitq);
 665         }
 666 
 667         return IRQ_HANDLED;
 668 }
 669 
 670 /*
 671  * For "byte-by-byte" block transactions:
 672  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 673  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 674  */
 675 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 676                                                union i2c_smbus_data *data,
 677                                                char read_write, int command,
 678                                                int hwpec)
 679 {
 680         int i, len;
 681         int smbcmd;
 682         int status;
 683         int result;
 684         const struct i2c_adapter *adap = &priv->adapter;
 685 
 686         if (command == I2C_SMBUS_BLOCK_PROC_CALL)
 687                 return -EOPNOTSUPP;
 688 
 689         result = i801_check_pre(priv);
 690         if (result < 0)
 691                 return result;
 692 
 693         len = data->block[0];
 694 
 695         if (read_write == I2C_SMBUS_WRITE) {
 696                 outb_p(len, SMBHSTDAT0(priv));
 697                 outb_p(data->block[1], SMBBLKDAT(priv));
 698         }
 699 
 700         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 701             read_write == I2C_SMBUS_READ)
 702                 smbcmd = I801_I2C_BLOCK_DATA;
 703         else
 704                 smbcmd = I801_BLOCK_DATA;
 705 
 706         if (priv->features & FEATURE_IRQ) {
 707                 priv->is_read = (read_write == I2C_SMBUS_READ);
 708                 if (len == 1 && priv->is_read)
 709                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 710                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 711                 priv->len = len;
 712                 priv->count = 0;
 713                 priv->data = &data->block[1];
 714 
 715                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 716                 result = wait_event_timeout(priv->waitq,
 717                                             (status = priv->status),
 718                                             adap->timeout);
 719                 if (!result) {
 720                         status = -ETIMEDOUT;
 721                         dev_warn(&priv->pci_dev->dev,
 722                                  "Timeout waiting for interrupt!\n");
 723                 }
 724                 priv->status = 0;
 725                 return i801_check_post(priv, status);
 726         }
 727 
 728         for (i = 1; i <= len; i++) {
 729                 if (i == len && read_write == I2C_SMBUS_READ)
 730                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 731                 outb_p(smbcmd, SMBHSTCNT(priv));
 732 
 733                 if (i == 1)
 734                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 735                                SMBHSTCNT(priv));
 736 
 737                 status = i801_wait_byte_done(priv);
 738                 if (status)
 739                         goto exit;
 740 
 741                 if (i == 1 && read_write == I2C_SMBUS_READ
 742                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 743                         len = inb_p(SMBHSTDAT0(priv));
 744                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 745                                 dev_err(&priv->pci_dev->dev,
 746                                         "Illegal SMBus block read size %d\n",
 747                                         len);
 748                                 /* Recover */
 749                                 while (inb_p(SMBHSTSTS(priv)) &
 750                                        SMBHSTSTS_HOST_BUSY)
 751                                         outb_p(SMBHSTSTS_BYTE_DONE,
 752                                                SMBHSTSTS(priv));
 753                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 754                                 return -EPROTO;
 755                         }
 756                         data->block[0] = len;
 757                 }
 758 
 759                 /* Retrieve/store value in SMBBLKDAT */
 760                 if (read_write == I2C_SMBUS_READ)
 761                         data->block[i] = inb_p(SMBBLKDAT(priv));
 762                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 763                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 764 
 765                 /* signals SMBBLKDAT ready */
 766                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 767         }
 768 
 769         status = i801_wait_intr(priv);
 770 exit:
 771         return i801_check_post(priv, status);
 772 }
 773 
 774 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 775 {
 776         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 777         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 778                 return -EIO;
 779         return 0;
 780 }
 781 
 782 /* Block transaction function */
 783 static int i801_block_transaction(struct i801_priv *priv,
 784                                   union i2c_smbus_data *data, char read_write,
 785                                   int command, int hwpec)
 786 {
 787         int result = 0;
 788         unsigned char hostc;
 789 
 790         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 791                 if (read_write == I2C_SMBUS_WRITE) {
 792                         /* set I2C_EN bit in configuration register */
 793                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 794                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 795                                               hostc | SMBHSTCFG_I2C_EN);
 796                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 797                         dev_err(&priv->pci_dev->dev,
 798                                 "I2C block read is unsupported!\n");
 799                         return -EOPNOTSUPP;
 800                 }
 801         }
 802 
 803         if (read_write == I2C_SMBUS_WRITE
 804          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 805                 if (data->block[0] < 1)
 806                         data->block[0] = 1;
 807                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 808                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 809         } else {
 810                 data->block[0] = 32;    /* max for SMBus block reads */
 811         }
 812 
 813         /* Experience has shown that the block buffer can only be used for
 814            SMBus (not I2C) block transactions, even though the datasheet
 815            doesn't mention this limitation. */
 816         if ((priv->features & FEATURE_BLOCK_BUFFER)
 817          && command != I2C_SMBUS_I2C_BLOCK_DATA
 818          && i801_set_block_buffer_mode(priv) == 0)
 819                 result = i801_block_transaction_by_block(priv, data,
 820                                                          read_write,
 821                                                          command, hwpec);
 822         else
 823                 result = i801_block_transaction_byte_by_byte(priv, data,
 824                                                              read_write,
 825                                                              command, hwpec);
 826 
 827         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 828          && read_write == I2C_SMBUS_WRITE) {
 829                 /* restore saved configuration register value */
 830                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 831         }
 832         return result;
 833 }
 834 
 835 /* Return negative errno on error. */
 836 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 837                        unsigned short flags, char read_write, u8 command,
 838                        int size, union i2c_smbus_data *data)
 839 {
 840         int hwpec;
 841         int block = 0;
 842         int ret = 0, xact = 0;
 843         struct i801_priv *priv = i2c_get_adapdata(adap);
 844 
 845         mutex_lock(&priv->acpi_lock);
 846         if (priv->acpi_reserved) {
 847                 mutex_unlock(&priv->acpi_lock);
 848                 return -EBUSY;
 849         }
 850 
 851         pm_runtime_get_sync(&priv->pci_dev->dev);
 852 
 853         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 854                 && size != I2C_SMBUS_QUICK
 855                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 856 
 857         switch (size) {
 858         case I2C_SMBUS_QUICK:
 859                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 860                        SMBHSTADD(priv));
 861                 xact = I801_QUICK;
 862                 break;
 863         case I2C_SMBUS_BYTE:
 864                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 865                        SMBHSTADD(priv));
 866                 if (read_write == I2C_SMBUS_WRITE)
 867                         outb_p(command, SMBHSTCMD(priv));
 868                 xact = I801_BYTE;
 869                 break;
 870         case I2C_SMBUS_BYTE_DATA:
 871                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 872                        SMBHSTADD(priv));
 873                 outb_p(command, SMBHSTCMD(priv));
 874                 if (read_write == I2C_SMBUS_WRITE)
 875                         outb_p(data->byte, SMBHSTDAT0(priv));
 876                 xact = I801_BYTE_DATA;
 877                 break;
 878         case I2C_SMBUS_WORD_DATA:
 879                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 880                        SMBHSTADD(priv));
 881                 outb_p(command, SMBHSTCMD(priv));
 882                 if (read_write == I2C_SMBUS_WRITE) {
 883                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 884                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 885                 }
 886                 xact = I801_WORD_DATA;
 887                 break;
 888         case I2C_SMBUS_BLOCK_DATA:
 889                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 890                        SMBHSTADD(priv));
 891                 outb_p(command, SMBHSTCMD(priv));
 892                 block = 1;
 893                 break;
 894         case I2C_SMBUS_I2C_BLOCK_DATA:
 895                 /*
 896                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 897                  * bit should be cleared here, even when reading.
 898                  * However if SPD Write Disable is set (Lynx Point and later),
 899                  * the read will fail if we don't set the R/#W bit.
 900                  */
 901                 outb_p(((addr & 0x7f) << 1) |
 902                        ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 903                         (read_write & 0x01) : 0),
 904                        SMBHSTADD(priv));
 905                 if (read_write == I2C_SMBUS_READ) {
 906                         /* NB: page 240 of ICH5 datasheet also shows
 907                          * that DATA1 is the cmd field when reading */
 908                         outb_p(command, SMBHSTDAT1(priv));
 909                 } else
 910                         outb_p(command, SMBHSTCMD(priv));
 911                 block = 1;
 912                 break;
 913         case I2C_SMBUS_BLOCK_PROC_CALL:
 914                 /*
 915                  * Bit 0 of the slave address register always indicate a write
 916                  * command.
 917                  */
 918                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 919                 outb_p(command, SMBHSTCMD(priv));
 920                 block = 1;
 921                 break;
 922         default:
 923                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 924                         size);
 925                 ret = -EOPNOTSUPP;
 926                 goto out;
 927         }
 928 
 929         if (hwpec)      /* enable/disable hardware PEC */
 930                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 931         else
 932                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 933                        SMBAUXCTL(priv));
 934 
 935         if (block)
 936                 ret = i801_block_transaction(priv, data, read_write, size,
 937                                              hwpec);
 938         else
 939                 ret = i801_transaction(priv, xact);
 940 
 941         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 942            time, so we forcibly disable it after every transaction. Turn off
 943            E32B for the same reason. */
 944         if (hwpec || block)
 945                 outb_p(inb_p(SMBAUXCTL(priv)) &
 946                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 947 
 948         if (block)
 949                 goto out;
 950         if (ret)
 951                 goto out;
 952         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 953                 goto out;
 954 
 955         switch (xact & 0x7f) {
 956         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 957         case I801_BYTE_DATA:
 958                 data->byte = inb_p(SMBHSTDAT0(priv));
 959                 break;
 960         case I801_WORD_DATA:
 961                 data->word = inb_p(SMBHSTDAT0(priv)) +
 962                              (inb_p(SMBHSTDAT1(priv)) << 8);
 963                 break;
 964         }
 965 
 966 out:
 967         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 968         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 969         mutex_unlock(&priv->acpi_lock);
 970         return ret;
 971 }
 972 
 973 
 974 static u32 i801_func(struct i2c_adapter *adapter)
 975 {
 976         struct i801_priv *priv = i2c_get_adapdata(adapter);
 977 
 978         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 979                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 980                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 981                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 982                ((priv->features & FEATURE_BLOCK_PROC) ?
 983                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
 984                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 985                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 986                ((priv->features & FEATURE_HOST_NOTIFY) ?
 987                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 988 }
 989 
 990 static void i801_enable_host_notify(struct i2c_adapter *adapter)
 991 {
 992         struct i801_priv *priv = i2c_get_adapdata(adapter);
 993 
 994         if (!(priv->features & FEATURE_HOST_NOTIFY))
 995                 return;
 996 
 997         if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
 998                 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
 999                        SMBSLVCMD(priv));
1000 
1001         /* clear Host Notify bit to allow a new notification */
1002         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
1003 }
1004 
1005 static void i801_disable_host_notify(struct i801_priv *priv)
1006 {
1007         if (!(priv->features & FEATURE_HOST_NOTIFY))
1008                 return;
1009 
1010         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
1011 }
1012 
1013 static const struct i2c_algorithm smbus_algorithm = {
1014         .smbus_xfer     = i801_access,
1015         .functionality  = i801_func,
1016 };
1017 
1018 static const struct pci_device_id i801_ids[] = {
1019         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
1020         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
1021         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
1022         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
1023         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1024         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1025         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1026         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1027         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1028         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1029         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1030         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1031         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1032         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1033         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1034         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1035         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1036         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1037         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1038         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1039         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1040         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1041         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1042         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1043         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1044         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1045         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1046         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1047         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1048         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1049         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1050         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1051         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1052         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1053         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1054         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1055         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1056         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1057         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1058         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1059         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1060         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1061         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1062         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1063         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1064         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1065         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1066         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1067         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
1068         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
1069         { 0, }
1070 };
1071 
1072 MODULE_DEVICE_TABLE(pci, i801_ids);
1073 
1074 #if defined CONFIG_X86 && defined CONFIG_DMI
1075 static unsigned char apanel_addr;
1076 
1077 /* Scan the system ROM for the signature "FJKEYINF" */
1078 static __init const void __iomem *bios_signature(const void __iomem *bios)
1079 {
1080         ssize_t offset;
1081         const unsigned char signature[] = "FJKEYINF";
1082 
1083         for (offset = 0; offset < 0x10000; offset += 0x10) {
1084                 if (check_signature(bios + offset, signature,
1085                                     sizeof(signature)-1))
1086                         return bios + offset;
1087         }
1088         return NULL;
1089 }
1090 
1091 static void __init input_apanel_init(void)
1092 {
1093         void __iomem *bios;
1094         const void __iomem *p;
1095 
1096         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1097         p = bios_signature(bios);
1098         if (p) {
1099                 /* just use the first address */
1100                 apanel_addr = readb(p + 8 + 3) >> 1;
1101         }
1102         iounmap(bios);
1103 }
1104 
1105 struct dmi_onboard_device_info {
1106         const char *name;
1107         u8 type;
1108         unsigned short i2c_addr;
1109         const char *i2c_type;
1110 };
1111 
1112 static const struct dmi_onboard_device_info dmi_devices[] = {
1113         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1114         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1115         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1116 };
1117 
1118 static void dmi_check_onboard_device(u8 type, const char *name,
1119                                      struct i2c_adapter *adap)
1120 {
1121         int i;
1122         struct i2c_board_info info;
1123 
1124         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1125                 /* & ~0x80, ignore enabled/disabled bit */
1126                 if ((type & ~0x80) != dmi_devices[i].type)
1127                         continue;
1128                 if (strcasecmp(name, dmi_devices[i].name))
1129                         continue;
1130 
1131                 memset(&info, 0, sizeof(struct i2c_board_info));
1132                 info.addr = dmi_devices[i].i2c_addr;
1133                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1134                 i2c_new_device(adap, &info);
1135                 break;
1136         }
1137 }
1138 
1139 /* We use our own function to check for onboard devices instead of
1140    dmi_find_device() as some buggy BIOS's have the devices we are interested
1141    in marked as disabled */
1142 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1143 {
1144         int i, count;
1145 
1146         if (dm->type != 10)
1147                 return;
1148 
1149         count = (dm->length - sizeof(struct dmi_header)) / 2;
1150         for (i = 0; i < count; i++) {
1151                 const u8 *d = (char *)(dm + 1) + (i * 2);
1152                 const char *name = ((char *) dm) + dm->length;
1153                 u8 type = d[0];
1154                 u8 s = d[1];
1155 
1156                 if (!s)
1157                         continue;
1158                 s--;
1159                 while (s > 0 && name[0]) {
1160                         name += strlen(name) + 1;
1161                         s--;
1162                 }
1163                 if (name[0] == 0) /* Bogus string reference */
1164                         continue;
1165 
1166                 dmi_check_onboard_device(type, name, adap);
1167         }
1168 }
1169 
1170 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1171 static const char *const acpi_smo8800_ids[] = {
1172         "SMO8800",
1173         "SMO8801",
1174         "SMO8810",
1175         "SMO8811",
1176         "SMO8820",
1177         "SMO8821",
1178         "SMO8830",
1179         "SMO8831",
1180 };
1181 
1182 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1183                                              u32 nesting_level,
1184                                              void *context,
1185                                              void **return_value)
1186 {
1187         struct acpi_device_info *info;
1188         acpi_status status;
1189         char *hid;
1190         int i;
1191 
1192         status = acpi_get_object_info(obj_handle, &info);
1193         if (ACPI_FAILURE(status))
1194                 return AE_OK;
1195 
1196         if (!(info->valid & ACPI_VALID_HID))
1197                 goto smo88xx_not_found;
1198 
1199         hid = info->hardware_id.string;
1200         if (!hid)
1201                 goto smo88xx_not_found;
1202 
1203         i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1204         if (i < 0)
1205                 goto smo88xx_not_found;
1206 
1207         kfree(info);
1208 
1209         *((bool *)return_value) = true;
1210         return AE_CTRL_TERMINATE;
1211 
1212 smo88xx_not_found:
1213         kfree(info);
1214         return AE_OK;
1215 }
1216 
1217 static bool is_dell_system_with_lis3lv02d(void)
1218 {
1219         bool found;
1220         const char *vendor;
1221 
1222         vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1223         if (!vendor || strcmp(vendor, "Dell Inc."))
1224                 return false;
1225 
1226         /*
1227          * Check that ACPI device SMO88xx is present and is functioning.
1228          * Function acpi_get_devices() already filters all ACPI devices
1229          * which are not present or are not functioning.
1230          * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1231          * accelerometer but unfortunately ACPI does not provide any other
1232          * information (like I2C address).
1233          */
1234         found = false;
1235         acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1236                          (void **)&found);
1237 
1238         return found;
1239 }
1240 
1241 /*
1242  * Accelerometer's I2C address is not specified in DMI nor ACPI,
1243  * so it is needed to define mapping table based on DMI product names.
1244  */
1245 static const struct {
1246         const char *dmi_product_name;
1247         unsigned short i2c_addr;
1248 } dell_lis3lv02d_devices[] = {
1249         /*
1250          * Dell platform team told us that these Latitude devices have
1251          * ST microelectronics accelerometer at I2C address 0x29.
1252          */
1253         { "Latitude E5250",     0x29 },
1254         { "Latitude E5450",     0x29 },
1255         { "Latitude E5550",     0x29 },
1256         { "Latitude E6440",     0x29 },
1257         { "Latitude E6440 ATG", 0x29 },
1258         { "Latitude E6540",     0x29 },
1259         /*
1260          * Additional individual entries were added after verification.
1261          */
1262         { "Vostro V131",        0x1d },
1263 };
1264 
1265 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1266 {
1267         struct i2c_board_info info;
1268         const char *dmi_product_name;
1269         int i;
1270 
1271         dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1272         for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1273                 if (strcmp(dmi_product_name,
1274                            dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1275                         break;
1276         }
1277 
1278         if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1279                 dev_warn(&priv->pci_dev->dev,
1280                          "Accelerometer lis3lv02d is present on SMBus but its"
1281                          " address is unknown, skipping registration\n");
1282                 return;
1283         }
1284 
1285         memset(&info, 0, sizeof(struct i2c_board_info));
1286         info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1287         strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1288         i2c_new_device(&priv->adapter, &info);
1289 }
1290 
1291 /* Register optional slaves */
1292 static void i801_probe_optional_slaves(struct i801_priv *priv)
1293 {
1294         /* Only register slaves on main SMBus channel */
1295         if (priv->features & FEATURE_IDF)
1296                 return;
1297 
1298         if (apanel_addr) {
1299                 struct i2c_board_info info;
1300 
1301                 memset(&info, 0, sizeof(struct i2c_board_info));
1302                 info.addr = apanel_addr;
1303                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1304                 i2c_new_device(&priv->adapter, &info);
1305         }
1306 
1307         if (dmi_name_in_vendors("FUJITSU"))
1308                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1309 
1310         if (is_dell_system_with_lis3lv02d())
1311                 register_dell_lis3lv02d_i2c_device(priv);
1312 }
1313 #else
1314 static void __init input_apanel_init(void) {}
1315 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1316 #endif  /* CONFIG_X86 && CONFIG_DMI */
1317 
1318 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1319 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1320         .gpio_chip = "gpio_ich",
1321         .values = { 0x02, 0x03 },
1322         .n_values = 2,
1323         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1324         .gpios = { 52, 53 },
1325         .n_gpios = 2,
1326 };
1327 
1328 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1329         .gpio_chip = "gpio_ich",
1330         .values = { 0x02, 0x03, 0x01 },
1331         .n_values = 3,
1332         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1333         .gpios = { 52, 53 },
1334         .n_gpios = 2,
1335 };
1336 
1337 static const struct dmi_system_id mux_dmi_table[] = {
1338         {
1339                 .matches = {
1340                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1341                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1342                 },
1343                 .driver_data = &i801_mux_config_asus_z8_d12,
1344         },
1345         {
1346                 .matches = {
1347                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1348                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1349                 },
1350                 .driver_data = &i801_mux_config_asus_z8_d12,
1351         },
1352         {
1353                 .matches = {
1354                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1355                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1356                 },
1357                 .driver_data = &i801_mux_config_asus_z8_d12,
1358         },
1359         {
1360                 .matches = {
1361                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1362                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1363                 },
1364                 .driver_data = &i801_mux_config_asus_z8_d12,
1365         },
1366         {
1367                 .matches = {
1368                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1369                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1370                 },
1371                 .driver_data = &i801_mux_config_asus_z8_d12,
1372         },
1373         {
1374                 .matches = {
1375                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1376                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1377                 },
1378                 .driver_data = &i801_mux_config_asus_z8_d12,
1379         },
1380         {
1381                 .matches = {
1382                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1383                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1384                 },
1385                 .driver_data = &i801_mux_config_asus_z8_d18,
1386         },
1387         {
1388                 .matches = {
1389                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1390                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1391                 },
1392                 .driver_data = &i801_mux_config_asus_z8_d18,
1393         },
1394         {
1395                 .matches = {
1396                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1397                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1398                 },
1399                 .driver_data = &i801_mux_config_asus_z8_d12,
1400         },
1401         { }
1402 };
1403 
1404 /* Setup multiplexing if needed */
1405 static int i801_add_mux(struct i801_priv *priv)
1406 {
1407         struct device *dev = &priv->adapter.dev;
1408         const struct i801_mux_config *mux_config;
1409         struct i2c_mux_gpio_platform_data gpio_data;
1410         struct gpiod_lookup_table *lookup;
1411         int err, i;
1412 
1413         if (!priv->mux_drvdata)
1414                 return 0;
1415         mux_config = priv->mux_drvdata;
1416 
1417         /* Prepare the platform data */
1418         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1419         gpio_data.parent = priv->adapter.nr;
1420         gpio_data.values = mux_config->values;
1421         gpio_data.n_values = mux_config->n_values;
1422         gpio_data.classes = mux_config->classes;
1423         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1424 
1425         /* Register GPIO descriptor lookup table */
1426         lookup = devm_kzalloc(dev,
1427                               struct_size(lookup, table, mux_config->n_gpios),
1428                               GFP_KERNEL);
1429         if (!lookup)
1430                 return -ENOMEM;
1431         lookup->dev_id = "i2c-mux-gpio";
1432         for (i = 0; i < mux_config->n_gpios; i++) {
1433                 lookup->table[i].chip_label = mux_config->gpio_chip;
1434                 lookup->table[i].chip_hwnum = mux_config->gpios[i];
1435                 lookup->table[i].con_id = "mux";
1436         }
1437         gpiod_add_lookup_table(lookup);
1438         priv->lookup = lookup;
1439 
1440         /*
1441          * Register the mux device, we use PLATFORM_DEVID_NONE here
1442          * because since we are referring to the GPIO chip by name we are
1443          * anyways in deep trouble if there is more than one of these
1444          * devices, and there should likely only be one platform controller
1445          * hub.
1446          */
1447         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1448                                 PLATFORM_DEVID_NONE, &gpio_data,
1449                                 sizeof(struct i2c_mux_gpio_platform_data));
1450         if (IS_ERR(priv->mux_pdev)) {
1451                 err = PTR_ERR(priv->mux_pdev);
1452                 gpiod_remove_lookup_table(lookup);
1453                 priv->mux_pdev = NULL;
1454                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1455                 return err;
1456         }
1457 
1458         return 0;
1459 }
1460 
1461 static void i801_del_mux(struct i801_priv *priv)
1462 {
1463         if (priv->mux_pdev)
1464                 platform_device_unregister(priv->mux_pdev);
1465         if (priv->lookup)
1466                 gpiod_remove_lookup_table(priv->lookup);
1467 }
1468 
1469 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1470 {
1471         const struct dmi_system_id *id;
1472         const struct i801_mux_config *mux_config;
1473         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1474         int i;
1475 
1476         id = dmi_first_match(mux_dmi_table);
1477         if (id) {
1478                 /* Remove branch classes from trunk */
1479                 mux_config = id->driver_data;
1480                 for (i = 0; i < mux_config->n_values; i++)
1481                         class &= ~mux_config->classes[i];
1482 
1483                 /* Remember for later */
1484                 priv->mux_drvdata = mux_config;
1485         }
1486 
1487         return class;
1488 }
1489 #else
1490 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1491 static inline void i801_del_mux(struct i801_priv *priv) { }
1492 
1493 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1494 {
1495         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1496 }
1497 #endif
1498 
1499 static const struct itco_wdt_platform_data spt_tco_platform_data = {
1500         .name = "Intel PCH",
1501         .version = 4,
1502 };
1503 
1504 static DEFINE_SPINLOCK(p2sb_spinlock);
1505 
1506 static struct platform_device *
1507 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1508                  struct resource *tco_res)
1509 {
1510         struct resource *res;
1511         unsigned int devfn;
1512         u64 base64_addr;
1513         u32 base_addr;
1514         u8 hidden;
1515 
1516         /*
1517          * We must access the NO_REBOOT bit over the Primary to Sideband
1518          * bridge (P2SB). The BIOS prevents the P2SB device from being
1519          * enumerated by the PCI subsystem, so we need to unhide/hide it
1520          * to lookup the P2SB BAR.
1521          */
1522         spin_lock(&p2sb_spinlock);
1523 
1524         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1525 
1526         /* Unhide the P2SB device, if it is hidden */
1527         pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1528         if (hidden)
1529                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1530 
1531         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1532         base64_addr = base_addr & 0xfffffff0;
1533 
1534         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1535         base64_addr |= (u64)base_addr << 32;
1536 
1537         /* Hide the P2SB device, if it was hidden before */
1538         if (hidden)
1539                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1540         spin_unlock(&p2sb_spinlock);
1541 
1542         res = &tco_res[1];
1543         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1544                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1545         else
1546                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1547 
1548         res->end = res->start + 3;
1549         res->flags = IORESOURCE_MEM;
1550 
1551         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1552                                         tco_res, 2, &spt_tco_platform_data,
1553                                         sizeof(spt_tco_platform_data));
1554 }
1555 
1556 static const struct itco_wdt_platform_data cnl_tco_platform_data = {
1557         .name = "Intel PCH",
1558         .version = 6,
1559 };
1560 
1561 static struct platform_device *
1562 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1563                  struct resource *tco_res)
1564 {
1565         return platform_device_register_resndata(&pci_dev->dev,
1566                         "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data,
1567                         sizeof(cnl_tco_platform_data));
1568 }
1569 
1570 static void i801_add_tco(struct i801_priv *priv)
1571 {
1572         struct pci_dev *pci_dev = priv->pci_dev;
1573         struct resource tco_res[2], *res;
1574         u32 tco_base, tco_ctl;
1575 
1576         /* If we have ACPI based watchdog use that instead */
1577         if (acpi_has_watchdog())
1578                 return;
1579 
1580         if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1581                 return;
1582 
1583         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1584         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1585         if (!(tco_ctl & TCOCTL_EN))
1586                 return;
1587 
1588         memset(tco_res, 0, sizeof(tco_res));
1589         /*
1590          * Always populate the main iTCO IO resource here. The second entry
1591          * for NO_REBOOT MMIO is filled by the SPT specific function.
1592          */
1593         res = &tco_res[0];
1594         res->start = tco_base & ~1;
1595         res->end = res->start + 32 - 1;
1596         res->flags = IORESOURCE_IO;
1597 
1598         if (priv->features & FEATURE_TCO_CNL)
1599                 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1600         else
1601                 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1602 
1603         if (IS_ERR(priv->tco_pdev))
1604                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1605 }
1606 
1607 #ifdef CONFIG_ACPI
1608 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1609                                       acpi_physical_address address)
1610 {
1611         return address >= priv->smba &&
1612                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1613 }
1614 
1615 static acpi_status
1616 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1617                      u64 *value, void *handler_context, void *region_context)
1618 {
1619         struct i801_priv *priv = handler_context;
1620         struct pci_dev *pdev = priv->pci_dev;
1621         acpi_status status;
1622 
1623         /*
1624          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1625          * further access from the driver itself. This device is now owned
1626          * by the system firmware.
1627          */
1628         mutex_lock(&priv->acpi_lock);
1629 
1630         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1631                 priv->acpi_reserved = true;
1632 
1633                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1634                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1635 
1636                 /*
1637                  * BIOS is accessing the host controller so prevent it from
1638                  * suspending automatically from now on.
1639                  */
1640                 pm_runtime_get_sync(&pdev->dev);
1641         }
1642 
1643         if ((function & ACPI_IO_MASK) == ACPI_READ)
1644                 status = acpi_os_read_port(address, (u32 *)value, bits);
1645         else
1646                 status = acpi_os_write_port(address, (u32)*value, bits);
1647 
1648         mutex_unlock(&priv->acpi_lock);
1649 
1650         return status;
1651 }
1652 
1653 static int i801_acpi_probe(struct i801_priv *priv)
1654 {
1655         struct acpi_device *adev;
1656         acpi_status status;
1657 
1658         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1659         if (adev) {
1660                 status = acpi_install_address_space_handler(adev->handle,
1661                                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1662                                 NULL, priv);
1663                 if (ACPI_SUCCESS(status))
1664                         return 0;
1665         }
1666 
1667         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1668 }
1669 
1670 static void i801_acpi_remove(struct i801_priv *priv)
1671 {
1672         struct acpi_device *adev;
1673 
1674         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1675         if (!adev)
1676                 return;
1677 
1678         acpi_remove_address_space_handler(adev->handle,
1679                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1680 
1681         mutex_lock(&priv->acpi_lock);
1682         if (priv->acpi_reserved)
1683                 pm_runtime_put(&priv->pci_dev->dev);
1684         mutex_unlock(&priv->acpi_lock);
1685 }
1686 #else
1687 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1688 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1689 #endif
1690 
1691 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1692 {
1693         unsigned char temp;
1694         int err, i;
1695         struct i801_priv *priv;
1696 
1697         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1698         if (!priv)
1699                 return -ENOMEM;
1700 
1701         i2c_set_adapdata(&priv->adapter, priv);
1702         priv->adapter.owner = THIS_MODULE;
1703         priv->adapter.class = i801_get_adapter_class(priv);
1704         priv->adapter.algo = &smbus_algorithm;
1705         priv->adapter.dev.parent = &dev->dev;
1706         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1707         priv->adapter.retries = 3;
1708         mutex_init(&priv->acpi_lock);
1709 
1710         priv->pci_dev = dev;
1711         switch (dev->device) {
1712         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1713         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1714         case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1715         case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1716         case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1717         case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1718                 priv->features |= FEATURE_BLOCK_PROC;
1719                 priv->features |= FEATURE_I2C_BLOCK_READ;
1720                 priv->features |= FEATURE_IRQ;
1721                 priv->features |= FEATURE_SMBUS_PEC;
1722                 priv->features |= FEATURE_BLOCK_BUFFER;
1723                 priv->features |= FEATURE_TCO_SPT;
1724                 priv->features |= FEATURE_HOST_NOTIFY;
1725                 break;
1726 
1727         case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1728         case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1729         case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1730         case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1731         case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1732         case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
1733         case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
1734                 priv->features |= FEATURE_BLOCK_PROC;
1735                 priv->features |= FEATURE_I2C_BLOCK_READ;
1736                 priv->features |= FEATURE_IRQ;
1737                 priv->features |= FEATURE_SMBUS_PEC;
1738                 priv->features |= FEATURE_BLOCK_BUFFER;
1739                 priv->features |= FEATURE_TCO_CNL;
1740                 priv->features |= FEATURE_HOST_NOTIFY;
1741                 break;
1742 
1743         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1744         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1745         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1746         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1747         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1748         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1749                 priv->features |= FEATURE_IDF;
1750                 /* fall through */
1751         default:
1752                 priv->features |= FEATURE_BLOCK_PROC;
1753                 priv->features |= FEATURE_I2C_BLOCK_READ;
1754                 priv->features |= FEATURE_IRQ;
1755                 /* fall through */
1756         case PCI_DEVICE_ID_INTEL_82801DB_3:
1757                 priv->features |= FEATURE_SMBUS_PEC;
1758                 priv->features |= FEATURE_BLOCK_BUFFER;
1759                 /* fall through */
1760         case PCI_DEVICE_ID_INTEL_82801CA_3:
1761                 priv->features |= FEATURE_HOST_NOTIFY;
1762                 /* fall through */
1763         case PCI_DEVICE_ID_INTEL_82801BA_2:
1764         case PCI_DEVICE_ID_INTEL_82801AB_3:
1765         case PCI_DEVICE_ID_INTEL_82801AA_3:
1766                 break;
1767         }
1768 
1769         /* Disable features on user request */
1770         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1771                 if (priv->features & disable_features & (1 << i))
1772                         dev_notice(&dev->dev, "%s disabled by user\n",
1773                                    i801_feature_names[i]);
1774         }
1775         priv->features &= ~disable_features;
1776 
1777         err = pcim_enable_device(dev);
1778         if (err) {
1779                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1780                         err);
1781                 return err;
1782         }
1783         pcim_pin_device(dev);
1784 
1785         /* Determine the address of the SMBus area */
1786         priv->smba = pci_resource_start(dev, SMBBAR);
1787         if (!priv->smba) {
1788                 dev_err(&dev->dev,
1789                         "SMBus base address uninitialized, upgrade BIOS\n");
1790                 return -ENODEV;
1791         }
1792 
1793         if (i801_acpi_probe(priv))
1794                 return -ENODEV;
1795 
1796         err = pcim_iomap_regions(dev, 1 << SMBBAR,
1797                                  dev_driver_string(&dev->dev));
1798         if (err) {
1799                 dev_err(&dev->dev,
1800                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1801                         priv->smba,
1802                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1803                 i801_acpi_remove(priv);
1804                 return err;
1805         }
1806 
1807         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1808         priv->original_hstcfg = temp;
1809         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1810         if (!(temp & SMBHSTCFG_HST_EN)) {
1811                 dev_info(&dev->dev, "Enabling SMBus device\n");
1812                 temp |= SMBHSTCFG_HST_EN;
1813         }
1814         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1815 
1816         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1817                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1818                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1819                 priv->features &= ~FEATURE_IRQ;
1820         }
1821         if (temp & SMBHSTCFG_SPD_WD)
1822                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1823 
1824         /* Clear special mode bits */
1825         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1826                 outb_p(inb_p(SMBAUXCTL(priv)) &
1827                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1828 
1829         /* Remember original Host Notify setting */
1830         if (priv->features & FEATURE_HOST_NOTIFY)
1831                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1832 
1833         /* Default timeout in interrupt mode: 200 ms */
1834         priv->adapter.timeout = HZ / 5;
1835 
1836         if (dev->irq == IRQ_NOTCONNECTED)
1837                 priv->features &= ~FEATURE_IRQ;
1838 
1839         if (priv->features & FEATURE_IRQ) {
1840                 u16 pcictl, pcists;
1841 
1842                 /* Complain if an interrupt is already pending */
1843                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1844                 if (pcists & SMBPCISTS_INTS)
1845                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1846 
1847                 /* Check if interrupts have been disabled */
1848                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1849                 if (pcictl & SMBPCICTL_INTDIS) {
1850                         dev_info(&dev->dev, "Interrupts are disabled\n");
1851                         priv->features &= ~FEATURE_IRQ;
1852                 }
1853         }
1854 
1855         if (priv->features & FEATURE_IRQ) {
1856                 init_waitqueue_head(&priv->waitq);
1857 
1858                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1859                                        IRQF_SHARED,
1860                                        dev_driver_string(&dev->dev), priv);
1861                 if (err) {
1862                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1863                                 dev->irq, err);
1864                         priv->features &= ~FEATURE_IRQ;
1865                 }
1866         }
1867         dev_info(&dev->dev, "SMBus using %s\n",
1868                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1869 
1870         i801_add_tco(priv);
1871 
1872         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1873                 "SMBus I801 adapter at %04lx", priv->smba);
1874         err = i2c_add_adapter(&priv->adapter);
1875         if (err) {
1876                 i801_acpi_remove(priv);
1877                 return err;
1878         }
1879 
1880         i801_enable_host_notify(&priv->adapter);
1881 
1882         i801_probe_optional_slaves(priv);
1883         /* We ignore errors - multiplexing is optional */
1884         i801_add_mux(priv);
1885 
1886         pci_set_drvdata(dev, priv);
1887 
1888         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1889         pm_runtime_use_autosuspend(&dev->dev);
1890         pm_runtime_put_autosuspend(&dev->dev);
1891         pm_runtime_allow(&dev->dev);
1892 
1893         return 0;
1894 }
1895 
1896 static void i801_remove(struct pci_dev *dev)
1897 {
1898         struct i801_priv *priv = pci_get_drvdata(dev);
1899 
1900         pm_runtime_forbid(&dev->dev);
1901         pm_runtime_get_noresume(&dev->dev);
1902 
1903         i801_disable_host_notify(priv);
1904         i801_del_mux(priv);
1905         i2c_del_adapter(&priv->adapter);
1906         i801_acpi_remove(priv);
1907         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1908 
1909         platform_device_unregister(priv->tco_pdev);
1910 
1911         /*
1912          * do not call pci_disable_device(dev) since it can cause hard hangs on
1913          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1914          */
1915 }
1916 
1917 static void i801_shutdown(struct pci_dev *dev)
1918 {
1919         struct i801_priv *priv = pci_get_drvdata(dev);
1920 
1921         /* Restore config registers to avoid hard hang on some systems */
1922         i801_disable_host_notify(priv);
1923         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1924 }
1925 
1926 #ifdef CONFIG_PM_SLEEP
1927 static int i801_suspend(struct device *dev)
1928 {
1929         struct pci_dev *pci_dev = to_pci_dev(dev);
1930         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1931 
1932         pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1933         return 0;
1934 }
1935 
1936 static int i801_resume(struct device *dev)
1937 {
1938         struct i801_priv *priv = dev_get_drvdata(dev);
1939 
1940         i801_enable_host_notify(&priv->adapter);
1941 
1942         return 0;
1943 }
1944 #endif
1945 
1946 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1947 
1948 static struct pci_driver i801_driver = {
1949         .name           = "i801_smbus",
1950         .id_table       = i801_ids,
1951         .probe          = i801_probe,
1952         .remove         = i801_remove,
1953         .shutdown       = i801_shutdown,
1954         .driver         = {
1955                 .pm     = &i801_pm_ops,
1956         },
1957 };
1958 
1959 static int __init i2c_i801_init(void)
1960 {
1961         if (dmi_name_in_vendors("FUJITSU"))
1962                 input_apanel_init();
1963         return pci_register_driver(&i801_driver);
1964 }
1965 
1966 static void __exit i2c_i801_exit(void)
1967 {
1968         pci_unregister_driver(&i801_driver);
1969 }
1970 
1971 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1972 MODULE_DESCRIPTION("I801 SMBus driver");
1973 MODULE_LICENSE("GPL");
1974 
1975 module_init(i2c_i801_init);
1976 module_exit(i2c_i801_exit);

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