drivers/i2c/busses/i2c-s3c2410.c

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This source file includes following definitions.
s3c24xx_get_device_quirks
s3c24xx_i2c_master_complete
s3c24xx_i2c_disable_ack
s3c24xx_i2c_enable_ack
s3c24xx_i2c_disable_irq
s3c24xx_i2c_enable_irq
is_ack
s3c24xx_i2c_message_start
s3c24xx_i2c_stop
is_lastmsg
is_msglast
is_msgend
i2c_s3c_irq_nextbyte
s3c24xx_i2c_irq
s3c24xx_i2c_disable_bus
s3c24xx_i2c_set_master
s3c24xx_i2c_wait_idle
s3c24xx_i2c_doxfer
s3c24xx_i2c_xfer
s3c24xx_i2c_func
s3c24xx_i2c_calcdivisor
s3c24xx_i2c_clockrate
s3c24xx_i2c_cpufreq_transition
s3c24xx_i2c_register_cpufreq
s3c24xx_i2c_deregister_cpufreq
s3c24xx_i2c_register_cpufreq
s3c24xx_i2c_deregister_cpufreq
s3c24xx_i2c_parse_dt_gpio
s3c24xx_i2c_parse_dt_gpio
s3c24xx_i2c_init
s3c24xx_i2c_parse_dt
s3c24xx_i2c_parse_dt
s3c24xx_i2c_probe
s3c24xx_i2c_remove
s3c24xx_i2c_suspend_noirq
s3c24xx_i2c_resume_noirq
i2c_adap_s3c_init
i2c_adap_s3c_exit
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
   3  *
   4  * Copyright (C) 2004,2005,2009 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * S3C2410 I2C Controller
   8 */
   9 
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 
  13 #include <linux/i2c.h>
  14 #include <linux/init.h>
  15 #include <linux/time.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/delay.h>
  18 #include <linux/errno.h>
  19 #include <linux/err.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/clk.h>
  23 #include <linux/cpufreq.h>
  24 #include <linux/slab.h>
  25 #include <linux/io.h>
  26 #include <linux/of.h>
  27 #include <linux/gpio/consumer.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/mfd/syscon.h>
  30 #include <linux/regmap.h>
  31 
  32 #include <asm/irq.h>
  33 
  34 #include <linux/platform_data/i2c-s3c2410.h>
  35 
  36 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
  37 
  38 #define S3C2410_IICCON                  0x00
  39 #define S3C2410_IICSTAT                 0x04
  40 #define S3C2410_IICADD                  0x08
  41 #define S3C2410_IICDS                   0x0C
  42 #define S3C2440_IICLC                   0x10
  43 
  44 #define S3C2410_IICCON_ACKEN            (1 << 7)
  45 #define S3C2410_IICCON_TXDIV_16         (0 << 6)
  46 #define S3C2410_IICCON_TXDIV_512        (1 << 6)
  47 #define S3C2410_IICCON_IRQEN            (1 << 5)
  48 #define S3C2410_IICCON_IRQPEND          (1 << 4)
  49 #define S3C2410_IICCON_SCALE(x)         ((x) & 0xf)
  50 #define S3C2410_IICCON_SCALEMASK        (0xf)
  51 
  52 #define S3C2410_IICSTAT_MASTER_RX       (2 << 6)
  53 #define S3C2410_IICSTAT_MASTER_TX       (3 << 6)
  54 #define S3C2410_IICSTAT_SLAVE_RX        (0 << 6)
  55 #define S3C2410_IICSTAT_SLAVE_TX        (1 << 6)
  56 #define S3C2410_IICSTAT_MODEMASK        (3 << 6)
  57 
  58 #define S3C2410_IICSTAT_START           (1 << 5)
  59 #define S3C2410_IICSTAT_BUSBUSY         (1 << 5)
  60 #define S3C2410_IICSTAT_TXRXEN          (1 << 4)
  61 #define S3C2410_IICSTAT_ARBITR          (1 << 3)
  62 #define S3C2410_IICSTAT_ASSLAVE         (1 << 2)
  63 #define S3C2410_IICSTAT_ADDR0           (1 << 1)
  64 #define S3C2410_IICSTAT_LASTBIT         (1 << 0)
  65 
  66 #define S3C2410_IICLC_SDA_DELAY0        (0 << 0)
  67 #define S3C2410_IICLC_SDA_DELAY5        (1 << 0)
  68 #define S3C2410_IICLC_SDA_DELAY10       (2 << 0)
  69 #define S3C2410_IICLC_SDA_DELAY15       (3 << 0)
  70 #define S3C2410_IICLC_SDA_DELAY_MASK    (3 << 0)
  71 
  72 #define S3C2410_IICLC_FILTER_ON         (1 << 2)
  73 
  74 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
  75 #define QUIRK_S3C2440           (1 << 0)
  76 #define QUIRK_HDMIPHY           (1 << 1)
  77 #define QUIRK_NO_GPIO           (1 << 2)
  78 #define QUIRK_POLL              (1 << 3)
  79 
  80 /* Max time to wait for bus to become idle after a xfer (in us) */
  81 #define S3C2410_IDLE_TIMEOUT    5000
  82 
  83 /* Exynos5 Sysreg offset */
  84 #define EXYNOS5_SYS_I2C_CFG     0x0234
  85 
  86 /* i2c controller state */
  87 enum s3c24xx_i2c_state {
  88         STATE_IDLE,
  89         STATE_START,
  90         STATE_READ,
  91         STATE_WRITE,
  92         STATE_STOP
  93 };
  94 
  95 struct s3c24xx_i2c {
  96         wait_queue_head_t       wait;
  97         kernel_ulong_t          quirks;
  98 
  99         struct i2c_msg          *msg;
 100         unsigned int            msg_num;
 101         unsigned int            msg_idx;
 102         unsigned int            msg_ptr;
 103 
 104         unsigned int            tx_setup;
 105         unsigned int            irq;
 106 
 107         enum s3c24xx_i2c_state  state;
 108         unsigned long           clkrate;
 109 
 110         void __iomem            *regs;
 111         struct clk              *clk;
 112         struct device           *dev;
 113         struct i2c_adapter      adap;
 114 
 115         struct s3c2410_platform_i2c     *pdata;
 116         struct gpio_desc        *gpios[2];
 117         struct pinctrl          *pctrl;
 118 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
 119         struct notifier_block   freq_transition;
 120 #endif
 121         struct regmap           *sysreg;
 122         unsigned int            sys_i2c_cfg;
 123 };
 124 
 125 static const struct platform_device_id s3c24xx_driver_ids[] = {
 126         {
 127                 .name           = "s3c2410-i2c",
 128                 .driver_data    = 0,
 129         }, {
 130                 .name           = "s3c2440-i2c",
 131                 .driver_data    = QUIRK_S3C2440,
 132         }, {
 133                 .name           = "s3c2440-hdmiphy-i2c",
 134                 .driver_data    = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
 135         }, { },
 136 };
 137 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
 138 
 139 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
 140 
 141 #ifdef CONFIG_OF
 142 static const struct of_device_id s3c24xx_i2c_match[] = {
 143         { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
 144         { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
 145         { .compatible = "samsung,s3c2440-hdmiphy-i2c",
 146           .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
 147         { .compatible = "samsung,exynos5-sata-phy-i2c",
 148           .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
 149         {},
 150 };
 151 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
 152 #endif
 153 
 154 /*
 155  * Get controller type either from device tree or platform device variant.
 156  */
 157 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
 158 {
 159         if (pdev->dev.of_node) {
 160                 const struct of_device_id *match;
 161 
 162                 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
 163                 return (kernel_ulong_t)match->data;
 164         }
 165 
 166         return platform_get_device_id(pdev)->driver_data;
 167 }
 168 
 169 /*
 170  * Complete the message and wake up the caller, using the given return code,
 171  * or zero to mean ok.
 172  */
 173 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 174 {
 175         dev_dbg(i2c->dev, "master_complete %d\n", ret);
 176 
 177         i2c->msg_ptr = 0;
 178         i2c->msg = NULL;
 179         i2c->msg_idx++;
 180         i2c->msg_num = 0;
 181         if (ret)
 182                 i2c->msg_idx = ret;
 183 
 184         if (!(i2c->quirks & QUIRK_POLL))
 185                 wake_up(&i2c->wait);
 186 }
 187 
 188 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 189 {
 190         unsigned long tmp;
 191 
 192         tmp = readl(i2c->regs + S3C2410_IICCON);
 193         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 194 }
 195 
 196 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 197 {
 198         unsigned long tmp;
 199 
 200         tmp = readl(i2c->regs + S3C2410_IICCON);
 201         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 202 }
 203 
 204 /* irq enable/disable functions */
 205 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 206 {
 207         unsigned long tmp;
 208 
 209         tmp = readl(i2c->regs + S3C2410_IICCON);
 210         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 211 }
 212 
 213 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 214 {
 215         unsigned long tmp;
 216 
 217         tmp = readl(i2c->regs + S3C2410_IICCON);
 218         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 219 }
 220 
 221 static bool is_ack(struct s3c24xx_i2c *i2c)
 222 {
 223         int tries;
 224 
 225         for (tries = 50; tries; --tries) {
 226                 if (readl(i2c->regs + S3C2410_IICCON)
 227                         & S3C2410_IICCON_IRQPEND) {
 228                         if (!(readl(i2c->regs + S3C2410_IICSTAT)
 229                                 & S3C2410_IICSTAT_LASTBIT))
 230                                 return true;
 231                 }
 232                 usleep_range(1000, 2000);
 233         }
 234         dev_err(i2c->dev, "ack was not received\n");
 235         return false;
 236 }
 237 
 238 /*
 239  * put the start of a message onto the bus
 240  */
 241 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 242                                       struct i2c_msg *msg)
 243 {
 244         unsigned int addr = (msg->addr & 0x7f) << 1;
 245         unsigned long stat;
 246         unsigned long iiccon;
 247 
 248         stat = 0;
 249         stat |=  S3C2410_IICSTAT_TXRXEN;
 250 
 251         if (msg->flags & I2C_M_RD) {
 252                 stat |= S3C2410_IICSTAT_MASTER_RX;
 253                 addr |= 1;
 254         } else
 255                 stat |= S3C2410_IICSTAT_MASTER_TX;
 256 
 257         if (msg->flags & I2C_M_REV_DIR_ADDR)
 258                 addr ^= 1;
 259 
 260         /* todo - check for whether ack wanted or not */
 261         s3c24xx_i2c_enable_ack(i2c);
 262 
 263         iiccon = readl(i2c->regs + S3C2410_IICCON);
 264         writel(stat, i2c->regs + S3C2410_IICSTAT);
 265 
 266         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
 267         writeb(addr, i2c->regs + S3C2410_IICDS);
 268 
 269         /*
 270          * delay here to ensure the data byte has gotten onto the bus
 271          * before the transaction is started
 272          */
 273         ndelay(i2c->tx_setup);
 274 
 275         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
 276         writel(iiccon, i2c->regs + S3C2410_IICCON);
 277 
 278         stat |= S3C2410_IICSTAT_START;
 279         writel(stat, i2c->regs + S3C2410_IICSTAT);
 280 
 281         if (i2c->quirks & QUIRK_POLL) {
 282                 while ((i2c->msg_num != 0) && is_ack(i2c)) {
 283                         i2c_s3c_irq_nextbyte(i2c, stat);
 284                         stat = readl(i2c->regs + S3C2410_IICSTAT);
 285 
 286                         if (stat & S3C2410_IICSTAT_ARBITR)
 287                                 dev_err(i2c->dev, "deal with arbitration loss\n");
 288                 }
 289         }
 290 }
 291 
 292 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 293 {
 294         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 295 
 296         dev_dbg(i2c->dev, "STOP\n");
 297 
 298         /*
 299          * The datasheet says that the STOP sequence should be:
 300          *  1) I2CSTAT.5 = 0    - Clear BUSY (or 'generate STOP')
 301          *  2) I2CCON.4 = 0     - Clear IRQPEND
 302          *  3) Wait until the stop condition takes effect.
 303          *  4*) I2CSTAT.4 = 0   - Clear TXRXEN
 304          *
 305          * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
 306          *
 307          * However, after much experimentation, it appears that:
 308          * a) normal buses automatically clear BUSY and transition from
 309          *    Master->Slave when they complete generating a STOP condition.
 310          *    Therefore, step (3) can be done in doxfer() by polling I2CCON.4
 311          *    after starting the STOP generation here.
 312          * b) HDMIPHY bus does neither, so there is no way to do step 3.
 313          *    There is no indication when this bus has finished generating
 314          *    STOP.
 315          *
 316          * In fact, we have found that as soon as the IRQPEND bit is cleared in
 317          * step 2, the HDMIPHY bus generates the STOP condition, and then
 318          * immediately starts transferring another data byte, even though the
 319          * bus is supposedly stopped.  This is presumably because the bus is
 320          * still in "Master" mode, and its BUSY bit is still set.
 321          *
 322          * To avoid these extra post-STOP transactions on HDMI phy devices, we
 323          * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
 324          * instead of first generating a proper STOP condition.  This should
 325          * float SDA & SCK terminating the transfer.  Subsequent transfers
 326          *  start with a proper START condition, and proceed normally.
 327          *
 328          * The HDMIPHY bus is an internal bus that always has exactly two
 329          * devices, the host as Master and the HDMIPHY device as the slave.
 330          * Skipping the STOP condition has been tested on this bus and works.
 331          */
 332         if (i2c->quirks & QUIRK_HDMIPHY) {
 333                 /* Stop driving the I2C pins */
 334                 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
 335         } else {
 336                 /* stop the transfer */
 337                 iicstat &= ~S3C2410_IICSTAT_START;
 338         }
 339         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 340 
 341         i2c->state = STATE_STOP;
 342 
 343         s3c24xx_i2c_master_complete(i2c, ret);
 344         s3c24xx_i2c_disable_irq(i2c);
 345 }
 346 
 347 /*
 348  * helper functions to determine the current state in the set of
 349  * messages we are sending
 350  */
 351 
 352 /*
 353  * returns TRUE if the current message is the last in the set
 354  */
 355 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 356 {
 357         return i2c->msg_idx >= (i2c->msg_num - 1);
 358 }
 359 
 360 /*
 361  * returns TRUE if we this is the last byte in the current message
 362  */
 363 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 364 {
 365         /*
 366          * msg->len is always 1 for the first byte of smbus block read.
 367          * Actual length will be read from slave. More bytes will be
 368          * read according to the length then.
 369          */
 370         if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 371                 return 0;
 372 
 373         return i2c->msg_ptr == i2c->msg->len-1;
 374 }
 375 
 376 /*
 377  * returns TRUE if we reached the end of the current message
 378  */
 379 static inline int is_msgend(struct s3c24xx_i2c *i2c)
 380 {
 381         return i2c->msg_ptr >= i2c->msg->len;
 382 }
 383 
 384 /*
 385  * process an interrupt and work out what to do
 386  */
 387 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 388 {
 389         unsigned long tmp;
 390         unsigned char byte;
 391         int ret = 0;
 392 
 393         switch (i2c->state) {
 394 
 395         case STATE_IDLE:
 396                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
 397                 goto out;
 398 
 399         case STATE_STOP:
 400                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
 401                 s3c24xx_i2c_disable_irq(i2c);
 402                 goto out_ack;
 403 
 404         case STATE_START:
 405                 /*
 406                  * last thing we did was send a start condition on the
 407                  * bus, or started a new i2c message
 408                  */
 409                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
 410                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 411                         /* ack was not received... */
 412                         dev_dbg(i2c->dev, "ack was not received\n");
 413                         s3c24xx_i2c_stop(i2c, -ENXIO);
 414                         goto out_ack;
 415                 }
 416 
 417                 if (i2c->msg->flags & I2C_M_RD)
 418                         i2c->state = STATE_READ;
 419                 else
 420                         i2c->state = STATE_WRITE;
 421 
 422                 /*
 423                  * Terminate the transfer if there is nothing to do
 424                  * as this is used by the i2c probe to find devices.
 425                  */
 426                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
 427                         s3c24xx_i2c_stop(i2c, 0);
 428                         goto out_ack;
 429                 }
 430 
 431                 if (i2c->state == STATE_READ)
 432                         goto prepare_read;
 433 
 434                 /*
 435                  * fall through to the write state, as we will need to
 436                  * send a byte as well
 437                  */
 438                 /* Fall through */
 439 
 440         case STATE_WRITE:
 441                 /*
 442                  * we are writing data to the device... check for the
 443                  * end of the message, and if so, work out what to do
 444                  */
 445                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 446                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
 447                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
 448 
 449                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
 450                                 goto out_ack;
 451                         }
 452                 }
 453 
 454  retry_write:
 455 
 456                 if (!is_msgend(i2c)) {
 457                         byte = i2c->msg->buf[i2c->msg_ptr++];
 458                         writeb(byte, i2c->regs + S3C2410_IICDS);
 459 
 460                         /*
 461                          * delay after writing the byte to allow the
 462                          * data setup time on the bus, as writing the
 463                          * data to the register causes the first bit
 464                          * to appear on SDA, and SCL will change as
 465                          * soon as the interrupt is acknowledged
 466                          */
 467                         ndelay(i2c->tx_setup);
 468 
 469                 } else if (!is_lastmsg(i2c)) {
 470                         /* we need to go to the next i2c message */
 471 
 472                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
 473 
 474                         i2c->msg_ptr = 0;
 475                         i2c->msg_idx++;
 476                         i2c->msg++;
 477 
 478                         /* check to see if we need to do another message */
 479                         if (i2c->msg->flags & I2C_M_NOSTART) {
 480 
 481                                 if (i2c->msg->flags & I2C_M_RD) {
 482                                         /*
 483                                          * cannot do this, the controller
 484                                          * forces us to send a new START
 485                                          * when we change direction
 486                                          */
 487                                         s3c24xx_i2c_stop(i2c, -EINVAL);
 488                                 }
 489 
 490                                 goto retry_write;
 491                         } else {
 492                                 /* send the new start */
 493                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
 494                                 i2c->state = STATE_START;
 495                         }
 496 
 497                 } else {
 498                         /* send stop */
 499                         s3c24xx_i2c_stop(i2c, 0);
 500                 }
 501                 break;
 502 
 503         case STATE_READ:
 504                 /*
 505                  * we have a byte of data in the data register, do
 506                  * something with it, and then work out whether we are
 507                  * going to do any more read/write
 508                  */
 509                 byte = readb(i2c->regs + S3C2410_IICDS);
 510                 i2c->msg->buf[i2c->msg_ptr++] = byte;
 511 
 512                 /* Add actual length to read for smbus block read */
 513                 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 514                         i2c->msg->len += byte;
 515  prepare_read:
 516                 if (is_msglast(i2c)) {
 517                         /* last byte of buffer */
 518 
 519                         if (is_lastmsg(i2c))
 520                                 s3c24xx_i2c_disable_ack(i2c);
 521 
 522                 } else if (is_msgend(i2c)) {
 523                         /*
 524                          * ok, we've read the entire buffer, see if there
 525                          * is anything else we need to do
 526                          */
 527                         if (is_lastmsg(i2c)) {
 528                                 /* last message, send stop and complete */
 529                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
 530 
 531                                 s3c24xx_i2c_stop(i2c, 0);
 532                         } else {
 533                                 /* go to the next transfer */
 534                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
 535 
 536                                 i2c->msg_ptr = 0;
 537                                 i2c->msg_idx++;
 538                                 i2c->msg++;
 539                         }
 540                 }
 541 
 542                 break;
 543         }
 544 
 545         /* acknowlegde the IRQ and get back on with the work */
 546 
 547  out_ack:
 548         tmp = readl(i2c->regs + S3C2410_IICCON);
 549         tmp &= ~S3C2410_IICCON_IRQPEND;
 550         writel(tmp, i2c->regs + S3C2410_IICCON);
 551  out:
 552         return ret;
 553 }
 554 
 555 /*
 556  * top level IRQ servicing routine
 557  */
 558 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
 559 {
 560         struct s3c24xx_i2c *i2c = dev_id;
 561         unsigned long status;
 562         unsigned long tmp;
 563 
 564         status = readl(i2c->regs + S3C2410_IICSTAT);
 565 
 566         if (status & S3C2410_IICSTAT_ARBITR) {
 567                 /* deal with arbitration loss */
 568                 dev_err(i2c->dev, "deal with arbitration loss\n");
 569         }
 570 
 571         if (i2c->state == STATE_IDLE) {
 572                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 573 
 574                 tmp = readl(i2c->regs + S3C2410_IICCON);
 575                 tmp &= ~S3C2410_IICCON_IRQPEND;
 576                 writel(tmp, i2c->regs +  S3C2410_IICCON);
 577                 goto out;
 578         }
 579 
 580         /*
 581          * pretty much this leaves us with the fact that we've
 582          * transmitted or received whatever byte we last sent
 583          */
 584         i2c_s3c_irq_nextbyte(i2c, status);
 585 
 586  out:
 587         return IRQ_HANDLED;
 588 }
 589 
 590 /*
 591  * Disable the bus so that we won't get any interrupts from now on, or try
 592  * to drive any lines. This is the default state when we don't have
 593  * anything to send/receive.
 594  *
 595  * If there is an event on the bus, or we have a pre-existing event at
 596  * kernel boot time, we may not notice the event and the I2C controller
 597  * will lock the bus with the I2C clock line low indefinitely.
 598  */
 599 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
 600 {
 601         unsigned long tmp;
 602 
 603         /* Stop driving the I2C pins */
 604         tmp = readl(i2c->regs + S3C2410_IICSTAT);
 605         tmp &= ~S3C2410_IICSTAT_TXRXEN;
 606         writel(tmp, i2c->regs + S3C2410_IICSTAT);
 607 
 608         /* We don't expect any interrupts now, and don't want send acks */
 609         tmp = readl(i2c->regs + S3C2410_IICCON);
 610         tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
 611                 S3C2410_IICCON_ACKEN);
 612         writel(tmp, i2c->regs + S3C2410_IICCON);
 613 }
 614 
 615 
 616 /*
 617  * get the i2c bus for a master transaction
 618  */
 619 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 620 {
 621         unsigned long iicstat;
 622         int timeout = 400;
 623 
 624         while (timeout-- > 0) {
 625                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 626 
 627                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
 628                         return 0;
 629 
 630                 msleep(1);
 631         }
 632 
 633         return -ETIMEDOUT;
 634 }
 635 
 636 /*
 637  * wait for the i2c bus to become idle.
 638  */
 639 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
 640 {
 641         unsigned long iicstat;
 642         ktime_t start, now;
 643         unsigned long delay;
 644         int spins;
 645 
 646         /* ensure the stop has been through the bus */
 647 
 648         dev_dbg(i2c->dev, "waiting for bus idle\n");
 649 
 650         start = now = ktime_get();
 651 
 652         /*
 653          * Most of the time, the bus is already idle within a few usec of the
 654          * end of a transaction.  However, really slow i2c devices can stretch
 655          * the clock, delaying STOP generation.
 656          *
 657          * On slower SoCs this typically happens within a very small number of
 658          * instructions so busy wait briefly to avoid scheduling overhead.
 659          */
 660         spins = 3;
 661         iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 662         while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
 663                 cpu_relax();
 664                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 665         }
 666 
 667         /*
 668          * If we do get an appreciable delay as a compromise between idle
 669          * detection latency for the normal, fast case, and system load in the
 670          * slow device case, use an exponential back off in the polling loop,
 671          * up to 1/10th of the total timeout, then continue to poll at a
 672          * constant rate up to the timeout.
 673          */
 674         delay = 1;
 675         while ((iicstat & S3C2410_IICSTAT_START) &&
 676                ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
 677                 usleep_range(delay, 2 * delay);
 678                 if (delay < S3C2410_IDLE_TIMEOUT / 10)
 679                         delay <<= 1;
 680                 now = ktime_get();
 681                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 682         }
 683 
 684         if (iicstat & S3C2410_IICSTAT_START)
 685                 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
 686 }
 687 
 688 /*
 689  * this starts an i2c transfer
 690  */
 691 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 692                               struct i2c_msg *msgs, int num)
 693 {
 694         unsigned long timeout;
 695         int ret;
 696 
 697         ret = s3c24xx_i2c_set_master(i2c);
 698         if (ret != 0) {
 699                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
 700                 ret = -EAGAIN;
 701                 goto out;
 702         }
 703 
 704         i2c->msg     = msgs;
 705         i2c->msg_num = num;
 706         i2c->msg_ptr = 0;
 707         i2c->msg_idx = 0;
 708         i2c->state   = STATE_START;
 709 
 710         s3c24xx_i2c_enable_irq(i2c);
 711         s3c24xx_i2c_message_start(i2c, msgs);
 712 
 713         if (i2c->quirks & QUIRK_POLL) {
 714                 ret = i2c->msg_idx;
 715 
 716                 if (ret != num)
 717                         dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 718 
 719                 goto out;
 720         }
 721 
 722         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 723 
 724         ret = i2c->msg_idx;
 725 
 726         /*
 727          * Having these next two as dev_err() makes life very
 728          * noisy when doing an i2cdetect
 729          */
 730         if (timeout == 0)
 731                 dev_dbg(i2c->dev, "timeout\n");
 732         else if (ret != num)
 733                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 734 
 735         /* For QUIRK_HDMIPHY, bus is already disabled */
 736         if (i2c->quirks & QUIRK_HDMIPHY)
 737                 goto out;
 738 
 739         s3c24xx_i2c_wait_idle(i2c);
 740 
 741         s3c24xx_i2c_disable_bus(i2c);
 742 
 743  out:
 744         i2c->state = STATE_IDLE;
 745 
 746         return ret;
 747 }
 748 
 749 /*
 750  * first port of call from the i2c bus code when an message needs
 751  * transferring across the i2c bus.
 752  */
 753 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
 754                         struct i2c_msg *msgs, int num)
 755 {
 756         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
 757         int retry;
 758         int ret;
 759 
 760         ret = clk_enable(i2c->clk);
 761         if (ret)
 762                 return ret;
 763 
 764         for (retry = 0; retry < adap->retries; retry++) {
 765 
 766                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 767 
 768                 if (ret != -EAGAIN) {
 769                         clk_disable(i2c->clk);
 770                         return ret;
 771                 }
 772 
 773                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
 774 
 775                 udelay(100);
 776         }
 777 
 778         clk_disable(i2c->clk);
 779         return -EREMOTEIO;
 780 }
 781 
 782 /* declare our i2c functionality */
 783 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
 784 {
 785         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
 786                 I2C_FUNC_PROTOCOL_MANGLING;
 787 }
 788 
 789 /* i2c bus registration info */
 790 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
 791         .master_xfer            = s3c24xx_i2c_xfer,
 792         .functionality          = s3c24xx_i2c_func,
 793 };
 794 
 795 /*
 796  * return the divisor settings for a given frequency
 797  */
 798 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
 799                                    unsigned int *div1, unsigned int *divs)
 800 {
 801         unsigned int calc_divs = clkin / wanted;
 802         unsigned int calc_div1;
 803 
 804         if (calc_divs > (16*16))
 805                 calc_div1 = 512;
 806         else
 807                 calc_div1 = 16;
 808 
 809         calc_divs += calc_div1-1;
 810         calc_divs /= calc_div1;
 811 
 812         if (calc_divs == 0)
 813                 calc_divs = 1;
 814         if (calc_divs > 17)
 815                 calc_divs = 17;
 816 
 817         *divs = calc_divs;
 818         *div1 = calc_div1;
 819 
 820         return clkin / (calc_divs * calc_div1);
 821 }
 822 
 823 /*
 824  * work out a divisor for the user requested frequency setting,
 825  * either by the requested frequency, or scanning the acceptable
 826  * range of frequencies until something is found
 827  */
 828 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 829 {
 830         struct s3c2410_platform_i2c *pdata = i2c->pdata;
 831         unsigned long clkin = clk_get_rate(i2c->clk);
 832         unsigned int divs, div1;
 833         unsigned long target_frequency;
 834         u32 iiccon;
 835         int freq;
 836 
 837         i2c->clkrate = clkin;
 838         clkin /= 1000;          /* clkin now in KHz */
 839 
 840         dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
 841 
 842         target_frequency = pdata->frequency ? pdata->frequency : 100000;
 843 
 844         target_frequency /= 1000; /* Target frequency now in KHz */
 845 
 846         freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
 847 
 848         if (freq > target_frequency) {
 849                 dev_err(i2c->dev,
 850                         "Unable to achieve desired frequency %luKHz."   \
 851                         " Lowest achievable %dKHz\n", target_frequency, freq);
 852                 return -EINVAL;
 853         }
 854 
 855         *got = freq;
 856 
 857         iiccon = readl(i2c->regs + S3C2410_IICCON);
 858         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
 859         iiccon |= (divs-1);
 860 
 861         if (div1 == 512)
 862                 iiccon |= S3C2410_IICCON_TXDIV_512;
 863 
 864         if (i2c->quirks & QUIRK_POLL)
 865                 iiccon |= S3C2410_IICCON_SCALE(2);
 866 
 867         writel(iiccon, i2c->regs + S3C2410_IICCON);
 868 
 869         if (i2c->quirks & QUIRK_S3C2440) {
 870                 unsigned long sda_delay;
 871 
 872                 if (pdata->sda_delay) {
 873                         sda_delay = clkin * pdata->sda_delay;
 874                         sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
 875                         sda_delay = DIV_ROUND_UP(sda_delay, 5);
 876                         if (sda_delay > 3)
 877                                 sda_delay = 3;
 878                         sda_delay |= S3C2410_IICLC_FILTER_ON;
 879                 } else
 880                         sda_delay = 0;
 881 
 882                 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
 883                 writel(sda_delay, i2c->regs + S3C2440_IICLC);
 884         }
 885 
 886         return 0;
 887 }
 888 
 889 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
 890 
 891 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
 892 
 893 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
 894                                           unsigned long val, void *data)
 895 {
 896         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
 897         unsigned int got;
 898         int delta_f;
 899         int ret;
 900 
 901         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
 902 
 903         /* if we're post-change and the input clock has slowed down
 904          * or at pre-change and the clock is about to speed up, then
 905          * adjust our clock rate. <0 is slow, >0 speedup.
 906          */
 907 
 908         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
 909             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
 910                 i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
 911                 ret = s3c24xx_i2c_clockrate(i2c, &got);
 912                 i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
 913 
 914                 if (ret < 0)
 915                         dev_err(i2c->dev, "cannot find frequency (%d)\n", ret);
 916                 else
 917                         dev_info(i2c->dev, "setting freq %d\n", got);
 918         }
 919 
 920         return 0;
 921 }
 922 
 923 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 924 {
 925         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
 926 
 927         return cpufreq_register_notifier(&i2c->freq_transition,
 928                                          CPUFREQ_TRANSITION_NOTIFIER);
 929 }
 930 
 931 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 932 {
 933         cpufreq_unregister_notifier(&i2c->freq_transition,
 934                                     CPUFREQ_TRANSITION_NOTIFIER);
 935 }
 936 
 937 #else
 938 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 939 {
 940         return 0;
 941 }
 942 
 943 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 944 {
 945 }
 946 #endif
 947 
 948 #ifdef CONFIG_OF
 949 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 950 {
 951         int i;
 952 
 953         if (i2c->quirks & QUIRK_NO_GPIO)
 954                 return 0;
 955 
 956         for (i = 0; i < 2; i++) {
 957                 i2c->gpios[i] = devm_gpiod_get_index(i2c->dev, NULL,
 958                                                      i, GPIOD_ASIS);
 959                 if (IS_ERR(i2c->gpios[i])) {
 960                         dev_err(i2c->dev, "i2c gpio invalid at index %d\n", i);
 961                         return -EINVAL;
 962                 }
 963         }
 964         return 0;
 965 }
 966 
 967 #else
 968 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 969 {
 970         return 0;
 971 }
 972 #endif
 973 
 974 /*
 975  * initialise the controller, set the IO lines and frequency
 976  */
 977 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
 978 {
 979         struct s3c2410_platform_i2c *pdata;
 980         unsigned int freq;
 981 
 982         /* get the plafrom data */
 983 
 984         pdata = i2c->pdata;
 985 
 986         /* write slave address */
 987 
 988         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
 989 
 990         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
 991 
 992         writel(0, i2c->regs + S3C2410_IICCON);
 993         writel(0, i2c->regs + S3C2410_IICSTAT);
 994 
 995         /* we need to work out the divisors for the clock... */
 996 
 997         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
 998                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
 999                 return -EINVAL;
1000         }
1001 
1002         /* todo - check that the i2c lines aren't being dragged anywhere */
1003 
1004         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
1005         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
1006                 readl(i2c->regs + S3C2410_IICCON));
1007 
1008         return 0;
1009 }
1010 
1011 #ifdef CONFIG_OF
1012 /*
1013  * Parse the device tree node and retreive the platform data.
1014  */
1015 static void
1016 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1017 {
1018         struct s3c2410_platform_i2c *pdata = i2c->pdata;
1019         int id;
1020 
1021         if (!np)
1022                 return;
1023 
1024         pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
1025         of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1026         of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1027         of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1028                                 (u32 *)&pdata->frequency);
1029         /*
1030          * Exynos5's legacy i2c controller and new high speed i2c
1031          * controller have muxed interrupt sources. By default the
1032          * interrupts for 4-channel HS-I2C controller are enabled.
1033          * If nodes for first four channels of legacy i2c controller
1034          * are available then re-configure the interrupts via the
1035          * system register.
1036          */
1037         id = of_alias_get_id(np, "i2c");
1038         i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
1039                         "samsung,sysreg-phandle");
1040         if (IS_ERR(i2c->sysreg))
1041                 return;
1042 
1043         regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
1044 }
1045 #else
1046 static void
1047 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
1048 #endif
1049 
1050 static int s3c24xx_i2c_probe(struct platform_device *pdev)
1051 {
1052         struct s3c24xx_i2c *i2c;
1053         struct s3c2410_platform_i2c *pdata = NULL;
1054         struct resource *res;
1055         int ret;
1056 
1057         if (!pdev->dev.of_node) {
1058                 pdata = dev_get_platdata(&pdev->dev);
1059                 if (!pdata) {
1060                         dev_err(&pdev->dev, "no platform data\n");
1061                         return -EINVAL;
1062                 }
1063         }
1064 
1065         i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1066         if (!i2c)
1067                 return -ENOMEM;
1068 
1069         i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1070         if (!i2c->pdata)
1071                 return -ENOMEM;
1072 
1073         i2c->quirks = s3c24xx_get_device_quirks(pdev);
1074         i2c->sysreg = ERR_PTR(-ENOENT);
1075         if (pdata)
1076                 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1077         else
1078                 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1079 
1080         strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1081         i2c->adap.owner = THIS_MODULE;
1082         i2c->adap.algo = &s3c24xx_i2c_algorithm;
1083         i2c->adap.retries = 2;
1084         i2c->adap.class = I2C_CLASS_DEPRECATED;
1085         i2c->tx_setup = 50;
1086 
1087         init_waitqueue_head(&i2c->wait);
1088 
1089         /* find the clock and enable it */
1090         i2c->dev = &pdev->dev;
1091         i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1092         if (IS_ERR(i2c->clk)) {
1093                 dev_err(&pdev->dev, "cannot get clock\n");
1094                 return -ENOENT;
1095         }
1096 
1097         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1098 
1099         /* map the registers */
1100         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1101         i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1102 
1103         if (IS_ERR(i2c->regs))
1104                 return PTR_ERR(i2c->regs);
1105 
1106         dev_dbg(&pdev->dev, "registers %p (%p)\n",
1107                 i2c->regs, res);
1108 
1109         /* setup info block for the i2c core */
1110         i2c->adap.algo_data = i2c;
1111         i2c->adap.dev.parent = &pdev->dev;
1112         i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1113 
1114         /* inititalise the i2c gpio lines */
1115         if (i2c->pdata->cfg_gpio)
1116                 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1117         else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
1118                 return -EINVAL;
1119 
1120         /* initialise the i2c controller */
1121         ret = clk_prepare_enable(i2c->clk);
1122         if (ret) {
1123                 dev_err(&pdev->dev, "I2C clock enable failed\n");
1124                 return ret;
1125         }
1126 
1127         ret = s3c24xx_i2c_init(i2c);
1128         clk_disable(i2c->clk);
1129         if (ret != 0) {
1130                 dev_err(&pdev->dev, "I2C controller init failed\n");
1131                 clk_unprepare(i2c->clk);
1132                 return ret;
1133         }
1134 
1135         /*
1136          * find the IRQ for this unit (note, this relies on the init call to
1137          * ensure no current IRQs pending
1138          */
1139         if (!(i2c->quirks & QUIRK_POLL)) {
1140                 i2c->irq = ret = platform_get_irq(pdev, 0);
1141                 if (ret <= 0) {
1142                         dev_err(&pdev->dev, "cannot find IRQ\n");
1143                         clk_unprepare(i2c->clk);
1144                         return ret;
1145                 }
1146 
1147                 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
1148                                        0, dev_name(&pdev->dev), i2c);
1149                 if (ret != 0) {
1150                         dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1151                         clk_unprepare(i2c->clk);
1152                         return ret;
1153                 }
1154         }
1155 
1156         ret = s3c24xx_i2c_register_cpufreq(i2c);
1157         if (ret < 0) {
1158                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1159                 clk_unprepare(i2c->clk);
1160                 return ret;
1161         }
1162 
1163         /*
1164          * Note, previous versions of the driver used i2c_add_adapter()
1165          * to add the bus at any number. We now pass the bus number via
1166          * the platform data, so if unset it will now default to always
1167          * being bus 0.
1168          */
1169         i2c->adap.nr = i2c->pdata->bus_num;
1170         i2c->adap.dev.of_node = pdev->dev.of_node;
1171 
1172         platform_set_drvdata(pdev, i2c);
1173 
1174         pm_runtime_enable(&pdev->dev);
1175 
1176         ret = i2c_add_numbered_adapter(&i2c->adap);
1177         if (ret < 0) {
1178                 pm_runtime_disable(&pdev->dev);
1179                 s3c24xx_i2c_deregister_cpufreq(i2c);
1180                 clk_unprepare(i2c->clk);
1181                 return ret;
1182         }
1183 
1184         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1185         return 0;
1186 }
1187 
1188 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1189 {
1190         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1191 
1192         clk_unprepare(i2c->clk);
1193 
1194         pm_runtime_disable(&pdev->dev);
1195 
1196         s3c24xx_i2c_deregister_cpufreq(i2c);
1197 
1198         i2c_del_adapter(&i2c->adap);
1199 
1200         return 0;
1201 }
1202 
1203 #ifdef CONFIG_PM_SLEEP
1204 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1205 {
1206         struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1207 
1208         i2c_mark_adapter_suspended(&i2c->adap);
1209 
1210         if (!IS_ERR(i2c->sysreg))
1211                 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1212 
1213         return 0;
1214 }
1215 
1216 static int s3c24xx_i2c_resume_noirq(struct device *dev)
1217 {
1218         struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1219         int ret;
1220 
1221         if (!IS_ERR(i2c->sysreg))
1222                 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1223 
1224         ret = clk_enable(i2c->clk);
1225         if (ret)
1226                 return ret;
1227         s3c24xx_i2c_init(i2c);
1228         clk_disable(i2c->clk);
1229         i2c_mark_adapter_resumed(&i2c->adap);
1230 
1231         return 0;
1232 }
1233 #endif
1234 
1235 #ifdef CONFIG_PM
1236 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1237         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,
1238                                       s3c24xx_i2c_resume_noirq)
1239 };
1240 
1241 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1242 #else
1243 #define S3C24XX_DEV_PM_OPS NULL
1244 #endif
1245 
1246 static struct platform_driver s3c24xx_i2c_driver = {
1247         .probe          = s3c24xx_i2c_probe,
1248         .remove         = s3c24xx_i2c_remove,
1249         .id_table       = s3c24xx_driver_ids,
1250         .driver         = {
1251                 .name   = "s3c-i2c",
1252                 .pm     = S3C24XX_DEV_PM_OPS,
1253                 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1254         },
1255 };
1256 
1257 static int __init i2c_adap_s3c_init(void)
1258 {
1259         return platform_driver_register(&s3c24xx_i2c_driver);
1260 }
1261 subsys_initcall(i2c_adap_s3c_init);
1262 
1263 static void __exit i2c_adap_s3c_exit(void)
1264 {
1265         platform_driver_unregister(&s3c24xx_i2c_driver);
1266 }
1267 module_exit(i2c_adap_s3c_exit);
1268 
1269 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1270 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1271 MODULE_LICENSE("GPL");
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root/drivers/i2c/busses/i2c-s3c2410.c

DEFINITIONS
