1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* ------------------------------------------------------------------------- */
3 /* i2c-iop3xx.h algorithm driver definitions private to i2c-iop3xx.c */
4 /* ------------------------------------------------------------------------- */
5 /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
6 * <Peter dot Milne at D hyphen TACQ dot com>
7
8 */
9 /* ------------------------------------------------------------------------- */
10
11
12 #ifndef I2C_IOP3XX_H
13 #define I2C_IOP3XX_H 1
14
15 /*
16 * iop321 hardware bit definitions
17 */
18 #define IOP3XX_ICR_FAST_MODE 0x8000 /* 1=400kBps, 0=100kBps */
19 #define IOP3XX_ICR_UNIT_RESET 0x4000 /* 1=RESET */
20 #define IOP3XX_ICR_SAD_IE 0x2000 /* 1=Slave Detect Interrupt Enable */
21 #define IOP3XX_ICR_ALD_IE 0x1000 /* 1=Arb Loss Detect Interrupt Enable */
22 #define IOP3XX_ICR_SSD_IE 0x0800 /* 1=Slave STOP Detect Interrupt Enable */
23 #define IOP3XX_ICR_BERR_IE 0x0400 /* 1=Bus Error Interrupt Enable */
24 #define IOP3XX_ICR_RXFULL_IE 0x0200 /* 1=Receive Full Interrupt Enable */
25 #define IOP3XX_ICR_TXEMPTY_IE 0x0100 /* 1=Transmit Empty Interrupt Enable */
26 #define IOP3XX_ICR_GCD 0x0080 /* 1=General Call Disable */
27 /*
28 * IOP3XX_ICR_GCD: 1 disables response as slave. "This bit must be set
29 * when sending a master mode general call message from the I2C unit"
30 */
31 #define IOP3XX_ICR_UE 0x0040 /* 1=Unit Enable */
32 /*
33 * "NOTE: To avoid I2C bus integrity problems,
34 * the user needs to ensure that the GPIO Output Data Register -
35 * GPOD bits associated with an I2C port are cleared prior to setting
36 * the enable bit for that I2C serial port.
37 * The user prepares to enable I2C port 0 and
38 * I2C port 1 by clearing GPOD bits 7:6 and GPOD bits 5:4, respectively.
39 */
40 #define IOP3XX_ICR_SCLEN 0x0020 /* 1=SCL enable for master mode */
41 #define IOP3XX_ICR_MABORT 0x0010 /* 1=Send a STOP with no data
42 * NB TBYTE must be clear */
43 #define IOP3XX_ICR_TBYTE 0x0008 /* 1=Send/Receive a byte. i2c clears */
44 #define IOP3XX_ICR_NACK 0x0004 /* 1=reply with NACK */
45 #define IOP3XX_ICR_MSTOP 0x0002 /* 1=send a STOP after next data byte */
46 #define IOP3XX_ICR_MSTART 0x0001 /* 1=initiate a START */
47
48
49 #define IOP3XX_ISR_BERRD 0x0400 /* 1=BUS ERROR Detected */
50 #define IOP3XX_ISR_SAD 0x0200 /* 1=Slave ADdress Detected */
51 #define IOP3XX_ISR_GCAD 0x0100 /* 1=General Call Address Detected */
52 #define IOP3XX_ISR_RXFULL 0x0080 /* 1=Receive Full */
53 #define IOP3XX_ISR_TXEMPTY 0x0040 /* 1=Transmit Empty */
54 #define IOP3XX_ISR_ALD 0x0020 /* 1=Arbitration Loss Detected */
55 #define IOP3XX_ISR_SSD 0x0010 /* 1=Slave STOP Detected */
56 #define IOP3XX_ISR_BBUSY 0x0008 /* 1=Bus BUSY */
57 #define IOP3XX_ISR_UNITBUSY 0x0004 /* 1=Unit Busy */
58 #define IOP3XX_ISR_NACK 0x0002 /* 1=Unit Rx or Tx a NACK */
59 #define IOP3XX_ISR_RXREAD 0x0001 /* 1=READ 0=WRITE (R/W bit of slave addr */
60
61 #define IOP3XX_ISR_CLEARBITS 0x07f0
62
63 #define IOP3XX_ISAR_SAMASK 0x007f
64
65 #define IOP3XX_IDBR_MASK 0x00ff
66
67 #define IOP3XX_IBMR_SCL 0x0002
68 #define IOP3XX_IBMR_SDA 0x0001
69
70 #define IOP3XX_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */
71 #define IOP3XX_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */
72
73 #define MYSAR 0 /* default slave address */
74
75 #define I2C_ERR 321
76 #define I2C_ERR_BERR (I2C_ERR+0)
77 #define I2C_ERR_ALD (I2C_ERR+1)
78
79
80 #define CR_OFFSET 0
81 #define SR_OFFSET 0x4
82 #define SAR_OFFSET 0x8
83 #define DBR_OFFSET 0xc
84 #define CCR_OFFSET 0x10
85 #define BMR_OFFSET 0x14
86
87 #define IOP3XX_I2C_IO_SIZE 0x18
88
89 struct i2c_algo_iop3xx_data {
90 void __iomem *ioaddr;
91 wait_queue_head_t waitq;
92 spinlock_t lock;
93 u32 SR_enabled, SR_received;
94 int id;
95 struct gpio_desc *gpio_scl;
96 struct gpio_desc *gpio_sda;
97 };
98
99 #endif /* I2C_IOP3XX_H */