This source file includes following definitions.
- jz4780_i2c_readw
- jz4780_i2c_writew
- jz4780_i2c_disable
- jz4780_i2c_enable
- jz4780_i2c_set_target
- jz4780_i2c_set_speed
- jz4780_i2c_cleanup
- jz4780_i2c_prepare
- jz4780_i2c_send_rcmd
- jz4780_i2c_trans_done
- jz4780_i2c_irq
- jz4780_i2c_txabrt
- jz4780_i2c_xfer_read
- jz4780_i2c_xfer_write
- jz4780_i2c_xfer
- jz4780_i2c_functionality
- jz4780_i2c_probe
- jz4780_i2c_remove
1
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3
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7
8
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/completion.h>
12 #include <linux/delay.h>
13 #include <linux/errno.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/sched.h>
22 #include <linux/slab.h>
23 #include <linux/time.h>
24
25 #define JZ4780_I2C_CTRL 0x00
26 #define JZ4780_I2C_TAR 0x04
27 #define JZ4780_I2C_SAR 0x08
28 #define JZ4780_I2C_DC 0x10
29 #define JZ4780_I2C_SHCNT 0x14
30 #define JZ4780_I2C_SLCNT 0x18
31 #define JZ4780_I2C_FHCNT 0x1C
32 #define JZ4780_I2C_FLCNT 0x20
33 #define JZ4780_I2C_INTST 0x2C
34 #define JZ4780_I2C_INTM 0x30
35 #define JZ4780_I2C_RXTL 0x38
36 #define JZ4780_I2C_TXTL 0x3C
37 #define JZ4780_I2C_CINTR 0x40
38 #define JZ4780_I2C_CRXUF 0x44
39 #define JZ4780_I2C_CRXOF 0x48
40 #define JZ4780_I2C_CTXOF 0x4C
41 #define JZ4780_I2C_CRXREQ 0x50
42 #define JZ4780_I2C_CTXABRT 0x54
43 #define JZ4780_I2C_CRXDONE 0x58
44 #define JZ4780_I2C_CACT 0x5C
45 #define JZ4780_I2C_CSTP 0x60
46 #define JZ4780_I2C_CSTT 0x64
47 #define JZ4780_I2C_CGC 0x68
48 #define JZ4780_I2C_ENB 0x6C
49 #define JZ4780_I2C_STA 0x70
50 #define JZ4780_I2C_TXABRT 0x80
51 #define JZ4780_I2C_DMACR 0x88
52 #define JZ4780_I2C_DMATDLR 0x8C
53 #define JZ4780_I2C_DMARDLR 0x90
54 #define JZ4780_I2C_SDASU 0x94
55 #define JZ4780_I2C_ACKGC 0x98
56 #define JZ4780_I2C_ENSTA 0x9C
57 #define JZ4780_I2C_SDAHD 0xD0
58
59 #define JZ4780_I2C_CTRL_STPHLD BIT(7)
60 #define JZ4780_I2C_CTRL_SLVDIS BIT(6)
61 #define JZ4780_I2C_CTRL_REST BIT(5)
62 #define JZ4780_I2C_CTRL_MATP BIT(4)
63 #define JZ4780_I2C_CTRL_SATP BIT(3)
64 #define JZ4780_I2C_CTRL_SPDF BIT(2)
65 #define JZ4780_I2C_CTRL_SPDS BIT(1)
66 #define JZ4780_I2C_CTRL_MD BIT(0)
67
68 #define JZ4780_I2C_STA_SLVACT BIT(6)
69 #define JZ4780_I2C_STA_MSTACT BIT(5)
70 #define JZ4780_I2C_STA_RFF BIT(4)
71 #define JZ4780_I2C_STA_RFNE BIT(3)
72 #define JZ4780_I2C_STA_TFE BIT(2)
73 #define JZ4780_I2C_STA_TFNF BIT(1)
74 #define JZ4780_I2C_STA_ACT BIT(0)
75
76 #define JZ4780_I2C_INTST_IGC BIT(11)
77 #define JZ4780_I2C_INTST_ISTT BIT(10)
78 #define JZ4780_I2C_INTST_ISTP BIT(9)
79 #define JZ4780_I2C_INTST_IACT BIT(8)
80 #define JZ4780_I2C_INTST_RXDN BIT(7)
81 #define JZ4780_I2C_INTST_TXABT BIT(6)
82 #define JZ4780_I2C_INTST_RDREQ BIT(5)
83 #define JZ4780_I2C_INTST_TXEMP BIT(4)
84 #define JZ4780_I2C_INTST_TXOF BIT(3)
85 #define JZ4780_I2C_INTST_RXFL BIT(2)
86 #define JZ4780_I2C_INTST_RXOF BIT(1)
87 #define JZ4780_I2C_INTST_RXUF BIT(0)
88
89 #define JZ4780_I2C_INTM_MIGC BIT(11)
90 #define JZ4780_I2C_INTM_MISTT BIT(10)
91 #define JZ4780_I2C_INTM_MISTP BIT(9)
92 #define JZ4780_I2C_INTM_MIACT BIT(8)
93 #define JZ4780_I2C_INTM_MRXDN BIT(7)
94 #define JZ4780_I2C_INTM_MTXABT BIT(6)
95 #define JZ4780_I2C_INTM_MRDREQ BIT(5)
96 #define JZ4780_I2C_INTM_MTXEMP BIT(4)
97 #define JZ4780_I2C_INTM_MTXOF BIT(3)
98 #define JZ4780_I2C_INTM_MRXFL BIT(2)
99 #define JZ4780_I2C_INTM_MRXOF BIT(1)
100 #define JZ4780_I2C_INTM_MRXUF BIT(0)
101
102 #define JZ4780_I2C_DC_READ BIT(8)
103
104 #define JZ4780_I2C_SDAHD_HDENB BIT(8)
105
106 #define JZ4780_I2C_ENB_I2C BIT(0)
107
108 #define JZ4780_I2CSHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
109 #define JZ4780_I2CSLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
110 #define JZ4780_I2CFHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
111 #define JZ4780_I2CFLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
112
113 #define JZ4780_I2C_FIFO_LEN 16
114 #define TX_LEVEL 3
115 #define RX_LEVEL (JZ4780_I2C_FIFO_LEN - TX_LEVEL - 1)
116
117 #define JZ4780_I2C_TIMEOUT 300
118
119 #define BUFSIZE 200
120
121 struct jz4780_i2c {
122 void __iomem *iomem;
123 int irq;
124 struct clk *clk;
125 struct i2c_adapter adap;
126
127
128 spinlock_t lock;
129
130
131 unsigned char *rbuf;
132 int rd_total_len;
133 int rd_data_xfered;
134 int rd_cmd_xfered;
135
136 unsigned char *wbuf;
137 int wt_len;
138
139 int is_write;
140 int stop_hold;
141 int speed;
142
143 int data_buf[BUFSIZE];
144 int cmd_buf[BUFSIZE];
145 int cmd;
146
147
148 struct completion trans_waitq;
149 };
150
151 static inline unsigned short jz4780_i2c_readw(struct jz4780_i2c *i2c,
152 unsigned long offset)
153 {
154 return readw(i2c->iomem + offset);
155 }
156
157 static inline void jz4780_i2c_writew(struct jz4780_i2c *i2c,
158 unsigned long offset, unsigned short val)
159 {
160 writew(val, i2c->iomem + offset);
161 }
162
163 static int jz4780_i2c_disable(struct jz4780_i2c *i2c)
164 {
165 unsigned short regval;
166 unsigned long loops = 5;
167
168 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 0);
169
170 do {
171 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
172 if (!(regval & JZ4780_I2C_ENB_I2C))
173 return 0;
174
175 usleep_range(5000, 15000);
176 } while (--loops);
177
178 dev_err(&i2c->adap.dev, "disable failed: ENSTA=0x%04x\n", regval);
179 return -ETIMEDOUT;
180 }
181
182 static int jz4780_i2c_enable(struct jz4780_i2c *i2c)
183 {
184 unsigned short regval;
185 unsigned long loops = 5;
186
187 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 1);
188
189 do {
190 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
191 if (regval & JZ4780_I2C_ENB_I2C)
192 return 0;
193
194 usleep_range(5000, 15000);
195 } while (--loops);
196
197 dev_err(&i2c->adap.dev, "enable failed: ENSTA=0x%04x\n", regval);
198 return -ETIMEDOUT;
199 }
200
201 static int jz4780_i2c_set_target(struct jz4780_i2c *i2c, unsigned char address)
202 {
203 unsigned short regval;
204 unsigned long loops = 5;
205
206 do {
207 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
208 if ((regval & JZ4780_I2C_STA_TFE) &&
209 !(regval & JZ4780_I2C_STA_MSTACT))
210 break;
211
212 usleep_range(5000, 15000);
213 } while (--loops);
214
215 if (loops) {
216 jz4780_i2c_writew(i2c, JZ4780_I2C_TAR, address);
217 return 0;
218 }
219
220 dev_err(&i2c->adap.dev,
221 "set device to address 0x%02x failed, STA=0x%04x\n",
222 address, regval);
223
224 return -ENXIO;
225 }
226
227 static int jz4780_i2c_set_speed(struct jz4780_i2c *i2c)
228 {
229 int dev_clk_khz = clk_get_rate(i2c->clk) / 1000;
230 int cnt_high = 0;
231 int cnt_low = 0;
232 int cnt_period = 0;
233 int setup_time = 0;
234 int hold_time = 0;
235 unsigned short tmp = 0;
236 int i2c_clk = i2c->speed;
237
238 if (jz4780_i2c_disable(i2c))
239 dev_dbg(&i2c->adap.dev, "i2c not disabled\n");
240
241
242
243
244
245
246 cnt_period = dev_clk_khz / i2c_clk;
247
248 if (i2c_clk <= 100)
249 cnt_high = (cnt_period * 4000) / (4700 + 4000);
250 else
251 cnt_high = (cnt_period * 600) / (1300 + 600);
252
253 cnt_low = cnt_period - cnt_high;
254
255
256
257
258
259
260
261
262 if (i2c_clk <= 100) {
263 tmp = JZ4780_I2C_CTRL_SPDS | JZ4780_I2C_CTRL_REST
264 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
265 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
266
267 jz4780_i2c_writew(i2c, JZ4780_I2C_SHCNT,
268 JZ4780_I2CSHCNT_ADJUST(cnt_high));
269 jz4780_i2c_writew(i2c, JZ4780_I2C_SLCNT,
270 JZ4780_I2CSLCNT_ADJUST(cnt_low));
271 } else {
272 tmp = JZ4780_I2C_CTRL_SPDF | JZ4780_I2C_CTRL_REST
273 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
274 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
275
276 jz4780_i2c_writew(i2c, JZ4780_I2C_FHCNT,
277 JZ4780_I2CFHCNT_ADJUST(cnt_high));
278 jz4780_i2c_writew(i2c, JZ4780_I2C_FLCNT,
279 JZ4780_I2CFLCNT_ADJUST(cnt_low));
280 }
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300 if (i2c_clk <= 100) {
301 setup_time = 300;
302 hold_time = 400;
303 } else {
304 setup_time = 450;
305 hold_time = 450;
306 }
307
308 hold_time = ((hold_time * dev_clk_khz) / 1000000) - 1;
309 setup_time = ((setup_time * dev_clk_khz) / 1000000) + 1;
310
311 if (setup_time > 255)
312 setup_time = 255;
313
314 if (setup_time <= 0)
315 setup_time = 1;
316
317 jz4780_i2c_writew(i2c, JZ4780_I2C_SDASU, setup_time);
318
319 if (hold_time > 255)
320 hold_time = 255;
321
322 if (hold_time >= 0) {
323
324 hold_time |= JZ4780_I2C_SDAHD_HDENB;
325 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, hold_time);
326 } else {
327
328 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, 0);
329 }
330
331 return 0;
332 }
333
334 static int jz4780_i2c_cleanup(struct jz4780_i2c *i2c)
335 {
336 int ret;
337 unsigned long flags;
338 unsigned short tmp;
339
340 spin_lock_irqsave(&i2c->lock, flags);
341
342
343 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
344 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
345 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
346
347
348 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
349
350
351 jz4780_i2c_readw(i2c, JZ4780_I2C_CTXABRT);
352 jz4780_i2c_readw(i2c, JZ4780_I2C_CINTR);
353
354
355 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
356 tmp &= ~JZ4780_I2C_ENB_I2C;
357 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
358 udelay(10);
359 tmp |= JZ4780_I2C_ENB_I2C;
360 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
361
362 spin_unlock_irqrestore(&i2c->lock, flags);
363
364 ret = jz4780_i2c_disable(i2c);
365 if (ret)
366 dev_err(&i2c->adap.dev,
367 "unable to disable device during cleanup!\n");
368
369 if (unlikely(jz4780_i2c_readw(i2c, JZ4780_I2C_INTM)
370 & jz4780_i2c_readw(i2c, JZ4780_I2C_INTST)))
371 dev_err(&i2c->adap.dev,
372 "device has interrupts after a complete cleanup!\n");
373
374 return ret;
375 }
376
377 static int jz4780_i2c_prepare(struct jz4780_i2c *i2c)
378 {
379 jz4780_i2c_set_speed(i2c);
380 return jz4780_i2c_enable(i2c);
381 }
382
383 static void jz4780_i2c_send_rcmd(struct jz4780_i2c *i2c, int cmd_count)
384 {
385 int i;
386
387 for (i = 0; i < cmd_count; i++)
388 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ);
389 }
390
391 static void jz4780_i2c_trans_done(struct jz4780_i2c *i2c)
392 {
393 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
394 complete(&i2c->trans_waitq);
395 }
396
397 static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id)
398 {
399 unsigned short tmp;
400 unsigned short intst;
401 unsigned short intmsk;
402 struct jz4780_i2c *i2c = dev_id;
403 unsigned long flags;
404
405 spin_lock_irqsave(&i2c->lock, flags);
406 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
407 intst = jz4780_i2c_readw(i2c, JZ4780_I2C_INTST);
408
409 intst &= intmsk;
410
411 if (intst & JZ4780_I2C_INTST_TXABT) {
412 jz4780_i2c_trans_done(i2c);
413 goto done;
414 }
415
416 if (intst & JZ4780_I2C_INTST_RXOF) {
417 dev_dbg(&i2c->adap.dev, "received fifo overflow!\n");
418 jz4780_i2c_trans_done(i2c);
419 goto done;
420 }
421
422
423
424
425
426 if (i2c->is_write == 0) {
427 int rd_left;
428
429 while ((jz4780_i2c_readw(i2c, JZ4780_I2C_STA)
430 & JZ4780_I2C_STA_RFNE)) {
431 *(i2c->rbuf++) = jz4780_i2c_readw(i2c, JZ4780_I2C_DC)
432 & 0xff;
433 i2c->rd_data_xfered++;
434 if (i2c->rd_data_xfered == i2c->rd_total_len) {
435 jz4780_i2c_trans_done(i2c);
436 goto done;
437 }
438 }
439
440 rd_left = i2c->rd_total_len - i2c->rd_data_xfered;
441
442 if (rd_left <= JZ4780_I2C_FIFO_LEN)
443 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, rd_left - 1);
444 }
445
446 if (intst & JZ4780_I2C_INTST_TXEMP) {
447 if (i2c->is_write == 0) {
448 int cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered;
449 int max_send = (JZ4780_I2C_FIFO_LEN - 1)
450 - (i2c->rd_cmd_xfered
451 - i2c->rd_data_xfered);
452 int cmd_to_send = min(cmd_left, max_send);
453
454 if (i2c->rd_cmd_xfered != 0)
455 cmd_to_send = min(cmd_to_send,
456 JZ4780_I2C_FIFO_LEN
457 - TX_LEVEL - 1);
458
459 if (cmd_to_send) {
460 jz4780_i2c_send_rcmd(i2c, cmd_to_send);
461 i2c->rd_cmd_xfered += cmd_to_send;
462 }
463
464 cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered;
465 if (cmd_left == 0) {
466 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
467 intmsk &= ~JZ4780_I2C_INTM_MTXEMP;
468 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, intmsk);
469
470 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
471 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
472 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
473 }
474 } else {
475 unsigned short data;
476 unsigned short i2c_sta;
477
478 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
479
480 while ((i2c_sta & JZ4780_I2C_STA_TFNF) &&
481 (i2c->wt_len > 0)) {
482 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
483 data = *i2c->wbuf;
484 data &= ~JZ4780_I2C_DC_READ;
485 jz4780_i2c_writew(i2c, JZ4780_I2C_DC,
486 data);
487 i2c->wbuf++;
488 i2c->wt_len--;
489 }
490
491 if (i2c->wt_len == 0) {
492 if (!i2c->stop_hold) {
493 tmp = jz4780_i2c_readw(i2c,
494 JZ4780_I2C_CTRL);
495 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
496 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL,
497 tmp);
498 }
499
500 jz4780_i2c_trans_done(i2c);
501 goto done;
502 }
503 }
504 }
505
506 done:
507 spin_unlock_irqrestore(&i2c->lock, flags);
508 return IRQ_HANDLED;
509 }
510
511 static void jz4780_i2c_txabrt(struct jz4780_i2c *i2c, int src)
512 {
513 dev_dbg(&i2c->adap.dev, "txabrt: 0x%08x, cmd: %d, send: %d, recv: %d\n",
514 src, i2c->cmd, i2c->cmd_buf[i2c->cmd], i2c->data_buf[i2c->cmd]);
515 }
516
517 static inline int jz4780_i2c_xfer_read(struct jz4780_i2c *i2c,
518 unsigned char *buf, int len, int cnt,
519 int idx)
520 {
521 int ret = 0;
522 long timeout;
523 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
524 unsigned short tmp;
525 unsigned long flags;
526
527 memset(buf, 0, len);
528
529 spin_lock_irqsave(&i2c->lock, flags);
530
531 i2c->stop_hold = 0;
532 i2c->is_write = 0;
533 i2c->rbuf = buf;
534 i2c->rd_total_len = len;
535 i2c->rd_data_xfered = 0;
536 i2c->rd_cmd_xfered = 0;
537
538 if (len <= JZ4780_I2C_FIFO_LEN)
539 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, len - 1);
540 else
541 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, RX_LEVEL);
542
543 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, TX_LEVEL);
544
545 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM,
546 JZ4780_I2C_INTM_MRXFL | JZ4780_I2C_INTM_MTXEMP
547 | JZ4780_I2C_INTM_MTXABT | JZ4780_I2C_INTM_MRXOF);
548
549 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
550 tmp |= JZ4780_I2C_CTRL_STPHLD;
551 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
552
553 spin_unlock_irqrestore(&i2c->lock, flags);
554
555 timeout = wait_for_completion_timeout(&i2c->trans_waitq,
556 msecs_to_jiffies(wait_time));
557
558 if (!timeout) {
559 dev_err(&i2c->adap.dev, "irq read timeout\n");
560 dev_dbg(&i2c->adap.dev, "send cmd count:%d %d\n",
561 i2c->cmd, i2c->cmd_buf[i2c->cmd]);
562 dev_dbg(&i2c->adap.dev, "receive data count:%d %d\n",
563 i2c->cmd, i2c->data_buf[i2c->cmd]);
564 ret = -EIO;
565 }
566
567 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
568 if (tmp) {
569 jz4780_i2c_txabrt(i2c, tmp);
570 ret = -EIO;
571 }
572
573 return ret;
574 }
575
576 static inline int jz4780_i2c_xfer_write(struct jz4780_i2c *i2c,
577 unsigned char *buf, int len,
578 int cnt, int idx)
579 {
580 int ret = 0;
581 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
582 long timeout;
583 unsigned short tmp;
584 unsigned long flags;
585
586 spin_lock_irqsave(&i2c->lock, flags);
587
588 if (idx < (cnt - 1))
589 i2c->stop_hold = 1;
590 else
591 i2c->stop_hold = 0;
592
593 i2c->is_write = 1;
594 i2c->wbuf = buf;
595 i2c->wt_len = len;
596
597 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, TX_LEVEL);
598
599 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, JZ4780_I2C_INTM_MTXEMP
600 | JZ4780_I2C_INTM_MTXABT);
601
602 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
603 tmp |= JZ4780_I2C_CTRL_STPHLD;
604 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
605
606 spin_unlock_irqrestore(&i2c->lock, flags);
607
608 timeout = wait_for_completion_timeout(&i2c->trans_waitq,
609 msecs_to_jiffies(wait_time));
610 if (timeout && !i2c->stop_hold) {
611 unsigned short i2c_sta;
612 int write_in_process;
613
614 timeout = JZ4780_I2C_TIMEOUT * 100;
615 for (; timeout > 0; timeout--) {
616 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
617
618 write_in_process = (i2c_sta & JZ4780_I2C_STA_MSTACT) ||
619 !(i2c_sta & JZ4780_I2C_STA_TFE);
620 if (!write_in_process)
621 break;
622 udelay(10);
623 }
624 }
625
626 if (!timeout) {
627 dev_err(&i2c->adap.dev, "write wait timeout\n");
628 ret = -EIO;
629 }
630
631 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
632 if (tmp) {
633 jz4780_i2c_txabrt(i2c, tmp);
634 ret = -EIO;
635 }
636
637 return ret;
638 }
639
640 static int jz4780_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
641 int count)
642 {
643 int i = -EIO;
644 int ret = 0;
645 struct jz4780_i2c *i2c = adap->algo_data;
646
647 ret = jz4780_i2c_prepare(i2c);
648 if (ret) {
649 dev_err(&i2c->adap.dev, "I2C prepare failed\n");
650 goto out;
651 }
652
653 if (msg->addr != jz4780_i2c_readw(i2c, JZ4780_I2C_TAR)) {
654 ret = jz4780_i2c_set_target(i2c, msg->addr);
655 if (ret)
656 goto out;
657 }
658 for (i = 0; i < count; i++, msg++) {
659 if (msg->flags & I2C_M_RD)
660 ret = jz4780_i2c_xfer_read(i2c, msg->buf, msg->len,
661 count, i);
662 else
663 ret = jz4780_i2c_xfer_write(i2c, msg->buf, msg->len,
664 count, i);
665
666 if (ret)
667 goto out;
668 }
669
670 ret = i;
671
672 out:
673 jz4780_i2c_cleanup(i2c);
674 return ret;
675 }
676
677 static u32 jz4780_i2c_functionality(struct i2c_adapter *adap)
678 {
679 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
680 }
681
682 static const struct i2c_algorithm jz4780_i2c_algorithm = {
683 .master_xfer = jz4780_i2c_xfer,
684 .functionality = jz4780_i2c_functionality,
685 };
686
687 static const struct of_device_id jz4780_i2c_of_matches[] = {
688 { .compatible = "ingenic,jz4780-i2c", },
689 { }
690 };
691 MODULE_DEVICE_TABLE(of, jz4780_i2c_of_matches);
692
693 static int jz4780_i2c_probe(struct platform_device *pdev)
694 {
695 int ret = 0;
696 unsigned int clk_freq = 0;
697 unsigned short tmp;
698 struct resource *r;
699 struct jz4780_i2c *i2c;
700
701 i2c = devm_kzalloc(&pdev->dev, sizeof(struct jz4780_i2c), GFP_KERNEL);
702 if (!i2c)
703 return -ENOMEM;
704
705 i2c->adap.owner = THIS_MODULE;
706 i2c->adap.algo = &jz4780_i2c_algorithm;
707 i2c->adap.algo_data = i2c;
708 i2c->adap.retries = 5;
709 i2c->adap.dev.parent = &pdev->dev;
710 i2c->adap.dev.of_node = pdev->dev.of_node;
711 sprintf(i2c->adap.name, "%s", pdev->name);
712
713 init_completion(&i2c->trans_waitq);
714 spin_lock_init(&i2c->lock);
715
716 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
717 i2c->iomem = devm_ioremap_resource(&pdev->dev, r);
718 if (IS_ERR(i2c->iomem))
719 return PTR_ERR(i2c->iomem);
720
721 platform_set_drvdata(pdev, i2c);
722
723 i2c->clk = devm_clk_get(&pdev->dev, NULL);
724 if (IS_ERR(i2c->clk))
725 return PTR_ERR(i2c->clk);
726
727 ret = clk_prepare_enable(i2c->clk);
728 if (ret)
729 return ret;
730
731 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
732 &clk_freq);
733 if (ret) {
734 dev_err(&pdev->dev, "clock-frequency not specified in DT\n");
735 goto err;
736 }
737
738 i2c->speed = clk_freq / 1000;
739 if (i2c->speed == 0) {
740 ret = -EINVAL;
741 dev_err(&pdev->dev, "clock-frequency minimum is 1000\n");
742 goto err;
743 }
744 jz4780_i2c_set_speed(i2c);
745
746 dev_info(&pdev->dev, "Bus frequency is %d KHz\n", i2c->speed);
747
748 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
749 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
750 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
751
752 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0x0);
753
754 i2c->irq = platform_get_irq(pdev, 0);
755 ret = devm_request_irq(&pdev->dev, i2c->irq, jz4780_i2c_irq, 0,
756 dev_name(&pdev->dev), i2c);
757 if (ret)
758 goto err;
759
760 ret = i2c_add_adapter(&i2c->adap);
761 if (ret < 0)
762 goto err;
763
764 return 0;
765
766 err:
767 clk_disable_unprepare(i2c->clk);
768 return ret;
769 }
770
771 static int jz4780_i2c_remove(struct platform_device *pdev)
772 {
773 struct jz4780_i2c *i2c = platform_get_drvdata(pdev);
774
775 clk_disable_unprepare(i2c->clk);
776 i2c_del_adapter(&i2c->adap);
777 return 0;
778 }
779
780 static struct platform_driver jz4780_i2c_driver = {
781 .probe = jz4780_i2c_probe,
782 .remove = jz4780_i2c_remove,
783 .driver = {
784 .name = "jz4780-i2c",
785 .of_match_table = of_match_ptr(jz4780_i2c_of_matches),
786 },
787 };
788
789 module_platform_driver(jz4780_i2c_driver);
790
791 MODULE_LICENSE("GPL");
792 MODULE_AUTHOR("ztyan<ztyan@ingenic.cn>");
793 MODULE_DESCRIPTION("i2c driver for JZ4780 SoCs");