drivers/i2c/busses/i2c-bcm-iproc.c

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This source file includes following definitions.
iproc_i2c_rd_reg
iproc_i2c_wr_reg
bcm_iproc_i2c_slave_init
bcm_iproc_i2c_check_slave_status
bcm_iproc_i2c_slave_isr
bcm_iproc_i2c_read_valid_bytes
bcm_iproc_i2c_send
bcm_iproc_i2c_read
bcm_iproc_i2c_process_m_event
bcm_iproc_i2c_isr
bcm_iproc_i2c_init
bcm_iproc_i2c_enable_disable
bcm_iproc_i2c_check_status
bcm_iproc_i2c_xfer_wait
bcm_iproc_i2c_xfer_single_msg
bcm_iproc_i2c_xfer
bcm_iproc_i2c_functionality
bcm_iproc_i2c_cfg_speed
bcm_iproc_i2c_probe
bcm_iproc_i2c_remove
bcm_iproc_i2c_suspend
bcm_iproc_i2c_resume
bcm_iproc_i2c_reg_slave
bcm_iproc_i2c_unreg_slave
   1 /*
   2  * Copyright (C) 2014 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13 
  14 #include <linux/delay.h>
  15 #include <linux/i2c.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23 
  24 #define IDM_CTRL_DIRECT_OFFSET       0x00
  25 #define CFG_OFFSET                   0x00
  26 #define CFG_RESET_SHIFT              31
  27 #define CFG_EN_SHIFT                 30
  28 #define CFG_SLAVE_ADDR_0_SHIFT       28
  29 #define CFG_M_RETRY_CNT_SHIFT        16
  30 #define CFG_M_RETRY_CNT_MASK         0x0f
  31 
  32 #define TIM_CFG_OFFSET               0x04
  33 #define TIM_CFG_MODE_400_SHIFT       31
  34 #define TIM_RAND_SLAVE_STRETCH_SHIFT      24
  35 #define TIM_RAND_SLAVE_STRETCH_MASK       0x7f
  36 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT  16
  37 #define TIM_PERIODIC_SLAVE_STRETCH_MASK   0x7f
  38 
  39 #define S_CFG_SMBUS_ADDR_OFFSET           0x08
  40 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT      31
  41 #define S_CFG_NIC_SMB_ADDR3_SHIFT         24
  42 #define S_CFG_NIC_SMB_ADDR3_MASK          0x7f
  43 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT      23
  44 #define S_CFG_NIC_SMB_ADDR2_SHIFT         16
  45 #define S_CFG_NIC_SMB_ADDR2_MASK          0x7f
  46 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT      15
  47 #define S_CFG_NIC_SMB_ADDR1_SHIFT         8
  48 #define S_CFG_NIC_SMB_ADDR1_MASK          0x7f
  49 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT      7
  50 #define S_CFG_NIC_SMB_ADDR0_SHIFT         0
  51 #define S_CFG_NIC_SMB_ADDR0_MASK          0x7f
  52 
  53 #define M_FIFO_CTRL_OFFSET           0x0c
  54 #define M_FIFO_RX_FLUSH_SHIFT        31
  55 #define M_FIFO_TX_FLUSH_SHIFT        30
  56 #define M_FIFO_RX_CNT_SHIFT          16
  57 #define M_FIFO_RX_CNT_MASK           0x7f
  58 #define M_FIFO_RX_THLD_SHIFT         8
  59 #define M_FIFO_RX_THLD_MASK          0x3f
  60 
  61 #define S_FIFO_CTRL_OFFSET           0x10
  62 #define S_FIFO_RX_FLUSH_SHIFT        31
  63 #define S_FIFO_TX_FLUSH_SHIFT        30
  64 #define S_FIFO_RX_CNT_SHIFT          16
  65 #define S_FIFO_RX_CNT_MASK           0x7f
  66 #define S_FIFO_RX_THLD_SHIFT         8
  67 #define S_FIFO_RX_THLD_MASK          0x3f
  68 
  69 #define M_CMD_OFFSET                 0x30
  70 #define M_CMD_START_BUSY_SHIFT       31
  71 #define M_CMD_STATUS_SHIFT           25
  72 #define M_CMD_STATUS_MASK            0x07
  73 #define M_CMD_STATUS_SUCCESS         0x0
  74 #define M_CMD_STATUS_LOST_ARB        0x1
  75 #define M_CMD_STATUS_NACK_ADDR       0x2
  76 #define M_CMD_STATUS_NACK_DATA       0x3
  77 #define M_CMD_STATUS_TIMEOUT         0x4
  78 #define M_CMD_STATUS_FIFO_UNDERRUN   0x5
  79 #define M_CMD_STATUS_RX_FIFO_FULL    0x6
  80 #define M_CMD_PROTOCOL_SHIFT         9
  81 #define M_CMD_PROTOCOL_MASK          0xf
  82 #define M_CMD_PROTOCOL_BLK_WR        0x7
  83 #define M_CMD_PROTOCOL_BLK_RD        0x8
  84 #define M_CMD_PEC_SHIFT              8
  85 #define M_CMD_RD_CNT_SHIFT           0
  86 #define M_CMD_RD_CNT_MASK            0xff
  87 
  88 #define S_CMD_OFFSET                 0x34
  89 #define S_CMD_START_BUSY_SHIFT       31
  90 #define S_CMD_STATUS_SHIFT           23
  91 #define S_CMD_STATUS_MASK            0x07
  92 #define S_CMD_STATUS_SUCCESS         0x0
  93 #define S_CMD_STATUS_TIMEOUT         0x5
  94 
  95 #define IE_OFFSET                    0x38
  96 #define IE_M_RX_FIFO_FULL_SHIFT      31
  97 #define IE_M_RX_THLD_SHIFT           30
  98 #define IE_M_START_BUSY_SHIFT        28
  99 #define IE_M_TX_UNDERRUN_SHIFT       27
 100 #define IE_S_RX_FIFO_FULL_SHIFT      26
 101 #define IE_S_RX_THLD_SHIFT           25
 102 #define IE_S_RX_EVENT_SHIFT          24
 103 #define IE_S_START_BUSY_SHIFT        23
 104 #define IE_S_TX_UNDERRUN_SHIFT       22
 105 #define IE_S_RD_EVENT_SHIFT          21
 106 
 107 #define IS_OFFSET                    0x3c
 108 #define IS_M_RX_FIFO_FULL_SHIFT      31
 109 #define IS_M_RX_THLD_SHIFT           30
 110 #define IS_M_START_BUSY_SHIFT        28
 111 #define IS_M_TX_UNDERRUN_SHIFT       27
 112 #define IS_S_RX_FIFO_FULL_SHIFT      26
 113 #define IS_S_RX_THLD_SHIFT           25
 114 #define IS_S_RX_EVENT_SHIFT          24
 115 #define IS_S_START_BUSY_SHIFT        23
 116 #define IS_S_TX_UNDERRUN_SHIFT       22
 117 #define IS_S_RD_EVENT_SHIFT          21
 118 
 119 #define M_TX_OFFSET                  0x40
 120 #define M_TX_WR_STATUS_SHIFT         31
 121 #define M_TX_DATA_SHIFT              0
 122 #define M_TX_DATA_MASK               0xff
 123 
 124 #define M_RX_OFFSET                  0x44
 125 #define M_RX_STATUS_SHIFT            30
 126 #define M_RX_STATUS_MASK             0x03
 127 #define M_RX_PEC_ERR_SHIFT           29
 128 #define M_RX_DATA_SHIFT              0
 129 #define M_RX_DATA_MASK               0xff
 130 
 131 #define S_TX_OFFSET                  0x48
 132 #define S_TX_WR_STATUS_SHIFT         31
 133 #define S_TX_DATA_SHIFT              0
 134 #define S_TX_DATA_MASK               0xff
 135 
 136 #define S_RX_OFFSET                  0x4c
 137 #define S_RX_STATUS_SHIFT            30
 138 #define S_RX_STATUS_MASK             0x03
 139 #define S_RX_PEC_ERR_SHIFT           29
 140 #define S_RX_DATA_SHIFT              0
 141 #define S_RX_DATA_MASK               0xff
 142 
 143 #define I2C_TIMEOUT_MSEC             50000
 144 #define M_TX_RX_FIFO_SIZE            64
 145 #define M_RX_FIFO_MAX_THLD_VALUE     (M_TX_RX_FIFO_SIZE - 1)
 146 
 147 #define M_RX_MAX_READ_LEN            255
 148 #define M_RX_FIFO_THLD_VALUE         50
 149 
 150 #define IE_M_ALL_INTERRUPT_SHIFT     27
 151 #define IE_M_ALL_INTERRUPT_MASK      0x1e
 152 
 153 #define SLAVE_READ_WRITE_BIT_MASK    0x1
 154 #define SLAVE_READ_WRITE_BIT_SHIFT   0x1
 155 #define SLAVE_MAX_SIZE_TRANSACTION   64
 156 #define SLAVE_CLOCK_STRETCH_TIME     25
 157 
 158 #define IE_S_ALL_INTERRUPT_SHIFT     21
 159 #define IE_S_ALL_INTERRUPT_MASK      0x3f
 160 
 161 enum i2c_slave_read_status {
 162         I2C_SLAVE_RX_FIFO_EMPTY = 0,
 163         I2C_SLAVE_RX_START,
 164         I2C_SLAVE_RX_DATA,
 165         I2C_SLAVE_RX_END,
 166 };
 167 
 168 enum bus_speed_index {
 169         I2C_SPD_100K = 0,
 170         I2C_SPD_400K,
 171 };
 172 
 173 enum bcm_iproc_i2c_type {
 174         IPROC_I2C,
 175         IPROC_I2C_NIC
 176 };
 177 
 178 struct bcm_iproc_i2c_dev {
 179         struct device *device;
 180         enum bcm_iproc_i2c_type type;
 181         int irq;
 182 
 183         void __iomem *base;
 184         void __iomem *idm_base;
 185 
 186         u32 ape_addr_mask;
 187 
 188         /* lock for indirect access through IDM */
 189         spinlock_t idm_lock;
 190 
 191         struct i2c_adapter adapter;
 192         unsigned int bus_speed;
 193 
 194         struct completion done;
 195         int xfer_is_done;
 196 
 197         struct i2c_msg *msg;
 198 
 199         struct i2c_client *slave;
 200 
 201         /* bytes that have been transferred */
 202         unsigned int tx_bytes;
 203         /* bytes that have been read */
 204         unsigned int rx_bytes;
 205         unsigned int thld_bytes;
 206 };
 207 
 208 /*
 209  * Can be expanded in the future if more interrupt status bits are utilized
 210  */
 211 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
 212                 | BIT(IS_M_RX_THLD_SHIFT))
 213 
 214 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
 215                 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
 216                 | BIT(IS_S_TX_UNDERRUN_SHIFT))
 217 
 218 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
 219 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
 220 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 221                                          bool enable);
 222 
 223 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 224                                    u32 offset)
 225 {
 226         u32 val;
 227 
 228         if (iproc_i2c->idm_base) {
 229                 spin_lock(&iproc_i2c->idm_lock);
 230                 writel(iproc_i2c->ape_addr_mask,
 231                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 232                 val = readl(iproc_i2c->base + offset);
 233                 spin_unlock(&iproc_i2c->idm_lock);
 234         } else {
 235                 val = readl(iproc_i2c->base + offset);
 236         }
 237 
 238         return val;
 239 }
 240 
 241 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 242                                     u32 offset, u32 val)
 243 {
 244         if (iproc_i2c->idm_base) {
 245                 spin_lock(&iproc_i2c->idm_lock);
 246                 writel(iproc_i2c->ape_addr_mask,
 247                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 248                 writel(val, iproc_i2c->base + offset);
 249                 spin_unlock(&iproc_i2c->idm_lock);
 250         } else {
 251                 writel(val, iproc_i2c->base + offset);
 252         }
 253 }
 254 
 255 static void bcm_iproc_i2c_slave_init(
 256         struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
 257 {
 258         u32 val;
 259 
 260         if (need_reset) {
 261                 /* put controller in reset */
 262                 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 263                 val |= BIT(CFG_RESET_SHIFT);
 264                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 265 
 266                 /* wait 100 usec per spec */
 267                 udelay(100);
 268 
 269                 /* bring controller out of reset */
 270                 val &= ~(BIT(CFG_RESET_SHIFT));
 271                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 272         }
 273 
 274         /* flush TX/RX FIFOs */
 275         val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
 276         iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
 277 
 278         /* Maximum slave stretch time */
 279         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
 280         val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
 281         val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
 282         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
 283 
 284         /* Configure the slave address */
 285         val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
 286         val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
 287         val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
 288         val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
 289         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
 290 
 291         /* clear all pending slave interrupts */
 292         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
 293 
 294         /* Enable interrupt register to indicate a valid byte in receive fifo */
 295         val = BIT(IE_S_RX_EVENT_SHIFT);
 296         /* Enable interrupt register for the Slave BUSY command */
 297         val |= BIT(IE_S_START_BUSY_SHIFT);
 298         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 299 }
 300 
 301 static void bcm_iproc_i2c_check_slave_status(
 302         struct bcm_iproc_i2c_dev *iproc_i2c)
 303 {
 304         u32 val;
 305 
 306         val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
 307         /* status is valid only when START_BUSY is cleared after it was set */
 308         if (val & BIT(S_CMD_START_BUSY_SHIFT))
 309                 return;
 310 
 311         val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
 312         if (val == S_CMD_STATUS_TIMEOUT) {
 313                 dev_err(iproc_i2c->device, "slave random stretch time timeout\n");
 314 
 315                 /* re-initialize i2c for recovery */
 316                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 317                 bcm_iproc_i2c_slave_init(iproc_i2c, true);
 318                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 319         }
 320 }
 321 
 322 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
 323                                     u32 status)
 324 {
 325         u32 val;
 326         u8 value, rx_status;
 327 
 328         /* Slave RX byte receive */
 329         if (status & BIT(IS_S_RX_EVENT_SHIFT)) {
 330                 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
 331                 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
 332                 if (rx_status == I2C_SLAVE_RX_START) {
 333                         /* Start of SMBUS for Master write */
 334                         i2c_slave_event(iproc_i2c->slave,
 335                                         I2C_SLAVE_WRITE_REQUESTED, &value);
 336 
 337                         val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
 338                         value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
 339                         i2c_slave_event(iproc_i2c->slave,
 340                                         I2C_SLAVE_WRITE_RECEIVED, &value);
 341                 } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
 342                         /* Start of SMBUS for Master Read */
 343                         i2c_slave_event(iproc_i2c->slave,
 344                                         I2C_SLAVE_READ_REQUESTED, &value);
 345                         iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
 346 
 347                         val = BIT(S_CMD_START_BUSY_SHIFT);
 348                         iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 349 
 350                         /*
 351                          * Enable interrupt for TX FIFO becomes empty and
 352                          * less than PKT_LENGTH bytes were output on the SMBUS
 353                          */
 354                         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 355                         val |= BIT(IE_S_TX_UNDERRUN_SHIFT);
 356                         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 357                 } else {
 358                         /* Master write other than start */
 359                         value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
 360                         i2c_slave_event(iproc_i2c->slave,
 361                                         I2C_SLAVE_WRITE_RECEIVED, &value);
 362                         if (rx_status == I2C_SLAVE_RX_END)
 363                                 i2c_slave_event(iproc_i2c->slave,
 364                                                 I2C_SLAVE_STOP, &value);
 365                 }
 366         } else if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
 367                 /* Master read other than start */
 368                 i2c_slave_event(iproc_i2c->slave,
 369                                 I2C_SLAVE_READ_PROCESSED, &value);
 370 
 371                 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
 372                 val = BIT(S_CMD_START_BUSY_SHIFT);
 373                 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 374         }
 375 
 376         /* Stop */
 377         if (status & BIT(IS_S_START_BUSY_SHIFT)) {
 378                 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
 379                 /*
 380                  * Enable interrupt for TX FIFO becomes empty and
 381                  * less than PKT_LENGTH bytes were output on the SMBUS
 382                  */
 383                 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 384                 val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
 385                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 386         }
 387 
 388         /* clear interrupt status */
 389         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 390 
 391         bcm_iproc_i2c_check_slave_status(iproc_i2c);
 392         return true;
 393 }
 394 
 395 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
 396 {
 397         struct i2c_msg *msg = iproc_i2c->msg;
 398         uint32_t val;
 399 
 400         /* Read valid data from RX FIFO */
 401         while (iproc_i2c->rx_bytes < msg->len) {
 402                 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
 403 
 404                 /* rx fifo empty */
 405                 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
 406                         break;
 407 
 408                 msg->buf[iproc_i2c->rx_bytes] =
 409                         (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
 410                 iproc_i2c->rx_bytes++;
 411         }
 412 }
 413 
 414 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
 415 {
 416         struct i2c_msg *msg = iproc_i2c->msg;
 417         unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
 418         unsigned int i;
 419         u32 val;
 420 
 421         /* can only fill up to the FIFO size */
 422         tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
 423         for (i = 0; i < tx_bytes; i++) {
 424                 /* start from where we left over */
 425                 unsigned int idx = iproc_i2c->tx_bytes + i;
 426 
 427                 val = msg->buf[idx];
 428 
 429                 /* mark the last byte */
 430                 if (idx == msg->len - 1) {
 431                         val |= BIT(M_TX_WR_STATUS_SHIFT);
 432 
 433                         if (iproc_i2c->irq) {
 434                                 u32 tmp;
 435 
 436                                 /*
 437                                  * Since this is the last byte, we should now
 438                                  * disable TX FIFO underrun interrupt
 439                                  */
 440                                 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 441                                 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
 442                                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
 443                                                  tmp);
 444                         }
 445                 }
 446 
 447                 /* load data into TX FIFO */
 448                 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 449         }
 450 
 451         /* update number of transferred bytes */
 452         iproc_i2c->tx_bytes += tx_bytes;
 453 }
 454 
 455 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
 456 {
 457         struct i2c_msg *msg = iproc_i2c->msg;
 458         u32 bytes_left, val;
 459 
 460         bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
 461         bytes_left = msg->len - iproc_i2c->rx_bytes;
 462         if (bytes_left == 0) {
 463                 if (iproc_i2c->irq) {
 464                         /* finished reading all data, disable rx thld event */
 465                         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 466                         val &= ~BIT(IS_M_RX_THLD_SHIFT);
 467                         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 468                 }
 469         } else if (bytes_left < iproc_i2c->thld_bytes) {
 470                 /* set bytes left as threshold */
 471                 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 472                 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 473                 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
 474                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 475                 iproc_i2c->thld_bytes = bytes_left;
 476         }
 477         /*
 478          * bytes_left >= iproc_i2c->thld_bytes,
 479          * hence no need to change the THRESHOLD SET.
 480          * It will remain as iproc_i2c->thld_bytes itself
 481          */
 482 }
 483 
 484 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
 485                                           u32 status)
 486 {
 487         /* TX FIFO is empty and we have more data to send */
 488         if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
 489                 bcm_iproc_i2c_send(iproc_i2c);
 490 
 491         /* RX FIFO threshold is reached and data needs to be read out */
 492         if (status & BIT(IS_M_RX_THLD_SHIFT))
 493                 bcm_iproc_i2c_read(iproc_i2c);
 494 
 495         /* transfer is done */
 496         if (status & BIT(IS_M_START_BUSY_SHIFT)) {
 497                 iproc_i2c->xfer_is_done = 1;
 498                 if (iproc_i2c->irq)
 499                         complete(&iproc_i2c->done);
 500         }
 501 }
 502 
 503 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
 504 {
 505         struct bcm_iproc_i2c_dev *iproc_i2c = data;
 506         u32 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
 507         bool ret;
 508         u32 sl_status = status & ISR_MASK_SLAVE;
 509 
 510         if (sl_status) {
 511                 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, sl_status);
 512                 if (ret)
 513                         return IRQ_HANDLED;
 514                 else
 515                         return IRQ_NONE;
 516         }
 517 
 518         status &= ISR_MASK;
 519         if (!status)
 520                 return IRQ_NONE;
 521 
 522         /* process all master based events */
 523         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 524         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 525 
 526         return IRQ_HANDLED;
 527 }
 528 
 529 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
 530 {
 531         u32 val;
 532 
 533         /* put controller in reset */
 534         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 535         val |= BIT(CFG_RESET_SHIFT);
 536         val &= ~(BIT(CFG_EN_SHIFT));
 537         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 538 
 539         /* wait 100 usec per spec */
 540         udelay(100);
 541 
 542         /* bring controller out of reset */
 543         val &= ~(BIT(CFG_RESET_SHIFT));
 544         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 545 
 546         /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
 547         val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
 548         iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 549         /* disable all interrupts */
 550         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 551         val &= ~(IE_M_ALL_INTERRUPT_MASK <<
 552                         IE_M_ALL_INTERRUPT_SHIFT);
 553         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 554 
 555         /* clear all pending interrupts */
 556         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
 557 
 558         return 0;
 559 }
 560 
 561 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 562                                          bool enable)
 563 {
 564         u32 val;
 565 
 566         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 567         if (enable)
 568                 val |= BIT(CFG_EN_SHIFT);
 569         else
 570                 val &= ~BIT(CFG_EN_SHIFT);
 571         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 572 }
 573 
 574 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
 575                                       struct i2c_msg *msg)
 576 {
 577         u32 val;
 578 
 579         val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
 580         val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
 581 
 582         switch (val) {
 583         case M_CMD_STATUS_SUCCESS:
 584                 return 0;
 585 
 586         case M_CMD_STATUS_LOST_ARB:
 587                 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
 588                 return -EAGAIN;
 589 
 590         case M_CMD_STATUS_NACK_ADDR:
 591                 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
 592                 return -ENXIO;
 593 
 594         case M_CMD_STATUS_NACK_DATA:
 595                 dev_dbg(iproc_i2c->device, "NAK data\n");
 596                 return -ENXIO;
 597 
 598         case M_CMD_STATUS_TIMEOUT:
 599                 dev_dbg(iproc_i2c->device, "bus timeout\n");
 600                 return -ETIMEDOUT;
 601 
 602         case M_CMD_STATUS_FIFO_UNDERRUN:
 603                 dev_dbg(iproc_i2c->device, "FIFO under-run\n");
 604                 return -ENXIO;
 605 
 606         case M_CMD_STATUS_RX_FIFO_FULL:
 607                 dev_dbg(iproc_i2c->device, "RX FIFO full\n");
 608                 return -ETIMEDOUT;
 609 
 610         default:
 611                 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
 612 
 613                 /* re-initialize i2c for recovery */
 614                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 615                 bcm_iproc_i2c_init(iproc_i2c);
 616                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 617 
 618                 return -EIO;
 619         }
 620 }
 621 
 622 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
 623                                    struct i2c_msg *msg,
 624                                    u32 cmd)
 625 {
 626         unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
 627         u32 val, status;
 628         int ret;
 629 
 630         iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
 631 
 632         if (iproc_i2c->irq) {
 633                 time_left = wait_for_completion_timeout(&iproc_i2c->done,
 634                                                         time_left);
 635                 /* disable all interrupts */
 636                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
 637                 /* read it back to flush the write */
 638                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 639                 /* make sure the interrupt handler isn't running */
 640                 synchronize_irq(iproc_i2c->irq);
 641 
 642         } else { /* polling mode */
 643                 unsigned long timeout = jiffies + time_left;
 644 
 645                 do {
 646                         status = iproc_i2c_rd_reg(iproc_i2c,
 647                                                   IS_OFFSET) & ISR_MASK;
 648                         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 649                         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 650 
 651                         if (time_after(jiffies, timeout)) {
 652                                 time_left = 0;
 653                                 break;
 654                         }
 655 
 656                         cpu_relax();
 657                         cond_resched();
 658                 } while (!iproc_i2c->xfer_is_done);
 659         }
 660 
 661         if (!time_left && !iproc_i2c->xfer_is_done) {
 662                 dev_err(iproc_i2c->device, "transaction timed out\n");
 663 
 664                 /* flush both TX/RX FIFOs */
 665                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 666                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 667                 return -ETIMEDOUT;
 668         }
 669 
 670         ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
 671         if (ret) {
 672                 /* flush both TX/RX FIFOs */
 673                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 674                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 675                 return ret;
 676         }
 677 
 678         return 0;
 679 }
 680 
 681 static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
 682                                          struct i2c_msg *msg)
 683 {
 684         int i;
 685         u8 addr;
 686         u32 val, tmp, val_intr_en;
 687         unsigned int tx_bytes;
 688 
 689         /* check if bus is busy */
 690         if (!!(iproc_i2c_rd_reg(iproc_i2c,
 691                                 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
 692                 dev_warn(iproc_i2c->device, "bus is busy\n");
 693                 return -EBUSY;
 694         }
 695 
 696         iproc_i2c->msg = msg;
 697 
 698         /* format and load slave address into the TX FIFO */
 699         addr = i2c_8bit_addr_from_msg(msg);
 700         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
 701 
 702         /*
 703          * For a write transaction, load data into the TX FIFO. Only allow
 704          * loading up to TX FIFO size - 1 bytes of data since the first byte
 705          * has been used up by the slave address
 706          */
 707         tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
 708         if (!(msg->flags & I2C_M_RD)) {
 709                 for (i = 0; i < tx_bytes; i++) {
 710                         val = msg->buf[i];
 711 
 712                         /* mark the last byte */
 713                         if (i == msg->len - 1)
 714                                 val |= BIT(M_TX_WR_STATUS_SHIFT);
 715 
 716                         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 717                 }
 718                 iproc_i2c->tx_bytes = tx_bytes;
 719         }
 720 
 721         /* mark as incomplete before starting the transaction */
 722         if (iproc_i2c->irq)
 723                 reinit_completion(&iproc_i2c->done);
 724 
 725         iproc_i2c->xfer_is_done = 0;
 726 
 727         /*
 728          * Enable the "start busy" interrupt, which will be triggered after the
 729          * transaction is done, i.e., the internal start_busy bit, transitions
 730          * from 1 to 0.
 731          */
 732         val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
 733 
 734         /*
 735          * If TX data size is larger than the TX FIFO, need to enable TX
 736          * underrun interrupt, which will be triggerred when the TX FIFO is
 737          * empty. When that happens we can then pump more data into the FIFO
 738          */
 739         if (!(msg->flags & I2C_M_RD) &&
 740             msg->len > iproc_i2c->tx_bytes)
 741                 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
 742 
 743         /*
 744          * Now we can activate the transfer. For a read operation, specify the
 745          * number of bytes to read
 746          */
 747         val = BIT(M_CMD_START_BUSY_SHIFT);
 748         if (msg->flags & I2C_M_RD) {
 749                 iproc_i2c->rx_bytes = 0;
 750                 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
 751                         iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
 752                 else
 753                         iproc_i2c->thld_bytes = msg->len;
 754 
 755                 /* set threshold value */
 756                 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 757                 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 758                 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
 759                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
 760 
 761                 /* enable the RX threshold interrupt */
 762                 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
 763 
 764                 val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) |
 765                        (msg->len << M_CMD_RD_CNT_SHIFT);
 766         } else {
 767                 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
 768         }
 769 
 770         if (iproc_i2c->irq)
 771                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
 772 
 773         return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
 774 }
 775 
 776 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
 777                               struct i2c_msg msgs[], int num)
 778 {
 779         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
 780         int ret, i;
 781 
 782         /* go through all messages */
 783         for (i = 0; i < num; i++) {
 784                 ret = bcm_iproc_i2c_xfer_single_msg(iproc_i2c, &msgs[i]);
 785                 if (ret) {
 786                         dev_dbg(iproc_i2c->device, "xfer failed\n");
 787                         return ret;
 788                 }
 789         }
 790 
 791         return num;
 792 }
 793 
 794 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
 795 {
 796         u32 val;
 797 
 798         /* We do not support the SMBUS Quick command */
 799         val = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 800 
 801         if (adap->algo->reg_slave)
 802                 val |= I2C_FUNC_SLAVE;
 803 
 804         return val;
 805 }
 806 
 807 static struct i2c_algorithm bcm_iproc_algo = {
 808         .master_xfer = bcm_iproc_i2c_xfer,
 809         .functionality = bcm_iproc_i2c_functionality,
 810         .reg_slave = bcm_iproc_i2c_reg_slave,
 811         .unreg_slave = bcm_iproc_i2c_unreg_slave,
 812 };
 813 
 814 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
 815         .max_read_len = M_RX_MAX_READ_LEN,
 816 };
 817 
 818 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
 819 {
 820         unsigned int bus_speed;
 821         u32 val;
 822         int ret = of_property_read_u32(iproc_i2c->device->of_node,
 823                                        "clock-frequency", &bus_speed);
 824         if (ret < 0) {
 825                 dev_info(iproc_i2c->device,
 826                         "unable to interpret clock-frequency DT property\n");
 827                 bus_speed = 100000;
 828         }
 829 
 830         if (bus_speed < 100000) {
 831                 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
 832                         bus_speed);
 833                 dev_err(iproc_i2c->device,
 834                         "valid speeds are 100khz and 400khz\n");
 835                 return -EINVAL;
 836         } else if (bus_speed < 400000) {
 837                 bus_speed = 100000;
 838         } else {
 839                 bus_speed = 400000;
 840         }
 841 
 842         iproc_i2c->bus_speed = bus_speed;
 843         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
 844         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
 845         val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
 846         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
 847 
 848         dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
 849 
 850         return 0;
 851 }
 852 
 853 static int bcm_iproc_i2c_probe(struct platform_device *pdev)
 854 {
 855         int irq, ret = 0;
 856         struct bcm_iproc_i2c_dev *iproc_i2c;
 857         struct i2c_adapter *adap;
 858         struct resource *res;
 859 
 860         iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
 861                                  GFP_KERNEL);
 862         if (!iproc_i2c)
 863                 return -ENOMEM;
 864 
 865         platform_set_drvdata(pdev, iproc_i2c);
 866         iproc_i2c->device = &pdev->dev;
 867         iproc_i2c->type =
 868                 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
 869         init_completion(&iproc_i2c->done);
 870 
 871         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 872         iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
 873         if (IS_ERR(iproc_i2c->base))
 874                 return PTR_ERR(iproc_i2c->base);
 875 
 876         if (iproc_i2c->type == IPROC_I2C_NIC) {
 877                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 878                 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
 879                                                             res);
 880                 if (IS_ERR(iproc_i2c->idm_base))
 881                         return PTR_ERR(iproc_i2c->idm_base);
 882 
 883                 ret = of_property_read_u32(iproc_i2c->device->of_node,
 884                                            "brcm,ape-hsls-addr-mask",
 885                                            &iproc_i2c->ape_addr_mask);
 886                 if (ret < 0) {
 887                         dev_err(iproc_i2c->device,
 888                                 "'brcm,ape-hsls-addr-mask' missing\n");
 889                         return -EINVAL;
 890                 }
 891 
 892                 spin_lock_init(&iproc_i2c->idm_lock);
 893 
 894                 /* no slave support */
 895                 bcm_iproc_algo.reg_slave = NULL;
 896                 bcm_iproc_algo.unreg_slave = NULL;
 897         }
 898 
 899         ret = bcm_iproc_i2c_init(iproc_i2c);
 900         if (ret)
 901                 return ret;
 902 
 903         ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
 904         if (ret)
 905                 return ret;
 906 
 907         irq = platform_get_irq(pdev, 0);
 908         if (irq > 0) {
 909                 ret = devm_request_irq(iproc_i2c->device, irq,
 910                                        bcm_iproc_i2c_isr, 0, pdev->name,
 911                                        iproc_i2c);
 912                 if (ret < 0) {
 913                         dev_err(iproc_i2c->device,
 914                                 "unable to request irq %i\n", irq);
 915                         return ret;
 916                 }
 917 
 918                 iproc_i2c->irq = irq;
 919         } else {
 920                 dev_warn(iproc_i2c->device,
 921                          "no irq resource, falling back to poll mode\n");
 922         }
 923 
 924         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 925 
 926         adap = &iproc_i2c->adapter;
 927         i2c_set_adapdata(adap, iproc_i2c);
 928         snprintf(adap->name, sizeof(adap->name),
 929                 "Broadcom iProc (%s)",
 930                 of_node_full_name(iproc_i2c->device->of_node));
 931         adap->algo = &bcm_iproc_algo;
 932         adap->quirks = &bcm_iproc_i2c_quirks;
 933         adap->dev.parent = &pdev->dev;
 934         adap->dev.of_node = pdev->dev.of_node;
 935 
 936         return i2c_add_adapter(adap);
 937 }
 938 
 939 static int bcm_iproc_i2c_remove(struct platform_device *pdev)
 940 {
 941         struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
 942 
 943         if (iproc_i2c->irq) {
 944                 /*
 945                  * Make sure there's no pending interrupt when we remove the
 946                  * adapter
 947                  */
 948                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
 949                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 950                 synchronize_irq(iproc_i2c->irq);
 951         }
 952 
 953         i2c_del_adapter(&iproc_i2c->adapter);
 954         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 955 
 956         return 0;
 957 }
 958 
 959 #ifdef CONFIG_PM_SLEEP
 960 
 961 static int bcm_iproc_i2c_suspend(struct device *dev)
 962 {
 963         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
 964 
 965         if (iproc_i2c->irq) {
 966                 /*
 967                  * Make sure there's no pending interrupt when we go into
 968                  * suspend
 969                  */
 970                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
 971                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 972                 synchronize_irq(iproc_i2c->irq);
 973         }
 974 
 975         /* now disable the controller */
 976         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 977 
 978         return 0;
 979 }
 980 
 981 static int bcm_iproc_i2c_resume(struct device *dev)
 982 {
 983         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
 984         int ret;
 985         u32 val;
 986 
 987         /*
 988          * Power domain could have been shut off completely in system deep
 989          * sleep, so re-initialize the block here
 990          */
 991         ret = bcm_iproc_i2c_init(iproc_i2c);
 992         if (ret)
 993                 return ret;
 994 
 995         /* configure to the desired bus speed */
 996         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
 997         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
 998         val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
 999         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1000 
1001         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1002 
1003         return 0;
1004 }
1005 
1006 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
1007         .suspend_late = &bcm_iproc_i2c_suspend,
1008         .resume_early = &bcm_iproc_i2c_resume
1009 };
1010 
1011 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
1012 #else
1013 #define BCM_IPROC_I2C_PM_OPS NULL
1014 #endif /* CONFIG_PM_SLEEP */
1015 
1016 
1017 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
1018 {
1019         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1020 
1021         if (iproc_i2c->slave)
1022                 return -EBUSY;
1023 
1024         if (slave->flags & I2C_CLIENT_TEN)
1025                 return -EAFNOSUPPORT;
1026 
1027         iproc_i2c->slave = slave;
1028         bcm_iproc_i2c_slave_init(iproc_i2c, false);
1029         return 0;
1030 }
1031 
1032 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1033 {
1034         u32 tmp;
1035         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1036 
1037         if (!iproc_i2c->slave)
1038                 return -EINVAL;
1039 
1040         iproc_i2c->slave = NULL;
1041 
1042         /* disable all slave interrupts */
1043         tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1044         tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1045                         IE_S_ALL_INTERRUPT_SHIFT);
1046         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
1047 
1048         /* Erase the slave address programmed */
1049         tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1050         tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1051         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
1052 
1053         return 0;
1054 }
1055 
1056 static const struct of_device_id bcm_iproc_i2c_of_match[] = {
1057         {
1058                 .compatible = "brcm,iproc-i2c",
1059                 .data = (int *)IPROC_I2C,
1060         }, {
1061                 .compatible = "brcm,iproc-nic-i2c",
1062                 .data = (int *)IPROC_I2C_NIC,
1063         },
1064         { /* sentinel */ }
1065 };
1066 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
1067 
1068 static struct platform_driver bcm_iproc_i2c_driver = {
1069         .driver = {
1070                 .name = "bcm-iproc-i2c",
1071                 .of_match_table = bcm_iproc_i2c_of_match,
1072                 .pm = BCM_IPROC_I2C_PM_OPS,
1073         },
1074         .probe = bcm_iproc_i2c_probe,
1075         .remove = bcm_iproc_i2c_remove,
1076 };
1077 module_platform_driver(bcm_iproc_i2c_driver);
1078 
1079 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1080 MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
1081 MODULE_LICENSE("GPL v2");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/i2c/busses/i2c-bcm-iproc.c

DEFINITIONS
