This source file includes following definitions.
- mtk_i2c_readw
- mtk_i2c_writew
- mtk_i2c_clock_enable
- mtk_i2c_clock_disable
- mtk_i2c_init_hw
- mtk_i2c_calculate_speed
- mtk_i2c_set_speed
- mtk_i2c_set_4g_mode
- mtk_i2c_do_transfer
- mtk_i2c_transfer
- mtk_i2c_irq
- mtk_i2c_functionality
- mtk_i2c_parse_dt
- mtk_i2c_probe
- mtk_i2c_remove
- mtk_i2c_resume
1
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5
6
7 #include <linux/clk.h>
8 #include <linux/completion.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/err.h>
13 #include <linux/errno.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/mm.h>
20 #include <linux/module.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/scatterlist.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28
29 #define I2C_RS_TRANSFER (1 << 4)
30 #define I2C_ARB_LOST (1 << 3)
31 #define I2C_HS_NACKERR (1 << 2)
32 #define I2C_ACKERR (1 << 1)
33 #define I2C_TRANSAC_COMP (1 << 0)
34 #define I2C_TRANSAC_START (1 << 0)
35 #define I2C_RS_MUL_CNFG (1 << 15)
36 #define I2C_RS_MUL_TRIG (1 << 14)
37 #define I2C_DCM_DISABLE 0x0000
38 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
39 #define I2C_IO_CONFIG_PUSH_PULL 0x0000
40 #define I2C_SOFT_RST 0x0001
41 #define I2C_FIFO_ADDR_CLR 0x0001
42 #define I2C_DELAY_LEN 0x0002
43 #define I2C_ST_START_CON 0x8001
44 #define I2C_FS_START_CON 0x1800
45 #define I2C_TIME_CLR_VALUE 0x0000
46 #define I2C_TIME_DEFAULT_VALUE 0x0003
47 #define I2C_WRRD_TRANAC_VALUE 0x0002
48 #define I2C_RD_TRANAC_VALUE 0x0001
49
50 #define I2C_DMA_CON_TX 0x0000
51 #define I2C_DMA_CON_RX 0x0001
52 #define I2C_DMA_START_EN 0x0001
53 #define I2C_DMA_INT_FLAG_NONE 0x0000
54 #define I2C_DMA_CLR_FLAG 0x0000
55 #define I2C_DMA_HARD_RST 0x0002
56 #define I2C_DMA_4G_MODE 0x0001
57
58 #define I2C_DEFAULT_CLK_DIV 5
59 #define I2C_DEFAULT_SPEED 100000
60 #define MAX_FS_MODE_SPEED 400000
61 #define MAX_HS_MODE_SPEED 3400000
62 #define MAX_SAMPLE_CNT_DIV 8
63 #define MAX_STEP_CNT_DIV 64
64 #define MAX_HS_STEP_CNT_DIV 8
65
66 #define I2C_CONTROL_RS (0x1 << 1)
67 #define I2C_CONTROL_DMA_EN (0x1 << 2)
68 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
69 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
70 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
71 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
72 #define I2C_CONTROL_DMAACK_EN (0x1 << 8)
73 #define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
74 #define I2C_CONTROL_WRAPPER (0x1 << 0)
75
76 #define I2C_DRV_NAME "i2c-mt65xx"
77
78 enum DMA_REGS_OFFSET {
79 OFFSET_INT_FLAG = 0x0,
80 OFFSET_INT_EN = 0x04,
81 OFFSET_EN = 0x08,
82 OFFSET_RST = 0x0c,
83 OFFSET_CON = 0x18,
84 OFFSET_TX_MEM_ADDR = 0x1c,
85 OFFSET_RX_MEM_ADDR = 0x20,
86 OFFSET_TX_LEN = 0x24,
87 OFFSET_RX_LEN = 0x28,
88 OFFSET_TX_4G_MODE = 0x54,
89 OFFSET_RX_4G_MODE = 0x58,
90 };
91
92 enum i2c_trans_st_rs {
93 I2C_TRANS_STOP = 0,
94 I2C_TRANS_REPEATED_START,
95 };
96
97 enum mtk_trans_op {
98 I2C_MASTER_WR = 1,
99 I2C_MASTER_RD,
100 I2C_MASTER_WRRD,
101 };
102
103 enum I2C_REGS_OFFSET {
104 OFFSET_DATA_PORT,
105 OFFSET_SLAVE_ADDR,
106 OFFSET_INTR_MASK,
107 OFFSET_INTR_STAT,
108 OFFSET_CONTROL,
109 OFFSET_TRANSFER_LEN,
110 OFFSET_TRANSAC_LEN,
111 OFFSET_DELAY_LEN,
112 OFFSET_TIMING,
113 OFFSET_START,
114 OFFSET_EXT_CONF,
115 OFFSET_FIFO_STAT,
116 OFFSET_FIFO_THRESH,
117 OFFSET_FIFO_ADDR_CLR,
118 OFFSET_IO_CONFIG,
119 OFFSET_RSV_DEBUG,
120 OFFSET_HS,
121 OFFSET_SOFTRESET,
122 OFFSET_DCM_EN,
123 OFFSET_PATH_DIR,
124 OFFSET_DEBUGSTAT,
125 OFFSET_DEBUGCTRL,
126 OFFSET_TRANSFER_LEN_AUX,
127 OFFSET_CLOCK_DIV,
128 OFFSET_LTIMING,
129 };
130
131 static const u16 mt_i2c_regs_v1[] = {
132 [OFFSET_DATA_PORT] = 0x0,
133 [OFFSET_SLAVE_ADDR] = 0x4,
134 [OFFSET_INTR_MASK] = 0x8,
135 [OFFSET_INTR_STAT] = 0xc,
136 [OFFSET_CONTROL] = 0x10,
137 [OFFSET_TRANSFER_LEN] = 0x14,
138 [OFFSET_TRANSAC_LEN] = 0x18,
139 [OFFSET_DELAY_LEN] = 0x1c,
140 [OFFSET_TIMING] = 0x20,
141 [OFFSET_START] = 0x24,
142 [OFFSET_EXT_CONF] = 0x28,
143 [OFFSET_FIFO_STAT] = 0x30,
144 [OFFSET_FIFO_THRESH] = 0x34,
145 [OFFSET_FIFO_ADDR_CLR] = 0x38,
146 [OFFSET_IO_CONFIG] = 0x40,
147 [OFFSET_RSV_DEBUG] = 0x44,
148 [OFFSET_HS] = 0x48,
149 [OFFSET_SOFTRESET] = 0x50,
150 [OFFSET_DCM_EN] = 0x54,
151 [OFFSET_PATH_DIR] = 0x60,
152 [OFFSET_DEBUGSTAT] = 0x64,
153 [OFFSET_DEBUGCTRL] = 0x68,
154 [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
155 [OFFSET_CLOCK_DIV] = 0x70,
156 };
157
158 static const u16 mt_i2c_regs_v2[] = {
159 [OFFSET_DATA_PORT] = 0x0,
160 [OFFSET_SLAVE_ADDR] = 0x4,
161 [OFFSET_INTR_MASK] = 0x8,
162 [OFFSET_INTR_STAT] = 0xc,
163 [OFFSET_CONTROL] = 0x10,
164 [OFFSET_TRANSFER_LEN] = 0x14,
165 [OFFSET_TRANSAC_LEN] = 0x18,
166 [OFFSET_DELAY_LEN] = 0x1c,
167 [OFFSET_TIMING] = 0x20,
168 [OFFSET_START] = 0x24,
169 [OFFSET_EXT_CONF] = 0x28,
170 [OFFSET_LTIMING] = 0x2c,
171 [OFFSET_HS] = 0x30,
172 [OFFSET_IO_CONFIG] = 0x34,
173 [OFFSET_FIFO_ADDR_CLR] = 0x38,
174 [OFFSET_TRANSFER_LEN_AUX] = 0x44,
175 [OFFSET_CLOCK_DIV] = 0x48,
176 [OFFSET_SOFTRESET] = 0x50,
177 [OFFSET_DEBUGSTAT] = 0xe0,
178 [OFFSET_DEBUGCTRL] = 0xe8,
179 [OFFSET_FIFO_STAT] = 0xf4,
180 [OFFSET_FIFO_THRESH] = 0xf8,
181 [OFFSET_DCM_EN] = 0xf88,
182 };
183
184 struct mtk_i2c_compatible {
185 const struct i2c_adapter_quirks *quirks;
186 const u16 *regs;
187 unsigned char pmic_i2c: 1;
188 unsigned char dcm: 1;
189 unsigned char auto_restart: 1;
190 unsigned char aux_len_reg: 1;
191 unsigned char support_33bits: 1;
192 unsigned char timing_adjust: 1;
193 unsigned char dma_sync: 1;
194 unsigned char ltiming_adjust: 1;
195 };
196
197 struct mtk_i2c {
198 struct i2c_adapter adap;
199 struct device *dev;
200 struct completion msg_complete;
201
202
203 void __iomem *base;
204 void __iomem *pdmabase;
205 struct clk *clk_main;
206 struct clk *clk_dma;
207 struct clk *clk_pmic;
208 struct clk *clk_arb;
209 bool have_pmic;
210 bool use_push_pull;
211
212 u16 irq_stat;
213 unsigned int clk_src_div;
214 unsigned int speed_hz;
215 enum mtk_trans_op op;
216 u16 timing_reg;
217 u16 high_speed_reg;
218 u16 ltiming_reg;
219 unsigned char auto_restart;
220 bool ignore_restart_irq;
221 const struct mtk_i2c_compatible *dev_comp;
222 };
223
224 static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
225 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
226 .max_num_msgs = 1,
227 .max_write_len = 255,
228 .max_read_len = 255,
229 .max_comb_1st_msg_len = 255,
230 .max_comb_2nd_msg_len = 31,
231 };
232
233 static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
234 .max_num_msgs = 255,
235 };
236
237 static const struct i2c_adapter_quirks mt8183_i2c_quirks = {
238 .flags = I2C_AQ_NO_ZERO_LEN,
239 };
240
241 static const struct mtk_i2c_compatible mt2712_compat = {
242 .regs = mt_i2c_regs_v1,
243 .pmic_i2c = 0,
244 .dcm = 1,
245 .auto_restart = 1,
246 .aux_len_reg = 1,
247 .support_33bits = 1,
248 .timing_adjust = 1,
249 .dma_sync = 0,
250 .ltiming_adjust = 0,
251 };
252
253 static const struct mtk_i2c_compatible mt6577_compat = {
254 .quirks = &mt6577_i2c_quirks,
255 .regs = mt_i2c_regs_v1,
256 .pmic_i2c = 0,
257 .dcm = 1,
258 .auto_restart = 0,
259 .aux_len_reg = 0,
260 .support_33bits = 0,
261 .timing_adjust = 0,
262 .dma_sync = 0,
263 .ltiming_adjust = 0,
264 };
265
266 static const struct mtk_i2c_compatible mt6589_compat = {
267 .quirks = &mt6577_i2c_quirks,
268 .regs = mt_i2c_regs_v1,
269 .pmic_i2c = 1,
270 .dcm = 0,
271 .auto_restart = 0,
272 .aux_len_reg = 0,
273 .support_33bits = 0,
274 .timing_adjust = 0,
275 .dma_sync = 0,
276 .ltiming_adjust = 0,
277 };
278
279 static const struct mtk_i2c_compatible mt7622_compat = {
280 .quirks = &mt7622_i2c_quirks,
281 .regs = mt_i2c_regs_v1,
282 .pmic_i2c = 0,
283 .dcm = 1,
284 .auto_restart = 1,
285 .aux_len_reg = 1,
286 .support_33bits = 0,
287 .timing_adjust = 0,
288 .dma_sync = 0,
289 .ltiming_adjust = 0,
290 };
291
292 static const struct mtk_i2c_compatible mt8173_compat = {
293 .regs = mt_i2c_regs_v1,
294 .pmic_i2c = 0,
295 .dcm = 1,
296 .auto_restart = 1,
297 .aux_len_reg = 1,
298 .support_33bits = 1,
299 .timing_adjust = 0,
300 .dma_sync = 0,
301 .ltiming_adjust = 0,
302 };
303
304 static const struct mtk_i2c_compatible mt8183_compat = {
305 .quirks = &mt8183_i2c_quirks,
306 .regs = mt_i2c_regs_v2,
307 .pmic_i2c = 0,
308 .dcm = 0,
309 .auto_restart = 1,
310 .aux_len_reg = 1,
311 .support_33bits = 1,
312 .timing_adjust = 1,
313 .dma_sync = 1,
314 .ltiming_adjust = 1,
315 };
316
317 static const struct of_device_id mtk_i2c_of_match[] = {
318 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
319 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
320 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
321 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
322 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
323 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
324 {}
325 };
326 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
327
328 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
329 {
330 return readw(i2c->base + i2c->dev_comp->regs[reg]);
331 }
332
333 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
334 enum I2C_REGS_OFFSET reg)
335 {
336 writew(val, i2c->base + i2c->dev_comp->regs[reg]);
337 }
338
339 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
340 {
341 int ret;
342
343 ret = clk_prepare_enable(i2c->clk_dma);
344 if (ret)
345 return ret;
346
347 ret = clk_prepare_enable(i2c->clk_main);
348 if (ret)
349 goto err_main;
350
351 if (i2c->have_pmic) {
352 ret = clk_prepare_enable(i2c->clk_pmic);
353 if (ret)
354 goto err_pmic;
355 }
356
357 if (i2c->clk_arb) {
358 ret = clk_prepare_enable(i2c->clk_arb);
359 if (ret)
360 goto err_arb;
361 }
362
363 return 0;
364
365 err_arb:
366 if (i2c->have_pmic)
367 clk_disable_unprepare(i2c->clk_pmic);
368 err_pmic:
369 clk_disable_unprepare(i2c->clk_main);
370 err_main:
371 clk_disable_unprepare(i2c->clk_dma);
372
373 return ret;
374 }
375
376 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
377 {
378 if (i2c->clk_arb)
379 clk_disable_unprepare(i2c->clk_arb);
380
381 if (i2c->have_pmic)
382 clk_disable_unprepare(i2c->clk_pmic);
383
384 clk_disable_unprepare(i2c->clk_main);
385 clk_disable_unprepare(i2c->clk_dma);
386 }
387
388 static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
389 {
390 u16 control_reg;
391
392 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
393
394
395 if (i2c->use_push_pull)
396 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
397 else
398 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
399
400 if (i2c->dev_comp->dcm)
401 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
402
403 if (i2c->dev_comp->timing_adjust)
404 mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, OFFSET_CLOCK_DIV);
405
406 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
407 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
408 if (i2c->dev_comp->ltiming_adjust)
409 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
410
411
412 if (i2c->have_pmic)
413 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
414
415 control_reg = I2C_CONTROL_ACKERR_DET_EN |
416 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
417 if (i2c->dev_comp->dma_sync)
418 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
419
420 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
421 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
422
423 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
424 udelay(50);
425 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
426 }
427
428
429
430
431
432
433
434
435
436
437
438
439 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
440 unsigned int target_speed,
441 unsigned int *timing_step_cnt,
442 unsigned int *timing_sample_cnt)
443 {
444 unsigned int step_cnt;
445 unsigned int sample_cnt;
446 unsigned int max_step_cnt;
447 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
448 unsigned int base_step_cnt;
449 unsigned int opt_div;
450 unsigned int best_mul;
451 unsigned int cnt_mul;
452
453 if (target_speed > MAX_HS_MODE_SPEED)
454 target_speed = MAX_HS_MODE_SPEED;
455
456 if (target_speed > MAX_FS_MODE_SPEED)
457 max_step_cnt = MAX_HS_STEP_CNT_DIV;
458 else
459 max_step_cnt = MAX_STEP_CNT_DIV;
460
461 base_step_cnt = max_step_cnt;
462
463 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
464 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
465
466
467
468
469
470
471
472 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
473 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
474 cnt_mul = step_cnt * sample_cnt;
475 if (step_cnt > max_step_cnt)
476 continue;
477
478 if (cnt_mul < best_mul) {
479 best_mul = cnt_mul;
480 base_sample_cnt = sample_cnt;
481 base_step_cnt = step_cnt;
482 if (best_mul == opt_div)
483 break;
484 }
485 }
486
487 sample_cnt = base_sample_cnt;
488 step_cnt = base_step_cnt;
489
490 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
491
492
493
494 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
495 return -EINVAL;
496 }
497
498 *timing_step_cnt = step_cnt - 1;
499 *timing_sample_cnt = sample_cnt - 1;
500
501 return 0;
502 }
503
504 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
505 {
506 unsigned int clk_src;
507 unsigned int step_cnt;
508 unsigned int sample_cnt;
509 unsigned int l_step_cnt;
510 unsigned int l_sample_cnt;
511 unsigned int target_speed;
512 int ret;
513
514 clk_src = parent_clk / i2c->clk_src_div;
515 target_speed = i2c->speed_hz;
516
517 if (target_speed > MAX_FS_MODE_SPEED) {
518
519 ret = mtk_i2c_calculate_speed(i2c, clk_src, MAX_FS_MODE_SPEED,
520 &l_step_cnt, &l_sample_cnt);
521 if (ret < 0)
522 return ret;
523
524 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
525
526
527 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
528 &step_cnt, &sample_cnt);
529 if (ret < 0)
530 return ret;
531
532 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
533 (sample_cnt << 12) | (step_cnt << 8);
534
535 if (i2c->dev_comp->ltiming_adjust)
536 i2c->ltiming_reg = (l_sample_cnt << 6) | l_step_cnt |
537 (sample_cnt << 12) | (step_cnt << 9);
538 } else {
539 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
540 &step_cnt, &sample_cnt);
541 if (ret < 0)
542 return ret;
543
544 i2c->timing_reg = (sample_cnt << 8) | step_cnt;
545
546
547 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
548
549 if (i2c->dev_comp->ltiming_adjust)
550 i2c->ltiming_reg = (sample_cnt << 6) | step_cnt;
551 }
552
553 return 0;
554 }
555
556 static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
557 {
558 return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
559 }
560
561 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
562 int num, int left_num)
563 {
564 u16 addr_reg;
565 u16 start_reg;
566 u16 control_reg;
567 u16 restart_flag = 0;
568 u32 reg_4g_mode;
569 u8 *dma_rd_buf = NULL;
570 u8 *dma_wr_buf = NULL;
571 dma_addr_t rpaddr = 0;
572 dma_addr_t wpaddr = 0;
573 int ret;
574
575 i2c->irq_stat = 0;
576
577 if (i2c->auto_restart)
578 restart_flag = I2C_RS_TRANSFER;
579
580 reinit_completion(&i2c->msg_complete);
581
582 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
583 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
584 if ((i2c->speed_hz > MAX_FS_MODE_SPEED) || (left_num >= 1))
585 control_reg |= I2C_CONTROL_RS;
586
587 if (i2c->op == I2C_MASTER_WRRD)
588 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
589
590 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
591
592
593 if (i2c->speed_hz <= I2C_DEFAULT_SPEED)
594 mtk_i2c_writew(i2c, I2C_ST_START_CON, OFFSET_EXT_CONF);
595 else
596 mtk_i2c_writew(i2c, I2C_FS_START_CON, OFFSET_EXT_CONF);
597
598 addr_reg = i2c_8bit_addr_from_msg(msgs);
599 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
600
601
602 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
603 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
604
605 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
606
607
608 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
609 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
610
611
612 if (i2c->op == I2C_MASTER_WRRD) {
613 if (i2c->dev_comp->aux_len_reg) {
614 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
615 mtk_i2c_writew(i2c, (msgs + 1)->len,
616 OFFSET_TRANSFER_LEN_AUX);
617 } else {
618 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
619 OFFSET_TRANSFER_LEN);
620 }
621 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
622 } else {
623 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
624 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
625 }
626
627
628 if (i2c->op == I2C_MASTER_RD) {
629 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
630 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
631
632 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
633 if (!dma_rd_buf)
634 return -ENOMEM;
635
636 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
637 msgs->len, DMA_FROM_DEVICE);
638 if (dma_mapping_error(i2c->dev, rpaddr)) {
639 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false);
640
641 return -ENOMEM;
642 }
643
644 if (i2c->dev_comp->support_33bits) {
645 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
646 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
647 }
648
649 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
650 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
651 } else if (i2c->op == I2C_MASTER_WR) {
652 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
653 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
654
655 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
656 if (!dma_wr_buf)
657 return -ENOMEM;
658
659 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
660 msgs->len, DMA_TO_DEVICE);
661 if (dma_mapping_error(i2c->dev, wpaddr)) {
662 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
663
664 return -ENOMEM;
665 }
666
667 if (i2c->dev_comp->support_33bits) {
668 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
669 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
670 }
671
672 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
673 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
674 } else {
675 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
676 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
677
678 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
679 if (!dma_wr_buf)
680 return -ENOMEM;
681
682 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
683 msgs->len, DMA_TO_DEVICE);
684 if (dma_mapping_error(i2c->dev, wpaddr)) {
685 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
686
687 return -ENOMEM;
688 }
689
690 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1);
691 if (!dma_rd_buf) {
692 dma_unmap_single(i2c->dev, wpaddr,
693 msgs->len, DMA_TO_DEVICE);
694
695 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
696
697 return -ENOMEM;
698 }
699
700 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
701 (msgs + 1)->len,
702 DMA_FROM_DEVICE);
703 if (dma_mapping_error(i2c->dev, rpaddr)) {
704 dma_unmap_single(i2c->dev, wpaddr,
705 msgs->len, DMA_TO_DEVICE);
706
707 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
708 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false);
709
710 return -ENOMEM;
711 }
712
713 if (i2c->dev_comp->support_33bits) {
714 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
715 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
716
717 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
718 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
719 }
720
721 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
722 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
723 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
724 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
725 }
726
727 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
728
729 if (!i2c->auto_restart) {
730 start_reg = I2C_TRANSAC_START;
731 } else {
732 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
733 if (left_num >= 1)
734 start_reg |= I2C_RS_MUL_CNFG;
735 }
736 mtk_i2c_writew(i2c, start_reg, OFFSET_START);
737
738 ret = wait_for_completion_timeout(&i2c->msg_complete,
739 i2c->adap.timeout);
740
741
742 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
743 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
744
745 if (i2c->op == I2C_MASTER_WR) {
746 dma_unmap_single(i2c->dev, wpaddr,
747 msgs->len, DMA_TO_DEVICE);
748
749 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
750 } else if (i2c->op == I2C_MASTER_RD) {
751 dma_unmap_single(i2c->dev, rpaddr,
752 msgs->len, DMA_FROM_DEVICE);
753
754 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true);
755 } else {
756 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
757 DMA_TO_DEVICE);
758 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
759 DMA_FROM_DEVICE);
760
761 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
762 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true);
763 }
764
765 if (ret == 0) {
766 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
767 mtk_i2c_init_hw(i2c);
768 return -ETIMEDOUT;
769 }
770
771 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
772 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
773 mtk_i2c_init_hw(i2c);
774 return -ENXIO;
775 }
776
777 return 0;
778 }
779
780 static int mtk_i2c_transfer(struct i2c_adapter *adap,
781 struct i2c_msg msgs[], int num)
782 {
783 int ret;
784 int left_num = num;
785 struct mtk_i2c *i2c = i2c_get_adapdata(adap);
786
787 ret = mtk_i2c_clock_enable(i2c);
788 if (ret)
789 return ret;
790
791 i2c->auto_restart = i2c->dev_comp->auto_restart;
792
793
794 if (i2c->auto_restart && num == 2) {
795 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
796 msgs[0].addr == msgs[1].addr) {
797 i2c->auto_restart = 0;
798 }
799 }
800
801 if (i2c->auto_restart && num >= 2 && i2c->speed_hz > MAX_FS_MODE_SPEED)
802
803
804
805 i2c->ignore_restart_irq = true;
806 else
807 i2c->ignore_restart_irq = false;
808
809 while (left_num--) {
810 if (!msgs->buf) {
811 dev_dbg(i2c->dev, "data buffer is NULL.\n");
812 ret = -EINVAL;
813 goto err_exit;
814 }
815
816 if (msgs->flags & I2C_M_RD)
817 i2c->op = I2C_MASTER_RD;
818 else
819 i2c->op = I2C_MASTER_WR;
820
821 if (!i2c->auto_restart) {
822 if (num > 1) {
823
824 i2c->op = I2C_MASTER_WRRD;
825 left_num--;
826 }
827 }
828
829
830 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
831 if (ret < 0)
832 goto err_exit;
833
834 msgs++;
835 }
836
837 ret = num;
838
839 err_exit:
840 mtk_i2c_clock_disable(i2c);
841 return ret;
842 }
843
844 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
845 {
846 struct mtk_i2c *i2c = dev_id;
847 u16 restart_flag = 0;
848 u16 intr_stat;
849
850 if (i2c->auto_restart)
851 restart_flag = I2C_RS_TRANSFER;
852
853 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
854 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
855
856
857
858
859
860
861 i2c->irq_stat |= intr_stat;
862
863 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
864 i2c->ignore_restart_irq = false;
865 i2c->irq_stat = 0;
866 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
867 I2C_TRANSAC_START, OFFSET_START);
868 } else {
869 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
870 complete(&i2c->msg_complete);
871 }
872
873 return IRQ_HANDLED;
874 }
875
876 static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
877 {
878 if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN))
879 return I2C_FUNC_I2C |
880 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
881 else
882 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
883 }
884
885 static const struct i2c_algorithm mtk_i2c_algorithm = {
886 .master_xfer = mtk_i2c_transfer,
887 .functionality = mtk_i2c_functionality,
888 };
889
890 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
891 {
892 int ret;
893
894 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
895 if (ret < 0)
896 i2c->speed_hz = I2C_DEFAULT_SPEED;
897
898 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
899 if (ret < 0)
900 return ret;
901
902 if (i2c->clk_src_div == 0)
903 return -EINVAL;
904
905 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
906 i2c->use_push_pull =
907 of_property_read_bool(np, "mediatek,use-push-pull");
908
909 return 0;
910 }
911
912 static int mtk_i2c_probe(struct platform_device *pdev)
913 {
914 int ret = 0;
915 struct mtk_i2c *i2c;
916 struct clk *clk;
917 struct resource *res;
918 int irq;
919
920 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
921 if (!i2c)
922 return -ENOMEM;
923
924 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
925 i2c->base = devm_ioremap_resource(&pdev->dev, res);
926 if (IS_ERR(i2c->base))
927 return PTR_ERR(i2c->base);
928
929 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
930 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
931 if (IS_ERR(i2c->pdmabase))
932 return PTR_ERR(i2c->pdmabase);
933
934 irq = platform_get_irq(pdev, 0);
935 if (irq <= 0)
936 return irq;
937
938 init_completion(&i2c->msg_complete);
939
940 i2c->dev_comp = of_device_get_match_data(&pdev->dev);
941 i2c->adap.dev.of_node = pdev->dev.of_node;
942 i2c->dev = &pdev->dev;
943 i2c->adap.dev.parent = &pdev->dev;
944 i2c->adap.owner = THIS_MODULE;
945 i2c->adap.algo = &mtk_i2c_algorithm;
946 i2c->adap.quirks = i2c->dev_comp->quirks;
947 i2c->adap.timeout = 2 * HZ;
948 i2c->adap.retries = 1;
949
950 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
951 if (ret)
952 return -EINVAL;
953
954 if (i2c->dev_comp->timing_adjust)
955 i2c->clk_src_div *= I2C_DEFAULT_CLK_DIV;
956
957 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
958 return -EINVAL;
959
960 i2c->clk_main = devm_clk_get(&pdev->dev, "main");
961 if (IS_ERR(i2c->clk_main)) {
962 dev_err(&pdev->dev, "cannot get main clock\n");
963 return PTR_ERR(i2c->clk_main);
964 }
965
966 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
967 if (IS_ERR(i2c->clk_dma)) {
968 dev_err(&pdev->dev, "cannot get dma clock\n");
969 return PTR_ERR(i2c->clk_dma);
970 }
971
972 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
973 if (IS_ERR(i2c->clk_arb))
974 i2c->clk_arb = NULL;
975
976 clk = i2c->clk_main;
977 if (i2c->have_pmic) {
978 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
979 if (IS_ERR(i2c->clk_pmic)) {
980 dev_err(&pdev->dev, "cannot get pmic clock\n");
981 return PTR_ERR(i2c->clk_pmic);
982 }
983 clk = i2c->clk_pmic;
984 }
985
986 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
987
988 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk));
989 if (ret) {
990 dev_err(&pdev->dev, "Failed to set the speed.\n");
991 return -EINVAL;
992 }
993
994 if (i2c->dev_comp->support_33bits) {
995 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
996 if (ret) {
997 dev_err(&pdev->dev, "dma_set_mask return error.\n");
998 return ret;
999 }
1000 }
1001
1002 ret = mtk_i2c_clock_enable(i2c);
1003 if (ret) {
1004 dev_err(&pdev->dev, "clock enable failed!\n");
1005 return ret;
1006 }
1007 mtk_i2c_init_hw(i2c);
1008 mtk_i2c_clock_disable(i2c);
1009
1010 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
1011 IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
1012 if (ret < 0) {
1013 dev_err(&pdev->dev,
1014 "Request I2C IRQ %d fail\n", irq);
1015 return ret;
1016 }
1017
1018 i2c_set_adapdata(&i2c->adap, i2c);
1019 ret = i2c_add_adapter(&i2c->adap);
1020 if (ret)
1021 return ret;
1022
1023 platform_set_drvdata(pdev, i2c);
1024
1025 return 0;
1026 }
1027
1028 static int mtk_i2c_remove(struct platform_device *pdev)
1029 {
1030 struct mtk_i2c *i2c = platform_get_drvdata(pdev);
1031
1032 i2c_del_adapter(&i2c->adap);
1033
1034 return 0;
1035 }
1036
1037 #ifdef CONFIG_PM_SLEEP
1038 static int mtk_i2c_resume(struct device *dev)
1039 {
1040 int ret;
1041 struct mtk_i2c *i2c = dev_get_drvdata(dev);
1042
1043 ret = mtk_i2c_clock_enable(i2c);
1044 if (ret) {
1045 dev_err(dev, "clock enable failed!\n");
1046 return ret;
1047 }
1048
1049 mtk_i2c_init_hw(i2c);
1050
1051 mtk_i2c_clock_disable(i2c);
1052
1053 return 0;
1054 }
1055 #endif
1056
1057 static const struct dev_pm_ops mtk_i2c_pm = {
1058 SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume)
1059 };
1060
1061 static struct platform_driver mtk_i2c_driver = {
1062 .probe = mtk_i2c_probe,
1063 .remove = mtk_i2c_remove,
1064 .driver = {
1065 .name = I2C_DRV_NAME,
1066 .pm = &mtk_i2c_pm,
1067 .of_match_table = of_match_ptr(mtk_i2c_of_match),
1068 },
1069 };
1070
1071 module_platform_driver(mtk_i2c_driver);
1072
1073 MODULE_LICENSE("GPL v2");
1074 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
1075 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");