drivers/i2c/busses/i2c-riic.c

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This source file includes following definitions.
riic_clear_set_bit
riic_xfer
riic_tdre_isr
riic_tend_isr
riic_rdrf_isr
riic_stop_isr
riic_func
riic_init_hw
riic_i2c_probe
riic_i2c_remove
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas RIIC driver
   4  *
   5  * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
   6  * Copyright (C) 2013 Renesas Solutions Corp.
   7  */
   8 
   9 /*
  10  * This i2c core has a lot of interrupts, namely 8. We use their chaining as
  11  * some kind of state machine.
  12  *
  13  * 1) The main xfer routine kicks off a transmission by putting the start bit
  14  * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
  15  * since we need to send the slave address + RW bit in every case.
  16  *
  17  * 2) TIE sends slave address + RW bit and selects how to continue.
  18  *
  19  * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
  20  * are done, we switch over to the transmission done interrupt (TEIE) and mark
  21  * the message as completed (includes sending STOP) there.
  22  *
  23  * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
  24  * needed to start clocking, then we keep receiving until we are done. Note
  25  * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
  26  * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
  27  * message to create the final NACK as sketched in the datasheet. This caused
  28  * some subtle races (when byte n was processed and byte n+1 was already
  29  * waiting), though, and I started with the safe approach.
  30  *
  31  * 4) If we got a NACK somewhere, we flag the error and stop the transmission
  32  * via NAKIE.
  33  *
  34  * Also check the comments in the interrupt routines for some gory details.
  35  */
  36 
  37 #include <linux/clk.h>
  38 #include <linux/completion.h>
  39 #include <linux/err.h>
  40 #include <linux/i2c.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/io.h>
  43 #include <linux/module.h>
  44 #include <linux/of.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/pm_runtime.h>
  47 
  48 #define RIIC_ICCR1      0x00
  49 #define RIIC_ICCR2      0x04
  50 #define RIIC_ICMR1      0x08
  51 #define RIIC_ICMR3      0x10
  52 #define RIIC_ICSER      0x18
  53 #define RIIC_ICIER      0x1c
  54 #define RIIC_ICSR2      0x24
  55 #define RIIC_ICBRL      0x34
  56 #define RIIC_ICBRH      0x38
  57 #define RIIC_ICDRT      0x3c
  58 #define RIIC_ICDRR      0x40
  59 
  60 #define ICCR1_ICE       0x80
  61 #define ICCR1_IICRST    0x40
  62 #define ICCR1_SOWP      0x10
  63 
  64 #define ICCR2_BBSY      0x80
  65 #define ICCR2_SP        0x08
  66 #define ICCR2_RS        0x04
  67 #define ICCR2_ST        0x02
  68 
  69 #define ICMR1_CKS_MASK  0x70
  70 #define ICMR1_BCWP      0x08
  71 #define ICMR1_CKS(_x)   ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
  72 
  73 #define ICMR3_RDRFS     0x20
  74 #define ICMR3_ACKWP     0x10
  75 #define ICMR3_ACKBT     0x08
  76 
  77 #define ICIER_TIE       0x80
  78 #define ICIER_TEIE      0x40
  79 #define ICIER_RIE       0x20
  80 #define ICIER_NAKIE     0x10
  81 #define ICIER_SPIE      0x08
  82 
  83 #define ICSR2_NACKF     0x10
  84 
  85 #define ICBR_RESERVED   0xe0 /* Should be 1 on writes */
  86 
  87 #define RIIC_INIT_MSG   -1
  88 
  89 struct riic_dev {
  90         void __iomem *base;
  91         u8 *buf;
  92         struct i2c_msg *msg;
  93         int bytes_left;
  94         int err;
  95         int is_last;
  96         struct completion msg_done;
  97         struct i2c_adapter adapter;
  98         struct clk *clk;
  99 };
 100 
 101 struct riic_irq_desc {
 102         int res_num;
 103         irq_handler_t isr;
 104         char *name;
 105 };
 106 
 107 static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
 108 {
 109         writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
 110 }
 111 
 112 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 113 {
 114         struct riic_dev *riic = i2c_get_adapdata(adap);
 115         unsigned long time_left;
 116         int i;
 117         u8 start_bit;
 118 
 119         pm_runtime_get_sync(adap->dev.parent);
 120 
 121         if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
 122                 riic->err = -EBUSY;
 123                 goto out;
 124         }
 125 
 126         reinit_completion(&riic->msg_done);
 127         riic->err = 0;
 128 
 129         writeb(0, riic->base + RIIC_ICSR2);
 130 
 131         for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
 132                 riic->bytes_left = RIIC_INIT_MSG;
 133                 riic->buf = msgs[i].buf;
 134                 riic->msg = &msgs[i];
 135                 riic->is_last = (i == num - 1);
 136 
 137                 writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER);
 138 
 139                 writeb(start_bit, riic->base + RIIC_ICCR2);
 140 
 141                 time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
 142                 if (time_left == 0)
 143                         riic->err = -ETIMEDOUT;
 144 
 145                 if (riic->err)
 146                         break;
 147 
 148                 start_bit = ICCR2_RS;
 149         }
 150 
 151  out:
 152         pm_runtime_put(adap->dev.parent);
 153 
 154         return riic->err ?: num;
 155 }
 156 
 157 static irqreturn_t riic_tdre_isr(int irq, void *data)
 158 {
 159         struct riic_dev *riic = data;
 160         u8 val;
 161 
 162         if (!riic->bytes_left)
 163                 return IRQ_NONE;
 164 
 165         if (riic->bytes_left == RIIC_INIT_MSG) {
 166                 if (riic->msg->flags & I2C_M_RD)
 167                         /* On read, switch over to receive interrupt */
 168                         riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
 169                 else
 170                         /* On write, initialize length */
 171                         riic->bytes_left = riic->msg->len;
 172 
 173                 val = i2c_8bit_addr_from_msg(riic->msg);
 174         } else {
 175                 val = *riic->buf;
 176                 riic->buf++;
 177                 riic->bytes_left--;
 178         }
 179 
 180         /*
 181          * Switch to transmission ended interrupt when done. Do check here
 182          * after bytes_left was initialized to support SMBUS_QUICK (new msg has
 183          * 0 length then)
 184          */
 185         if (riic->bytes_left == 0)
 186                 riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
 187 
 188         /*
 189          * This acks the TIE interrupt. We get another TIE immediately if our
 190          * value could be moved to the shadow shift register right away. So
 191          * this must be after updates to ICIER (where we want to disable TIE)!
 192          */
 193         writeb(val, riic->base + RIIC_ICDRT);
 194 
 195         return IRQ_HANDLED;
 196 }
 197 
 198 static irqreturn_t riic_tend_isr(int irq, void *data)
 199 {
 200         struct riic_dev *riic = data;
 201 
 202         if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
 203                 /* We got a NACKIE */
 204                 readb(riic->base + RIIC_ICDRR); /* dummy read */
 205                 riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2);
 206                 riic->err = -ENXIO;
 207         } else if (riic->bytes_left) {
 208                 return IRQ_NONE;
 209         }
 210 
 211         if (riic->is_last || riic->err) {
 212                 riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
 213                 writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
 214         } else {
 215                 /* Transfer is complete, but do not send STOP */
 216                 riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
 217                 complete(&riic->msg_done);
 218         }
 219 
 220         return IRQ_HANDLED;
 221 }
 222 
 223 static irqreturn_t riic_rdrf_isr(int irq, void *data)
 224 {
 225         struct riic_dev *riic = data;
 226 
 227         if (!riic->bytes_left)
 228                 return IRQ_NONE;
 229 
 230         if (riic->bytes_left == RIIC_INIT_MSG) {
 231                 riic->bytes_left = riic->msg->len;
 232                 readb(riic->base + RIIC_ICDRR); /* dummy read */
 233                 return IRQ_HANDLED;
 234         }
 235 
 236         if (riic->bytes_left == 1) {
 237                 /* STOP must come before we set ACKBT! */
 238                 if (riic->is_last) {
 239                         riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
 240                         writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
 241                 }
 242 
 243                 riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
 244 
 245         } else {
 246                 riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
 247         }
 248 
 249         /* Reading acks the RIE interrupt */
 250         *riic->buf = readb(riic->base + RIIC_ICDRR);
 251         riic->buf++;
 252         riic->bytes_left--;
 253 
 254         return IRQ_HANDLED;
 255 }
 256 
 257 static irqreturn_t riic_stop_isr(int irq, void *data)
 258 {
 259         struct riic_dev *riic = data;
 260 
 261         /* read back registers to confirm writes have fully propagated */
 262         writeb(0, riic->base + RIIC_ICSR2);
 263         readb(riic->base + RIIC_ICSR2);
 264         writeb(0, riic->base + RIIC_ICIER);
 265         readb(riic->base + RIIC_ICIER);
 266 
 267         complete(&riic->msg_done);
 268 
 269         return IRQ_HANDLED;
 270 }
 271 
 272 static u32 riic_func(struct i2c_adapter *adap)
 273 {
 274         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 275 }
 276 
 277 static const struct i2c_algorithm riic_algo = {
 278         .master_xfer    = riic_xfer,
 279         .functionality  = riic_func,
 280 };
 281 
 282 static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
 283 {
 284         int ret = 0;
 285         unsigned long rate;
 286         int total_ticks, cks, brl, brh;
 287 
 288         pm_runtime_get_sync(riic->adapter.dev.parent);
 289 
 290         if (t->bus_freq_hz > 400000) {
 291                 dev_err(&riic->adapter.dev,
 292                         "unsupported bus speed (%dHz). 400000 max\n",
 293                         t->bus_freq_hz);
 294                 ret = -EINVAL;
 295                 goto out;
 296         }
 297 
 298         rate = clk_get_rate(riic->clk);
 299 
 300         /*
 301          * Assume the default register settings:
 302          *  FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
 303          *  FER.NFE = 1 (noise circuit enabled)
 304          *  MR3.NF = 0 (1 cycle of noise filtered out)
 305          *
 306          * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
 307          * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
 308          */
 309 
 310         /*
 311          * Determine reference clock rate. We must be able to get the desired
 312          * frequency with only 62 clock ticks max (31 high, 31 low).
 313          * Aim for a duty of 60% LOW, 40% HIGH.
 314          */
 315         total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);
 316 
 317         for (cks = 0; cks < 7; cks++) {
 318                 /*
 319                  * 60% low time must be less than BRL + 2 + 1
 320                  * BRL max register value is 0x1F.
 321                  */
 322                 brl = ((total_ticks * 6) / 10);
 323                 if (brl <= (0x1F + 3))
 324                         break;
 325 
 326                 total_ticks /= 2;
 327                 rate /= 2;
 328         }
 329 
 330         if (brl > (0x1F + 3)) {
 331                 dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
 332                         (unsigned long)t->bus_freq_hz);
 333                 ret = -EINVAL;
 334                 goto out;
 335         }
 336 
 337         brh = total_ticks - brl;
 338 
 339         /* Remove automatic clock ticks for sync circuit and NF */
 340         if (cks == 0) {
 341                 brl -= 4;
 342                 brh -= 4;
 343         } else {
 344                 brl -= 3;
 345                 brh -= 3;
 346         }
 347 
 348         /*
 349          * Remove clock ticks for rise and fall times. Convert ns to clock
 350          * ticks.
 351          */
 352         brl -= t->scl_fall_ns / (1000000000 / rate);
 353         brh -= t->scl_rise_ns / (1000000000 / rate);
 354 
 355         /* Adjust for min register values for when SCLE=1 and NFE=1 */
 356         if (brl < 1)
 357                 brl = 1;
 358         if (brh < 1)
 359                 brh = 1;
 360 
 361         pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
 362                  rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
 363                  t->scl_fall_ns / (1000000000 / rate),
 364                  t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
 365 
 366         /* Changing the order of accessing IICRST and ICE may break things! */
 367         writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
 368         riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
 369 
 370         writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
 371         writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH);
 372         writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL);
 373 
 374         writeb(0, riic->base + RIIC_ICSER);
 375         writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);
 376 
 377         riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
 378 
 379 out:
 380         pm_runtime_put(riic->adapter.dev.parent);
 381         return ret;
 382 }
 383 
 384 static struct riic_irq_desc riic_irqs[] = {
 385         { .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
 386         { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
 387         { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
 388         { .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
 389         { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
 390 };
 391 
 392 static int riic_i2c_probe(struct platform_device *pdev)
 393 {
 394         struct riic_dev *riic;
 395         struct i2c_adapter *adap;
 396         struct resource *res;
 397         struct i2c_timings i2c_t;
 398         int i, ret;
 399 
 400         riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
 401         if (!riic)
 402                 return -ENOMEM;
 403 
 404         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 405         riic->base = devm_ioremap_resource(&pdev->dev, res);
 406         if (IS_ERR(riic->base))
 407                 return PTR_ERR(riic->base);
 408 
 409         riic->clk = devm_clk_get(&pdev->dev, NULL);
 410         if (IS_ERR(riic->clk)) {
 411                 dev_err(&pdev->dev, "missing controller clock");
 412                 return PTR_ERR(riic->clk);
 413         }
 414 
 415         for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
 416                 res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num);
 417                 if (!res)
 418                         return -ENODEV;
 419 
 420                 ret = devm_request_irq(&pdev->dev, res->start, riic_irqs[i].isr,
 421                                         0, riic_irqs[i].name, riic);
 422                 if (ret) {
 423                         dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
 424                         return ret;
 425                 }
 426         }
 427 
 428         adap = &riic->adapter;
 429         i2c_set_adapdata(adap, riic);
 430         strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
 431         adap->owner = THIS_MODULE;
 432         adap->algo = &riic_algo;
 433         adap->dev.parent = &pdev->dev;
 434         adap->dev.of_node = pdev->dev.of_node;
 435 
 436         init_completion(&riic->msg_done);
 437 
 438         i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
 439 
 440         pm_runtime_enable(&pdev->dev);
 441 
 442         ret = riic_init_hw(riic, &i2c_t);
 443         if (ret)
 444                 goto out;
 445 
 446         ret = i2c_add_adapter(adap);
 447         if (ret)
 448                 goto out;
 449 
 450         platform_set_drvdata(pdev, riic);
 451 
 452         dev_info(&pdev->dev, "registered with %dHz bus speed\n",
 453                  i2c_t.bus_freq_hz);
 454         return 0;
 455 
 456 out:
 457         pm_runtime_disable(&pdev->dev);
 458         return ret;
 459 }
 460 
 461 static int riic_i2c_remove(struct platform_device *pdev)
 462 {
 463         struct riic_dev *riic = platform_get_drvdata(pdev);
 464 
 465         pm_runtime_get_sync(&pdev->dev);
 466         writeb(0, riic->base + RIIC_ICIER);
 467         pm_runtime_put(&pdev->dev);
 468         i2c_del_adapter(&riic->adapter);
 469         pm_runtime_disable(&pdev->dev);
 470 
 471         return 0;
 472 }
 473 
 474 static const struct of_device_id riic_i2c_dt_ids[] = {
 475         { .compatible = "renesas,riic-rz" },
 476         { /* Sentinel */ },
 477 };
 478 
 479 static struct platform_driver riic_i2c_driver = {
 480         .probe          = riic_i2c_probe,
 481         .remove         = riic_i2c_remove,
 482         .driver         = {
 483                 .name   = "i2c-riic",
 484                 .of_match_table = riic_i2c_dt_ids,
 485         },
 486 };
 487 
 488 module_platform_driver(riic_i2c_driver);
 489 
 490 MODULE_DESCRIPTION("Renesas RIIC adapter");
 491 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
 492 MODULE_LICENSE("GPL v2");
 493 MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/i2c/busses/i2c-riic.c

DEFINITIONS
