drivers/i2c/busses/i2c-rcar.c

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This source file includes following definitions.
rcar_i2c_write
rcar_i2c_read
rcar_i2c_get_scl
rcar_i2c_set_scl
rcar_i2c_set_sda
rcar_i2c_get_bus_free
rcar_i2c_init
rcar_i2c_bus_barrier
rcar_i2c_clock_calculate
rcar_i2c_prepare_msg
rcar_i2c_next_msg
rcar_i2c_dma_unmap
rcar_i2c_cleanup_dma
rcar_i2c_dma_callback
rcar_i2c_dma
rcar_i2c_irq_send
rcar_i2c_irq_recv
rcar_i2c_slave_irq
rcar_i2c_irq
rcar_i2c_request_dma_chan
rcar_i2c_request_dma
rcar_i2c_release_dma
rcar_i2c_do_reset
rcar_i2c_master_xfer
rcar_reg_slave
rcar_unreg_slave
rcar_i2c_func
rcar_i2c_probe
rcar_i2c_remove
rcar_i2c_suspend
rcar_i2c_resume
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for the Renesas R-Car I2C unit
   4  *
   5  * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
   6  * Copyright (C) 2011-2019 Renesas Electronics Corporation
   7  *
   8  * Copyright (C) 2012-14 Renesas Solutions Corp.
   9  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  10  *
  11  * This file is based on the drivers/i2c/busses/i2c-sh7760.c
  12  * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
  13  */
  14 #include <linux/bitops.h>
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/i2c.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/reset.h>
  29 #include <linux/slab.h>
  30 
  31 /* register offsets */
  32 #define ICSCR   0x00    /* slave ctrl */
  33 #define ICMCR   0x04    /* master ctrl */
  34 #define ICSSR   0x08    /* slave status */
  35 #define ICMSR   0x0C    /* master status */
  36 #define ICSIER  0x10    /* slave irq enable */
  37 #define ICMIER  0x14    /* master irq enable */
  38 #define ICCCR   0x18    /* clock dividers */
  39 #define ICSAR   0x1C    /* slave address */
  40 #define ICMAR   0x20    /* master address */
  41 #define ICRXTX  0x24    /* data port */
  42 #define ICFBSCR 0x38    /* first bit setup cycle (Gen3) */
  43 #define ICDMAER 0x3c    /* DMA enable (Gen3) */
  44 
  45 /* ICSCR */
  46 #define SDBS    (1 << 3)        /* slave data buffer select */
  47 #define SIE     (1 << 2)        /* slave interface enable */
  48 #define GCAE    (1 << 1)        /* general call address enable */
  49 #define FNA     (1 << 0)        /* forced non acknowledgment */
  50 
  51 /* ICMCR */
  52 #define MDBS    (1 << 7)        /* non-fifo mode switch */
  53 #define FSCL    (1 << 6)        /* override SCL pin */
  54 #define FSDA    (1 << 5)        /* override SDA pin */
  55 #define OBPC    (1 << 4)        /* override pins */
  56 #define MIE     (1 << 3)        /* master if enable */
  57 #define TSBE    (1 << 2)
  58 #define FSB     (1 << 1)        /* force stop bit */
  59 #define ESG     (1 << 0)        /* enable start bit gen */
  60 
  61 /* ICSSR (also for ICSIER) */
  62 #define GCAR    (1 << 6)        /* general call received */
  63 #define STM     (1 << 5)        /* slave transmit mode */
  64 #define SSR     (1 << 4)        /* stop received */
  65 #define SDE     (1 << 3)        /* slave data empty */
  66 #define SDT     (1 << 2)        /* slave data transmitted */
  67 #define SDR     (1 << 1)        /* slave data received */
  68 #define SAR     (1 << 0)        /* slave addr received */
  69 
  70 /* ICMSR (also for ICMIE) */
  71 #define MNR     (1 << 6)        /* nack received */
  72 #define MAL     (1 << 5)        /* arbitration lost */
  73 #define MST     (1 << 4)        /* sent a stop */
  74 #define MDE     (1 << 3)
  75 #define MDT     (1 << 2)
  76 #define MDR     (1 << 1)
  77 #define MAT     (1 << 0)        /* slave addr xfer done */
  78 
  79 /* ICDMAER */
  80 #define RSDMAE  (1 << 3)        /* DMA Slave Received Enable */
  81 #define TSDMAE  (1 << 2)        /* DMA Slave Transmitted Enable */
  82 #define RMDMAE  (1 << 1)        /* DMA Master Received Enable */
  83 #define TMDMAE  (1 << 0)        /* DMA Master Transmitted Enable */
  84 
  85 /* ICFBSCR */
  86 #define TCYC17  0x0f            /* 17*Tcyc delay 1st bit between SDA and SCL */
  87 
  88 #define RCAR_MIN_DMA_LEN        8
  89 
  90 #define RCAR_BUS_PHASE_START    (MDBS | MIE | ESG)
  91 #define RCAR_BUS_PHASE_DATA     (MDBS | MIE)
  92 #define RCAR_BUS_MASK_DATA      (~(ESG | FSB) & 0xFF)
  93 #define RCAR_BUS_PHASE_STOP     (MDBS | MIE | FSB)
  94 
  95 #define RCAR_IRQ_SEND   (MNR | MAL | MST | MAT | MDE)
  96 #define RCAR_IRQ_RECV   (MNR | MAL | MST | MAT | MDR)
  97 #define RCAR_IRQ_STOP   (MST)
  98 
  99 #define RCAR_IRQ_ACK_SEND       (~(MAT | MDE) & 0x7F)
 100 #define RCAR_IRQ_ACK_RECV       (~(MAT | MDR) & 0x7F)
 101 
 102 #define ID_LAST_MSG     (1 << 0)
 103 #define ID_FIRST_MSG    (1 << 1)
 104 #define ID_DONE         (1 << 2)
 105 #define ID_ARBLOST      (1 << 3)
 106 #define ID_NACK         (1 << 4)
 107 /* persistent flags */
 108 #define ID_P_REP_AFTER_RD       BIT(29)
 109 #define ID_P_NO_RXDMA           BIT(30) /* HW forbids RXDMA sometimes */
 110 #define ID_P_PM_BLOCKED         BIT(31)
 111 #define ID_P_MASK               GENMASK(31, 29)
 112 
 113 enum rcar_i2c_type {
 114         I2C_RCAR_GEN1,
 115         I2C_RCAR_GEN2,
 116         I2C_RCAR_GEN3,
 117 };
 118 
 119 struct rcar_i2c_priv {
 120         void __iomem *io;
 121         struct i2c_adapter adap;
 122         struct i2c_msg *msg;
 123         int msgs_left;
 124         struct clk *clk;
 125 
 126         wait_queue_head_t wait;
 127 
 128         int pos;
 129         u32 icccr;
 130         u32 flags;
 131         u8 recovery_icmcr;      /* protected by adapter lock */
 132         enum rcar_i2c_type devtype;
 133         struct i2c_client *slave;
 134 
 135         struct resource *res;
 136         struct dma_chan *dma_tx;
 137         struct dma_chan *dma_rx;
 138         struct scatterlist sg;
 139         enum dma_data_direction dma_direction;
 140 
 141         struct reset_control *rstc;
 142         int irq;
 143 };
 144 
 145 #define rcar_i2c_priv_to_dev(p)         ((p)->adap.dev.parent)
 146 #define rcar_i2c_is_recv(p)             ((p)->msg->flags & I2C_M_RD)
 147 
 148 #define LOOP_TIMEOUT    1024
 149 
 150 
 151 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
 152 {
 153         writel(val, priv->io + reg);
 154 }
 155 
 156 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
 157 {
 158         return readl(priv->io + reg);
 159 }
 160 
 161 static int rcar_i2c_get_scl(struct i2c_adapter *adap)
 162 {
 163         struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
 164 
 165         return !!(rcar_i2c_read(priv, ICMCR) & FSCL);
 166 
 167 };
 168 
 169 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
 170 {
 171         struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
 172 
 173         if (val)
 174                 priv->recovery_icmcr |= FSCL;
 175         else
 176                 priv->recovery_icmcr &= ~FSCL;
 177 
 178         rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
 179 };
 180 
 181 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
 182 {
 183         struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
 184 
 185         if (val)
 186                 priv->recovery_icmcr |= FSDA;
 187         else
 188                 priv->recovery_icmcr &= ~FSDA;
 189 
 190         rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
 191 };
 192 
 193 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap)
 194 {
 195         struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
 196 
 197         return !(rcar_i2c_read(priv, ICMCR) & FSDA);
 198 
 199 };
 200 
 201 static struct i2c_bus_recovery_info rcar_i2c_bri = {
 202         .get_scl = rcar_i2c_get_scl,
 203         .set_scl = rcar_i2c_set_scl,
 204         .set_sda = rcar_i2c_set_sda,
 205         .get_bus_free = rcar_i2c_get_bus_free,
 206         .recover_bus = i2c_generic_scl_recovery,
 207 };
 208 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
 209 {
 210         /* reset master mode */
 211         rcar_i2c_write(priv, ICMIER, 0);
 212         rcar_i2c_write(priv, ICMCR, MDBS);
 213         rcar_i2c_write(priv, ICMSR, 0);
 214         /* start clock */
 215         rcar_i2c_write(priv, ICCCR, priv->icccr);
 216 
 217         if (priv->devtype == I2C_RCAR_GEN3)
 218                 rcar_i2c_write(priv, ICFBSCR, TCYC17);
 219 
 220 }
 221 
 222 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
 223 {
 224         int i;
 225 
 226         for (i = 0; i < LOOP_TIMEOUT; i++) {
 227                 /* make sure that bus is not busy */
 228                 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
 229                         return 0;
 230                 udelay(1);
 231         }
 232 
 233         /* Waiting did not help, try to recover */
 234         priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
 235         return i2c_recover_bus(&priv->adap);
 236 }
 237 
 238 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t)
 239 {
 240         u32 scgd, cdf, round, ick, sum, scl, cdf_width;
 241         unsigned long rate;
 242         struct device *dev = rcar_i2c_priv_to_dev(priv);
 243 
 244         /* Fall back to previously used values if not supplied */
 245         t->bus_freq_hz = t->bus_freq_hz ?: 100000;
 246         t->scl_fall_ns = t->scl_fall_ns ?: 35;
 247         t->scl_rise_ns = t->scl_rise_ns ?: 200;
 248         t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50;
 249 
 250         switch (priv->devtype) {
 251         case I2C_RCAR_GEN1:
 252                 cdf_width = 2;
 253                 break;
 254         case I2C_RCAR_GEN2:
 255         case I2C_RCAR_GEN3:
 256                 cdf_width = 3;
 257                 break;
 258         default:
 259                 dev_err(dev, "device type error\n");
 260                 return -EIO;
 261         }
 262 
 263         /*
 264          * calculate SCL clock
 265          * see
 266          *      ICCCR
 267          *
 268          * ick  = clkp / (1 + CDF)
 269          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 270          *
 271          * ick  : I2C internal clock < 20 MHz
 272          * ticf : I2C SCL falling time
 273          * tr   : I2C SCL rising  time
 274          * intd : LSI internal delay
 275          * clkp : peripheral_clk
 276          * F[]  : integer up-valuation
 277          */
 278         rate = clk_get_rate(priv->clk);
 279         cdf = rate / 20000000;
 280         if (cdf >= 1U << cdf_width) {
 281                 dev_err(dev, "Input clock %lu too high\n", rate);
 282                 return -EIO;
 283         }
 284         ick = rate / (cdf + 1);
 285 
 286         /*
 287          * it is impossible to calculate large scale
 288          * number on u32. separate it
 289          *
 290          * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
 291          *  = F[sum * ick / 1000000000]
 292          *  = F[(ick / 1000000) * sum / 1000]
 293          */
 294         sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns;
 295         round = (ick + 500000) / 1000000 * sum;
 296         round = (round + 500) / 1000;
 297 
 298         /*
 299          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 300          *
 301          * Calculation result (= SCL) should be less than
 302          * bus_speed for hardware safety
 303          *
 304          * We could use something along the lines of
 305          *      div = ick / (bus_speed + 1) + 1;
 306          *      scgd = (div - 20 - round + 7) / 8;
 307          *      scl = ick / (20 + (scgd * 8) + round);
 308          * (not fully verified) but that would get pretty involved
 309          */
 310         for (scgd = 0; scgd < 0x40; scgd++) {
 311                 scl = ick / (20 + (scgd * 8) + round);
 312                 if (scl <= t->bus_freq_hz)
 313                         goto scgd_find;
 314         }
 315         dev_err(dev, "it is impossible to calculate best SCL\n");
 316         return -EIO;
 317 
 318 scgd_find:
 319         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
 320                 scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd);
 321 
 322         /* keep icccr value */
 323         priv->icccr = scgd << cdf_width | cdf;
 324 
 325         return 0;
 326 }
 327 
 328 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
 329 {
 330         int read = !!rcar_i2c_is_recv(priv);
 331 
 332         priv->pos = 0;
 333         if (priv->msgs_left == 1)
 334                 priv->flags |= ID_LAST_MSG;
 335 
 336         rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
 337         /*
 338          * We don't have a test case but the HW engineers say that the write order
 339          * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
 340          * it didn't cause a drawback for me, let's rather be safe than sorry.
 341          */
 342         if (priv->flags & ID_FIRST_MSG) {
 343                 rcar_i2c_write(priv, ICMSR, 0);
 344                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
 345         } else {
 346                 if (priv->flags & ID_P_REP_AFTER_RD)
 347                         priv->flags &= ~ID_P_REP_AFTER_RD;
 348                 else
 349                         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
 350                 rcar_i2c_write(priv, ICMSR, 0);
 351         }
 352         rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
 353 }
 354 
 355 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
 356 {
 357         priv->msg++;
 358         priv->msgs_left--;
 359         priv->flags &= ID_P_MASK;
 360         rcar_i2c_prepare_msg(priv);
 361 }
 362 
 363 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
 364 {
 365         struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
 366                 ? priv->dma_rx : priv->dma_tx;
 367 
 368         dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
 369                          sg_dma_len(&priv->sg), priv->dma_direction);
 370 
 371         /* Gen3 can only do one RXDMA per transfer and we just completed it */
 372         if (priv->devtype == I2C_RCAR_GEN3 &&
 373             priv->dma_direction == DMA_FROM_DEVICE)
 374                 priv->flags |= ID_P_NO_RXDMA;
 375 
 376         priv->dma_direction = DMA_NONE;
 377 
 378         /* Disable DMA Master Received/Transmitted, must be last! */
 379         rcar_i2c_write(priv, ICDMAER, 0);
 380 }
 381 
 382 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv)
 383 {
 384         if (priv->dma_direction == DMA_NONE)
 385                 return;
 386         else if (priv->dma_direction == DMA_FROM_DEVICE)
 387                 dmaengine_terminate_all(priv->dma_rx);
 388         else if (priv->dma_direction == DMA_TO_DEVICE)
 389                 dmaengine_terminate_all(priv->dma_tx);
 390 
 391         rcar_i2c_dma_unmap(priv);
 392 }
 393 
 394 static void rcar_i2c_dma_callback(void *data)
 395 {
 396         struct rcar_i2c_priv *priv = data;
 397 
 398         priv->pos += sg_dma_len(&priv->sg);
 399 
 400         rcar_i2c_dma_unmap(priv);
 401 }
 402 
 403 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv)
 404 {
 405         struct device *dev = rcar_i2c_priv_to_dev(priv);
 406         struct i2c_msg *msg = priv->msg;
 407         bool read = msg->flags & I2C_M_RD;
 408         enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 409         struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
 410         struct dma_async_tx_descriptor *txdesc;
 411         dma_addr_t dma_addr;
 412         dma_cookie_t cookie;
 413         unsigned char *buf;
 414         int len;
 415 
 416         /* Do various checks to see if DMA is feasible at all */
 417         if (IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN ||
 418             !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA))
 419                 return false;
 420 
 421         if (read) {
 422                 /*
 423                  * The last two bytes needs to be fetched using PIO in
 424                  * order for the STOP phase to work.
 425                  */
 426                 buf = priv->msg->buf;
 427                 len = priv->msg->len - 2;
 428         } else {
 429                 /*
 430                  * First byte in message was sent using PIO.
 431                  */
 432                 buf = priv->msg->buf + 1;
 433                 len = priv->msg->len - 1;
 434         }
 435 
 436         dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
 437         if (dma_mapping_error(chan->device->dev, dma_addr)) {
 438                 dev_dbg(dev, "dma map failed, using PIO\n");
 439                 return false;
 440         }
 441 
 442         sg_dma_len(&priv->sg) = len;
 443         sg_dma_address(&priv->sg) = dma_addr;
 444 
 445         priv->dma_direction = dir;
 446 
 447         txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
 448                                          read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
 449                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 450         if (!txdesc) {
 451                 dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
 452                 rcar_i2c_cleanup_dma(priv);
 453                 return false;
 454         }
 455 
 456         txdesc->callback = rcar_i2c_dma_callback;
 457         txdesc->callback_param = priv;
 458 
 459         cookie = dmaengine_submit(txdesc);
 460         if (dma_submit_error(cookie)) {
 461                 dev_dbg(dev, "submitting dma failed, using PIO\n");
 462                 rcar_i2c_cleanup_dma(priv);
 463                 return false;
 464         }
 465 
 466         /* Enable DMA Master Received/Transmitted */
 467         if (read)
 468                 rcar_i2c_write(priv, ICDMAER, RMDMAE);
 469         else
 470                 rcar_i2c_write(priv, ICDMAER, TMDMAE);
 471 
 472         dma_async_issue_pending(chan);
 473         return true;
 474 }
 475 
 476 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
 477 {
 478         struct i2c_msg *msg = priv->msg;
 479 
 480         /* FIXME: sometimes, unknown interrupt happened. Do nothing */
 481         if (!(msr & MDE))
 482                 return;
 483 
 484         /* Check if DMA can be enabled and take over */
 485         if (priv->pos == 1 && rcar_i2c_dma(priv))
 486                 return;
 487 
 488         if (priv->pos < msg->len) {
 489                 /*
 490                  * Prepare next data to ICRXTX register.
 491                  * This data will go to _SHIFT_ register.
 492                  *
 493                  *    *
 494                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
 495                  */
 496                 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
 497                 priv->pos++;
 498         } else {
 499                 /*
 500                  * The last data was pushed to ICRXTX on _PREV_ empty irq.
 501                  * It is on _SHIFT_ register, and will sent to I2C bus.
 502                  *
 503                  *                *
 504                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
 505                  */
 506 
 507                 if (priv->flags & ID_LAST_MSG) {
 508                         /*
 509                          * If current msg is the _LAST_ msg,
 510                          * prepare stop condition here.
 511                          * ID_DONE will be set on STOP irq.
 512                          */
 513                         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
 514                 } else {
 515                         rcar_i2c_next_msg(priv);
 516                         return;
 517                 }
 518         }
 519 
 520         rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
 521 }
 522 
 523 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
 524 {
 525         struct i2c_msg *msg = priv->msg;
 526 
 527         /* FIXME: sometimes, unknown interrupt happened. Do nothing */
 528         if (!(msr & MDR))
 529                 return;
 530 
 531         if (msr & MAT) {
 532                 /*
 533                  * Address transfer phase finished, but no data at this point.
 534                  * Try to use DMA to receive data.
 535                  */
 536                 rcar_i2c_dma(priv);
 537         } else if (priv->pos < msg->len) {
 538                 /* get received data */
 539                 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
 540                 priv->pos++;
 541         }
 542 
 543         /* If next received data is the _LAST_, go to new phase. */
 544         if (priv->pos + 1 == msg->len) {
 545                 if (priv->flags & ID_LAST_MSG) {
 546                         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
 547                 } else {
 548                         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
 549                         priv->flags |= ID_P_REP_AFTER_RD;
 550                 }
 551         }
 552 
 553         if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
 554                 rcar_i2c_next_msg(priv);
 555         else
 556                 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
 557 }
 558 
 559 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
 560 {
 561         u32 ssr_raw, ssr_filtered;
 562         u8 value;
 563 
 564         ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
 565         ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
 566 
 567         if (!ssr_filtered)
 568                 return false;
 569 
 570         /* address detected */
 571         if (ssr_filtered & SAR) {
 572                 /* read or write request */
 573                 if (ssr_raw & STM) {
 574                         i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
 575                         rcar_i2c_write(priv, ICRXTX, value);
 576                         rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
 577                 } else {
 578                         i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
 579                         rcar_i2c_read(priv, ICRXTX);    /* dummy read */
 580                         rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
 581                 }
 582 
 583                 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff);
 584         }
 585 
 586         /* master sent stop */
 587         if (ssr_filtered & SSR) {
 588                 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
 589                 rcar_i2c_write(priv, ICSIER, SAR | SSR);
 590                 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
 591         }
 592 
 593         /* master wants to write to us */
 594         if (ssr_filtered & SDR) {
 595                 int ret;
 596 
 597                 value = rcar_i2c_read(priv, ICRXTX);
 598                 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
 599                 /* Send NACK in case of error */
 600                 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
 601                 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
 602         }
 603 
 604         /* master wants to read from us */
 605         if (ssr_filtered & SDE) {
 606                 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
 607                 rcar_i2c_write(priv, ICRXTX, value);
 608                 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
 609         }
 610 
 611         return true;
 612 }
 613 
 614 /*
 615  * This driver has a lock-free design because there are IP cores (at least
 616  * R-Car Gen2) which have an inherent race condition in their hardware design.
 617  * There, we need to clear RCAR_BUS_MASK_DATA bits as soon as possible after
 618  * the interrupt was generated, otherwise an unwanted repeated message gets
 619  * generated. It turned out that taking a spinlock at the beginning of the ISR
 620  * was already causing repeated messages. Thus, this driver was converted to
 621  * the now lockless behaviour. Please keep this in mind when hacking the driver.
 622  */
 623 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
 624 {
 625         struct rcar_i2c_priv *priv = ptr;
 626         u32 msr, val;
 627 
 628         /* Clear START or STOP immediately, except for REPSTART after read */
 629         if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) {
 630                 val = rcar_i2c_read(priv, ICMCR);
 631                 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
 632         }
 633 
 634         msr = rcar_i2c_read(priv, ICMSR);
 635 
 636         /* Only handle interrupts that are currently enabled */
 637         msr &= rcar_i2c_read(priv, ICMIER);
 638         if (!msr) {
 639                 if (rcar_i2c_slave_irq(priv))
 640                         return IRQ_HANDLED;
 641 
 642                 return IRQ_NONE;
 643         }
 644 
 645         /* Arbitration lost */
 646         if (msr & MAL) {
 647                 priv->flags |= ID_DONE | ID_ARBLOST;
 648                 goto out;
 649         }
 650 
 651         /* Nack */
 652         if (msr & MNR) {
 653                 /* HW automatically sends STOP after received NACK */
 654                 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
 655                 priv->flags |= ID_NACK;
 656                 goto out;
 657         }
 658 
 659         /* Stop */
 660         if (msr & MST) {
 661                 priv->msgs_left--; /* The last message also made it */
 662                 priv->flags |= ID_DONE;
 663                 goto out;
 664         }
 665 
 666         if (rcar_i2c_is_recv(priv))
 667                 rcar_i2c_irq_recv(priv, msr);
 668         else
 669                 rcar_i2c_irq_send(priv, msr);
 670 
 671 out:
 672         if (priv->flags & ID_DONE) {
 673                 rcar_i2c_write(priv, ICMIER, 0);
 674                 rcar_i2c_write(priv, ICMSR, 0);
 675                 wake_up(&priv->wait);
 676         }
 677 
 678         return IRQ_HANDLED;
 679 }
 680 
 681 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
 682                                         enum dma_transfer_direction dir,
 683                                         dma_addr_t port_addr)
 684 {
 685         struct dma_chan *chan;
 686         struct dma_slave_config cfg;
 687         char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
 688         int ret;
 689 
 690         chan = dma_request_chan(dev, chan_name);
 691         if (IS_ERR(chan)) {
 692                 dev_dbg(dev, "request_channel failed for %s (%ld)\n",
 693                         chan_name, PTR_ERR(chan));
 694                 return chan;
 695         }
 696 
 697         memset(&cfg, 0, sizeof(cfg));
 698         cfg.direction = dir;
 699         if (dir == DMA_MEM_TO_DEV) {
 700                 cfg.dst_addr = port_addr;
 701                 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 702         } else {
 703                 cfg.src_addr = port_addr;
 704                 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 705         }
 706 
 707         ret = dmaengine_slave_config(chan, &cfg);
 708         if (ret) {
 709                 dev_dbg(dev, "slave_config failed for %s (%d)\n",
 710                         chan_name, ret);
 711                 dma_release_channel(chan);
 712                 return ERR_PTR(ret);
 713         }
 714 
 715         dev_dbg(dev, "got DMA channel for %s\n", chan_name);
 716         return chan;
 717 }
 718 
 719 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
 720                                  struct i2c_msg *msg)
 721 {
 722         struct device *dev = rcar_i2c_priv_to_dev(priv);
 723         bool read;
 724         struct dma_chan *chan;
 725         enum dma_transfer_direction dir;
 726 
 727         read = msg->flags & I2C_M_RD;
 728 
 729         chan = read ? priv->dma_rx : priv->dma_tx;
 730         if (PTR_ERR(chan) != -EPROBE_DEFER)
 731                 return;
 732 
 733         dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
 734         chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
 735 
 736         if (read)
 737                 priv->dma_rx = chan;
 738         else
 739                 priv->dma_tx = chan;
 740 }
 741 
 742 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
 743 {
 744         if (!IS_ERR(priv->dma_tx)) {
 745                 dma_release_channel(priv->dma_tx);
 746                 priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
 747         }
 748 
 749         if (!IS_ERR(priv->dma_rx)) {
 750                 dma_release_channel(priv->dma_rx);
 751                 priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
 752         }
 753 }
 754 
 755 /* I2C is a special case, we need to poll the status of a reset */
 756 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
 757 {
 758         int i, ret;
 759 
 760         ret = reset_control_reset(priv->rstc);
 761         if (ret)
 762                 return ret;
 763 
 764         for (i = 0; i < LOOP_TIMEOUT; i++) {
 765                 ret = reset_control_status(priv->rstc);
 766                 if (ret == 0)
 767                         return 0;
 768                 udelay(1);
 769         }
 770 
 771         return -ETIMEDOUT;
 772 }
 773 
 774 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
 775                                 struct i2c_msg *msgs,
 776                                 int num)
 777 {
 778         struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
 779         struct device *dev = rcar_i2c_priv_to_dev(priv);
 780         int i, ret;
 781         long time_left;
 782 
 783         pm_runtime_get_sync(dev);
 784 
 785         /* Check bus state before init otherwise bus busy info will be lost */
 786         ret = rcar_i2c_bus_barrier(priv);
 787         if (ret < 0)
 788                 goto out;
 789 
 790         /* Gen3 needs a reset before allowing RXDMA once */
 791         if (priv->devtype == I2C_RCAR_GEN3) {
 792                 priv->flags |= ID_P_NO_RXDMA;
 793                 if (!IS_ERR(priv->rstc)) {
 794                         ret = rcar_i2c_do_reset(priv);
 795                         if (ret == 0)
 796                                 priv->flags &= ~ID_P_NO_RXDMA;
 797                 }
 798         }
 799 
 800         rcar_i2c_init(priv);
 801 
 802         for (i = 0; i < num; i++)
 803                 rcar_i2c_request_dma(priv, msgs + i);
 804 
 805         /* init first message */
 806         priv->msg = msgs;
 807         priv->msgs_left = num;
 808         priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG;
 809         rcar_i2c_prepare_msg(priv);
 810 
 811         time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
 812                                      num * adap->timeout);
 813 
 814         /* cleanup DMA if it couldn't complete properly due to an error */
 815         if (priv->dma_direction != DMA_NONE)
 816                 rcar_i2c_cleanup_dma(priv);
 817 
 818         if (!time_left) {
 819                 rcar_i2c_init(priv);
 820                 ret = -ETIMEDOUT;
 821         } else if (priv->flags & ID_NACK) {
 822                 ret = -ENXIO;
 823         } else if (priv->flags & ID_ARBLOST) {
 824                 ret = -EAGAIN;
 825         } else {
 826                 ret = num - priv->msgs_left; /* The number of transfer */
 827         }
 828 out:
 829         pm_runtime_put(dev);
 830 
 831         if (ret < 0 && ret != -ENXIO)
 832                 dev_err(dev, "error %d : %x\n", ret, priv->flags);
 833 
 834         return ret;
 835 }
 836 
 837 static int rcar_reg_slave(struct i2c_client *slave)
 838 {
 839         struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
 840 
 841         if (priv->slave)
 842                 return -EBUSY;
 843 
 844         if (slave->flags & I2C_CLIENT_TEN)
 845                 return -EAFNOSUPPORT;
 846 
 847         /* Keep device active for slave address detection logic */
 848         pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
 849 
 850         priv->slave = slave;
 851         rcar_i2c_write(priv, ICSAR, slave->addr);
 852         rcar_i2c_write(priv, ICSSR, 0);
 853         rcar_i2c_write(priv, ICSIER, SAR | SSR);
 854         rcar_i2c_write(priv, ICSCR, SIE | SDBS);
 855 
 856         return 0;
 857 }
 858 
 859 static int rcar_unreg_slave(struct i2c_client *slave)
 860 {
 861         struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
 862 
 863         WARN_ON(!priv->slave);
 864 
 865         /* disable irqs and ensure none is running before clearing ptr */
 866         rcar_i2c_write(priv, ICSIER, 0);
 867         rcar_i2c_write(priv, ICSCR, 0);
 868 
 869         synchronize_irq(priv->irq);
 870         priv->slave = NULL;
 871 
 872         pm_runtime_put(rcar_i2c_priv_to_dev(priv));
 873 
 874         return 0;
 875 }
 876 
 877 static u32 rcar_i2c_func(struct i2c_adapter *adap)
 878 {
 879         /*
 880          * This HW can't do:
 881          * I2C_SMBUS_QUICK (setting FSB during START didn't work)
 882          * I2C_M_NOSTART (automatically sends address after START)
 883          * I2C_M_IGNORE_NAK (automatically sends STOP after NAK)
 884          */
 885         return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
 886                 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 887 }
 888 
 889 static const struct i2c_algorithm rcar_i2c_algo = {
 890         .master_xfer    = rcar_i2c_master_xfer,
 891         .functionality  = rcar_i2c_func,
 892         .reg_slave      = rcar_reg_slave,
 893         .unreg_slave    = rcar_unreg_slave,
 894 };
 895 
 896 static const struct i2c_adapter_quirks rcar_i2c_quirks = {
 897         .flags = I2C_AQ_NO_ZERO_LEN,
 898 };
 899 
 900 static const struct of_device_id rcar_i2c_dt_ids[] = {
 901         { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
 902         { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
 903         { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
 904         { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
 905         { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
 906         { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
 907         { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
 908         { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
 909         { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
 910         { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },    /* Deprecated */
 911         { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
 912         { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
 913         { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
 914         {},
 915 };
 916 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
 917 
 918 static int rcar_i2c_probe(struct platform_device *pdev)
 919 {
 920         struct rcar_i2c_priv *priv;
 921         struct i2c_adapter *adap;
 922         struct device *dev = &pdev->dev;
 923         struct i2c_timings i2c_t;
 924         int ret;
 925 
 926         /* Otherwise logic will break because some bytes must always use PIO */
 927         BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length");
 928 
 929         priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
 930         if (!priv)
 931                 return -ENOMEM;
 932 
 933         priv->clk = devm_clk_get(dev, NULL);
 934         if (IS_ERR(priv->clk)) {
 935                 dev_err(dev, "cannot get clock\n");
 936                 return PTR_ERR(priv->clk);
 937         }
 938 
 939         priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 940 
 941         priv->io = devm_ioremap_resource(dev, priv->res);
 942         if (IS_ERR(priv->io))
 943                 return PTR_ERR(priv->io);
 944 
 945         priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
 946         init_waitqueue_head(&priv->wait);
 947 
 948         adap = &priv->adap;
 949         adap->nr = pdev->id;
 950         adap->algo = &rcar_i2c_algo;
 951         adap->class = I2C_CLASS_DEPRECATED;
 952         adap->retries = 3;
 953         adap->dev.parent = dev;
 954         adap->dev.of_node = dev->of_node;
 955         adap->bus_recovery_info = &rcar_i2c_bri;
 956         adap->quirks = &rcar_i2c_quirks;
 957         i2c_set_adapdata(adap, priv);
 958         strlcpy(adap->name, pdev->name, sizeof(adap->name));
 959 
 960         i2c_parse_fw_timings(dev, &i2c_t, false);
 961 
 962         /* Init DMA */
 963         sg_init_table(&priv->sg, 1);
 964         priv->dma_direction = DMA_NONE;
 965         priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
 966 
 967         /* Activate device for clock calculation */
 968         pm_runtime_enable(dev);
 969         pm_runtime_get_sync(dev);
 970         ret = rcar_i2c_clock_calculate(priv, &i2c_t);
 971         if (ret < 0)
 972                 goto out_pm_put;
 973 
 974         if (priv->devtype == I2C_RCAR_GEN3) {
 975                 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 976                 if (!IS_ERR(priv->rstc)) {
 977                         ret = reset_control_status(priv->rstc);
 978                         if (ret < 0)
 979                                 priv->rstc = ERR_PTR(-ENOTSUPP);
 980                 }
 981         }
 982 
 983         /* Stay always active when multi-master to keep arbitration working */
 984         if (of_property_read_bool(dev->of_node, "multi-master"))
 985                 priv->flags |= ID_P_PM_BLOCKED;
 986         else
 987                 pm_runtime_put(dev);
 988 
 989 
 990         priv->irq = platform_get_irq(pdev, 0);
 991         ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, dev_name(dev), priv);
 992         if (ret < 0) {
 993                 dev_err(dev, "cannot get irq %d\n", priv->irq);
 994                 goto out_pm_disable;
 995         }
 996 
 997         platform_set_drvdata(pdev, priv);
 998 
 999         ret = i2c_add_numbered_adapter(adap);
1000         if (ret < 0)
1001                 goto out_pm_disable;
1002 
1003         dev_info(dev, "probed\n");
1004 
1005         return 0;
1006 
1007  out_pm_put:
1008         pm_runtime_put(dev);
1009  out_pm_disable:
1010         pm_runtime_disable(dev);
1011         return ret;
1012 }
1013 
1014 static int rcar_i2c_remove(struct platform_device *pdev)
1015 {
1016         struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
1017         struct device *dev = &pdev->dev;
1018 
1019         i2c_del_adapter(&priv->adap);
1020         rcar_i2c_release_dma(priv);
1021         if (priv->flags & ID_P_PM_BLOCKED)
1022                 pm_runtime_put(dev);
1023         pm_runtime_disable(dev);
1024 
1025         return 0;
1026 }
1027 
1028 #ifdef CONFIG_PM_SLEEP
1029 static int rcar_i2c_suspend(struct device *dev)
1030 {
1031         struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1032 
1033         i2c_mark_adapter_suspended(&priv->adap);
1034         return 0;
1035 }
1036 
1037 static int rcar_i2c_resume(struct device *dev)
1038 {
1039         struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1040 
1041         i2c_mark_adapter_resumed(&priv->adap);
1042         return 0;
1043 }
1044 
1045 static const struct dev_pm_ops rcar_i2c_pm_ops = {
1046         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume)
1047 };
1048 
1049 #define DEV_PM_OPS (&rcar_i2c_pm_ops)
1050 #else
1051 #define DEV_PM_OPS NULL
1052 #endif /* CONFIG_PM_SLEEP */
1053 
1054 static struct platform_driver rcar_i2c_driver = {
1055         .driver = {
1056                 .name   = "i2c-rcar",
1057                 .of_match_table = rcar_i2c_dt_ids,
1058                 .pm     = DEV_PM_OPS,
1059         },
1060         .probe          = rcar_i2c_probe,
1061         .remove         = rcar_i2c_remove,
1062 };
1063 
1064 module_platform_driver(rcar_i2c_driver);
1065 
1066 MODULE_LICENSE("GPL v2");
1067 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
1068 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/i2c/busses/i2c-rcar.c

DEFINITIONS
