This source file includes following definitions.
- gpu_enable_i2c_bus
- gpu_i2c_check_status
- gpu_i2c_read
- gpu_i2c_start
- gpu_i2c_stop
- gpu_i2c_write
- gpu_i2c_master_xfer
- gpu_i2c_functionality
- gpu_populate_client
- gpu_i2c_probe
- gpu_i2c_remove
- gpu_i2c_suspend
- gpu_i2c_resume
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8 #include <linux/delay.h>
9 #include <linux/i2c.h>
10 #include <linux/interrupt.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm.h>
16 #include <linux/pm_runtime.h>
17
18 #include <asm/unaligned.h>
19
20
21 #define I2C_MST_CNTL 0x00
22 #define I2C_MST_CNTL_GEN_START BIT(0)
23 #define I2C_MST_CNTL_GEN_STOP BIT(1)
24 #define I2C_MST_CNTL_CMD_READ (1 << 2)
25 #define I2C_MST_CNTL_CMD_WRITE (2 << 2)
26 #define I2C_MST_CNTL_BURST_SIZE_SHIFT 6
27 #define I2C_MST_CNTL_GEN_NACK BIT(28)
28 #define I2C_MST_CNTL_STATUS GENMASK(30, 29)
29 #define I2C_MST_CNTL_STATUS_OKAY (0 << 29)
30 #define I2C_MST_CNTL_STATUS_NO_ACK (1 << 29)
31 #define I2C_MST_CNTL_STATUS_TIMEOUT (2 << 29)
32 #define I2C_MST_CNTL_STATUS_BUS_BUSY (3 << 29)
33 #define I2C_MST_CNTL_CYCLE_TRIGGER BIT(31)
34
35 #define I2C_MST_ADDR 0x04
36
37 #define I2C_MST_I2C0_TIMING 0x08
38 #define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ 0x10e
39 #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT 16
40 #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX 255
41 #define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK BIT(24)
42
43 #define I2C_MST_DATA 0x0c
44
45 #define I2C_MST_HYBRID_PADCTL 0x20
46 #define I2C_MST_HYBRID_PADCTL_MODE_I2C BIT(0)
47 #define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV BIT(14)
48 #define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV BIT(15)
49
50 struct gpu_i2c_dev {
51 struct device *dev;
52 void __iomem *regs;
53 struct i2c_adapter adapter;
54 struct i2c_board_info *gpu_ccgx_ucsi;
55 struct i2c_client *ccgx_client;
56 };
57
58 static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd)
59 {
60 u32 val;
61
62
63 val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL);
64 val |= I2C_MST_HYBRID_PADCTL_MODE_I2C |
65 I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
66 I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV;
67 writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL);
68
69
70 val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ;
71 val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX
72 << I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT);
73 val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK;
74 writel(val, i2cd->regs + I2C_MST_I2C0_TIMING);
75 }
76
77 static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd)
78 {
79 u32 val;
80 int ret;
81
82 ret = readl_poll_timeout(i2cd->regs + I2C_MST_CNTL, val,
83 !(val & I2C_MST_CNTL_CYCLE_TRIGGER) ||
84 (val & I2C_MST_CNTL_STATUS) != I2C_MST_CNTL_STATUS_BUS_BUSY,
85 500, 1000 * USEC_PER_MSEC);
86
87 if (ret) {
88 dev_err(i2cd->dev, "i2c timeout error %x\n", val);
89 return -ETIMEDOUT;
90 }
91
92 val = readl(i2cd->regs + I2C_MST_CNTL);
93 switch (val & I2C_MST_CNTL_STATUS) {
94 case I2C_MST_CNTL_STATUS_OKAY:
95 return 0;
96 case I2C_MST_CNTL_STATUS_NO_ACK:
97 return -ENXIO;
98 case I2C_MST_CNTL_STATUS_TIMEOUT:
99 return -ETIMEDOUT;
100 default:
101 return 0;
102 }
103 }
104
105 static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len)
106 {
107 int status;
108 u32 val;
109
110 val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ |
111 (len << I2C_MST_CNTL_BURST_SIZE_SHIFT) |
112 I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK;
113 writel(val, i2cd->regs + I2C_MST_CNTL);
114
115 status = gpu_i2c_check_status(i2cd);
116 if (status < 0)
117 return status;
118
119 val = readl(i2cd->regs + I2C_MST_DATA);
120 switch (len) {
121 case 1:
122 data[0] = val;
123 break;
124 case 2:
125 put_unaligned_be16(val, data);
126 break;
127 case 3:
128 put_unaligned_be16(val >> 8, data);
129 data[2] = val;
130 break;
131 case 4:
132 put_unaligned_be32(val, data);
133 break;
134 default:
135 break;
136 }
137 return status;
138 }
139
140 static int gpu_i2c_start(struct gpu_i2c_dev *i2cd)
141 {
142 writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL);
143 return gpu_i2c_check_status(i2cd);
144 }
145
146 static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd)
147 {
148 writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL);
149 return gpu_i2c_check_status(i2cd);
150 }
151
152 static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data)
153 {
154 u32 val;
155
156 writel(data, i2cd->regs + I2C_MST_DATA);
157
158 val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT);
159 writel(val, i2cd->regs + I2C_MST_CNTL);
160
161 return gpu_i2c_check_status(i2cd);
162 }
163
164 static int gpu_i2c_master_xfer(struct i2c_adapter *adap,
165 struct i2c_msg *msgs, int num)
166 {
167 struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap);
168 int status, status2;
169 bool send_stop = true;
170 int i, j;
171
172
173
174
175
176 pm_runtime_get_sync(i2cd->dev);
177 for (i = 0; i < num; i++) {
178 if (msgs[i].flags & I2C_M_RD) {
179
180 writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR);
181
182 status = gpu_i2c_read(i2cd, msgs[i].buf, msgs[i].len);
183 if (status < 0)
184 goto exit;
185 } else {
186 u8 addr = i2c_8bit_addr_from_msg(msgs + i);
187
188 status = gpu_i2c_start(i2cd);
189 if (status < 0) {
190 if (i == 0)
191 send_stop = false;
192 goto exit;
193 }
194
195 status = gpu_i2c_write(i2cd, addr);
196 if (status < 0)
197 goto exit;
198
199 for (j = 0; j < msgs[i].len; j++) {
200 status = gpu_i2c_write(i2cd, msgs[i].buf[j]);
201 if (status < 0)
202 goto exit;
203 }
204 }
205 }
206 send_stop = false;
207 status = gpu_i2c_stop(i2cd);
208 if (status < 0)
209 goto exit;
210
211 status = i;
212 exit:
213 if (send_stop) {
214 status2 = gpu_i2c_stop(i2cd);
215 if (status2 < 0)
216 dev_err(i2cd->dev, "i2c stop failed %d\n", status2);
217 }
218 pm_runtime_mark_last_busy(i2cd->dev);
219 pm_runtime_put_autosuspend(i2cd->dev);
220 return status;
221 }
222
223 static const struct i2c_adapter_quirks gpu_i2c_quirks = {
224 .max_read_len = 4,
225 .max_comb_2nd_msg_len = 4,
226 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
227 };
228
229 static u32 gpu_i2c_functionality(struct i2c_adapter *adap)
230 {
231 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
232 }
233
234 static const struct i2c_algorithm gpu_i2c_algorithm = {
235 .master_xfer = gpu_i2c_master_xfer,
236 .functionality = gpu_i2c_functionality,
237 };
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251
252 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
253 static const struct pci_device_id gpu_i2c_ids[] = {
254 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
255 PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00},
256 { }
257 };
258 MODULE_DEVICE_TABLE(pci, gpu_i2c_ids);
259
260 static const struct property_entry ccgx_props[] = {
261
262 PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'),
263 { }
264 };
265
266 static int gpu_populate_client(struct gpu_i2c_dev *i2cd, int irq)
267 {
268 i2cd->gpu_ccgx_ucsi = devm_kzalloc(i2cd->dev,
269 sizeof(*i2cd->gpu_ccgx_ucsi),
270 GFP_KERNEL);
271 if (!i2cd->gpu_ccgx_ucsi)
272 return -ENOMEM;
273
274 strlcpy(i2cd->gpu_ccgx_ucsi->type, "ccgx-ucsi",
275 sizeof(i2cd->gpu_ccgx_ucsi->type));
276 i2cd->gpu_ccgx_ucsi->addr = 0x8;
277 i2cd->gpu_ccgx_ucsi->irq = irq;
278 i2cd->gpu_ccgx_ucsi->properties = ccgx_props;
279 i2cd->ccgx_client = i2c_new_device(&i2cd->adapter, i2cd->gpu_ccgx_ucsi);
280 if (!i2cd->ccgx_client)
281 return -ENODEV;
282
283 return 0;
284 }
285
286 static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id)
287 {
288 struct gpu_i2c_dev *i2cd;
289 int status;
290
291 i2cd = devm_kzalloc(&pdev->dev, sizeof(*i2cd), GFP_KERNEL);
292 if (!i2cd)
293 return -ENOMEM;
294
295 i2cd->dev = &pdev->dev;
296 dev_set_drvdata(&pdev->dev, i2cd);
297
298 status = pcim_enable_device(pdev);
299 if (status < 0) {
300 dev_err(&pdev->dev, "pcim_enable_device failed %d\n", status);
301 return status;
302 }
303
304 pci_set_master(pdev);
305
306 i2cd->regs = pcim_iomap(pdev, 0, 0);
307 if (!i2cd->regs) {
308 dev_err(&pdev->dev, "pcim_iomap failed\n");
309 return -ENOMEM;
310 }
311
312 status = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
313 if (status < 0) {
314 dev_err(&pdev->dev, "pci_alloc_irq_vectors err %d\n", status);
315 return status;
316 }
317
318 gpu_enable_i2c_bus(i2cd);
319
320 i2c_set_adapdata(&i2cd->adapter, i2cd);
321 i2cd->adapter.owner = THIS_MODULE;
322 strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
323 sizeof(i2cd->adapter.name));
324 i2cd->adapter.algo = &gpu_i2c_algorithm;
325 i2cd->adapter.quirks = &gpu_i2c_quirks;
326 i2cd->adapter.dev.parent = &pdev->dev;
327 status = i2c_add_adapter(&i2cd->adapter);
328 if (status < 0)
329 goto free_irq_vectors;
330
331 status = gpu_populate_client(i2cd, pdev->irq);
332 if (status < 0) {
333 dev_err(&pdev->dev, "gpu_populate_client failed %d\n", status);
334 goto del_adapter;
335 }
336
337 pm_runtime_set_autosuspend_delay(&pdev->dev, 3000);
338 pm_runtime_use_autosuspend(&pdev->dev);
339 pm_runtime_put_autosuspend(&pdev->dev);
340 pm_runtime_allow(&pdev->dev);
341
342 return 0;
343
344 del_adapter:
345 i2c_del_adapter(&i2cd->adapter);
346 free_irq_vectors:
347 pci_free_irq_vectors(pdev);
348 return status;
349 }
350
351 static void gpu_i2c_remove(struct pci_dev *pdev)
352 {
353 struct gpu_i2c_dev *i2cd = dev_get_drvdata(&pdev->dev);
354
355 pm_runtime_get_noresume(i2cd->dev);
356 i2c_del_adapter(&i2cd->adapter);
357 pci_free_irq_vectors(pdev);
358 }
359
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363
364
365 static __maybe_unused int gpu_i2c_suspend(struct device *dev)
366 {
367 return 0;
368 }
369
370 static __maybe_unused int gpu_i2c_resume(struct device *dev)
371 {
372 struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev);
373
374 gpu_enable_i2c_bus(i2cd);
375
376
377
378
379
380
381 pm_request_resume(&i2cd->ccgx_client->dev);
382 return 0;
383 }
384
385 static UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, gpu_i2c_suspend, gpu_i2c_resume,
386 NULL);
387
388 static struct pci_driver gpu_i2c_driver = {
389 .name = "nvidia-gpu",
390 .id_table = gpu_i2c_ids,
391 .probe = gpu_i2c_probe,
392 .remove = gpu_i2c_remove,
393 .driver = {
394 .pm = &gpu_i2c_driver_pm,
395 },
396 };
397
398 module_pci_driver(gpu_i2c_driver);
399
400 MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
401 MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver");
402 MODULE_LICENSE("GPL v2");