root/drivers/i2c/busses/i2c-designware-master.c

DEFINITIONS

1. i2c_dw_configure_fifo_master
2. i2c_dw_set_timings_master
3. i2c_dw_init_master
4. i2c_dw_xfer_init
5. i2c_dw_xfer_msg
6. i2c_dw_recv_len
7. i2c_dw_read
8. i2c_dw_xfer
9. i2c_dw_read_clear_intrbits
10. i2c_dw_irq_handler_master
11. i2c_dw_isr
12. i2c_dw_prepare_recovery
13. i2c_dw_unprepare_recovery
14. i2c_dw_init_recovery_info
15. i2c_dw_probe

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Synopsys DesignWare I2C adapter driver (master only).
   4  *
   5  * Based on the TI DAVINCI I2C adapter driver.
   6  *
   7  * Copyright (C) 2006 Texas Instruments.
   8  * Copyright (C) 2007 MontaVista Software Inc.
   9  * Copyright (C) 2009 Provigent Ltd.
  10  */
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/export.h>
  15 #include <linux/gpio/consumer.h>
  16 #include <linux/i2c.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/reset.h>
  22 
  23 #include "i2c-designware-core.h"
  24 
  25 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
  26 {
  27         /* Configure Tx/Rx FIFO threshold levels */
  28         dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
  29         dw_writel(dev, 0, DW_IC_RX_TL);
  30 
  31         /* Configure the I2C master */
  32         dw_writel(dev, dev->master_cfg, DW_IC_CON);
  33 }
  34 
  35 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
  36 {
  37         const char *mode_str, *fp_str = "";
  38         u32 comp_param1;
  39         u32 sda_falling_time, scl_falling_time;
  40         struct i2c_timings *t = &dev->timings;
  41         u32 ic_clk;
  42         int ret;
  43 
  44         ret = i2c_dw_acquire_lock(dev);
  45         if (ret)
  46                 return ret;
  47         comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
  48         i2c_dw_release_lock(dev);
  49 
  50         /* Set standard and fast speed dividers for high/low periods */
  51         sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
  52         scl_falling_time = t->scl_fall_ns ?: 300; /* ns */
  53 
  54         /* Calculate SCL timing parameters for standard mode if not set */
  55         if (!dev->ss_hcnt || !dev->ss_lcnt) {
  56                 ic_clk = i2c_dw_clk_rate(dev);
  57                 dev->ss_hcnt =
  58                         i2c_dw_scl_hcnt(ic_clk,
  59                                         4000,   /* tHD;STA = tHIGH = 4.0 us */
  60                                         sda_falling_time,
  61                                         0,      /* 0: DW default, 1: Ideal */
  62                                         0);     /* No offset */
  63                 dev->ss_lcnt =
  64                         i2c_dw_scl_lcnt(ic_clk,
  65                                         4700,   /* tLOW = 4.7 us */
  66                                         scl_falling_time,
  67                                         0);     /* No offset */
  68         }
  69         dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
  70                 dev->ss_hcnt, dev->ss_lcnt);
  71 
  72         /*
  73          * Set SCL timing parameters for fast mode or fast mode plus. Only
  74          * difference is the timing parameter values since the registers are
  75          * the same.
  76          */
  77         if (t->bus_freq_hz == 1000000) {
  78                 /*
  79                  * Check are fast mode plus parameters available and use
  80                  * fast mode if not.
  81                  */
  82                 if (dev->fp_hcnt && dev->fp_lcnt) {
  83                         dev->fs_hcnt = dev->fp_hcnt;
  84                         dev->fs_lcnt = dev->fp_lcnt;
  85                         fp_str = " Plus";
  86                 }
  87         }
  88         /*
  89          * Calculate SCL timing parameters for fast mode if not set. They are
  90          * needed also in high speed mode.
  91          */
  92         if (!dev->fs_hcnt || !dev->fs_lcnt) {
  93                 ic_clk = i2c_dw_clk_rate(dev);
  94                 dev->fs_hcnt =
  95                         i2c_dw_scl_hcnt(ic_clk,
  96                                         600,    /* tHD;STA = tHIGH = 0.6 us */
  97                                         sda_falling_time,
  98                                         0,      /* 0: DW default, 1: Ideal */
  99                                         0);     /* No offset */
 100                 dev->fs_lcnt =
 101                         i2c_dw_scl_lcnt(ic_clk,
 102                                         1300,   /* tLOW = 1.3 us */
 103                                         scl_falling_time,
 104                                         0);     /* No offset */
 105         }
 106         dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
 107                 fp_str, dev->fs_hcnt, dev->fs_lcnt);
 108 
 109         /* Check is high speed possible and fall back to fast mode if not */
 110         if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
 111                 DW_IC_CON_SPEED_HIGH) {
 112                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 113                         != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
 114                         dev_err(dev->dev, "High Speed not supported!\n");
 115                         dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
 116                         dev->master_cfg |= DW_IC_CON_SPEED_FAST;
 117                         dev->hs_hcnt = 0;
 118                         dev->hs_lcnt = 0;
 119                 } else if (dev->hs_hcnt && dev->hs_lcnt) {
 120                         dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
 121                                 dev->hs_hcnt, dev->hs_lcnt);
 122                 }
 123         }
 124 
 125         ret = i2c_dw_set_sda_hold(dev);
 126         if (ret)
 127                 goto out;
 128 
 129         switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) {
 130         case DW_IC_CON_SPEED_STD:
 131                 mode_str = "Standard Mode";
 132                 break;
 133         case DW_IC_CON_SPEED_HIGH:
 134                 mode_str = "High Speed Mode";
 135                 break;
 136         default:
 137                 mode_str = "Fast Mode";
 138         }
 139         dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str);
 140 
 141 out:
 142         return ret;
 143 }
 144 
 145 /**
 146  * i2c_dw_init() - Initialize the designware I2C master hardware
 147  * @dev: device private data
 148  *
 149  * This functions configures and enables the I2C master.
 150  * This function is called during I2C init function, and in case of timeout at
 151  * run time.
 152  */
 153 static int i2c_dw_init_master(struct dw_i2c_dev *dev)
 154 {
 155         int ret;
 156 
 157         ret = i2c_dw_acquire_lock(dev);
 158         if (ret)
 159                 return ret;
 160 
 161         /* Disable the adapter */
 162         __i2c_dw_disable(dev);
 163 
 164         /* Write standard speed timing parameters */
 165         dw_writel(dev, dev->ss_hcnt, DW_IC_SS_SCL_HCNT);
 166         dw_writel(dev, dev->ss_lcnt, DW_IC_SS_SCL_LCNT);
 167 
 168         /* Write fast mode/fast mode plus timing parameters */
 169         dw_writel(dev, dev->fs_hcnt, DW_IC_FS_SCL_HCNT);
 170         dw_writel(dev, dev->fs_lcnt, DW_IC_FS_SCL_LCNT);
 171 
 172         /* Write high speed timing parameters if supported */
 173         if (dev->hs_hcnt && dev->hs_lcnt) {
 174                 dw_writel(dev, dev->hs_hcnt, DW_IC_HS_SCL_HCNT);
 175                 dw_writel(dev, dev->hs_lcnt, DW_IC_HS_SCL_LCNT);
 176         }
 177 
 178         /* Write SDA hold time if supported */
 179         if (dev->sda_hold_time)
 180                 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
 181 
 182         i2c_dw_configure_fifo_master(dev);
 183         i2c_dw_release_lock(dev);
 184 
 185         return 0;
 186 }
 187 
 188 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 189 {
 190         struct i2c_msg *msgs = dev->msgs;
 191         u32 ic_con, ic_tar = 0;
 192 
 193         /* Disable the adapter */
 194         __i2c_dw_disable(dev);
 195 
 196         /* If the slave address is ten bit address, enable 10BITADDR */
 197         ic_con = dw_readl(dev, DW_IC_CON);
 198         if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
 199                 ic_con |= DW_IC_CON_10BITADDR_MASTER;
 200                 /*
 201                  * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
 202                  * mode has to be enabled via bit 12 of IC_TAR register.
 203                  * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
 204                  * detected from registers.
 205                  */
 206                 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
 207         } else {
 208                 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
 209         }
 210 
 211         dw_writel(dev, ic_con, DW_IC_CON);
 212 
 213         /*
 214          * Set the slave (target) address and enable 10-bit addressing mode
 215          * if applicable.
 216          */
 217         dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
 218 
 219         /* Enforce disabled interrupts (due to HW issues) */
 220         i2c_dw_disable_int(dev);
 221 
 222         /* Enable the adapter */
 223         __i2c_dw_enable(dev);
 224 
 225         /* Dummy read to avoid the register getting stuck on Bay Trail */
 226         dw_readl(dev, DW_IC_ENABLE_STATUS);
 227 
 228         /* Clear and enable interrupts */
 229         dw_readl(dev, DW_IC_CLR_INTR);
 230         dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK);
 231 }
 232 
 233 /*
 234  * Initiate (and continue) low level master read/write transaction.
 235  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 236  * messages into the tx buffer.  Even if the size of i2c_msg data is
 237  * longer than the size of the tx buffer, it handles everything.
 238  */
 239 static void
 240 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 241 {
 242         struct i2c_msg *msgs = dev->msgs;
 243         u32 intr_mask;
 244         int tx_limit, rx_limit;
 245         u32 addr = msgs[dev->msg_write_idx].addr;
 246         u32 buf_len = dev->tx_buf_len;
 247         u8 *buf = dev->tx_buf;
 248         bool need_restart = false;
 249 
 250         intr_mask = DW_IC_INTR_MASTER_MASK;
 251 
 252         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 253                 u32 flags = msgs[dev->msg_write_idx].flags;
 254 
 255                 /*
 256                  * If target address has changed, we need to
 257                  * reprogram the target address in the I2C
 258                  * adapter when we are done with this transfer.
 259                  */
 260                 if (msgs[dev->msg_write_idx].addr != addr) {
 261                         dev_err(dev->dev,
 262                                 "%s: invalid target address\n", __func__);
 263                         dev->msg_err = -EINVAL;
 264                         break;
 265                 }
 266 
 267                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 268                         /* new i2c_msg */
 269                         buf = msgs[dev->msg_write_idx].buf;
 270                         buf_len = msgs[dev->msg_write_idx].len;
 271 
 272                         /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
 273                          * IC_RESTART_EN are set, we must manually
 274                          * set restart bit between messages.
 275                          */
 276                         if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
 277                                         (dev->msg_write_idx > 0))
 278                                 need_restart = true;
 279                 }
 280 
 281                 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
 282                 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
 283 
 284                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 285                         u32 cmd = 0;
 286 
 287                         /*
 288                          * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
 289                          * manually set the stop bit. However, it cannot be
 290                          * detected from the registers so we set it always
 291                          * when writing/reading the last byte.
 292                          */
 293 
 294                         /*
 295                          * i2c-core always sets the buffer length of
 296                          * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
 297                          * be adjusted when receiving the first byte.
 298                          * Thus we can't stop the transaction here.
 299                          */
 300                         if (dev->msg_write_idx == dev->msgs_num - 1 &&
 301                             buf_len == 1 && !(flags & I2C_M_RECV_LEN))
 302                                 cmd |= BIT(9);
 303 
 304                         if (need_restart) {
 305                                 cmd |= BIT(10);
 306                                 need_restart = false;
 307                         }
 308 
 309                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 310 
 311                                 /* Avoid rx buffer overrun */
 312                                 if (dev->rx_outstanding >= dev->rx_fifo_depth)
 313                                         break;
 314 
 315                                 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
 316                                 rx_limit--;
 317                                 dev->rx_outstanding++;
 318                         } else
 319                                 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
 320                         tx_limit--; buf_len--;
 321                 }
 322 
 323                 dev->tx_buf = buf;
 324                 dev->tx_buf_len = buf_len;
 325 
 326                 /*
 327                  * Because we don't know the buffer length in the
 328                  * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
 329                  * the transaction here.
 330                  */
 331                 if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
 332                         /* more bytes to be written */
 333                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 334                         break;
 335                 } else
 336                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 337         }
 338 
 339         /*
 340          * If i2c_msg index search is completed, we don't need TX_EMPTY
 341          * interrupt any more.
 342          */
 343         if (dev->msg_write_idx == dev->msgs_num)
 344                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 345 
 346         if (dev->msg_err)
 347                 intr_mask = 0;
 348 
 349         dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
 350 }
 351 
 352 static u8
 353 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
 354 {
 355         struct i2c_msg *msgs = dev->msgs;
 356         u32 flags = msgs[dev->msg_read_idx].flags;
 357 
 358         /*
 359          * Adjust the buffer length and mask the flag
 360          * after receiving the first byte.
 361          */
 362         len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
 363         dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
 364         msgs[dev->msg_read_idx].len = len;
 365         msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
 366 
 367         return len;
 368 }
 369 
 370 static void
 371 i2c_dw_read(struct dw_i2c_dev *dev)
 372 {
 373         struct i2c_msg *msgs = dev->msgs;
 374         int rx_valid;
 375 
 376         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 377                 u32 len;
 378                 u8 *buf;
 379 
 380                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 381                         continue;
 382 
 383                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 384                         len = msgs[dev->msg_read_idx].len;
 385                         buf = msgs[dev->msg_read_idx].buf;
 386                 } else {
 387                         len = dev->rx_buf_len;
 388                         buf = dev->rx_buf;
 389                 }
 390 
 391                 rx_valid = dw_readl(dev, DW_IC_RXFLR);
 392 
 393                 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
 394                         u32 flags = msgs[dev->msg_read_idx].flags;
 395 
 396                         *buf = dw_readl(dev, DW_IC_DATA_CMD);
 397                         /* Ensure length byte is a valid value */
 398                         if (flags & I2C_M_RECV_LEN &&
 399                                 *buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) {
 400                                 len = i2c_dw_recv_len(dev, *buf);
 401                         }
 402                         buf++;
 403                         dev->rx_outstanding--;
 404                 }
 405 
 406                 if (len > 0) {
 407                         dev->status |= STATUS_READ_IN_PROGRESS;
 408                         dev->rx_buf_len = len;
 409                         dev->rx_buf = buf;
 410                         return;
 411                 } else
 412                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 413         }
 414 }
 415 
 416 /*
 417  * Prepare controller for a transaction and call i2c_dw_xfer_msg.
 418  */
 419 static int
 420 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 421 {
 422         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 423         int ret;
 424 
 425         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 426 
 427         pm_runtime_get_sync(dev->dev);
 428 
 429         if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) {
 430                 ret = -ESHUTDOWN;
 431                 goto done_nolock;
 432         }
 433 
 434         reinit_completion(&dev->cmd_complete);
 435         dev->msgs = msgs;
 436         dev->msgs_num = num;
 437         dev->cmd_err = 0;
 438         dev->msg_write_idx = 0;
 439         dev->msg_read_idx = 0;
 440         dev->msg_err = 0;
 441         dev->status = STATUS_IDLE;
 442         dev->abort_source = 0;
 443         dev->rx_outstanding = 0;
 444 
 445         ret = i2c_dw_acquire_lock(dev);
 446         if (ret)
 447                 goto done_nolock;
 448 
 449         ret = i2c_dw_wait_bus_not_busy(dev);
 450         if (ret < 0)
 451                 goto done;
 452 
 453         /* Start the transfers */
 454         i2c_dw_xfer_init(dev);
 455 
 456         /* Wait for tx to complete */
 457         if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
 458                 dev_err(dev->dev, "controller timed out\n");
 459                 /* i2c_dw_init implicitly disables the adapter */
 460                 i2c_recover_bus(&dev->adapter);
 461                 i2c_dw_init_master(dev);
 462                 ret = -ETIMEDOUT;
 463                 goto done;
 464         }
 465 
 466         /*
 467          * We must disable the adapter before returning and signaling the end
 468          * of the current transfer. Otherwise the hardware might continue
 469          * generating interrupts which in turn causes a race condition with
 470          * the following transfer.  Needs some more investigation if the
 471          * additional interrupts are a hardware bug or this driver doesn't
 472          * handle them correctly yet.
 473          */
 474         __i2c_dw_disable_nowait(dev);
 475 
 476         if (dev->msg_err) {
 477                 ret = dev->msg_err;
 478                 goto done;
 479         }
 480 
 481         /* No error */
 482         if (likely(!dev->cmd_err && !dev->status)) {
 483                 ret = num;
 484                 goto done;
 485         }
 486 
 487         /* We have an error */
 488         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 489                 ret = i2c_dw_handle_tx_abort(dev);
 490                 goto done;
 491         }
 492 
 493         if (dev->status)
 494                 dev_err(dev->dev,
 495                         "transfer terminated early - interrupt latency too high?\n");
 496 
 497         ret = -EIO;
 498 
 499 done:
 500         i2c_dw_release_lock(dev);
 501 
 502 done_nolock:
 503         pm_runtime_mark_last_busy(dev->dev);
 504         pm_runtime_put_autosuspend(dev->dev);
 505 
 506         return ret;
 507 }
 508 
 509 static const struct i2c_algorithm i2c_dw_algo = {
 510         .master_xfer = i2c_dw_xfer,
 511         .functionality = i2c_dw_func,
 512 };
 513 
 514 static const struct i2c_adapter_quirks i2c_dw_quirks = {
 515         .flags = I2C_AQ_NO_ZERO_LEN,
 516 };
 517 
 518 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 519 {
 520         u32 stat;
 521 
 522         /*
 523          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 524          * Ths unmasked raw version of interrupt status bits are available
 525          * in the IC_RAW_INTR_STAT register.
 526          *
 527          * That is,
 528          *   stat = dw_readl(IC_INTR_STAT);
 529          * equals to,
 530          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 531          *
 532          * The raw version might be useful for debugging purposes.
 533          */
 534         stat = dw_readl(dev, DW_IC_INTR_STAT);
 535 
 536         /*
 537          * Do not use the IC_CLR_INTR register to clear interrupts, or
 538          * you'll miss some interrupts, triggered during the period from
 539          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 540          *
 541          * Instead, use the separately-prepared IC_CLR_* registers.
 542          */
 543         if (stat & DW_IC_INTR_RX_UNDER)
 544                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 545         if (stat & DW_IC_INTR_RX_OVER)
 546                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 547         if (stat & DW_IC_INTR_TX_OVER)
 548                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 549         if (stat & DW_IC_INTR_RD_REQ)
 550                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 551         if (stat & DW_IC_INTR_TX_ABRT) {
 552                 /*
 553                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 554                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 555                  */
 556                 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
 557                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 558         }
 559         if (stat & DW_IC_INTR_RX_DONE)
 560                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 561         if (stat & DW_IC_INTR_ACTIVITY)
 562                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 563         if (stat & DW_IC_INTR_STOP_DET)
 564                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 565         if (stat & DW_IC_INTR_START_DET)
 566                 dw_readl(dev, DW_IC_CLR_START_DET);
 567         if (stat & DW_IC_INTR_GEN_CALL)
 568                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 569 
 570         return stat;
 571 }
 572 
 573 /*
 574  * Interrupt service routine. This gets called whenever an I2C master interrupt
 575  * occurs.
 576  */
 577 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
 578 {
 579         u32 stat;
 580 
 581         stat = i2c_dw_read_clear_intrbits(dev);
 582         if (stat & DW_IC_INTR_TX_ABRT) {
 583                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 584                 dev->status = STATUS_IDLE;
 585 
 586                 /*
 587                  * Anytime TX_ABRT is set, the contents of the tx/rx
 588                  * buffers are flushed. Make sure to skip them.
 589                  */
 590                 dw_writel(dev, 0, DW_IC_INTR_MASK);
 591                 goto tx_aborted;
 592         }
 593 
 594         if (stat & DW_IC_INTR_RX_FULL)
 595                 i2c_dw_read(dev);
 596 
 597         if (stat & DW_IC_INTR_TX_EMPTY)
 598                 i2c_dw_xfer_msg(dev);
 599 
 600         /*
 601          * No need to modify or disable the interrupt mask here.
 602          * i2c_dw_xfer_msg() will take care of it according to
 603          * the current transmit status.
 604          */
 605 
 606 tx_aborted:
 607         if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
 608                 complete(&dev->cmd_complete);
 609         else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
 610                 /* Workaround to trigger pending interrupt */
 611                 stat = dw_readl(dev, DW_IC_INTR_MASK);
 612                 i2c_dw_disable_int(dev);
 613                 dw_writel(dev, stat, DW_IC_INTR_MASK);
 614         }
 615 
 616         return 0;
 617 }
 618 
 619 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 620 {
 621         struct dw_i2c_dev *dev = dev_id;
 622         u32 stat, enabled;
 623 
 624         enabled = dw_readl(dev, DW_IC_ENABLE);
 625         stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 626         dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
 627         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 628                 return IRQ_NONE;
 629 
 630         i2c_dw_irq_handler_master(dev);
 631 
 632         return IRQ_HANDLED;
 633 }
 634 
 635 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
 636 {
 637         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 638 
 639         i2c_dw_disable(dev);
 640         reset_control_assert(dev->rst);
 641         i2c_dw_prepare_clk(dev, false);
 642 }
 643 
 644 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
 645 {
 646         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 647 
 648         i2c_dw_prepare_clk(dev, true);
 649         reset_control_deassert(dev->rst);
 650         i2c_dw_init_master(dev);
 651 }
 652 
 653 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
 654 {
 655         struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
 656         struct i2c_adapter *adap = &dev->adapter;
 657         struct gpio_desc *gpio;
 658 
 659         gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
 660         if (IS_ERR_OR_NULL(gpio))
 661                 return PTR_ERR_OR_ZERO(gpio);
 662 
 663         rinfo->scl_gpiod = gpio;
 664 
 665         gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
 666         if (IS_ERR(gpio))
 667                 return PTR_ERR(gpio);
 668         rinfo->sda_gpiod = gpio;
 669 
 670         rinfo->recover_bus = i2c_generic_scl_recovery;
 671         rinfo->prepare_recovery = i2c_dw_prepare_recovery;
 672         rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
 673         adap->bus_recovery_info = rinfo;
 674 
 675         dev_info(dev->dev, "running with gpio recovery mode! scl%s",
 676                  rinfo->sda_gpiod ? ",sda" : "");
 677 
 678         return 0;
 679 }
 680 
 681 int i2c_dw_probe(struct dw_i2c_dev *dev)
 682 {
 683         struct i2c_adapter *adap = &dev->adapter;
 684         unsigned long irq_flags;
 685         int ret;
 686 
 687         init_completion(&dev->cmd_complete);
 688 
 689         dev->init = i2c_dw_init_master;
 690         dev->disable = i2c_dw_disable;
 691         dev->disable_int = i2c_dw_disable_int;
 692 
 693         ret = i2c_dw_set_reg_access(dev);
 694         if (ret)
 695                 return ret;
 696 
 697         ret = i2c_dw_set_timings_master(dev);
 698         if (ret)
 699                 return ret;
 700 
 701         ret = dev->init(dev);
 702         if (ret)
 703                 return ret;
 704 
 705         snprintf(adap->name, sizeof(adap->name),
 706                  "Synopsys DesignWare I2C adapter");
 707         adap->retries = 3;
 708         adap->algo = &i2c_dw_algo;
 709         adap->quirks = &i2c_dw_quirks;
 710         adap->dev.parent = dev->dev;
 711         i2c_set_adapdata(adap, dev);
 712 
 713         if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
 714                 irq_flags = IRQF_NO_SUSPEND;
 715         } else {
 716                 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
 717         }
 718 
 719         i2c_dw_disable_int(dev);
 720         ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
 721                                dev_name(dev->dev), dev);
 722         if (ret) {
 723                 dev_err(dev->dev, "failure requesting irq %i: %d\n",
 724                         dev->irq, ret);
 725                 return ret;
 726         }
 727 
 728         ret = i2c_dw_init_recovery_info(dev);
 729         if (ret)
 730                 return ret;
 731 
 732         /*
 733          * Increment PM usage count during adapter registration in order to
 734          * avoid possible spurious runtime suspend when adapter device is
 735          * registered to the device core and immediate resume in case bus has
 736          * registered I2C slaves that do I2C transfers in their probe.
 737          */
 738         pm_runtime_get_noresume(dev->dev);
 739         ret = i2c_add_numbered_adapter(adap);
 740         if (ret)
 741                 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
 742         pm_runtime_put_noidle(dev->dev);
 743 
 744         return ret;
 745 }
 746 EXPORT_SYMBOL_GPL(i2c_dw_probe);
 747 
 748 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
 749 MODULE_LICENSE("GPL");