root/drivers/i2c/busses/i2c-at91.h

INCLUDED FROM

DEFINITIONS

1. at91_init_twi_bus_slave
2. at91_twi_probe_slave

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  *  i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
   4  *
   5  *  Copyright (C) 2011 Weinmann Medical GmbH
   6  *  Author: Nikolaus Voss <n.voss@weinmann.de>
   7  *
   8  *  Evolved from original work by:
   9  *  Copyright (C) 2004 Rick Bronson
  10  *  Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
  11  *
  12  *  Borrowed heavily from original work by:
  13  *  Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
  14  */
  15 
  16 #include <linux/clk.h>
  17 #include <linux/completion.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/i2c.h>
  21 #include <linux/platform_data/dma-atmel.h>
  22 #include <linux/platform_device.h>
  23 
  24 #define AT91_I2C_TIMEOUT        msecs_to_jiffies(100)   /* transfer timeout */
  25 #define AT91_I2C_DMA_THRESHOLD  8                       /* enable DMA if transfer size is bigger than this threshold */
  26 #define AUTOSUSPEND_TIMEOUT             2000
  27 #define AT91_I2C_MAX_ALT_CMD_DATA_SIZE  256
  28 
  29 /* AT91 TWI register definitions */
  30 #define AT91_TWI_CR             0x0000  /* Control Register */
  31 #define AT91_TWI_START          BIT(0)  /* Send a Start Condition */
  32 #define AT91_TWI_STOP           BIT(1)  /* Send a Stop Condition */
  33 #define AT91_TWI_MSEN           BIT(2)  /* Master Transfer Enable */
  34 #define AT91_TWI_MSDIS          BIT(3)  /* Master Transfer Disable */
  35 #define AT91_TWI_SVEN           BIT(4)  /* Slave Transfer Enable */
  36 #define AT91_TWI_SVDIS          BIT(5)  /* Slave Transfer Disable */
  37 #define AT91_TWI_QUICK          BIT(6)  /* SMBus quick command */
  38 #define AT91_TWI_SWRST          BIT(7)  /* Software Reset */
  39 #define AT91_TWI_ACMEN          BIT(16) /* Alternative Command Mode Enable */
  40 #define AT91_TWI_ACMDIS         BIT(17) /* Alternative Command Mode Disable */
  41 #define AT91_TWI_THRCLR         BIT(24) /* Transmit Holding Register Clear */
  42 #define AT91_TWI_RHRCLR         BIT(25) /* Receive Holding Register Clear */
  43 #define AT91_TWI_LOCKCLR        BIT(26) /* Lock Clear */
  44 #define AT91_TWI_FIFOEN         BIT(28) /* FIFO Enable */
  45 #define AT91_TWI_FIFODIS        BIT(29) /* FIFO Disable */
  46 
  47 #define AT91_TWI_MMR            0x0004  /* Master Mode Register */
  48 #define AT91_TWI_IADRSZ_1       0x0100  /* Internal Device Address Size */
  49 #define AT91_TWI_MREAD          BIT(12) /* Master Read Direction */
  50 
  51 #define AT91_TWI_SMR            0x0008  /* Slave Mode Register */
  52 #define AT91_TWI_SMR_SADR_MAX   0x007f
  53 #define AT91_TWI_SMR_SADR(x)    (((x) & AT91_TWI_SMR_SADR_MAX) << 16)
  54 
  55 #define AT91_TWI_IADR           0x000c  /* Internal Address Register */
  56 
  57 #define AT91_TWI_CWGR           0x0010  /* Clock Waveform Generator Reg */
  58 #define AT91_TWI_CWGR_HOLD_MAX  0x1f
  59 #define AT91_TWI_CWGR_HOLD(x)   (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
  60 
  61 #define AT91_TWI_SR             0x0020  /* Status Register */
  62 #define AT91_TWI_TXCOMP         BIT(0)  /* Transmission Complete */
  63 #define AT91_TWI_RXRDY          BIT(1)  /* Receive Holding Register Ready */
  64 #define AT91_TWI_TXRDY          BIT(2)  /* Transmit Holding Register Ready */
  65 #define AT91_TWI_SVREAD         BIT(3)  /* Slave Read */
  66 #define AT91_TWI_SVACC          BIT(4)  /* Slave Access */
  67 #define AT91_TWI_OVRE           BIT(6)  /* Overrun Error */
  68 #define AT91_TWI_UNRE           BIT(7)  /* Underrun Error */
  69 #define AT91_TWI_NACK           BIT(8)  /* Not Acknowledged */
  70 #define AT91_TWI_EOSACC         BIT(11) /* End Of Slave Access */
  71 #define AT91_TWI_LOCK           BIT(23) /* TWI Lock due to Frame Errors */
  72 
  73 #define AT91_TWI_INT_MASK \
  74         (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK \
  75         | AT91_TWI_SVACC | AT91_TWI_EOSACC)
  76 
  77 #define AT91_TWI_IER            0x0024  /* Interrupt Enable Register */
  78 #define AT91_TWI_IDR            0x0028  /* Interrupt Disable Register */
  79 #define AT91_TWI_IMR            0x002c  /* Interrupt Mask Register */
  80 #define AT91_TWI_RHR            0x0030  /* Receive Holding Register */
  81 #define AT91_TWI_THR            0x0034  /* Transmit Holding Register */
  82 
  83 #define AT91_TWI_ACR            0x0040  /* Alternative Command Register */
  84 #define AT91_TWI_ACR_DATAL(len) ((len) & 0xff)
  85 #define AT91_TWI_ACR_DIR        BIT(8)
  86 
  87 #define AT91_TWI_FMR            0x0050  /* FIFO Mode Register */
  88 #define AT91_TWI_FMR_TXRDYM(mode)       (((mode) & 0x3) << 0)
  89 #define AT91_TWI_FMR_TXRDYM_MASK        (0x3 << 0)
  90 #define AT91_TWI_FMR_RXRDYM(mode)       (((mode) & 0x3) << 4)
  91 #define AT91_TWI_FMR_RXRDYM_MASK        (0x3 << 4)
  92 #define AT91_TWI_ONE_DATA       0x0
  93 #define AT91_TWI_TWO_DATA       0x1
  94 #define AT91_TWI_FOUR_DATA      0x2
  95 
  96 #define AT91_TWI_FLR            0x0054  /* FIFO Level Register */
  97 
  98 #define AT91_TWI_FSR            0x0060  /* FIFO Status Register */
  99 #define AT91_TWI_FIER           0x0064  /* FIFO Interrupt Enable Register */
 100 #define AT91_TWI_FIDR           0x0068  /* FIFO Interrupt Disable Register */
 101 #define AT91_TWI_FIMR           0x006c  /* FIFO Interrupt Mask Register */
 102 
 103 #define AT91_TWI_VER            0x00fc  /* Version Register */
 104 
 105 struct at91_twi_pdata {
 106         unsigned clk_max_div;
 107         unsigned clk_offset;
 108         bool has_unre_flag;
 109         bool has_alt_cmd;
 110         bool has_hold_field;
 111         struct at_dma_slave dma_slave;
 112 };
 113 
 114 struct at91_twi_dma {
 115         struct dma_chan *chan_rx;
 116         struct dma_chan *chan_tx;
 117         struct scatterlist sg[2];
 118         struct dma_async_tx_descriptor *data_desc;
 119         enum dma_data_direction direction;
 120         bool buf_mapped;
 121         bool xfer_in_progress;
 122 };
 123 
 124 struct at91_twi_dev {
 125         struct device *dev;
 126         void __iomem *base;
 127         struct completion cmd_complete;
 128         struct clk *clk;
 129         u8 *buf;
 130         size_t buf_len;
 131         struct i2c_msg *msg;
 132         int irq;
 133         unsigned imr;
 134         unsigned transfer_status;
 135         struct i2c_adapter adapter;
 136         unsigned twi_cwgr_reg;
 137         struct at91_twi_pdata *pdata;
 138         bool use_dma;
 139         bool use_alt_cmd;
 140         bool recv_len_abort;
 141         u32 fifo_size;
 142         struct at91_twi_dma dma;
 143         bool slave_detected;
 144 #ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL
 145         unsigned smr;
 146         struct i2c_client *slave;
 147 #endif
 148 };
 149 
 150 unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg);
 151 void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val);
 152 void at91_disable_twi_interrupts(struct at91_twi_dev *dev);
 153 void at91_twi_irq_save(struct at91_twi_dev *dev);
 154 void at91_twi_irq_restore(struct at91_twi_dev *dev);
 155 void at91_init_twi_bus(struct at91_twi_dev *dev);
 156 
 157 void at91_init_twi_bus_master(struct at91_twi_dev *dev);
 158 int at91_twi_probe_master(struct platform_device *pdev, u32 phy_addr,
 159                           struct at91_twi_dev *dev);
 160 
 161 #ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL
 162 void at91_init_twi_bus_slave(struct at91_twi_dev *dev);
 163 int at91_twi_probe_slave(struct platform_device *pdev, u32 phy_addr,
 164                          struct at91_twi_dev *dev);
 165 
 166 #else
 167 static inline void at91_init_twi_bus_slave(struct at91_twi_dev *dev) {}
 168 static inline int at91_twi_probe_slave(struct platform_device *pdev,
 169                                        u32 phy_addr, struct at91_twi_dev *dev)
 170 {
 171         return -EINVAL;
 172 }
 173 
 174 #endif