1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef _CORESIGHT_CORESIGHT_ETM_H
7 #define _CORESIGHT_CORESIGHT_ETM_H
8
9 #include <asm/local.h>
10 #include <linux/spinlock.h>
11 #include "coresight-priv.h"
12
13 /*
14 * Device registers:
15 * 0x000 - 0x2FC: Trace registers
16 * 0x300 - 0x314: Management registers
17 * 0x318 - 0xEFC: Trace registers
18 * 0xF00: Management registers
19 * 0xFA0 - 0xFA4: Trace registers
20 * 0xFA8 - 0xFFC: Management registers
21 */
22 /* Trace registers (0x000-0x2FC) */
23 /* Main control and configuration registers */
24 #define TRCPRGCTLR 0x004
25 #define TRCPROCSELR 0x008
26 #define TRCSTATR 0x00C
27 #define TRCCONFIGR 0x010
28 #define TRCAUXCTLR 0x018
29 #define TRCEVENTCTL0R 0x020
30 #define TRCEVENTCTL1R 0x024
31 #define TRCSTALLCTLR 0x02C
32 #define TRCTSCTLR 0x030
33 #define TRCSYNCPR 0x034
34 #define TRCCCCTLR 0x038
35 #define TRCBBCTLR 0x03C
36 #define TRCTRACEIDR 0x040
37 #define TRCQCTLR 0x044
38 /* Filtering control registers */
39 #define TRCVICTLR 0x080
40 #define TRCVIIECTLR 0x084
41 #define TRCVISSCTLR 0x088
42 #define TRCVIPCSSCTLR 0x08C
43 #define TRCVDCTLR 0x0A0
44 #define TRCVDSACCTLR 0x0A4
45 #define TRCVDARCCTLR 0x0A8
46 /* Derived resources registers */
47 #define TRCSEQEVRn(n) (0x100 + (n * 4))
48 #define TRCSEQRSTEVR 0x118
49 #define TRCSEQSTR 0x11C
50 #define TRCEXTINSELR 0x120
51 #define TRCCNTRLDVRn(n) (0x140 + (n * 4))
52 #define TRCCNTCTLRn(n) (0x150 + (n * 4))
53 #define TRCCNTVRn(n) (0x160 + (n * 4))
54 /* ID registers */
55 #define TRCIDR8 0x180
56 #define TRCIDR9 0x184
57 #define TRCIDR10 0x188
58 #define TRCIDR11 0x18C
59 #define TRCIDR12 0x190
60 #define TRCIDR13 0x194
61 #define TRCIMSPEC0 0x1C0
62 #define TRCIMSPECn(n) (0x1C0 + (n * 4))
63 #define TRCIDR0 0x1E0
64 #define TRCIDR1 0x1E4
65 #define TRCIDR2 0x1E8
66 #define TRCIDR3 0x1EC
67 #define TRCIDR4 0x1F0
68 #define TRCIDR5 0x1F4
69 #define TRCIDR6 0x1F8
70 #define TRCIDR7 0x1FC
71 /* Resource selection registers */
72 #define TRCRSCTLRn(n) (0x200 + (n * 4))
73 /* Single-shot comparator registers */
74 #define TRCSSCCRn(n) (0x280 + (n * 4))
75 #define TRCSSCSRn(n) (0x2A0 + (n * 4))
76 #define TRCSSPCICRn(n) (0x2C0 + (n * 4))
77 /* Management registers (0x300-0x314) */
78 #define TRCOSLAR 0x300
79 #define TRCOSLSR 0x304
80 #define TRCPDCR 0x310
81 #define TRCPDSR 0x314
82 /* Trace registers (0x318-0xEFC) */
83 /* Comparator registers */
84 #define TRCACVRn(n) (0x400 + (n * 8))
85 #define TRCACATRn(n) (0x480 + (n * 8))
86 #define TRCDVCVRn(n) (0x500 + (n * 16))
87 #define TRCDVCMRn(n) (0x580 + (n * 16))
88 #define TRCCIDCVRn(n) (0x600 + (n * 8))
89 #define TRCVMIDCVRn(n) (0x640 + (n * 8))
90 #define TRCCIDCCTLR0 0x680
91 #define TRCCIDCCTLR1 0x684
92 #define TRCVMIDCCTLR0 0x688
93 #define TRCVMIDCCTLR1 0x68C
94 /* Management register (0xF00) */
95 /* Integration control registers */
96 #define TRCITCTRL 0xF00
97 /* Trace registers (0xFA0-0xFA4) */
98 /* Claim tag registers */
99 #define TRCCLAIMSET 0xFA0
100 #define TRCCLAIMCLR 0xFA4
101 /* Management registers (0xFA8-0xFFC) */
102 #define TRCDEVAFF0 0xFA8
103 #define TRCDEVAFF1 0xFAC
104 #define TRCLAR 0xFB0
105 #define TRCLSR 0xFB4
106 #define TRCAUTHSTATUS 0xFB8
107 #define TRCDEVARCH 0xFBC
108 #define TRCDEVID 0xFC8
109 #define TRCDEVTYPE 0xFCC
110 #define TRCPIDR4 0xFD0
111 #define TRCPIDR5 0xFD4
112 #define TRCPIDR6 0xFD8
113 #define TRCPIDR7 0xFDC
114 #define TRCPIDR0 0xFE0
115 #define TRCPIDR1 0xFE4
116 #define TRCPIDR2 0xFE8
117 #define TRCPIDR3 0xFEC
118 #define TRCCIDR0 0xFF0
119 #define TRCCIDR1 0xFF4
120 #define TRCCIDR2 0xFF8
121 #define TRCCIDR3 0xFFC
122
123 /* ETMv4 resources */
124 #define ETM_MAX_NR_PE 8
125 #define ETMv4_MAX_CNTR 4
126 #define ETM_MAX_SEQ_STATES 4
127 #define ETM_MAX_EXT_INP_SEL 4
128 #define ETM_MAX_EXT_INP 256
129 #define ETM_MAX_EXT_OUT 4
130 #define ETM_MAX_SINGLE_ADDR_CMP 16
131 #define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2)
132 #define ETM_MAX_DATA_VAL_CMP 8
133 #define ETMv4_MAX_CTXID_CMP 8
134 #define ETM_MAX_VMID_CMP 8
135 #define ETM_MAX_PE_CMP 8
136 #define ETM_MAX_RES_SEL 16
137 #define ETM_MAX_SS_CMP 8
138
139 #define ETM_ARCH_V4 0x40
140 #define ETMv4_SYNC_MASK 0x1F
141 #define ETM_CYC_THRESHOLD_MASK 0xFFF
142 #define ETM_CYC_THRESHOLD_DEFAULT 0x100
143 #define ETMv4_EVENT_MASK 0xFF
144 #define ETM_CNTR_MAX_VAL 0xFFFF
145 #define ETM_TRACEID_MASK 0x3f
146
147 /* ETMv4 programming modes */
148 #define ETM_MODE_EXCLUDE BIT(0)
149 #define ETM_MODE_LOAD BIT(1)
150 #define ETM_MODE_STORE BIT(2)
151 #define ETM_MODE_LOAD_STORE BIT(3)
152 #define ETM_MODE_BB BIT(4)
153 #define ETMv4_MODE_CYCACC BIT(5)
154 #define ETMv4_MODE_CTXID BIT(6)
155 #define ETM_MODE_VMID BIT(7)
156 #define ETM_MODE_COND(val) BMVAL(val, 8, 10)
157 #define ETMv4_MODE_TIMESTAMP BIT(11)
158 #define ETM_MODE_RETURNSTACK BIT(12)
159 #define ETM_MODE_QELEM(val) BMVAL(val, 13, 14)
160 #define ETM_MODE_DATA_TRACE_ADDR BIT(15)
161 #define ETM_MODE_DATA_TRACE_VAL BIT(16)
162 #define ETM_MODE_ISTALL BIT(17)
163 #define ETM_MODE_DSTALL BIT(18)
164 #define ETM_MODE_ATB_TRIGGER BIT(19)
165 #define ETM_MODE_LPOVERRIDE BIT(20)
166 #define ETM_MODE_ISTALL_EN BIT(21)
167 #define ETM_MODE_DSTALL_EN BIT(22)
168 #define ETM_MODE_INSTPRIO BIT(23)
169 #define ETM_MODE_NOOVERFLOW BIT(24)
170 #define ETM_MODE_TRACE_RESET BIT(25)
171 #define ETM_MODE_TRACE_ERR BIT(26)
172 #define ETM_MODE_VIEWINST_STARTSTOP BIT(27)
173 #define ETMv4_MODE_ALL (GENMASK(27, 0) | \
174 ETM_MODE_EXCL_KERN | \
175 ETM_MODE_EXCL_USER)
176
177 #define TRCSTATR_IDLE_BIT 0
178 #define ETM_DEFAULT_ADDR_COMP 0
179
180 /* PowerDown Control Register bits */
181 #define TRCPDCR_PU BIT(3)
182
183 /* secure state access levels */
184 #define ETM_EXLEVEL_S_APP BIT(8)
185 #define ETM_EXLEVEL_S_OS BIT(9)
186 #define ETM_EXLEVEL_S_NA BIT(10)
187 #define ETM_EXLEVEL_S_HYP BIT(11)
188 /* non-secure state access levels */
189 #define ETM_EXLEVEL_NS_APP BIT(12)
190 #define ETM_EXLEVEL_NS_OS BIT(13)
191 #define ETM_EXLEVEL_NS_HYP BIT(14)
192 #define ETM_EXLEVEL_NS_NA BIT(15)
193
194 /**
195 * struct etmv4_config - configuration information related to an ETMv4
196 * @mode: Controls various modes supported by this ETM.
197 * @pe_sel: Controls which PE to trace.
198 * @cfg: Controls the tracing options.
199 * @eventctrl0: Controls the tracing of arbitrary events.
200 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
201 * @stallctl: If functionality that prevents trace unit buffer overflows
202 * is available.
203 * @ts_ctrl: Controls the insertion of global timestamps in the
204 * trace streams.
205 * @syncfreq: Controls how often trace synchronization requests occur.
206 * the TRCCCCTLR register.
207 * @ccctlr: Sets the threshold value for cycle counting.
208 * @vinst_ctrl: Controls instruction trace filtering.
209 * @viiectlr: Set or read, the address range comparators.
210 * @vissctlr: Set, or read, the single address comparators that control the
211 * ViewInst start-stop logic.
212 * @vipcssctlr: Set, or read, which PE comparator inputs can control the
213 * ViewInst start-stop logic.
214 * @seq_idx: Sequencor index selector.
215 * @seq_ctrl: Control for the sequencer state transition control register.
216 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
217 * @seq_state: Set, or read the sequencer state.
218 * @cntr_idx: Counter index seletor.
219 * @cntrldvr: Sets or returns the reload count value for a counter.
220 * @cntr_ctrl: Controls the operation of a counter.
221 * @cntr_val: Sets or returns the value for a counter.
222 * @res_idx: Resource index selector.
223 * @res_ctrl: Controls the selection of the resources in the trace unit.
224 * @ss_ctrl: Controls the corresponding single-shot comparator resource.
225 * @ss_status: The status of the corresponding single-shot comparator.
226 * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
227 * @addr_idx: Address comparator index selector.
228 * @addr_val: Value for address comparator.
229 * @addr_acc: Address comparator access type.
230 * @addr_type: Current status of the comparator register.
231 * @ctxid_idx: Context ID index selector.
232 * @ctxid_pid: Value of the context ID comparator.
233 * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
234 * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
235 * @vmid_idx: VM ID index selector.
236 * @vmid_val: Value of the VM ID comparator.
237 * @vmid_mask0: VM ID comparator mask for comparator 0-3.
238 * @vmid_mask1: VM ID comparator mask for comparator 4-7.
239 * @ext_inp: External input selection.
240 */
241 struct etmv4_config {
242 u32 mode;
243 u32 pe_sel;
244 u32 cfg;
245 u32 eventctrl0;
246 u32 eventctrl1;
247 u32 stall_ctrl;
248 u32 ts_ctrl;
249 u32 syncfreq;
250 u32 ccctlr;
251 u32 bb_ctrl;
252 u32 vinst_ctrl;
253 u32 viiectlr;
254 u32 vissctlr;
255 u32 vipcssctlr;
256 u8 seq_idx;
257 u32 seq_ctrl[ETM_MAX_SEQ_STATES];
258 u32 seq_rst;
259 u32 seq_state;
260 u8 cntr_idx;
261 u32 cntrldvr[ETMv4_MAX_CNTR];
262 u32 cntr_ctrl[ETMv4_MAX_CNTR];
263 u32 cntr_val[ETMv4_MAX_CNTR];
264 u8 res_idx;
265 u32 res_ctrl[ETM_MAX_RES_SEL];
266 u32 ss_ctrl[ETM_MAX_SS_CMP];
267 u32 ss_status[ETM_MAX_SS_CMP];
268 u32 ss_pe_cmp[ETM_MAX_SS_CMP];
269 u8 addr_idx;
270 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
271 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
272 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
273 u8 ctxid_idx;
274 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
275 u32 ctxid_mask0;
276 u32 ctxid_mask1;
277 u8 vmid_idx;
278 u64 vmid_val[ETM_MAX_VMID_CMP];
279 u32 vmid_mask0;
280 u32 vmid_mask1;
281 u32 ext_inp;
282 };
283
284 /**
285 * struct etm4_drvdata - specifics associated to an ETM component
286 * @base: Memory mapped base address for this component.
287 * @csdev: Component vitals needed by the framework.
288 * @spinlock: Only one at a time pls.
289 * @mode: This tracer's mode, i.e sysFS, Perf or disabled.
290 * @cpu: The cpu this component is affined to.
291 * @arch: ETM version number.
292 * @nr_pe: The number of processing entity available for tracing.
293 * @nr_pe_cmp: The number of processing entity comparator inputs that are
294 * available for tracing.
295 * @nr_addr_cmp:Number of pairs of address comparators available
296 * as found in ETMIDR4 0-3.
297 * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
298 * @nr_ext_inp: Number of external input.
299 * @numcidc: Number of contextID comparators.
300 * @numvmidc: Number of VMID comparators.
301 * @nrseqstate: The number of sequencer states that are implemented.
302 * @nr_event: Indicates how many events the trace unit support.
303 * @nr_resource:The number of resource selection pairs available for tracing.
304 * @nr_ss_cmp: Number of single-shot comparator controls that are available.
305 * @trcid: value of the current ID for this component.
306 * @trcid_size: Indicates the trace ID width.
307 * @ts_size: Global timestamp size field.
308 * @ctxid_size: Size of the context ID field to consider.
309 * @vmid_size: Size of the VM ID comparator to consider.
310 * @ccsize: Indicates the size of the cycle counter in bits.
311 * @ccitmin: minimum value that can be programmed in
312 * @s_ex_level: In secure state, indicates whether instruction tracing is
313 * supported for the corresponding Exception level.
314 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
315 * supported for the corresponding Exception level.
316 * @sticky_enable: true if ETM base configuration has been done.
317 * @boot_enable:True if we should start tracing at boot time.
318 * @os_unlock: True if access to management registers is allowed.
319 * @instrp0: Tracing of load and store instructions
320 * as P0 elements is supported.
321 * @trcbb: Indicates if the trace unit supports branch broadcast tracing.
322 * @trccond: If the trace unit supports conditional
323 * instruction tracing.
324 * @retstack: Indicates if the implementation supports a return stack.
325 * @trccci: Indicates if the trace unit supports cycle counting
326 * for instruction.
327 * @q_support: Q element support characteristics.
328 * @trc_error: Whether a trace unit can trace a system
329 * error exception.
330 * @syncpr: Indicates if an implementation has a fixed
331 * synchronization period.
332 * @stall_ctrl: Enables trace unit functionality that prevents trace
333 * unit buffer overflows.
334 * @sysstall: Does the system support stall control of the PE?
335 * @nooverflow: Indicate if overflow prevention is supported.
336 * @atbtrig: If the implementation can support ATB triggers
337 * @lpoverride: If the implementation can support low-power state over.
338 * @config: structure holding configuration parameters.
339 */
340 struct etmv4_drvdata {
341 void __iomem *base;
342 struct coresight_device *csdev;
343 spinlock_t spinlock;
344 local_t mode;
345 int cpu;
346 u8 arch;
347 u8 nr_pe;
348 u8 nr_pe_cmp;
349 u8 nr_addr_cmp;
350 u8 nr_cntr;
351 u8 nr_ext_inp;
352 u8 numcidc;
353 u8 numvmidc;
354 u8 nrseqstate;
355 u8 nr_event;
356 u8 nr_resource;
357 u8 nr_ss_cmp;
358 u8 trcid;
359 u8 trcid_size;
360 u8 ts_size;
361 u8 ctxid_size;
362 u8 vmid_size;
363 u8 ccsize;
364 u8 ccitmin;
365 u8 s_ex_level;
366 u8 ns_ex_level;
367 u8 q_support;
368 bool sticky_enable;
369 bool boot_enable;
370 bool os_unlock;
371 bool instrp0;
372 bool trcbb;
373 bool trccond;
374 bool retstack;
375 bool trccci;
376 bool trc_error;
377 bool syncpr;
378 bool stallctl;
379 bool sysstall;
380 bool nooverflow;
381 bool atbtrig;
382 bool lpoverride;
383 struct etmv4_config config;
384 };
385
386 /* Address comparator access types */
387 enum etm_addr_acctype {
388 ETM_INSTR_ADDR,
389 ETM_DATA_LOAD_ADDR,
390 ETM_DATA_STORE_ADDR,
391 ETM_DATA_LOAD_STORE_ADDR,
392 };
393
394 /* Address comparator context types */
395 enum etm_addr_ctxtype {
396 ETM_CTX_NONE,
397 ETM_CTX_CTXID,
398 ETM_CTX_VMID,
399 ETM_CTX_CTXID_VMID,
400 };
401
402 extern const struct attribute_group *coresight_etmv4_groups[];
403 void etm4_config_trace_mode(struct etmv4_config *config);
404 #endif