1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2016,2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #include <linux/interrupt.h>
8 #include <linux/irq.h>
9 #include <linux/irqdomain.h>
10 #include <linux/msi.h>
11 #include <linux/sched.h>
12
13 #include <linux/irqchip/arm-gic-v4.h>
14
15 /*
16 * WARNING: The blurb below assumes that you understand the
17 * intricacies of GICv3, GICv4, and how a guest's view of a GICv3 gets
18 * translated into GICv4 commands. So it effectively targets at most
19 * two individuals. You know who you are.
20 *
21 * The core GICv4 code is designed to *avoid* exposing too much of the
22 * core GIC code (that would in turn leak into the hypervisor code),
23 * and instead provide a hypervisor agnostic interface to the HW (of
24 * course, the astute reader will quickly realize that hypervisor
25 * agnostic actually means KVM-specific - what were you thinking?).
26 *
27 * In order to achieve a modicum of isolation, we try to hide most of
28 * the GICv4 "stuff" behind normal irqchip operations:
29 *
30 * - Any guest-visible VLPI is backed by a Linux interrupt (and a
31 * physical LPI which gets unmapped when the guest maps the
32 * VLPI). This allows the same DevID/EventID pair to be either
33 * mapped to the LPI (host) or the VLPI (guest). Note that this is
34 * exclusive, and you cannot have both.
35 *
36 * - Enabling/disabling a VLPI is done by issuing mask/unmask calls.
37 *
38 * - Guest INT/CLEAR commands are implemented through
39 * irq_set_irqchip_state().
40 *
41 * - The *bizarre* stuff (mapping/unmapping an interrupt to a VLPI, or
42 * issuing an INV after changing a priority) gets shoved into the
43 * irq_set_vcpu_affinity() method. While this is quite horrible
44 * (let's face it, this is the irqchip version of an ioctl), it
45 * confines the crap to a single location. And map/unmap really is
46 * about setting the affinity of a VLPI to a vcpu, so only INV is
47 * majorly out of place. So there.
48 *
49 * A number of commands are simply not provided by this interface, as
50 * they do not make direct sense. For example, MAPD is purely local to
51 * the virtual ITS (because it references a virtual device, and the
52 * physical ITS is still very much in charge of the physical
53 * device). Same goes for things like MAPC (the physical ITS deals
54 * with the actual vPE affinity, and not the braindead concept of
55 * collection). SYNC is not provided either, as each and every command
56 * is followed by a VSYNC. This could be relaxed in the future, should
57 * this be seen as a bottleneck (yes, this means *never*).
58 *
59 * But handling VLPIs is only one side of the job of the GICv4
60 * code. The other (darker) side is to take care of the doorbell
61 * interrupts which are delivered when a VLPI targeting a non-running
62 * vcpu is being made pending.
63 *
64 * The choice made here is that each vcpu (VPE in old northern GICv4
65 * dialect) gets a single doorbell LPI, no matter how many interrupts
66 * are targeting it. This has a nice property, which is that the
67 * interrupt becomes a handle for the VPE, and that the hypervisor
68 * code can manipulate it through the normal interrupt API:
69 *
70 * - VMs (or rather the VM abstraction that matters to the GIC)
71 * contain an irq domain where each interrupt maps to a VPE. In
72 * turn, this domain sits on top of the normal LPI allocator, and a
73 * specially crafted irq_chip implementation.
74 *
75 * - mask/unmask do what is expected on the doorbell interrupt.
76 *
77 * - irq_set_affinity is used to move a VPE from one redistributor to
78 * another.
79 *
80 * - irq_set_vcpu_affinity once again gets hijacked for the purpose of
81 * creating a new sub-API, namely scheduling/descheduling a VPE
82 * (which involves programming GICR_V{PROP,PEND}BASER) and
83 * performing INVALL operations.
84 */
85
86 static struct irq_domain *gic_domain;
87 static const struct irq_domain_ops *vpe_domain_ops;
88
89 int its_alloc_vcpu_irqs(struct its_vm *vm)
90 {
91 int vpe_base_irq, i;
92
93 vm->fwnode = irq_domain_alloc_named_id_fwnode("GICv4-vpe",
94 task_pid_nr(current));
95 if (!vm->fwnode)
96 goto err;
97
98 vm->domain = irq_domain_create_hierarchy(gic_domain, 0, vm->nr_vpes,
99 vm->fwnode, vpe_domain_ops,
100 vm);
101 if (!vm->domain)
102 goto err;
103
104 for (i = 0; i < vm->nr_vpes; i++) {
105 vm->vpes[i]->its_vm = vm;
106 vm->vpes[i]->idai = true;
107 }
108
109 vpe_base_irq = __irq_domain_alloc_irqs(vm->domain, -1, vm->nr_vpes,
110 NUMA_NO_NODE, vm,
111 false, NULL);
112 if (vpe_base_irq <= 0)
113 goto err;
114
115 for (i = 0; i < vm->nr_vpes; i++)
116 vm->vpes[i]->irq = vpe_base_irq + i;
117
118 return 0;
119
120 err:
121 if (vm->domain)
122 irq_domain_remove(vm->domain);
123 if (vm->fwnode)
124 irq_domain_free_fwnode(vm->fwnode);
125
126 return -ENOMEM;
127 }
128
129 void its_free_vcpu_irqs(struct its_vm *vm)
130 {
131 irq_domain_free_irqs(vm->vpes[0]->irq, vm->nr_vpes);
132 irq_domain_remove(vm->domain);
133 irq_domain_free_fwnode(vm->fwnode);
134 }
135
136 static int its_send_vpe_cmd(struct its_vpe *vpe, struct its_cmd_info *info)
137 {
138 return irq_set_vcpu_affinity(vpe->irq, info);
139 }
140
141 int its_schedule_vpe(struct its_vpe *vpe, bool on)
142 {
143 struct its_cmd_info info;
144
145 WARN_ON(preemptible());
146
147 info.cmd_type = on ? SCHEDULE_VPE : DESCHEDULE_VPE;
148
149 return its_send_vpe_cmd(vpe, &info);
150 }
151
152 int its_invall_vpe(struct its_vpe *vpe)
153 {
154 struct its_cmd_info info = {
155 .cmd_type = INVALL_VPE,
156 };
157
158 return its_send_vpe_cmd(vpe, &info);
159 }
160
161 int its_map_vlpi(int irq, struct its_vlpi_map *map)
162 {
163 struct its_cmd_info info = {
164 .cmd_type = MAP_VLPI,
165 {
166 .map = map,
167 },
168 };
169 int ret;
170
171 /*
172 * The host will never see that interrupt firing again, so it
173 * is vital that we don't do any lazy masking.
174 */
175 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
176
177 ret = irq_set_vcpu_affinity(irq, &info);
178 if (ret)
179 irq_clear_status_flags(irq, IRQ_DISABLE_UNLAZY);
180
181 return ret;
182 }
183
184 int its_get_vlpi(int irq, struct its_vlpi_map *map)
185 {
186 struct its_cmd_info info = {
187 .cmd_type = GET_VLPI,
188 {
189 .map = map,
190 },
191 };
192
193 return irq_set_vcpu_affinity(irq, &info);
194 }
195
196 int its_unmap_vlpi(int irq)
197 {
198 irq_clear_status_flags(irq, IRQ_DISABLE_UNLAZY);
199 return irq_set_vcpu_affinity(irq, NULL);
200 }
201
202 int its_prop_update_vlpi(int irq, u8 config, bool inv)
203 {
204 struct its_cmd_info info = {
205 .cmd_type = inv ? PROP_UPDATE_AND_INV_VLPI : PROP_UPDATE_VLPI,
206 {
207 .config = config,
208 },
209 };
210
211 return irq_set_vcpu_affinity(irq, &info);
212 }
213
214 int its_init_v4(struct irq_domain *domain, const struct irq_domain_ops *ops)
215 {
216 if (domain) {
217 pr_info("ITS: Enabling GICv4 support\n");
218 gic_domain = domain;
219 vpe_domain_ops = ops;
220 return 0;
221 }
222
223 pr_err("ITS: No GICv4 VPE domain allocated\n");
224 return -ENODEV;
225 }