This source file includes following definitions.
- intc_cascade
- intc_irq_set_mask
- ingenic_intc_irq_suspend
- ingenic_intc_irq_resume
- ingenic_intc_of_init
- intc_1chip_of_init
- intc_2chip_of_init
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6
7 #include <linux/errno.h>
8 #include <linux/init.h>
9 #include <linux/types.h>
10 #include <linux/interrupt.h>
11 #include <linux/ioport.h>
12 #include <linux/irqchip.h>
13 #include <linux/irqchip/ingenic.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/timex.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19
20 #include <asm/io.h>
21 #include <asm/mach-jz4740/irq.h>
22
23 struct ingenic_intc_data {
24 void __iomem *base;
25 unsigned num_chips;
26 };
27
28 #define JZ_REG_INTC_STATUS 0x00
29 #define JZ_REG_INTC_MASK 0x04
30 #define JZ_REG_INTC_SET_MASK 0x08
31 #define JZ_REG_INTC_CLEAR_MASK 0x0c
32 #define JZ_REG_INTC_PENDING 0x10
33 #define CHIP_SIZE 0x20
34
35 static irqreturn_t intc_cascade(int irq, void *data)
36 {
37 struct ingenic_intc_data *intc = irq_get_handler_data(irq);
38 uint32_t irq_reg;
39 unsigned i;
40
41 for (i = 0; i < intc->num_chips; i++) {
42 irq_reg = readl(intc->base + (i * CHIP_SIZE) +
43 JZ_REG_INTC_PENDING);
44 if (!irq_reg)
45 continue;
46
47 generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
48 }
49
50 return IRQ_HANDLED;
51 }
52
53 static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
54 {
55 struct irq_chip_regs *regs = &gc->chip_types->regs;
56
57 writel(mask, gc->reg_base + regs->enable);
58 writel(~mask, gc->reg_base + regs->disable);
59 }
60
61 void ingenic_intc_irq_suspend(struct irq_data *data)
62 {
63 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
64 intc_irq_set_mask(gc, gc->wake_active);
65 }
66
67 void ingenic_intc_irq_resume(struct irq_data *data)
68 {
69 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
70 intc_irq_set_mask(gc, gc->mask_cache);
71 }
72
73 static struct irqaction intc_cascade_action = {
74 .handler = intc_cascade,
75 .name = "SoC intc cascade interrupt",
76 };
77
78 static int __init ingenic_intc_of_init(struct device_node *node,
79 unsigned num_chips)
80 {
81 struct ingenic_intc_data *intc;
82 struct irq_chip_generic *gc;
83 struct irq_chip_type *ct;
84 struct irq_domain *domain;
85 int parent_irq, err = 0;
86 unsigned i;
87
88 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
89 if (!intc) {
90 err = -ENOMEM;
91 goto out_err;
92 }
93
94 parent_irq = irq_of_parse_and_map(node, 0);
95 if (!parent_irq) {
96 err = -EINVAL;
97 goto out_free;
98 }
99
100 err = irq_set_handler_data(parent_irq, intc);
101 if (err)
102 goto out_unmap_irq;
103
104 intc->num_chips = num_chips;
105 intc->base = of_iomap(node, 0);
106 if (!intc->base) {
107 err = -ENODEV;
108 goto out_unmap_irq;
109 }
110
111 domain = irq_domain_add_legacy(node, num_chips * 32,
112 JZ4740_IRQ_BASE, 0,
113 &irq_domain_simple_ops, NULL);
114 if (!domain) {
115 err = -ENOMEM;
116 goto out_unmap_base;
117 }
118
119 for (i = 0; i < num_chips; i++) {
120
121 writel(0xffffffff, intc->base + (i * CHIP_SIZE) +
122 JZ_REG_INTC_SET_MASK);
123
124 gc = irq_alloc_generic_chip("INTC", 1,
125 JZ4740_IRQ_BASE + (i * 32),
126 intc->base + (i * CHIP_SIZE),
127 handle_level_irq);
128
129 gc->wake_enabled = IRQ_MSK(32);
130
131 ct = gc->chip_types;
132 ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
133 ct->regs.disable = JZ_REG_INTC_SET_MASK;
134 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
135 ct->chip.irq_mask = irq_gc_mask_disable_reg;
136 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
137 ct->chip.irq_set_wake = irq_gc_set_wake;
138 ct->chip.irq_suspend = ingenic_intc_irq_suspend;
139 ct->chip.irq_resume = ingenic_intc_irq_resume;
140
141 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0,
142 IRQ_NOPROBE | IRQ_LEVEL);
143 }
144
145 setup_irq(parent_irq, &intc_cascade_action);
146 return 0;
147
148 out_unmap_base:
149 iounmap(intc->base);
150 out_unmap_irq:
151 irq_dispose_mapping(parent_irq);
152 out_free:
153 kfree(intc);
154 out_err:
155 return err;
156 }
157
158 static int __init intc_1chip_of_init(struct device_node *node,
159 struct device_node *parent)
160 {
161 return ingenic_intc_of_init(node, 1);
162 }
163 IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init);
164 IRQCHIP_DECLARE(jz4725b_intc, "ingenic,jz4725b-intc", intc_1chip_of_init);
165
166 static int __init intc_2chip_of_init(struct device_node *node,
167 struct device_node *parent)
168 {
169 return ingenic_intc_of_init(node, 2);
170 }
171 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
172 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
173 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);