root/drivers/irqchip/irq-bcm7120-l2.c

DEFINITIONS

1. bcm7120_l2_intc_irq_handle
2. bcm7120_l2_intc_suspend
3. bcm7120_l2_intc_resume
4. bcm7120_l2_intc_init_one
5. bcm7120_l2_intc_iomap_7120
6. bcm7120_l2_intc_iomap_3380
7. bcm7120_l2_intc_probe
8. bcm7120_l2_intc_probe_7120
9. bcm7120_l2_intc_probe_3380

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Broadcom BCM7120 style Level 2 interrupt controller driver
   4  *
   5  * Copyright (C) 2014 Broadcom Corporation
   6  */
   7 
   8 #define pr_fmt(fmt)     KBUILD_MODNAME  ": " fmt
   9 
  10 #include <linux/init.h>
  11 #include <linux/slab.h>
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/of.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/io.h>
  22 #include <linux/irqdomain.h>
  23 #include <linux/reboot.h>
  24 #include <linux/bitops.h>
  25 #include <linux/irqchip.h>
  26 #include <linux/irqchip/chained_irq.h>
  27 
  28 /* Register offset in the L2 interrupt controller */
  29 #define IRQEN           0x00
  30 #define IRQSTAT         0x04
  31 
  32 #define MAX_WORDS       4
  33 #define MAX_MAPPINGS    (MAX_WORDS * 2)
  34 #define IRQS_PER_WORD   32
  35 
  36 struct bcm7120_l1_intc_data {
  37         struct bcm7120_l2_intc_data *b;
  38         u32 irq_map_mask[MAX_WORDS];
  39 };
  40 
  41 struct bcm7120_l2_intc_data {
  42         unsigned int n_words;
  43         void __iomem *map_base[MAX_MAPPINGS];
  44         void __iomem *pair_base[MAX_WORDS];
  45         int en_offset[MAX_WORDS];
  46         int stat_offset[MAX_WORDS];
  47         struct irq_domain *domain;
  48         bool can_wake;
  49         u32 irq_fwd_mask[MAX_WORDS];
  50         struct bcm7120_l1_intc_data *l1_data;
  51         int num_parent_irqs;
  52         const __be32 *map_mask_prop;
  53 };
  54 
  55 static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
  56 {
  57         struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
  58         struct bcm7120_l2_intc_data *b = data->b;
  59         struct irq_chip *chip = irq_desc_get_chip(desc);
  60         unsigned int idx;
  61 
  62         chained_irq_enter(chip, desc);
  63 
  64         for (idx = 0; idx < b->n_words; idx++) {
  65                 int base = idx * IRQS_PER_WORD;
  66                 struct irq_chip_generic *gc =
  67                         irq_get_domain_generic_chip(b->domain, base);
  68                 unsigned long pending;
  69                 int hwirq;
  70 
  71                 irq_gc_lock(gc);
  72                 pending = irq_reg_readl(gc, b->stat_offset[idx]) &
  73                                             gc->mask_cache &
  74                                             data->irq_map_mask[idx];
  75                 irq_gc_unlock(gc);
  76 
  77                 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
  78                         generic_handle_irq(irq_find_mapping(b->domain,
  79                                            base + hwirq));
  80                 }
  81         }
  82 
  83         chained_irq_exit(chip, desc);
  84 }
  85 
  86 static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
  87 {
  88         struct bcm7120_l2_intc_data *b = gc->private;
  89         struct irq_chip_type *ct = gc->chip_types;
  90 
  91         irq_gc_lock(gc);
  92         if (b->can_wake)
  93                 irq_reg_writel(gc, gc->mask_cache | gc->wake_active,
  94                                ct->regs.mask);
  95         irq_gc_unlock(gc);
  96 }
  97 
  98 static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
  99 {
 100         struct irq_chip_type *ct = gc->chip_types;
 101 
 102         /* Restore the saved mask */
 103         irq_gc_lock(gc);
 104         irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
 105         irq_gc_unlock(gc);
 106 }
 107 
 108 static int bcm7120_l2_intc_init_one(struct device_node *dn,
 109                                         struct bcm7120_l2_intc_data *data,
 110                                         int irq, u32 *valid_mask)
 111 {
 112         struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
 113         int parent_irq;
 114         unsigned int idx;
 115 
 116         parent_irq = irq_of_parse_and_map(dn, irq);
 117         if (!parent_irq) {
 118                 pr_err("failed to map interrupt %d\n", irq);
 119                 return -EINVAL;
 120         }
 121 
 122         /* For multiple parent IRQs with multiple words, this looks like:
 123          * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
 124          *
 125          * We need to associate a given parent interrupt with its corresponding
 126          * map_mask in order to mask the status register with it because we
 127          * have the same handler being called for multiple parent interrupts.
 128          *
 129          * This is typically something needed on BCM7xxx (STB chips).
 130          */
 131         for (idx = 0; idx < data->n_words; idx++) {
 132                 if (data->map_mask_prop) {
 133                         l1_data->irq_map_mask[idx] |=
 134                                 be32_to_cpup(data->map_mask_prop +
 135                                              irq * data->n_words + idx);
 136                 } else {
 137                         l1_data->irq_map_mask[idx] = 0xffffffff;
 138                 }
 139                 valid_mask[idx] |= l1_data->irq_map_mask[idx];
 140         }
 141 
 142         l1_data->b = data;
 143 
 144         irq_set_chained_handler_and_data(parent_irq,
 145                                          bcm7120_l2_intc_irq_handle, l1_data);
 146         return 0;
 147 }
 148 
 149 static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
 150                                              struct bcm7120_l2_intc_data *data)
 151 {
 152         int ret;
 153 
 154         data->map_base[0] = of_iomap(dn, 0);
 155         if (!data->map_base[0]) {
 156                 pr_err("unable to map registers\n");
 157                 return -ENOMEM;
 158         }
 159 
 160         data->pair_base[0] = data->map_base[0];
 161         data->en_offset[0] = IRQEN;
 162         data->stat_offset[0] = IRQSTAT;
 163         data->n_words = 1;
 164 
 165         ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
 166                                          data->irq_fwd_mask, data->n_words);
 167         if (ret != 0 && ret != -EINVAL) {
 168                 /* property exists but has the wrong number of words */
 169                 pr_err("invalid brcm,int-fwd-mask property\n");
 170                 return -EINVAL;
 171         }
 172 
 173         data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
 174         if (!data->map_mask_prop ||
 175             (ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
 176                 pr_err("invalid brcm,int-map-mask property\n");
 177                 return -EINVAL;
 178         }
 179 
 180         return 0;
 181 }
 182 
 183 static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
 184                                              struct bcm7120_l2_intc_data *data)
 185 {
 186         unsigned int gc_idx;
 187 
 188         for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
 189                 unsigned int map_idx = gc_idx * 2;
 190                 void __iomem *en = of_iomap(dn, map_idx + 0);
 191                 void __iomem *stat = of_iomap(dn, map_idx + 1);
 192                 void __iomem *base = min(en, stat);
 193 
 194                 data->map_base[map_idx + 0] = en;
 195                 data->map_base[map_idx + 1] = stat;
 196 
 197                 if (!base)
 198                         break;
 199 
 200                 data->pair_base[gc_idx] = base;
 201                 data->en_offset[gc_idx] = en - base;
 202                 data->stat_offset[gc_idx] = stat - base;
 203         }
 204 
 205         if (!gc_idx) {
 206                 pr_err("unable to map registers\n");
 207                 return -EINVAL;
 208         }
 209 
 210         data->n_words = gc_idx;
 211         return 0;
 212 }
 213 
 214 static int __init bcm7120_l2_intc_probe(struct device_node *dn,
 215                                  struct device_node *parent,
 216                                  int (*iomap_regs_fn)(struct device_node *,
 217                                         struct bcm7120_l2_intc_data *),
 218                                  const char *intc_name)
 219 {
 220         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 221         struct bcm7120_l2_intc_data *data;
 222         struct irq_chip_generic *gc;
 223         struct irq_chip_type *ct;
 224         int ret = 0;
 225         unsigned int idx, irq, flags;
 226         u32 valid_mask[MAX_WORDS] = { };
 227 
 228         data = kzalloc(sizeof(*data), GFP_KERNEL);
 229         if (!data)
 230                 return -ENOMEM;
 231 
 232         data->num_parent_irqs = of_irq_count(dn);
 233         if (data->num_parent_irqs <= 0) {
 234                 pr_err("invalid number of parent interrupts\n");
 235                 ret = -ENOMEM;
 236                 goto out_unmap;
 237         }
 238 
 239         data->l1_data = kcalloc(data->num_parent_irqs, sizeof(*data->l1_data),
 240                                 GFP_KERNEL);
 241         if (!data->l1_data) {
 242                 ret = -ENOMEM;
 243                 goto out_free_l1_data;
 244         }
 245 
 246         ret = iomap_regs_fn(dn, data);
 247         if (ret < 0)
 248                 goto out_free_l1_data;
 249 
 250         for (irq = 0; irq < data->num_parent_irqs; irq++) {
 251                 ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
 252                 if (ret)
 253                         goto out_free_l1_data;
 254         }
 255 
 256         data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
 257                                              &irq_generic_chip_ops, NULL);
 258         if (!data->domain) {
 259                 ret = -ENOMEM;
 260                 goto out_free_l1_data;
 261         }
 262 
 263         /* MIPS chips strapped for BE will automagically configure the
 264          * peripheral registers for CPU-native byte order.
 265          */
 266         flags = IRQ_GC_INIT_MASK_CACHE;
 267         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
 268                 flags |= IRQ_GC_BE_IO;
 269 
 270         ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
 271                                 dn->full_name, handle_level_irq, clr, 0, flags);
 272         if (ret) {
 273                 pr_err("failed to allocate generic irq chip\n");
 274                 goto out_free_domain;
 275         }
 276 
 277         if (of_property_read_bool(dn, "brcm,irq-can-wake"))
 278                 data->can_wake = true;
 279 
 280         for (idx = 0; idx < data->n_words; idx++) {
 281                 irq = idx * IRQS_PER_WORD;
 282                 gc = irq_get_domain_generic_chip(data->domain, irq);
 283 
 284                 gc->unused = 0xffffffff & ~valid_mask[idx];
 285                 gc->private = data;
 286                 ct = gc->chip_types;
 287 
 288                 gc->reg_base = data->pair_base[idx];
 289                 ct->regs.mask = data->en_offset[idx];
 290 
 291                 /* gc->reg_base is defined and so is gc->writel */
 292                 irq_reg_writel(gc, data->irq_fwd_mask[idx],
 293                                data->en_offset[idx]);
 294 
 295                 ct->chip.irq_mask = irq_gc_mask_clr_bit;
 296                 ct->chip.irq_unmask = irq_gc_mask_set_bit;
 297                 ct->chip.irq_ack = irq_gc_noop;
 298                 gc->suspend = bcm7120_l2_intc_suspend;
 299                 gc->resume = bcm7120_l2_intc_resume;
 300 
 301                 /*
 302                  * Initialize mask-cache, in case we need it for
 303                  * saving/restoring fwd mask even w/o any child interrupts
 304                  * installed
 305                  */
 306                 gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);
 307 
 308                 if (data->can_wake) {
 309                         /* This IRQ chip can wake the system, set all
 310                          * relevant child interupts in wake_enabled mask
 311                          */
 312                         gc->wake_enabled = 0xffffffff;
 313                         gc->wake_enabled &= ~gc->unused;
 314                         ct->chip.irq_set_wake = irq_gc_set_wake;
 315                 }
 316         }
 317 
 318         pr_info("registered %s intc (%pOF, parent IRQ(s): %d)\n",
 319                 intc_name, dn, data->num_parent_irqs);
 320 
 321         return 0;
 322 
 323 out_free_domain:
 324         irq_domain_remove(data->domain);
 325 out_free_l1_data:
 326         kfree(data->l1_data);
 327 out_unmap:
 328         for (idx = 0; idx < MAX_MAPPINGS; idx++) {
 329                 if (data->map_base[idx])
 330                         iounmap(data->map_base[idx]);
 331         }
 332         kfree(data);
 333         return ret;
 334 }
 335 
 336 static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
 337                                              struct device_node *parent)
 338 {
 339         return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
 340                                      "BCM7120 L2");
 341 }
 342 
 343 static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
 344                                              struct device_node *parent)
 345 {
 346         return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
 347                                      "BCM3380 L2");
 348 }
 349 
 350 IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
 351                 bcm7120_l2_intc_probe_7120);
 352 
 353 IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
 354                 bcm7120_l2_intc_probe_3380);