drivers/irqchip/irq-brcmstb-l2.c

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This source file includes following definitions.
brcmstb_l2_mask_and_ack
brcmstb_l2_intc_irq_handle
brcmstb_l2_intc_suspend
brcmstb_l2_intc_resume
brcmstb_l2_intc_of_init
brcmstb_l2_edge_intc_of_init
brcmstb_l2_lvl_intc_of_init
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
   4  *
   5  * Copyright (C) 2014-2017 Broadcom
   6  */
   7 
   8 #define pr_fmt(fmt)     KBUILD_MODNAME  ": " fmt
   9 
  10 #include <linux/init.h>
  11 #include <linux/slab.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/of.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/io.h>
  22 #include <linux/irqdomain.h>
  23 #include <linux/irqchip.h>
  24 #include <linux/irqchip/chained_irq.h>
  25 
  26 struct brcmstb_intc_init_params {
  27         irq_flow_handler_t handler;
  28         int cpu_status;
  29         int cpu_clear;
  30         int cpu_mask_status;
  31         int cpu_mask_set;
  32         int cpu_mask_clear;
  33 };
  34 
  35 /* Register offsets in the L2 latched interrupt controller */
  36 static const struct brcmstb_intc_init_params l2_edge_intc_init = {
  37         .handler                = handle_edge_irq,
  38         .cpu_status             = 0x00,
  39         .cpu_clear              = 0x08,
  40         .cpu_mask_status        = 0x0c,
  41         .cpu_mask_set           = 0x10,
  42         .cpu_mask_clear         = 0x14
  43 };
  44 
  45 /* Register offsets in the L2 level interrupt controller */
  46 static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
  47         .handler                = handle_level_irq,
  48         .cpu_status             = 0x00,
  49         .cpu_clear              = -1, /* Register not present */
  50         .cpu_mask_status        = 0x04,
  51         .cpu_mask_set           = 0x08,
  52         .cpu_mask_clear         = 0x0C
  53 };
  54 
  55 /* L2 intc private data structure */
  56 struct brcmstb_l2_intc_data {
  57         struct irq_domain *domain;
  58         struct irq_chip_generic *gc;
  59         int status_offset;
  60         int mask_offset;
  61         bool can_wake;
  62         u32 saved_mask; /* for suspend/resume */
  63 };
  64 
  65 /**
  66  * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
  67  * @d: irq_data
  68  *
  69  * Chip has separate enable/disable registers instead of a single mask
  70  * register and pending interrupt is acknowledged by setting a bit.
  71  *
  72  * Note: This function is generic and could easily be added to the
  73  * generic irqchip implementation if there ever becomes a will to do so.
  74  * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
  75  *
  76  * e.g.: https://patchwork.kernel.org/patch/9831047/
  77  */
  78 static void brcmstb_l2_mask_and_ack(struct irq_data *d)
  79 {
  80         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  81         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  82         u32 mask = d->mask;
  83 
  84         irq_gc_lock(gc);
  85         irq_reg_writel(gc, mask, ct->regs.disable);
  86         *ct->mask_cache &= ~mask;
  87         irq_reg_writel(gc, mask, ct->regs.ack);
  88         irq_gc_unlock(gc);
  89 }
  90 
  91 static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
  92 {
  93         struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
  94         struct irq_chip *chip = irq_desc_get_chip(desc);
  95         unsigned int irq;
  96         u32 status;
  97 
  98         chained_irq_enter(chip, desc);
  99 
 100         status = irq_reg_readl(b->gc, b->status_offset) &
 101                 ~(irq_reg_readl(b->gc, b->mask_offset));
 102 
 103         if (status == 0) {
 104                 raw_spin_lock(&desc->lock);
 105                 handle_bad_irq(desc);
 106                 raw_spin_unlock(&desc->lock);
 107                 goto out;
 108         }
 109 
 110         do {
 111                 irq = ffs(status) - 1;
 112                 status &= ~(1 << irq);
 113                 generic_handle_irq(irq_linear_revmap(b->domain, irq));
 114         } while (status);
 115 out:
 116         chained_irq_exit(chip, desc);
 117 }
 118 
 119 static void brcmstb_l2_intc_suspend(struct irq_data *d)
 120 {
 121         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 122         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 123         struct brcmstb_l2_intc_data *b = gc->private;
 124         unsigned long flags;
 125 
 126         irq_gc_lock_irqsave(gc, flags);
 127         /* Save the current mask */
 128         b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
 129 
 130         if (b->can_wake) {
 131                 /* Program the wakeup mask */
 132                 irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
 133                 irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
 134         }
 135         irq_gc_unlock_irqrestore(gc, flags);
 136 }
 137 
 138 static void brcmstb_l2_intc_resume(struct irq_data *d)
 139 {
 140         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 141         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 142         struct brcmstb_l2_intc_data *b = gc->private;
 143         unsigned long flags;
 144 
 145         irq_gc_lock_irqsave(gc, flags);
 146         if (ct->chip.irq_ack) {
 147                 /* Clear unmasked non-wakeup interrupts */
 148                 irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
 149                                 ct->regs.ack);
 150         }
 151 
 152         /* Restore the saved mask */
 153         irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
 154         irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
 155         irq_gc_unlock_irqrestore(gc, flags);
 156 }
 157 
 158 static int __init brcmstb_l2_intc_of_init(struct device_node *np,
 159                                           struct device_node *parent,
 160                                           const struct brcmstb_intc_init_params
 161                                           *init_params)
 162 {
 163         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 164         struct brcmstb_l2_intc_data *data;
 165         struct irq_chip_type *ct;
 166         int ret;
 167         unsigned int flags;
 168         int parent_irq;
 169         void __iomem *base;
 170 
 171         data = kzalloc(sizeof(*data), GFP_KERNEL);
 172         if (!data)
 173                 return -ENOMEM;
 174 
 175         base = of_iomap(np, 0);
 176         if (!base) {
 177                 pr_err("failed to remap intc L2 registers\n");
 178                 ret = -ENOMEM;
 179                 goto out_free;
 180         }
 181 
 182         /* Disable all interrupts by default */
 183         writel(0xffffffff, base + init_params->cpu_mask_set);
 184 
 185         /* Wakeup interrupts may be retained from S5 (cold boot) */
 186         data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
 187         if (!data->can_wake && (init_params->cpu_clear >= 0))
 188                 writel(0xffffffff, base + init_params->cpu_clear);
 189 
 190         parent_irq = irq_of_parse_and_map(np, 0);
 191         if (!parent_irq) {
 192                 pr_err("failed to find parent interrupt\n");
 193                 ret = -EINVAL;
 194                 goto out_unmap;
 195         }
 196 
 197         data->domain = irq_domain_add_linear(np, 32,
 198                                 &irq_generic_chip_ops, NULL);
 199         if (!data->domain) {
 200                 ret = -ENOMEM;
 201                 goto out_unmap;
 202         }
 203 
 204         /* MIPS chips strapped for BE will automagically configure the
 205          * peripheral registers for CPU-native byte order.
 206          */
 207         flags = 0;
 208         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
 209                 flags |= IRQ_GC_BE_IO;
 210 
 211         /* Allocate a single Generic IRQ chip for this node */
 212         ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
 213                         np->full_name, init_params->handler, clr, 0, flags);
 214         if (ret) {
 215                 pr_err("failed to allocate generic irq chip\n");
 216                 goto out_free_domain;
 217         }
 218 
 219         /* Set the IRQ chaining logic */
 220         irq_set_chained_handler_and_data(parent_irq,
 221                                          brcmstb_l2_intc_irq_handle, data);
 222 
 223         data->gc = irq_get_domain_generic_chip(data->domain, 0);
 224         data->gc->reg_base = base;
 225         data->gc->private = data;
 226         data->status_offset = init_params->cpu_status;
 227         data->mask_offset = init_params->cpu_mask_status;
 228 
 229         ct = data->gc->chip_types;
 230 
 231         if (init_params->cpu_clear >= 0) {
 232                 ct->regs.ack = init_params->cpu_clear;
 233                 ct->chip.irq_ack = irq_gc_ack_set_bit;
 234                 ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
 235         } else {
 236                 /* No Ack - but still slightly more efficient to define this */
 237                 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
 238         }
 239 
 240         ct->chip.irq_mask = irq_gc_mask_disable_reg;
 241         ct->regs.disable = init_params->cpu_mask_set;
 242         ct->regs.mask = init_params->cpu_mask_status;
 243 
 244         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 245         ct->regs.enable = init_params->cpu_mask_clear;
 246 
 247         ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
 248         ct->chip.irq_resume = brcmstb_l2_intc_resume;
 249         ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;
 250 
 251         if (data->can_wake) {
 252                 /* This IRQ chip can wake the system, set all child interrupts
 253                  * in wake_enabled mask
 254                  */
 255                 data->gc->wake_enabled = 0xffffffff;
 256                 ct->chip.irq_set_wake = irq_gc_set_wake;
 257         }
 258 
 259         pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);
 260 
 261         return 0;
 262 
 263 out_free_domain:
 264         irq_domain_remove(data->domain);
 265 out_unmap:
 266         iounmap(base);
 267 out_free:
 268         kfree(data);
 269         return ret;
 270 }
 271 
 272 static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
 273         struct device_node *parent)
 274 {
 275         return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
 276 }
 277 IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
 278 
 279 static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
 280         struct device_node *parent)
 281 {
 282         return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
 283 }
 284 IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc",
 285         brcmstb_l2_lvl_intc_of_init);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/irqchip/irq-brcmstb-l2.c

DEFINITIONS
