This source file includes following definitions.
- get_its_list
- dev_event_to_col
- valid_col
- valid_vpe
- its_mask_encode
- its_encode_cmd
- its_encode_devid
- its_encode_event_id
- its_encode_phys_id
- its_encode_size
- its_encode_itt
- its_encode_valid
- its_encode_target
- its_encode_collection
- its_encode_vpeid
- its_encode_virt_id
- its_encode_db_phys_id
- its_encode_db_valid
- its_encode_seq_num
- its_encode_its_list
- its_encode_vpt_addr
- its_encode_vpt_size
- its_fixup_cmd
- its_build_mapd_cmd
- its_build_mapc_cmd
- its_build_mapti_cmd
- its_build_movi_cmd
- its_build_discard_cmd
- its_build_inv_cmd
- its_build_int_cmd
- its_build_clear_cmd
- its_build_invall_cmd
- its_build_vinvall_cmd
- its_build_vmapp_cmd
- its_build_vmapti_cmd
- its_build_vmovi_cmd
- its_build_vmovp_cmd
- its_cmd_ptr_to_offset
- its_queue_full
- its_allocate_entry
- its_post_commands
- its_flush_cmd
- its_wait_for_range_completion
- its_build_sync_cmd
- BUILD_SINGLE_CMD_FUNC
- BUILD_SINGLE_CMD_FUNC
- its_send_clear
- its_send_inv
- its_send_mapd
- its_send_mapc
- its_send_mapti
- its_send_movi
- its_send_discard
- its_send_invall
- its_send_vmapti
- its_send_vmovi
- its_send_vmapp
- its_send_vmovp
- its_send_vinvall
- its_get_event_id
- lpi_write_config
- lpi_update_config
- its_vlpi_set_doorbell
- its_mask_irq
- its_unmask_irq
- its_set_affinity
- its_irq_get_msi_base
- its_irq_compose_msi_msg
- its_irq_set_irqchip_state
- its_map_vm
- its_unmap_vm
- its_vlpi_map
- its_vlpi_get
- its_vlpi_unmap
- its_vlpi_prop_update
- its_irq_set_vcpu_affinity
- mk_lpi_range
- alloc_lpi_range
- merge_lpi_ranges
- free_lpi_range
- its_lpi_init
- its_lpi_alloc
- its_lpi_free
- gic_reset_prop_table
- its_allocate_prop_table
- its_free_prop_table
- gic_check_reserved_range
- gic_reserve_range
- its_setup_lpi_prop_table
- its_read_baser
- its_write_baser
- its_setup_baser
- its_parse_indirect_baser
- its_free_tables
- its_alloc_tables
- its_alloc_collections
- its_allocate_pending_table
- its_free_pending_table
- enabled_lpis_allowed
- allocate_lpi_tables
- its_clear_vpend_valid
- its_cpu_init_lpis
- its_cpu_init_collection
- its_cpu_init_collections
- its_find_device
- its_get_baser
- its_alloc_table_entry
- its_alloc_device_table
- its_alloc_vpe_table
- its_create_device
- its_free_device
- its_alloc_device_irq
- its_msi_prepare
- its_irq_gic_domain_alloc
- its_irq_domain_alloc
- its_irq_domain_activate
- its_irq_domain_deactivate
- its_irq_domain_free
- its_vpe_db_proxy_unmap_locked
- its_vpe_db_proxy_unmap
- its_vpe_db_proxy_map_locked
- its_vpe_db_proxy_move
- its_vpe_set_affinity
- its_vpe_schedule
- its_vpe_deschedule
- its_vpe_invall
- its_vpe_set_vcpu_affinity
- its_vpe_send_cmd
- its_vpe_send_inv
- its_vpe_mask_irq
- its_vpe_unmask_irq
- its_vpe_set_irqchip_state
- its_vpe_retrigger
- its_vpe_id_alloc
- its_vpe_id_free
- its_vpe_init
- its_vpe_teardown
- its_vpe_irq_domain_free
- its_vpe_irq_domain_alloc
- its_vpe_irq_domain_activate
- its_vpe_irq_domain_deactivate
- its_force_quiescent
- its_enable_quirk_cavium_22375
- its_enable_quirk_cavium_23144
- its_enable_quirk_qdf2400_e0065
- its_irq_get_msi_base_pre_its
- its_enable_quirk_socionext_synquacer
- its_enable_quirk_hip07_161600802
- its_enable_quirks
- its_save_disable
- its_restore_enable
- its_init_domain
- its_init_vpe_domain
- its_compute_its_list_map
- its_probe_one
- gic_rdists_supports_plpis
- redist_disable_lpis
- its_cpu_init
- its_of_probe
- acpi_get_its_numa_node
- gic_acpi_match_srat_its
- gic_acpi_parse_srat_its
- acpi_table_parse_srat_its
- acpi_its_srat_maps_free
- acpi_table_parse_srat_its
- acpi_get_its_numa_node
- acpi_its_srat_maps_free
- gic_acpi_parse_madt_its
- its_acpi_probe
- its_acpi_probe
- its_init
1
2
3
4
5
6
7 #include <linux/acpi.h>
8 #include <linux/acpi_iort.h>
9 #include <linux/bitmap.h>
10 #include <linux/cpu.h>
11 #include <linux/crash_dump.h>
12 #include <linux/delay.h>
13 #include <linux/dma-iommu.h>
14 #include <linux/efi.h>
15 #include <linux/interrupt.h>
16 #include <linux/irqdomain.h>
17 #include <linux/list.h>
18 #include <linux/log2.h>
19 #include <linux/memblock.h>
20 #include <linux/mm.h>
21 #include <linux/msi.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/percpu.h>
28 #include <linux/slab.h>
29 #include <linux/syscore_ops.h>
30
31 #include <linux/irqchip.h>
32 #include <linux/irqchip/arm-gic-v3.h>
33 #include <linux/irqchip/arm-gic-v4.h>
34
35 #include <asm/cputype.h>
36 #include <asm/exception.h>
37
38 #include "irq-gic-common.h"
39
40 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
41 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
42 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
43 #define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3)
44
45 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
46 #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
47
48 static u32 lpi_id_bits;
49
50
51
52
53
54
55 #define LPI_NRBITS lpi_id_bits
56 #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
57 #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
58
59 #define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
60
61
62
63
64
65
66 struct its_collection {
67 u64 target_address;
68 u16 col_id;
69 };
70
71
72
73
74
75 struct its_baser {
76 void *base;
77 u64 val;
78 u32 order;
79 u32 psz;
80 };
81
82 struct its_device;
83
84
85
86
87
88
89
90
91
92
93 struct its_node {
94 raw_spinlock_t lock;
95 struct mutex dev_alloc_lock;
96 struct list_head entry;
97 void __iomem *base;
98 phys_addr_t phys_base;
99 struct its_cmd_block *cmd_base;
100 struct its_cmd_block *cmd_write;
101 struct its_baser tables[GITS_BASER_NR_REGS];
102 struct its_collection *collections;
103 struct fwnode_handle *fwnode_handle;
104 u64 (*get_msi_base)(struct its_device *its_dev);
105 u64 cbaser_save;
106 u32 ctlr_save;
107 struct list_head its_device_list;
108 u64 flags;
109 unsigned long list_nr;
110 u32 ite_size;
111 u32 device_ids;
112 int numa_node;
113 unsigned int msi_domain_flags;
114 u32 pre_its_base;
115 bool is_v4;
116 int vlpi_redist_offset;
117 };
118
119 #define ITS_ITT_ALIGN SZ_256
120
121
122 #define ITS_MAX_VPEID_BITS (16)
123 #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
124
125
126 #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
127
128 struct event_lpi_map {
129 unsigned long *lpi_map;
130 u16 *col_map;
131 irq_hw_number_t lpi_base;
132 int nr_lpis;
133 struct mutex vlpi_lock;
134 struct its_vm *vm;
135 struct its_vlpi_map *vlpi_maps;
136 int nr_vlpis;
137 };
138
139
140
141
142
143
144
145 struct its_device {
146 struct list_head entry;
147 struct its_node *its;
148 struct event_lpi_map event_map;
149 void *itt;
150 u32 nr_ites;
151 u32 device_id;
152 bool shared;
153 };
154
155 static struct {
156 raw_spinlock_t lock;
157 struct its_device *dev;
158 struct its_vpe **vpes;
159 int next_victim;
160 } vpe_proxy;
161
162 static LIST_HEAD(its_nodes);
163 static DEFINE_RAW_SPINLOCK(its_lock);
164 static struct rdists *gic_rdists;
165 static struct irq_domain *its_parent;
166
167 static unsigned long its_list_map;
168 static u16 vmovp_seq_num;
169 static DEFINE_RAW_SPINLOCK(vmovp_lock);
170
171 static DEFINE_IDA(its_vpeid_ida);
172
173 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
174 #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
175 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
176 #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
177
178 static u16 get_its_list(struct its_vm *vm)
179 {
180 struct its_node *its;
181 unsigned long its_list = 0;
182
183 list_for_each_entry(its, &its_nodes, entry) {
184 if (!its->is_v4)
185 continue;
186
187 if (vm->vlpi_count[its->list_nr])
188 __set_bit(its->list_nr, &its_list);
189 }
190
191 return (u16)its_list;
192 }
193
194 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
195 u32 event)
196 {
197 struct its_node *its = its_dev->its;
198
199 return its->collections + its_dev->event_map.col_map[event];
200 }
201
202 static struct its_collection *valid_col(struct its_collection *col)
203 {
204 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
205 return NULL;
206
207 return col;
208 }
209
210 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
211 {
212 if (valid_col(its->collections + vpe->col_idx))
213 return vpe;
214
215 return NULL;
216 }
217
218
219
220
221
222 struct its_cmd_desc {
223 union {
224 struct {
225 struct its_device *dev;
226 u32 event_id;
227 } its_inv_cmd;
228
229 struct {
230 struct its_device *dev;
231 u32 event_id;
232 } its_clear_cmd;
233
234 struct {
235 struct its_device *dev;
236 u32 event_id;
237 } its_int_cmd;
238
239 struct {
240 struct its_device *dev;
241 int valid;
242 } its_mapd_cmd;
243
244 struct {
245 struct its_collection *col;
246 int valid;
247 } its_mapc_cmd;
248
249 struct {
250 struct its_device *dev;
251 u32 phys_id;
252 u32 event_id;
253 } its_mapti_cmd;
254
255 struct {
256 struct its_device *dev;
257 struct its_collection *col;
258 u32 event_id;
259 } its_movi_cmd;
260
261 struct {
262 struct its_device *dev;
263 u32 event_id;
264 } its_discard_cmd;
265
266 struct {
267 struct its_collection *col;
268 } its_invall_cmd;
269
270 struct {
271 struct its_vpe *vpe;
272 } its_vinvall_cmd;
273
274 struct {
275 struct its_vpe *vpe;
276 struct its_collection *col;
277 bool valid;
278 } its_vmapp_cmd;
279
280 struct {
281 struct its_vpe *vpe;
282 struct its_device *dev;
283 u32 virt_id;
284 u32 event_id;
285 bool db_enabled;
286 } its_vmapti_cmd;
287
288 struct {
289 struct its_vpe *vpe;
290 struct its_device *dev;
291 u32 event_id;
292 bool db_enabled;
293 } its_vmovi_cmd;
294
295 struct {
296 struct its_vpe *vpe;
297 struct its_collection *col;
298 u16 seq_num;
299 u16 its_list;
300 } its_vmovp_cmd;
301 };
302 };
303
304
305
306
307 struct its_cmd_block {
308 u64 raw_cmd[4];
309 };
310
311 #define ITS_CMD_QUEUE_SZ SZ_64K
312 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
313
314 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
315 struct its_cmd_block *,
316 struct its_cmd_desc *);
317
318 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
319 struct its_cmd_block *,
320 struct its_cmd_desc *);
321
322 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
323 {
324 u64 mask = GENMASK_ULL(h, l);
325 *raw_cmd &= ~mask;
326 *raw_cmd |= (val << l) & mask;
327 }
328
329 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
330 {
331 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
332 }
333
334 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
335 {
336 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
337 }
338
339 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
340 {
341 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
342 }
343
344 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
345 {
346 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
347 }
348
349 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
350 {
351 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
352 }
353
354 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
355 {
356 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
357 }
358
359 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
360 {
361 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
362 }
363
364 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
365 {
366 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
367 }
368
369 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
370 {
371 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
372 }
373
374 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
375 {
376 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
377 }
378
379 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
380 {
381 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
382 }
383
384 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
385 {
386 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
387 }
388
389 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
390 {
391 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
392 }
393
394 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
395 {
396 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
397 }
398
399 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
400 {
401 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
402 }
403
404 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
405 {
406 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
407 }
408
409 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
410 {
411 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
412 }
413
414 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
415 {
416
417 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
418 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
419 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
420 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
421 }
422
423 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
424 struct its_cmd_block *cmd,
425 struct its_cmd_desc *desc)
426 {
427 unsigned long itt_addr;
428 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
429
430 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
431 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
432
433 its_encode_cmd(cmd, GITS_CMD_MAPD);
434 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
435 its_encode_size(cmd, size - 1);
436 its_encode_itt(cmd, itt_addr);
437 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
438
439 its_fixup_cmd(cmd);
440
441 return NULL;
442 }
443
444 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
445 struct its_cmd_block *cmd,
446 struct its_cmd_desc *desc)
447 {
448 its_encode_cmd(cmd, GITS_CMD_MAPC);
449 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
450 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
451 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
452
453 its_fixup_cmd(cmd);
454
455 return desc->its_mapc_cmd.col;
456 }
457
458 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
459 struct its_cmd_block *cmd,
460 struct its_cmd_desc *desc)
461 {
462 struct its_collection *col;
463
464 col = dev_event_to_col(desc->its_mapti_cmd.dev,
465 desc->its_mapti_cmd.event_id);
466
467 its_encode_cmd(cmd, GITS_CMD_MAPTI);
468 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
469 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
470 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
471 its_encode_collection(cmd, col->col_id);
472
473 its_fixup_cmd(cmd);
474
475 return valid_col(col);
476 }
477
478 static struct its_collection *its_build_movi_cmd(struct its_node *its,
479 struct its_cmd_block *cmd,
480 struct its_cmd_desc *desc)
481 {
482 struct its_collection *col;
483
484 col = dev_event_to_col(desc->its_movi_cmd.dev,
485 desc->its_movi_cmd.event_id);
486
487 its_encode_cmd(cmd, GITS_CMD_MOVI);
488 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
489 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
490 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
491
492 its_fixup_cmd(cmd);
493
494 return valid_col(col);
495 }
496
497 static struct its_collection *its_build_discard_cmd(struct its_node *its,
498 struct its_cmd_block *cmd,
499 struct its_cmd_desc *desc)
500 {
501 struct its_collection *col;
502
503 col = dev_event_to_col(desc->its_discard_cmd.dev,
504 desc->its_discard_cmd.event_id);
505
506 its_encode_cmd(cmd, GITS_CMD_DISCARD);
507 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
508 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
509
510 its_fixup_cmd(cmd);
511
512 return valid_col(col);
513 }
514
515 static struct its_collection *its_build_inv_cmd(struct its_node *its,
516 struct its_cmd_block *cmd,
517 struct its_cmd_desc *desc)
518 {
519 struct its_collection *col;
520
521 col = dev_event_to_col(desc->its_inv_cmd.dev,
522 desc->its_inv_cmd.event_id);
523
524 its_encode_cmd(cmd, GITS_CMD_INV);
525 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
526 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
527
528 its_fixup_cmd(cmd);
529
530 return valid_col(col);
531 }
532
533 static struct its_collection *its_build_int_cmd(struct its_node *its,
534 struct its_cmd_block *cmd,
535 struct its_cmd_desc *desc)
536 {
537 struct its_collection *col;
538
539 col = dev_event_to_col(desc->its_int_cmd.dev,
540 desc->its_int_cmd.event_id);
541
542 its_encode_cmd(cmd, GITS_CMD_INT);
543 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
544 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
545
546 its_fixup_cmd(cmd);
547
548 return valid_col(col);
549 }
550
551 static struct its_collection *its_build_clear_cmd(struct its_node *its,
552 struct its_cmd_block *cmd,
553 struct its_cmd_desc *desc)
554 {
555 struct its_collection *col;
556
557 col = dev_event_to_col(desc->its_clear_cmd.dev,
558 desc->its_clear_cmd.event_id);
559
560 its_encode_cmd(cmd, GITS_CMD_CLEAR);
561 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
562 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
563
564 its_fixup_cmd(cmd);
565
566 return valid_col(col);
567 }
568
569 static struct its_collection *its_build_invall_cmd(struct its_node *its,
570 struct its_cmd_block *cmd,
571 struct its_cmd_desc *desc)
572 {
573 its_encode_cmd(cmd, GITS_CMD_INVALL);
574 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
575
576 its_fixup_cmd(cmd);
577
578 return NULL;
579 }
580
581 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
582 struct its_cmd_block *cmd,
583 struct its_cmd_desc *desc)
584 {
585 its_encode_cmd(cmd, GITS_CMD_VINVALL);
586 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
587
588 its_fixup_cmd(cmd);
589
590 return valid_vpe(its, desc->its_vinvall_cmd.vpe);
591 }
592
593 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
594 struct its_cmd_block *cmd,
595 struct its_cmd_desc *desc)
596 {
597 unsigned long vpt_addr;
598 u64 target;
599
600 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
601 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
602
603 its_encode_cmd(cmd, GITS_CMD_VMAPP);
604 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
605 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
606 its_encode_target(cmd, target);
607 its_encode_vpt_addr(cmd, vpt_addr);
608 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
609
610 its_fixup_cmd(cmd);
611
612 return valid_vpe(its, desc->its_vmapp_cmd.vpe);
613 }
614
615 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
616 struct its_cmd_block *cmd,
617 struct its_cmd_desc *desc)
618 {
619 u32 db;
620
621 if (desc->its_vmapti_cmd.db_enabled)
622 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
623 else
624 db = 1023;
625
626 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
627 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
628 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
629 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
630 its_encode_db_phys_id(cmd, db);
631 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
632
633 its_fixup_cmd(cmd);
634
635 return valid_vpe(its, desc->its_vmapti_cmd.vpe);
636 }
637
638 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
639 struct its_cmd_block *cmd,
640 struct its_cmd_desc *desc)
641 {
642 u32 db;
643
644 if (desc->its_vmovi_cmd.db_enabled)
645 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
646 else
647 db = 1023;
648
649 its_encode_cmd(cmd, GITS_CMD_VMOVI);
650 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
651 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
652 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
653 its_encode_db_phys_id(cmd, db);
654 its_encode_db_valid(cmd, true);
655
656 its_fixup_cmd(cmd);
657
658 return valid_vpe(its, desc->its_vmovi_cmd.vpe);
659 }
660
661 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
662 struct its_cmd_block *cmd,
663 struct its_cmd_desc *desc)
664 {
665 u64 target;
666
667 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
668 its_encode_cmd(cmd, GITS_CMD_VMOVP);
669 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
670 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
671 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
672 its_encode_target(cmd, target);
673
674 its_fixup_cmd(cmd);
675
676 return valid_vpe(its, desc->its_vmovp_cmd.vpe);
677 }
678
679 static u64 its_cmd_ptr_to_offset(struct its_node *its,
680 struct its_cmd_block *ptr)
681 {
682 return (ptr - its->cmd_base) * sizeof(*ptr);
683 }
684
685 static int its_queue_full(struct its_node *its)
686 {
687 int widx;
688 int ridx;
689
690 widx = its->cmd_write - its->cmd_base;
691 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
692
693
694 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
695 return 1;
696
697 return 0;
698 }
699
700 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
701 {
702 struct its_cmd_block *cmd;
703 u32 count = 1000000;
704
705 while (its_queue_full(its)) {
706 count--;
707 if (!count) {
708 pr_err_ratelimited("ITS queue not draining\n");
709 return NULL;
710 }
711 cpu_relax();
712 udelay(1);
713 }
714
715 cmd = its->cmd_write++;
716
717
718 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
719 its->cmd_write = its->cmd_base;
720
721
722 cmd->raw_cmd[0] = 0;
723 cmd->raw_cmd[1] = 0;
724 cmd->raw_cmd[2] = 0;
725 cmd->raw_cmd[3] = 0;
726
727 return cmd;
728 }
729
730 static struct its_cmd_block *its_post_commands(struct its_node *its)
731 {
732 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
733
734 writel_relaxed(wr, its->base + GITS_CWRITER);
735
736 return its->cmd_write;
737 }
738
739 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
740 {
741
742
743
744
745 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
746 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
747 else
748 dsb(ishst);
749 }
750
751 static int its_wait_for_range_completion(struct its_node *its,
752 u64 prev_idx,
753 struct its_cmd_block *to)
754 {
755 u64 rd_idx, to_idx, linear_idx;
756 u32 count = 1000000;
757
758
759 to_idx = its_cmd_ptr_to_offset(its, to);
760 if (to_idx < prev_idx)
761 to_idx += ITS_CMD_QUEUE_SZ;
762
763 linear_idx = prev_idx;
764
765 while (1) {
766 s64 delta;
767
768 rd_idx = readl_relaxed(its->base + GITS_CREADR);
769
770
771
772
773
774 delta = rd_idx - prev_idx;
775 if (rd_idx < prev_idx)
776 delta += ITS_CMD_QUEUE_SZ;
777
778 linear_idx += delta;
779 if (linear_idx >= to_idx)
780 break;
781
782 count--;
783 if (!count) {
784 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
785 to_idx, linear_idx);
786 return -1;
787 }
788 prev_idx = rd_idx;
789 cpu_relax();
790 udelay(1);
791 }
792
793 return 0;
794 }
795
796
797 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
798 void name(struct its_node *its, \
799 buildtype builder, \
800 struct its_cmd_desc *desc) \
801 { \
802 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
803 synctype *sync_obj; \
804 unsigned long flags; \
805 u64 rd_idx; \
806 \
807 raw_spin_lock_irqsave(&its->lock, flags); \
808 \
809 cmd = its_allocate_entry(its); \
810 if (!cmd) { \
811 raw_spin_unlock_irqrestore(&its->lock, flags); \
812 return; \
813 } \
814 sync_obj = builder(its, cmd, desc); \
815 its_flush_cmd(its, cmd); \
816 \
817 if (sync_obj) { \
818 sync_cmd = its_allocate_entry(its); \
819 if (!sync_cmd) \
820 goto post; \
821 \
822 buildfn(its, sync_cmd, sync_obj); \
823 its_flush_cmd(its, sync_cmd); \
824 } \
825 \
826 post: \
827 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
828 next_cmd = its_post_commands(its); \
829 raw_spin_unlock_irqrestore(&its->lock, flags); \
830 \
831 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
832 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
833 }
834
835 static void its_build_sync_cmd(struct its_node *its,
836 struct its_cmd_block *sync_cmd,
837 struct its_collection *sync_col)
838 {
839 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
840 its_encode_target(sync_cmd, sync_col->target_address);
841
842 its_fixup_cmd(sync_cmd);
843 }
844
845 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
846 struct its_collection, its_build_sync_cmd)
847
848 static void its_build_vsync_cmd(struct its_node *its,
849 struct its_cmd_block *sync_cmd,
850 struct its_vpe *sync_vpe)
851 {
852 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
853 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
854
855 its_fixup_cmd(sync_cmd);
856 }
857
858 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
859 struct its_vpe, its_build_vsync_cmd)
860
861 static void its_send_int(struct its_device *dev, u32 event_id)
862 {
863 struct its_cmd_desc desc;
864
865 desc.its_int_cmd.dev = dev;
866 desc.its_int_cmd.event_id = event_id;
867
868 its_send_single_command(dev->its, its_build_int_cmd, &desc);
869 }
870
871 static void its_send_clear(struct its_device *dev, u32 event_id)
872 {
873 struct its_cmd_desc desc;
874
875 desc.its_clear_cmd.dev = dev;
876 desc.its_clear_cmd.event_id = event_id;
877
878 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
879 }
880
881 static void its_send_inv(struct its_device *dev, u32 event_id)
882 {
883 struct its_cmd_desc desc;
884
885 desc.its_inv_cmd.dev = dev;
886 desc.its_inv_cmd.event_id = event_id;
887
888 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
889 }
890
891 static void its_send_mapd(struct its_device *dev, int valid)
892 {
893 struct its_cmd_desc desc;
894
895 desc.its_mapd_cmd.dev = dev;
896 desc.its_mapd_cmd.valid = !!valid;
897
898 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
899 }
900
901 static void its_send_mapc(struct its_node *its, struct its_collection *col,
902 int valid)
903 {
904 struct its_cmd_desc desc;
905
906 desc.its_mapc_cmd.col = col;
907 desc.its_mapc_cmd.valid = !!valid;
908
909 its_send_single_command(its, its_build_mapc_cmd, &desc);
910 }
911
912 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
913 {
914 struct its_cmd_desc desc;
915
916 desc.its_mapti_cmd.dev = dev;
917 desc.its_mapti_cmd.phys_id = irq_id;
918 desc.its_mapti_cmd.event_id = id;
919
920 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
921 }
922
923 static void its_send_movi(struct its_device *dev,
924 struct its_collection *col, u32 id)
925 {
926 struct its_cmd_desc desc;
927
928 desc.its_movi_cmd.dev = dev;
929 desc.its_movi_cmd.col = col;
930 desc.its_movi_cmd.event_id = id;
931
932 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
933 }
934
935 static void its_send_discard(struct its_device *dev, u32 id)
936 {
937 struct its_cmd_desc desc;
938
939 desc.its_discard_cmd.dev = dev;
940 desc.its_discard_cmd.event_id = id;
941
942 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
943 }
944
945 static void its_send_invall(struct its_node *its, struct its_collection *col)
946 {
947 struct its_cmd_desc desc;
948
949 desc.its_invall_cmd.col = col;
950
951 its_send_single_command(its, its_build_invall_cmd, &desc);
952 }
953
954 static void its_send_vmapti(struct its_device *dev, u32 id)
955 {
956 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
957 struct its_cmd_desc desc;
958
959 desc.its_vmapti_cmd.vpe = map->vpe;
960 desc.its_vmapti_cmd.dev = dev;
961 desc.its_vmapti_cmd.virt_id = map->vintid;
962 desc.its_vmapti_cmd.event_id = id;
963 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
964
965 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
966 }
967
968 static void its_send_vmovi(struct its_device *dev, u32 id)
969 {
970 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
971 struct its_cmd_desc desc;
972
973 desc.its_vmovi_cmd.vpe = map->vpe;
974 desc.its_vmovi_cmd.dev = dev;
975 desc.its_vmovi_cmd.event_id = id;
976 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
977
978 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
979 }
980
981 static void its_send_vmapp(struct its_node *its,
982 struct its_vpe *vpe, bool valid)
983 {
984 struct its_cmd_desc desc;
985
986 desc.its_vmapp_cmd.vpe = vpe;
987 desc.its_vmapp_cmd.valid = valid;
988 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
989
990 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
991 }
992
993 static void its_send_vmovp(struct its_vpe *vpe)
994 {
995 struct its_cmd_desc desc = {};
996 struct its_node *its;
997 unsigned long flags;
998 int col_id = vpe->col_idx;
999
1000 desc.its_vmovp_cmd.vpe = vpe;
1001
1002 if (!its_list_map) {
1003 its = list_first_entry(&its_nodes, struct its_node, entry);
1004 desc.its_vmovp_cmd.col = &its->collections[col_id];
1005 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1006 return;
1007 }
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017 raw_spin_lock_irqsave(&vmovp_lock, flags);
1018
1019 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1020 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1021
1022
1023 list_for_each_entry(its, &its_nodes, entry) {
1024 if (!its->is_v4)
1025 continue;
1026
1027 if (!vpe->its_vm->vlpi_count[its->list_nr])
1028 continue;
1029
1030 desc.its_vmovp_cmd.col = &its->collections[col_id];
1031 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1032 }
1033
1034 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1035 }
1036
1037 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1038 {
1039 struct its_cmd_desc desc;
1040
1041 desc.its_vinvall_cmd.vpe = vpe;
1042 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1043 }
1044
1045
1046
1047
1048
1049 static inline u32 its_get_event_id(struct irq_data *d)
1050 {
1051 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1052 return d->hwirq - its_dev->event_map.lpi_base;
1053 }
1054
1055 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1056 {
1057 irq_hw_number_t hwirq;
1058 void *va;
1059 u8 *cfg;
1060
1061 if (irqd_is_forwarded_to_vcpu(d)) {
1062 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1063 u32 event = its_get_event_id(d);
1064 struct its_vlpi_map *map;
1065
1066 va = page_address(its_dev->event_map.vm->vprop_page);
1067 map = &its_dev->event_map.vlpi_maps[event];
1068 hwirq = map->vintid;
1069
1070
1071 map->properties &= ~clr;
1072 map->properties |= set | LPI_PROP_GROUP1;
1073 } else {
1074 va = gic_rdists->prop_table_va;
1075 hwirq = d->hwirq;
1076 }
1077
1078 cfg = va + hwirq - 8192;
1079 *cfg &= ~clr;
1080 *cfg |= set | LPI_PROP_GROUP1;
1081
1082
1083
1084
1085
1086
1087 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1088 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1089 else
1090 dsb(ishst);
1091 }
1092
1093 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1094 {
1095 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1096
1097 lpi_write_config(d, clr, set);
1098 its_send_inv(its_dev, its_get_event_id(d));
1099 }
1100
1101 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1102 {
1103 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1104 u32 event = its_get_event_id(d);
1105
1106 if (its_dev->event_map.vlpi_maps[event].db_enabled == enable)
1107 return;
1108
1109 its_dev->event_map.vlpi_maps[event].db_enabled = enable;
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121 its_send_vmovi(its_dev, event);
1122 }
1123
1124 static void its_mask_irq(struct irq_data *d)
1125 {
1126 if (irqd_is_forwarded_to_vcpu(d))
1127 its_vlpi_set_doorbell(d, false);
1128
1129 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1130 }
1131
1132 static void its_unmask_irq(struct irq_data *d)
1133 {
1134 if (irqd_is_forwarded_to_vcpu(d))
1135 its_vlpi_set_doorbell(d, true);
1136
1137 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1138 }
1139
1140 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1141 bool force)
1142 {
1143 unsigned int cpu;
1144 const struct cpumask *cpu_mask = cpu_online_mask;
1145 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1146 struct its_collection *target_col;
1147 u32 id = its_get_event_id(d);
1148
1149
1150 if (irqd_is_forwarded_to_vcpu(d))
1151 return -EINVAL;
1152
1153
1154 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1155 if (its_dev->its->numa_node >= 0) {
1156 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1157 if (!cpumask_intersects(mask_val, cpu_mask))
1158 return -EINVAL;
1159 }
1160 }
1161
1162 cpu = cpumask_any_and(mask_val, cpu_mask);
1163
1164 if (cpu >= nr_cpu_ids)
1165 return -EINVAL;
1166
1167
1168 if (cpu != its_dev->event_map.col_map[id]) {
1169 target_col = &its_dev->its->collections[cpu];
1170 its_send_movi(its_dev, target_col, id);
1171 its_dev->event_map.col_map[id] = cpu;
1172 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1173 }
1174
1175 return IRQ_SET_MASK_OK_DONE;
1176 }
1177
1178 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1179 {
1180 struct its_node *its = its_dev->its;
1181
1182 return its->phys_base + GITS_TRANSLATER;
1183 }
1184
1185 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1186 {
1187 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1188 struct its_node *its;
1189 u64 addr;
1190
1191 its = its_dev->its;
1192 addr = its->get_msi_base(its_dev);
1193
1194 msg->address_lo = lower_32_bits(addr);
1195 msg->address_hi = upper_32_bits(addr);
1196 msg->data = its_get_event_id(d);
1197
1198 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1199 }
1200
1201 static int its_irq_set_irqchip_state(struct irq_data *d,
1202 enum irqchip_irq_state which,
1203 bool state)
1204 {
1205 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1206 u32 event = its_get_event_id(d);
1207
1208 if (which != IRQCHIP_STATE_PENDING)
1209 return -EINVAL;
1210
1211 if (state)
1212 its_send_int(its_dev, event);
1213 else
1214 its_send_clear(its_dev, event);
1215
1216 return 0;
1217 }
1218
1219 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1220 {
1221 unsigned long flags;
1222
1223
1224 if (!its_list_map)
1225 return;
1226
1227 raw_spin_lock_irqsave(&vmovp_lock, flags);
1228
1229
1230
1231
1232
1233 vm->vlpi_count[its->list_nr]++;
1234
1235 if (vm->vlpi_count[its->list_nr] == 1) {
1236 int i;
1237
1238 for (i = 0; i < vm->nr_vpes; i++) {
1239 struct its_vpe *vpe = vm->vpes[i];
1240 struct irq_data *d = irq_get_irq_data(vpe->irq);
1241
1242
1243 vpe->col_idx = cpumask_first(cpu_online_mask);
1244 its_send_vmapp(its, vpe, true);
1245 its_send_vinvall(its, vpe);
1246 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1247 }
1248 }
1249
1250 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1251 }
1252
1253 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1254 {
1255 unsigned long flags;
1256
1257
1258 if (!its_list_map)
1259 return;
1260
1261 raw_spin_lock_irqsave(&vmovp_lock, flags);
1262
1263 if (!--vm->vlpi_count[its->list_nr]) {
1264 int i;
1265
1266 for (i = 0; i < vm->nr_vpes; i++)
1267 its_send_vmapp(its, vm->vpes[i], false);
1268 }
1269
1270 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1271 }
1272
1273 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1274 {
1275 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1276 u32 event = its_get_event_id(d);
1277 int ret = 0;
1278
1279 if (!info->map)
1280 return -EINVAL;
1281
1282 mutex_lock(&its_dev->event_map.vlpi_lock);
1283
1284 if (!its_dev->event_map.vm) {
1285 struct its_vlpi_map *maps;
1286
1287 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1288 GFP_KERNEL);
1289 if (!maps) {
1290 ret = -ENOMEM;
1291 goto out;
1292 }
1293
1294 its_dev->event_map.vm = info->map->vm;
1295 its_dev->event_map.vlpi_maps = maps;
1296 } else if (its_dev->event_map.vm != info->map->vm) {
1297 ret = -EINVAL;
1298 goto out;
1299 }
1300
1301
1302 its_dev->event_map.vlpi_maps[event] = *info->map;
1303
1304 if (irqd_is_forwarded_to_vcpu(d)) {
1305
1306 its_send_vmovi(its_dev, event);
1307 } else {
1308
1309 its_map_vm(its_dev->its, info->map->vm);
1310
1311
1312
1313
1314
1315 irqd_set_forwarded_to_vcpu(d);
1316
1317
1318 lpi_write_config(d, 0xff, info->map->properties);
1319
1320
1321 its_send_discard(its_dev, event);
1322
1323
1324 its_send_vmapti(its_dev, event);
1325
1326
1327 its_dev->event_map.nr_vlpis++;
1328 }
1329
1330 out:
1331 mutex_unlock(&its_dev->event_map.vlpi_lock);
1332 return ret;
1333 }
1334
1335 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1336 {
1337 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1338 u32 event = its_get_event_id(d);
1339 int ret = 0;
1340
1341 mutex_lock(&its_dev->event_map.vlpi_lock);
1342
1343 if (!its_dev->event_map.vm ||
1344 !its_dev->event_map.vlpi_maps[event].vm) {
1345 ret = -EINVAL;
1346 goto out;
1347 }
1348
1349
1350 *info->map = its_dev->event_map.vlpi_maps[event];
1351
1352 out:
1353 mutex_unlock(&its_dev->event_map.vlpi_lock);
1354 return ret;
1355 }
1356
1357 static int its_vlpi_unmap(struct irq_data *d)
1358 {
1359 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1360 u32 event = its_get_event_id(d);
1361 int ret = 0;
1362
1363 mutex_lock(&its_dev->event_map.vlpi_lock);
1364
1365 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1366 ret = -EINVAL;
1367 goto out;
1368 }
1369
1370
1371 its_send_discard(its_dev, event);
1372
1373
1374 irqd_clr_forwarded_to_vcpu(d);
1375 its_send_mapti(its_dev, d->hwirq, event);
1376 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1377 LPI_PROP_ENABLED |
1378 LPI_PROP_GROUP1));
1379
1380
1381 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1382
1383
1384
1385
1386
1387 if (!--its_dev->event_map.nr_vlpis) {
1388 its_dev->event_map.vm = NULL;
1389 kfree(its_dev->event_map.vlpi_maps);
1390 }
1391
1392 out:
1393 mutex_unlock(&its_dev->event_map.vlpi_lock);
1394 return ret;
1395 }
1396
1397 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1398 {
1399 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1400
1401 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1402 return -EINVAL;
1403
1404 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1405 lpi_update_config(d, 0xff, info->config);
1406 else
1407 lpi_write_config(d, 0xff, info->config);
1408 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1409
1410 return 0;
1411 }
1412
1413 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1414 {
1415 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1416 struct its_cmd_info *info = vcpu_info;
1417
1418
1419 if (!its_dev->its->is_v4)
1420 return -EINVAL;
1421
1422
1423 if (!info)
1424 return its_vlpi_unmap(d);
1425
1426 switch (info->cmd_type) {
1427 case MAP_VLPI:
1428 return its_vlpi_map(d, info);
1429
1430 case GET_VLPI:
1431 return its_vlpi_get(d, info);
1432
1433 case PROP_UPDATE_VLPI:
1434 case PROP_UPDATE_AND_INV_VLPI:
1435 return its_vlpi_prop_update(d, info);
1436
1437 default:
1438 return -EINVAL;
1439 }
1440 }
1441
1442 static struct irq_chip its_irq_chip = {
1443 .name = "ITS",
1444 .irq_mask = its_mask_irq,
1445 .irq_unmask = its_unmask_irq,
1446 .irq_eoi = irq_chip_eoi_parent,
1447 .irq_set_affinity = its_set_affinity,
1448 .irq_compose_msi_msg = its_irq_compose_msi_msg,
1449 .irq_set_irqchip_state = its_irq_set_irqchip_state,
1450 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
1451 };
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469 #define ITS_MAX_LPI_NRBITS 16
1470
1471 static DEFINE_MUTEX(lpi_range_lock);
1472 static LIST_HEAD(lpi_range_list);
1473
1474 struct lpi_range {
1475 struct list_head entry;
1476 u32 base_id;
1477 u32 span;
1478 };
1479
1480 static struct lpi_range *mk_lpi_range(u32 base, u32 span)
1481 {
1482 struct lpi_range *range;
1483
1484 range = kmalloc(sizeof(*range), GFP_KERNEL);
1485 if (range) {
1486 range->base_id = base;
1487 range->span = span;
1488 }
1489
1490 return range;
1491 }
1492
1493 static int alloc_lpi_range(u32 nr_lpis, u32 *base)
1494 {
1495 struct lpi_range *range, *tmp;
1496 int err = -ENOSPC;
1497
1498 mutex_lock(&lpi_range_lock);
1499
1500 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
1501 if (range->span >= nr_lpis) {
1502 *base = range->base_id;
1503 range->base_id += nr_lpis;
1504 range->span -= nr_lpis;
1505
1506 if (range->span == 0) {
1507 list_del(&range->entry);
1508 kfree(range);
1509 }
1510
1511 err = 0;
1512 break;
1513 }
1514 }
1515
1516 mutex_unlock(&lpi_range_lock);
1517
1518 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
1519 return err;
1520 }
1521
1522 static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
1523 {
1524 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
1525 return;
1526 if (a->base_id + a->span != b->base_id)
1527 return;
1528 b->base_id = a->base_id;
1529 b->span += a->span;
1530 list_del(&a->entry);
1531 kfree(a);
1532 }
1533
1534 static int free_lpi_range(u32 base, u32 nr_lpis)
1535 {
1536 struct lpi_range *new, *old;
1537
1538 new = mk_lpi_range(base, nr_lpis);
1539 if (!new)
1540 return -ENOMEM;
1541
1542 mutex_lock(&lpi_range_lock);
1543
1544 list_for_each_entry_reverse(old, &lpi_range_list, entry) {
1545 if (old->base_id < base)
1546 break;
1547 }
1548
1549
1550
1551
1552
1553
1554
1555 list_add(&new->entry, &old->entry);
1556
1557
1558
1559
1560 merge_lpi_ranges(old, new);
1561 merge_lpi_ranges(new, list_next_entry(new, entry));
1562
1563 mutex_unlock(&lpi_range_lock);
1564 return 0;
1565 }
1566
1567 static int __init its_lpi_init(u32 id_bits)
1568 {
1569 u32 lpis = (1UL << id_bits) - 8192;
1570 u32 numlpis;
1571 int err;
1572
1573 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
1574
1575 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
1576 lpis = numlpis;
1577 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
1578 lpis);
1579 }
1580
1581
1582
1583
1584
1585 err = free_lpi_range(8192, lpis);
1586 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
1587 return err;
1588 }
1589
1590 static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
1591 {
1592 unsigned long *bitmap = NULL;
1593 int err = 0;
1594
1595 do {
1596 err = alloc_lpi_range(nr_irqs, base);
1597 if (!err)
1598 break;
1599
1600 nr_irqs /= 2;
1601 } while (nr_irqs > 0);
1602
1603 if (!nr_irqs)
1604 err = -ENOSPC;
1605
1606 if (err)
1607 goto out;
1608
1609 bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
1610 if (!bitmap)
1611 goto out;
1612
1613 *nr_ids = nr_irqs;
1614
1615 out:
1616 if (!bitmap)
1617 *base = *nr_ids = 0;
1618
1619 return bitmap;
1620 }
1621
1622 static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
1623 {
1624 WARN_ON(free_lpi_range(base, nr_ids));
1625 kfree(bitmap);
1626 }
1627
1628 static void gic_reset_prop_table(void *va)
1629 {
1630
1631 memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
1632
1633
1634 gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
1635 }
1636
1637 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
1638 {
1639 struct page *prop_page;
1640
1641 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
1642 if (!prop_page)
1643 return NULL;
1644
1645 gic_reset_prop_table(page_address(prop_page));
1646
1647 return prop_page;
1648 }
1649
1650 static void its_free_prop_table(struct page *prop_page)
1651 {
1652 free_pages((unsigned long)page_address(prop_page),
1653 get_order(LPI_PROPBASE_SZ));
1654 }
1655
1656 static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
1657 {
1658 phys_addr_t start, end, addr_end;
1659 u64 i;
1660
1661
1662
1663
1664
1665
1666 if (is_kdump_kernel())
1667 return true;
1668
1669 addr_end = addr + size - 1;
1670
1671 for_each_reserved_mem_region(i, &start, &end) {
1672 if (addr >= start && addr_end <= end)
1673 return true;
1674 }
1675
1676
1677 pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
1678 &addr, &addr_end);
1679 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
1680 return false;
1681 }
1682
1683 static int gic_reserve_range(phys_addr_t addr, unsigned long size)
1684 {
1685 if (efi_enabled(EFI_CONFIG_TABLES))
1686 return efi_mem_reserve_persistent(addr, size);
1687
1688 return 0;
1689 }
1690
1691 static int __init its_setup_lpi_prop_table(void)
1692 {
1693 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
1694 u64 val;
1695
1696 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
1697 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
1698
1699 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
1700 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
1701 LPI_PROPBASE_SZ,
1702 MEMREMAP_WB);
1703 gic_reset_prop_table(gic_rdists->prop_table_va);
1704 } else {
1705 struct page *page;
1706
1707 lpi_id_bits = min_t(u32,
1708 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
1709 ITS_MAX_LPI_NRBITS);
1710 page = its_allocate_prop_table(GFP_NOWAIT);
1711 if (!page) {
1712 pr_err("Failed to allocate PROPBASE\n");
1713 return -ENOMEM;
1714 }
1715
1716 gic_rdists->prop_table_pa = page_to_phys(page);
1717 gic_rdists->prop_table_va = page_address(page);
1718 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
1719 LPI_PROPBASE_SZ));
1720 }
1721
1722 pr_info("GICv3: using LPI property table @%pa\n",
1723 &gic_rdists->prop_table_pa);
1724
1725 return its_lpi_init(lpi_id_bits);
1726 }
1727
1728 static const char *its_base_type_string[] = {
1729 [GITS_BASER_TYPE_DEVICE] = "Devices",
1730 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
1731 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
1732 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
1733 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
1734 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
1735 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
1736 };
1737
1738 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
1739 {
1740 u32 idx = baser - its->tables;
1741
1742 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
1743 }
1744
1745 static void its_write_baser(struct its_node *its, struct its_baser *baser,
1746 u64 val)
1747 {
1748 u32 idx = baser - its->tables;
1749
1750 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
1751 baser->val = its_read_baser(its, baser);
1752 }
1753
1754 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
1755 u64 cache, u64 shr, u32 psz, u32 order,
1756 bool indirect)
1757 {
1758 u64 val = its_read_baser(its, baser);
1759 u64 esz = GITS_BASER_ENTRY_SIZE(val);
1760 u64 type = GITS_BASER_TYPE(val);
1761 u64 baser_phys, tmp;
1762 u32 alloc_pages;
1763 struct page *page;
1764 void *base;
1765
1766 retry_alloc_baser:
1767 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
1768 if (alloc_pages > GITS_BASER_PAGES_MAX) {
1769 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
1770 &its->phys_base, its_base_type_string[type],
1771 alloc_pages, GITS_BASER_PAGES_MAX);
1772 alloc_pages = GITS_BASER_PAGES_MAX;
1773 order = get_order(GITS_BASER_PAGES_MAX * psz);
1774 }
1775
1776 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
1777 if (!page)
1778 return -ENOMEM;
1779
1780 base = (void *)page_address(page);
1781 baser_phys = virt_to_phys(base);
1782
1783
1784 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
1785
1786
1787 if (psz != SZ_64K) {
1788 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
1789 free_pages((unsigned long)base, order);
1790 return -ENXIO;
1791 }
1792
1793
1794 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
1795 }
1796
1797 retry_baser:
1798 val = (baser_phys |
1799 (type << GITS_BASER_TYPE_SHIFT) |
1800 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
1801 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
1802 cache |
1803 shr |
1804 GITS_BASER_VALID);
1805
1806 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
1807
1808 switch (psz) {
1809 case SZ_4K:
1810 val |= GITS_BASER_PAGE_SIZE_4K;
1811 break;
1812 case SZ_16K:
1813 val |= GITS_BASER_PAGE_SIZE_16K;
1814 break;
1815 case SZ_64K:
1816 val |= GITS_BASER_PAGE_SIZE_64K;
1817 break;
1818 }
1819
1820 its_write_baser(its, baser, val);
1821 tmp = baser->val;
1822
1823 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
1824
1825
1826
1827
1828
1829
1830
1831 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
1832 if (!shr) {
1833 cache = GITS_BASER_nC;
1834 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
1835 }
1836 goto retry_baser;
1837 }
1838
1839 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
1840
1841
1842
1843
1844
1845 free_pages((unsigned long)base, order);
1846 baser->base = NULL;
1847
1848 switch (psz) {
1849 case SZ_16K:
1850 psz = SZ_4K;
1851 goto retry_alloc_baser;
1852 case SZ_64K:
1853 psz = SZ_16K;
1854 goto retry_alloc_baser;
1855 }
1856 }
1857
1858 if (val != tmp) {
1859 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
1860 &its->phys_base, its_base_type_string[type],
1861 val, tmp);
1862 free_pages((unsigned long)base, order);
1863 return -ENXIO;
1864 }
1865
1866 baser->order = order;
1867 baser->base = base;
1868 baser->psz = psz;
1869 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
1870
1871 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
1872 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
1873 its_base_type_string[type],
1874 (unsigned long)virt_to_phys(base),
1875 indirect ? "indirect" : "flat", (int)esz,
1876 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
1877
1878 return 0;
1879 }
1880
1881 static bool its_parse_indirect_baser(struct its_node *its,
1882 struct its_baser *baser,
1883 u32 psz, u32 *order, u32 ids)
1884 {
1885 u64 tmp = its_read_baser(its, baser);
1886 u64 type = GITS_BASER_TYPE(tmp);
1887 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
1888 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
1889 u32 new_order = *order;
1890 bool indirect = false;
1891
1892
1893 if ((esz << ids) > (psz * 2)) {
1894
1895
1896
1897
1898 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
1899 indirect = !!(baser->val & GITS_BASER_INDIRECT);
1900
1901 if (indirect) {
1902
1903
1904
1905
1906
1907
1908
1909 ids -= ilog2(psz / (int)esz);
1910 esz = GITS_LVL1_ENTRY_SIZE;
1911 }
1912 }
1913
1914
1915
1916
1917
1918
1919
1920
1921 new_order = max_t(u32, get_order(esz << ids), new_order);
1922 if (new_order >= MAX_ORDER) {
1923 new_order = MAX_ORDER - 1;
1924 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
1925 pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n",
1926 &its->phys_base, its_base_type_string[type],
1927 its->device_ids, ids);
1928 }
1929
1930 *order = new_order;
1931
1932 return indirect;
1933 }
1934
1935 static void its_free_tables(struct its_node *its)
1936 {
1937 int i;
1938
1939 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1940 if (its->tables[i].base) {
1941 free_pages((unsigned long)its->tables[i].base,
1942 its->tables[i].order);
1943 its->tables[i].base = NULL;
1944 }
1945 }
1946 }
1947
1948 static int its_alloc_tables(struct its_node *its)
1949 {
1950 u64 shr = GITS_BASER_InnerShareable;
1951 u64 cache = GITS_BASER_RaWaWb;
1952 u32 psz = SZ_64K;
1953 int err, i;
1954
1955 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
1956
1957 cache = GITS_BASER_nCnB;
1958
1959 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1960 struct its_baser *baser = its->tables + i;
1961 u64 val = its_read_baser(its, baser);
1962 u64 type = GITS_BASER_TYPE(val);
1963 u32 order = get_order(psz);
1964 bool indirect = false;
1965
1966 switch (type) {
1967 case GITS_BASER_TYPE_NONE:
1968 continue;
1969
1970 case GITS_BASER_TYPE_DEVICE:
1971 indirect = its_parse_indirect_baser(its, baser,
1972 psz, &order,
1973 its->device_ids);
1974 break;
1975
1976 case GITS_BASER_TYPE_VCPU:
1977 indirect = its_parse_indirect_baser(its, baser,
1978 psz, &order,
1979 ITS_MAX_VPEID_BITS);
1980 break;
1981 }
1982
1983 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
1984 if (err < 0) {
1985 its_free_tables(its);
1986 return err;
1987 }
1988
1989
1990 psz = baser->psz;
1991 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
1992 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
1993 }
1994
1995 return 0;
1996 }
1997
1998 static int its_alloc_collections(struct its_node *its)
1999 {
2000 int i;
2001
2002 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
2003 GFP_KERNEL);
2004 if (!its->collections)
2005 return -ENOMEM;
2006
2007 for (i = 0; i < nr_cpu_ids; i++)
2008 its->collections[i].target_address = ~0ULL;
2009
2010 return 0;
2011 }
2012
2013 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2014 {
2015 struct page *pend_page;
2016
2017 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2018 get_order(LPI_PENDBASE_SZ));
2019 if (!pend_page)
2020 return NULL;
2021
2022
2023 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2024
2025 return pend_page;
2026 }
2027
2028 static void its_free_pending_table(struct page *pt)
2029 {
2030 free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2031 }
2032
2033
2034
2035
2036
2037 static bool enabled_lpis_allowed(void)
2038 {
2039 phys_addr_t addr;
2040 u64 val;
2041
2042
2043 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2044 addr = val & GENMASK_ULL(51, 12);
2045
2046 return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2047 }
2048
2049 static int __init allocate_lpi_tables(void)
2050 {
2051 u64 val;
2052 int err, cpu;
2053
2054
2055
2056
2057
2058 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2059 if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2060 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2061 RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2062 pr_info("GICv3: Using preallocated redistributor tables\n");
2063 }
2064
2065 err = its_setup_lpi_prop_table();
2066 if (err)
2067 return err;
2068
2069
2070
2071
2072
2073
2074 for_each_possible_cpu(cpu) {
2075 struct page *pend_page;
2076
2077 pend_page = its_allocate_pending_table(GFP_NOWAIT);
2078 if (!pend_page) {
2079 pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
2080 return -ENOMEM;
2081 }
2082
2083 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
2084 }
2085
2086 return 0;
2087 }
2088
2089 static u64 its_clear_vpend_valid(void __iomem *vlpi_base)
2090 {
2091 u32 count = 1000000;
2092 bool clean;
2093 u64 val;
2094
2095 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2096 val &= ~GICR_VPENDBASER_Valid;
2097 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2098
2099 do {
2100 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2101 clean = !(val & GICR_VPENDBASER_Dirty);
2102 if (!clean) {
2103 count--;
2104 cpu_relax();
2105 udelay(1);
2106 }
2107 } while (!clean && count);
2108
2109 return val;
2110 }
2111
2112 static void its_cpu_init_lpis(void)
2113 {
2114 void __iomem *rbase = gic_data_rdist_rd_base();
2115 struct page *pend_page;
2116 phys_addr_t paddr;
2117 u64 val, tmp;
2118
2119 if (gic_data_rdist()->lpi_enabled)
2120 return;
2121
2122 val = readl_relaxed(rbase + GICR_CTLR);
2123 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
2124 (val & GICR_CTLR_ENABLE_LPIS)) {
2125
2126
2127
2128
2129 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
2130 paddr &= GENMASK_ULL(51, 12);
2131 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
2132 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2133
2134 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2135 paddr &= GENMASK_ULL(51, 16);
2136
2137 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
2138 its_free_pending_table(gic_data_rdist()->pend_page);
2139 gic_data_rdist()->pend_page = NULL;
2140
2141 goto out;
2142 }
2143
2144 pend_page = gic_data_rdist()->pend_page;
2145 paddr = page_to_phys(pend_page);
2146 WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
2147
2148
2149 val = (gic_rdists->prop_table_pa |
2150 GICR_PROPBASER_InnerShareable |
2151 GICR_PROPBASER_RaWaWb |
2152 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
2153
2154 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2155 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
2156
2157 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
2158 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
2159
2160
2161
2162
2163
2164 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
2165 GICR_PROPBASER_CACHEABILITY_MASK);
2166 val |= GICR_PROPBASER_nC;
2167 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2168 }
2169 pr_info_once("GIC: using cache flushing for LPI property table\n");
2170 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
2171 }
2172
2173
2174 val = (page_to_phys(pend_page) |
2175 GICR_PENDBASER_InnerShareable |
2176 GICR_PENDBASER_RaWaWb);
2177
2178 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2179 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2180
2181 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
2182
2183
2184
2185
2186 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
2187 GICR_PENDBASER_CACHEABILITY_MASK);
2188 val |= GICR_PENDBASER_nC;
2189 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2190 }
2191
2192
2193 val = readl_relaxed(rbase + GICR_CTLR);
2194 val |= GICR_CTLR_ENABLE_LPIS;
2195 writel_relaxed(val, rbase + GICR_CTLR);
2196
2197 if (gic_rdists->has_vlpis) {
2198 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2199
2200
2201
2202
2203
2204
2205
2206
2207 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2208 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
2209 smp_processor_id(), val);
2210 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2211
2212
2213
2214
2215
2216
2217 val = its_clear_vpend_valid(vlpi_base);
2218 WARN_ON(val & GICR_VPENDBASER_Dirty);
2219 }
2220
2221
2222 dsb(sy);
2223 out:
2224 gic_data_rdist()->lpi_enabled = true;
2225 pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
2226 smp_processor_id(),
2227 gic_data_rdist()->pend_page ? "allocated" : "reserved",
2228 &paddr);
2229 }
2230
2231 static void its_cpu_init_collection(struct its_node *its)
2232 {
2233 int cpu = smp_processor_id();
2234 u64 target;
2235
2236
2237 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
2238 struct device_node *cpu_node;
2239
2240 cpu_node = of_get_cpu_node(cpu, NULL);
2241 if (its->numa_node != NUMA_NO_NODE &&
2242 its->numa_node != of_node_to_nid(cpu_node))
2243 return;
2244 }
2245
2246
2247
2248
2249
2250 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
2251
2252
2253
2254
2255 target = gic_data_rdist()->phys_base;
2256 } else {
2257
2258 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2259 target = GICR_TYPER_CPU_NUMBER(target) << 16;
2260 }
2261
2262
2263 its->collections[cpu].target_address = target;
2264 its->collections[cpu].col_id = cpu;
2265
2266 its_send_mapc(its, &its->collections[cpu], 1);
2267 its_send_invall(its, &its->collections[cpu]);
2268 }
2269
2270 static void its_cpu_init_collections(void)
2271 {
2272 struct its_node *its;
2273
2274 raw_spin_lock(&its_lock);
2275
2276 list_for_each_entry(its, &its_nodes, entry)
2277 its_cpu_init_collection(its);
2278
2279 raw_spin_unlock(&its_lock);
2280 }
2281
2282 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
2283 {
2284 struct its_device *its_dev = NULL, *tmp;
2285 unsigned long flags;
2286
2287 raw_spin_lock_irqsave(&its->lock, flags);
2288
2289 list_for_each_entry(tmp, &its->its_device_list, entry) {
2290 if (tmp->device_id == dev_id) {
2291 its_dev = tmp;
2292 break;
2293 }
2294 }
2295
2296 raw_spin_unlock_irqrestore(&its->lock, flags);
2297
2298 return its_dev;
2299 }
2300
2301 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
2302 {
2303 int i;
2304
2305 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2306 if (GITS_BASER_TYPE(its->tables[i].val) == type)
2307 return &its->tables[i];
2308 }
2309
2310 return NULL;
2311 }
2312
2313 static bool its_alloc_table_entry(struct its_node *its,
2314 struct its_baser *baser, u32 id)
2315 {
2316 struct page *page;
2317 u32 esz, idx;
2318 __le64 *table;
2319
2320
2321 esz = GITS_BASER_ENTRY_SIZE(baser->val);
2322 if (!(baser->val & GITS_BASER_INDIRECT))
2323 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
2324
2325
2326 idx = id >> ilog2(baser->psz / esz);
2327 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
2328 return false;
2329
2330 table = baser->base;
2331
2332
2333 if (!table[idx]) {
2334 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
2335 get_order(baser->psz));
2336 if (!page)
2337 return false;
2338
2339
2340 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2341 gic_flush_dcache_to_poc(page_address(page), baser->psz);
2342
2343 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2344
2345
2346 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2347 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2348
2349
2350 dsb(sy);
2351 }
2352
2353 return true;
2354 }
2355
2356 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
2357 {
2358 struct its_baser *baser;
2359
2360 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
2361
2362
2363 if (!baser)
2364 return (ilog2(dev_id) < its->device_ids);
2365
2366 return its_alloc_table_entry(its, baser, dev_id);
2367 }
2368
2369 static bool its_alloc_vpe_table(u32 vpe_id)
2370 {
2371 struct its_node *its;
2372
2373
2374
2375
2376
2377
2378
2379
2380 list_for_each_entry(its, &its_nodes, entry) {
2381 struct its_baser *baser;
2382
2383 if (!its->is_v4)
2384 continue;
2385
2386 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
2387 if (!baser)
2388 return false;
2389
2390 if (!its_alloc_table_entry(its, baser, vpe_id))
2391 return false;
2392 }
2393
2394 return true;
2395 }
2396
2397 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2398 int nvecs, bool alloc_lpis)
2399 {
2400 struct its_device *dev;
2401 unsigned long *lpi_map = NULL;
2402 unsigned long flags;
2403 u16 *col_map = NULL;
2404 void *itt;
2405 int lpi_base;
2406 int nr_lpis;
2407 int nr_ites;
2408 int sz;
2409
2410 if (!its_alloc_device_table(its, dev_id))
2411 return NULL;
2412
2413 if (WARN_ON(!is_power_of_2(nvecs)))
2414 nvecs = roundup_pow_of_two(nvecs);
2415
2416 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2417
2418
2419
2420
2421 nr_ites = max(2, nvecs);
2422 sz = nr_ites * its->ite_size;
2423 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
2424 itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
2425 if (alloc_lpis) {
2426 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
2427 if (lpi_map)
2428 col_map = kcalloc(nr_lpis, sizeof(*col_map),
2429 GFP_KERNEL);
2430 } else {
2431 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
2432 nr_lpis = 0;
2433 lpi_base = 0;
2434 }
2435
2436 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
2437 kfree(dev);
2438 kfree(itt);
2439 kfree(lpi_map);
2440 kfree(col_map);
2441 return NULL;
2442 }
2443
2444 gic_flush_dcache_to_poc(itt, sz);
2445
2446 dev->its = its;
2447 dev->itt = itt;
2448 dev->nr_ites = nr_ites;
2449 dev->event_map.lpi_map = lpi_map;
2450 dev->event_map.col_map = col_map;
2451 dev->event_map.lpi_base = lpi_base;
2452 dev->event_map.nr_lpis = nr_lpis;
2453 mutex_init(&dev->event_map.vlpi_lock);
2454 dev->device_id = dev_id;
2455 INIT_LIST_HEAD(&dev->entry);
2456
2457 raw_spin_lock_irqsave(&its->lock, flags);
2458 list_add(&dev->entry, &its->its_device_list);
2459 raw_spin_unlock_irqrestore(&its->lock, flags);
2460
2461
2462 its_send_mapd(dev, 1);
2463
2464 return dev;
2465 }
2466
2467 static void its_free_device(struct its_device *its_dev)
2468 {
2469 unsigned long flags;
2470
2471 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
2472 list_del(&its_dev->entry);
2473 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
2474 kfree(its_dev->itt);
2475 kfree(its_dev);
2476 }
2477
2478 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
2479 {
2480 int idx;
2481
2482
2483 idx = bitmap_find_free_region(dev->event_map.lpi_map,
2484 dev->event_map.nr_lpis,
2485 get_count_order(nvecs));
2486 if (idx < 0)
2487 return -ENOSPC;
2488
2489 *hwirq = dev->event_map.lpi_base + idx;
2490
2491 return 0;
2492 }
2493
2494 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
2495 int nvec, msi_alloc_info_t *info)
2496 {
2497 struct its_node *its;
2498 struct its_device *its_dev;
2499 struct msi_domain_info *msi_info;
2500 u32 dev_id;
2501 int err = 0;
2502
2503
2504
2505
2506
2507
2508
2509 dev_id = info->scratchpad[0].ul;
2510
2511 msi_info = msi_get_domain_info(domain);
2512 its = msi_info->data;
2513
2514 if (!gic_rdists->has_direct_lpi &&
2515 vpe_proxy.dev &&
2516 vpe_proxy.dev->its == its &&
2517 dev_id == vpe_proxy.dev->device_id) {
2518
2519 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
2520 dev_id);
2521 return -EINVAL;
2522 }
2523
2524 mutex_lock(&its->dev_alloc_lock);
2525 its_dev = its_find_device(its, dev_id);
2526 if (its_dev) {
2527
2528
2529
2530
2531
2532 its_dev->shared = true;
2533 pr_debug("Reusing ITT for devID %x\n", dev_id);
2534 goto out;
2535 }
2536
2537 its_dev = its_create_device(its, dev_id, nvec, true);
2538 if (!its_dev) {
2539 err = -ENOMEM;
2540 goto out;
2541 }
2542
2543 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
2544 out:
2545 mutex_unlock(&its->dev_alloc_lock);
2546 info->scratchpad[0].ptr = its_dev;
2547 return err;
2548 }
2549
2550 static struct msi_domain_ops its_msi_domain_ops = {
2551 .msi_prepare = its_msi_prepare,
2552 };
2553
2554 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
2555 unsigned int virq,
2556 irq_hw_number_t hwirq)
2557 {
2558 struct irq_fwspec fwspec;
2559
2560 if (irq_domain_get_of_node(domain->parent)) {
2561 fwspec.fwnode = domain->parent->fwnode;
2562 fwspec.param_count = 3;
2563 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
2564 fwspec.param[1] = hwirq;
2565 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
2566 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
2567 fwspec.fwnode = domain->parent->fwnode;
2568 fwspec.param_count = 2;
2569 fwspec.param[0] = hwirq;
2570 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2571 } else {
2572 return -EINVAL;
2573 }
2574
2575 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
2576 }
2577
2578 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2579 unsigned int nr_irqs, void *args)
2580 {
2581 msi_alloc_info_t *info = args;
2582 struct its_device *its_dev = info->scratchpad[0].ptr;
2583 struct its_node *its = its_dev->its;
2584 irq_hw_number_t hwirq;
2585 int err;
2586 int i;
2587
2588 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
2589 if (err)
2590 return err;
2591
2592 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
2593 if (err)
2594 return err;
2595
2596 for (i = 0; i < nr_irqs; i++) {
2597 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
2598 if (err)
2599 return err;
2600
2601 irq_domain_set_hwirq_and_chip(domain, virq + i,
2602 hwirq + i, &its_irq_chip, its_dev);
2603 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i)));
2604 pr_debug("ID:%d pID:%d vID:%d\n",
2605 (int)(hwirq + i - its_dev->event_map.lpi_base),
2606 (int)(hwirq + i), virq + i);
2607 }
2608
2609 return 0;
2610 }
2611
2612 static int its_irq_domain_activate(struct irq_domain *domain,
2613 struct irq_data *d, bool reserve)
2614 {
2615 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2616 u32 event = its_get_event_id(d);
2617 const struct cpumask *cpu_mask = cpu_online_mask;
2618 int cpu;
2619
2620
2621 if (its_dev->its->numa_node >= 0)
2622 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
2623
2624
2625 cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
2626 if (cpu >= nr_cpu_ids) {
2627 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
2628 return -EINVAL;
2629
2630 cpu = cpumask_first(cpu_online_mask);
2631 }
2632
2633 its_dev->event_map.col_map[event] = cpu;
2634 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2635
2636
2637 its_send_mapti(its_dev, d->hwirq, event);
2638 return 0;
2639 }
2640
2641 static void its_irq_domain_deactivate(struct irq_domain *domain,
2642 struct irq_data *d)
2643 {
2644 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2645 u32 event = its_get_event_id(d);
2646
2647
2648 its_send_discard(its_dev, event);
2649 }
2650
2651 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2652 unsigned int nr_irqs)
2653 {
2654 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
2655 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2656 struct its_node *its = its_dev->its;
2657 int i;
2658
2659 bitmap_release_region(its_dev->event_map.lpi_map,
2660 its_get_event_id(irq_domain_get_irq_data(domain, virq)),
2661 get_count_order(nr_irqs));
2662
2663 for (i = 0; i < nr_irqs; i++) {
2664 struct irq_data *data = irq_domain_get_irq_data(domain,
2665 virq + i);
2666
2667 irq_domain_reset_irq_data(data);
2668 }
2669
2670 mutex_lock(&its->dev_alloc_lock);
2671
2672
2673
2674
2675
2676 if (!its_dev->shared &&
2677 bitmap_empty(its_dev->event_map.lpi_map,
2678 its_dev->event_map.nr_lpis)) {
2679 its_lpi_free(its_dev->event_map.lpi_map,
2680 its_dev->event_map.lpi_base,
2681 its_dev->event_map.nr_lpis);
2682 kfree(its_dev->event_map.col_map);
2683
2684
2685 its_send_mapd(its_dev, 0);
2686 its_free_device(its_dev);
2687 }
2688
2689 mutex_unlock(&its->dev_alloc_lock);
2690
2691 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2692 }
2693
2694 static const struct irq_domain_ops its_domain_ops = {
2695 .alloc = its_irq_domain_alloc,
2696 .free = its_irq_domain_free,
2697 .activate = its_irq_domain_activate,
2698 .deactivate = its_irq_domain_deactivate,
2699 };
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
2714 {
2715
2716 if (vpe->vpe_proxy_event == -1)
2717 return;
2718
2719 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
2720 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
2721
2722
2723
2724
2725
2726
2727
2728
2729 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2730 vpe_proxy.next_victim = vpe->vpe_proxy_event;
2731
2732 vpe->vpe_proxy_event = -1;
2733 }
2734
2735 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
2736 {
2737 if (!gic_rdists->has_direct_lpi) {
2738 unsigned long flags;
2739
2740 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2741 its_vpe_db_proxy_unmap_locked(vpe);
2742 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2743 }
2744 }
2745
2746 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
2747 {
2748
2749 if (vpe->vpe_proxy_event != -1)
2750 return;
2751
2752
2753 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2754 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
2755
2756
2757 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
2758 vpe->vpe_proxy_event = vpe_proxy.next_victim;
2759 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
2760
2761 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
2762 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
2763 }
2764
2765 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
2766 {
2767 unsigned long flags;
2768 struct its_collection *target_col;
2769
2770 if (gic_rdists->has_direct_lpi) {
2771 void __iomem *rdbase;
2772
2773 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
2774 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2775 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2776 cpu_relax();
2777
2778 return;
2779 }
2780
2781 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2782
2783 its_vpe_db_proxy_map_locked(vpe);
2784
2785 target_col = &vpe_proxy.dev->its->collections[to];
2786 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
2787 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
2788
2789 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2790 }
2791
2792 static int its_vpe_set_affinity(struct irq_data *d,
2793 const struct cpumask *mask_val,
2794 bool force)
2795 {
2796 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2797 int cpu = cpumask_first(mask_val);
2798
2799
2800
2801
2802
2803
2804
2805 if (vpe->col_idx != cpu) {
2806 int from = vpe->col_idx;
2807
2808 vpe->col_idx = cpu;
2809 its_send_vmovp(vpe);
2810 its_vpe_db_proxy_move(vpe, from, cpu);
2811 }
2812
2813 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2814
2815 return IRQ_SET_MASK_OK_DONE;
2816 }
2817
2818 static void its_vpe_schedule(struct its_vpe *vpe)
2819 {
2820 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2821 u64 val;
2822
2823
2824 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
2825 GENMASK_ULL(51, 12);
2826 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2827 val |= GICR_VPROPBASER_RaWb;
2828 val |= GICR_VPROPBASER_InnerShareable;
2829 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2830
2831 val = virt_to_phys(page_address(vpe->vpt_page)) &
2832 GENMASK_ULL(51, 16);
2833 val |= GICR_VPENDBASER_RaWaWb;
2834 val |= GICR_VPENDBASER_NonShareable;
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844 val |= GICR_VPENDBASER_PendingLast;
2845 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
2846 val |= GICR_VPENDBASER_Valid;
2847 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2848 }
2849
2850 static void its_vpe_deschedule(struct its_vpe *vpe)
2851 {
2852 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2853 u64 val;
2854
2855 val = its_clear_vpend_valid(vlpi_base);
2856
2857 if (unlikely(val & GICR_VPENDBASER_Dirty)) {
2858 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
2859 vpe->idai = false;
2860 vpe->pending_last = true;
2861 } else {
2862 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
2863 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
2864 }
2865 }
2866
2867 static void its_vpe_invall(struct its_vpe *vpe)
2868 {
2869 struct its_node *its;
2870
2871 list_for_each_entry(its, &its_nodes, entry) {
2872 if (!its->is_v4)
2873 continue;
2874
2875 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
2876 continue;
2877
2878
2879
2880
2881
2882 its_send_vinvall(its, vpe);
2883 return;
2884 }
2885 }
2886
2887 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
2888 {
2889 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2890 struct its_cmd_info *info = vcpu_info;
2891
2892 switch (info->cmd_type) {
2893 case SCHEDULE_VPE:
2894 its_vpe_schedule(vpe);
2895 return 0;
2896
2897 case DESCHEDULE_VPE:
2898 its_vpe_deschedule(vpe);
2899 return 0;
2900
2901 case INVALL_VPE:
2902 its_vpe_invall(vpe);
2903 return 0;
2904
2905 default:
2906 return -EINVAL;
2907 }
2908 }
2909
2910 static void its_vpe_send_cmd(struct its_vpe *vpe,
2911 void (*cmd)(struct its_device *, u32))
2912 {
2913 unsigned long flags;
2914
2915 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2916
2917 its_vpe_db_proxy_map_locked(vpe);
2918 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
2919
2920 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2921 }
2922
2923 static void its_vpe_send_inv(struct irq_data *d)
2924 {
2925 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2926
2927 if (gic_rdists->has_direct_lpi) {
2928 void __iomem *rdbase;
2929
2930 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2931 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR);
2932 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2933 cpu_relax();
2934 } else {
2935 its_vpe_send_cmd(vpe, its_send_inv);
2936 }
2937 }
2938
2939 static void its_vpe_mask_irq(struct irq_data *d)
2940 {
2941
2942
2943
2944
2945
2946
2947 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
2948 its_vpe_send_inv(d);
2949 }
2950
2951 static void its_vpe_unmask_irq(struct irq_data *d)
2952 {
2953
2954 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
2955 its_vpe_send_inv(d);
2956 }
2957
2958 static int its_vpe_set_irqchip_state(struct irq_data *d,
2959 enum irqchip_irq_state which,
2960 bool state)
2961 {
2962 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2963
2964 if (which != IRQCHIP_STATE_PENDING)
2965 return -EINVAL;
2966
2967 if (gic_rdists->has_direct_lpi) {
2968 void __iomem *rdbase;
2969
2970 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2971 if (state) {
2972 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
2973 } else {
2974 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2975 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2976 cpu_relax();
2977 }
2978 } else {
2979 if (state)
2980 its_vpe_send_cmd(vpe, its_send_int);
2981 else
2982 its_vpe_send_cmd(vpe, its_send_clear);
2983 }
2984
2985 return 0;
2986 }
2987
2988 static int its_vpe_retrigger(struct irq_data *d)
2989 {
2990 return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
2991 }
2992
2993 static struct irq_chip its_vpe_irq_chip = {
2994 .name = "GICv4-vpe",
2995 .irq_mask = its_vpe_mask_irq,
2996 .irq_unmask = its_vpe_unmask_irq,
2997 .irq_eoi = irq_chip_eoi_parent,
2998 .irq_set_affinity = its_vpe_set_affinity,
2999 .irq_retrigger = its_vpe_retrigger,
3000 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
3001 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
3002 };
3003
3004 static int its_vpe_id_alloc(void)
3005 {
3006 return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
3007 }
3008
3009 static void its_vpe_id_free(u16 id)
3010 {
3011 ida_simple_remove(&its_vpeid_ida, id);
3012 }
3013
3014 static int its_vpe_init(struct its_vpe *vpe)
3015 {
3016 struct page *vpt_page;
3017 int vpe_id;
3018
3019
3020 vpe_id = its_vpe_id_alloc();
3021 if (vpe_id < 0)
3022 return vpe_id;
3023
3024
3025 vpt_page = its_allocate_pending_table(GFP_KERNEL);
3026 if (!vpt_page) {
3027 its_vpe_id_free(vpe_id);
3028 return -ENOMEM;
3029 }
3030
3031 if (!its_alloc_vpe_table(vpe_id)) {
3032 its_vpe_id_free(vpe_id);
3033 its_free_pending_table(vpt_page);
3034 return -ENOMEM;
3035 }
3036
3037 vpe->vpe_id = vpe_id;
3038 vpe->vpt_page = vpt_page;
3039 vpe->vpe_proxy_event = -1;
3040
3041 return 0;
3042 }
3043
3044 static void its_vpe_teardown(struct its_vpe *vpe)
3045 {
3046 its_vpe_db_proxy_unmap(vpe);
3047 its_vpe_id_free(vpe->vpe_id);
3048 its_free_pending_table(vpe->vpt_page);
3049 }
3050
3051 static void its_vpe_irq_domain_free(struct irq_domain *domain,
3052 unsigned int virq,
3053 unsigned int nr_irqs)
3054 {
3055 struct its_vm *vm = domain->host_data;
3056 int i;
3057
3058 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3059
3060 for (i = 0; i < nr_irqs; i++) {
3061 struct irq_data *data = irq_domain_get_irq_data(domain,
3062 virq + i);
3063 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
3064
3065 BUG_ON(vm != vpe->its_vm);
3066
3067 clear_bit(data->hwirq, vm->db_bitmap);
3068 its_vpe_teardown(vpe);
3069 irq_domain_reset_irq_data(data);
3070 }
3071
3072 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
3073 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
3074 its_free_prop_table(vm->vprop_page);
3075 }
3076 }
3077
3078 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3079 unsigned int nr_irqs, void *args)
3080 {
3081 struct its_vm *vm = args;
3082 unsigned long *bitmap;
3083 struct page *vprop_page;
3084 int base, nr_ids, i, err = 0;
3085
3086 BUG_ON(!vm);
3087
3088 bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
3089 if (!bitmap)
3090 return -ENOMEM;
3091
3092 if (nr_ids < nr_irqs) {
3093 its_lpi_free(bitmap, base, nr_ids);
3094 return -ENOMEM;
3095 }
3096
3097 vprop_page = its_allocate_prop_table(GFP_KERNEL);
3098 if (!vprop_page) {
3099 its_lpi_free(bitmap, base, nr_ids);
3100 return -ENOMEM;
3101 }
3102
3103 vm->db_bitmap = bitmap;
3104 vm->db_lpi_base = base;
3105 vm->nr_db_lpis = nr_ids;
3106 vm->vprop_page = vprop_page;
3107
3108 for (i = 0; i < nr_irqs; i++) {
3109 vm->vpes[i]->vpe_db_lpi = base + i;
3110 err = its_vpe_init(vm->vpes[i]);
3111 if (err)
3112 break;
3113 err = its_irq_gic_domain_alloc(domain, virq + i,
3114 vm->vpes[i]->vpe_db_lpi);
3115 if (err)
3116 break;
3117 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
3118 &its_vpe_irq_chip, vm->vpes[i]);
3119 set_bit(i, bitmap);
3120 }
3121
3122 if (err) {
3123 if (i > 0)
3124 its_vpe_irq_domain_free(domain, virq, i - 1);
3125
3126 its_lpi_free(bitmap, base, nr_ids);
3127 its_free_prop_table(vprop_page);
3128 }
3129
3130 return err;
3131 }
3132
3133 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
3134 struct irq_data *d, bool reserve)
3135 {
3136 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3137 struct its_node *its;
3138
3139
3140 if (its_list_map)
3141 return 0;
3142
3143
3144 vpe->col_idx = cpumask_first(cpu_online_mask);
3145
3146 list_for_each_entry(its, &its_nodes, entry) {
3147 if (!its->is_v4)
3148 continue;
3149
3150 its_send_vmapp(its, vpe, true);
3151 its_send_vinvall(its, vpe);
3152 }
3153
3154 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
3155
3156 return 0;
3157 }
3158
3159 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
3160 struct irq_data *d)
3161 {
3162 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3163 struct its_node *its;
3164
3165
3166
3167
3168
3169 if (its_list_map)
3170 return;
3171
3172 list_for_each_entry(its, &its_nodes, entry) {
3173 if (!its->is_v4)
3174 continue;
3175
3176 its_send_vmapp(its, vpe, false);
3177 }
3178 }
3179
3180 static const struct irq_domain_ops its_vpe_domain_ops = {
3181 .alloc = its_vpe_irq_domain_alloc,
3182 .free = its_vpe_irq_domain_free,
3183 .activate = its_vpe_irq_domain_activate,
3184 .deactivate = its_vpe_irq_domain_deactivate,
3185 };
3186
3187 static int its_force_quiescent(void __iomem *base)
3188 {
3189 u32 count = 1000000;
3190 u32 val;
3191
3192 val = readl_relaxed(base + GITS_CTLR);
3193
3194
3195
3196
3197
3198 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
3199 return 0;
3200
3201
3202 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
3203 writel_relaxed(val, base + GITS_CTLR);
3204
3205
3206 while (1) {
3207 val = readl_relaxed(base + GITS_CTLR);
3208 if (val & GITS_CTLR_QUIESCENT)
3209 return 0;
3210
3211 count--;
3212 if (!count)
3213 return -EBUSY;
3214
3215 cpu_relax();
3216 udelay(1);
3217 }
3218 }
3219
3220 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
3221 {
3222 struct its_node *its = data;
3223
3224
3225 its->device_ids = 0x14;
3226 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
3227
3228 return true;
3229 }
3230
3231 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
3232 {
3233 struct its_node *its = data;
3234
3235 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
3236
3237 return true;
3238 }
3239
3240 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
3241 {
3242 struct its_node *its = data;
3243
3244
3245 its->ite_size = 16;
3246
3247 return true;
3248 }
3249
3250 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
3251 {
3252 struct its_node *its = its_dev->its;
3253
3254
3255
3256
3257
3258
3259
3260
3261 return its->pre_its_base + (its_dev->device_id << 2);
3262 }
3263
3264 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
3265 {
3266 struct its_node *its = data;
3267 u32 pre_its_window[2];
3268 u32 ids;
3269
3270 if (!fwnode_property_read_u32_array(its->fwnode_handle,
3271 "socionext,synquacer-pre-its",
3272 pre_its_window,
3273 ARRAY_SIZE(pre_its_window))) {
3274
3275 its->pre_its_base = pre_its_window[0];
3276 its->get_msi_base = its_irq_get_msi_base_pre_its;
3277
3278 ids = ilog2(pre_its_window[1]) - 2;
3279 if (its->device_ids > ids)
3280 its->device_ids = ids;
3281
3282
3283 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
3284 return true;
3285 }
3286 return false;
3287 }
3288
3289 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
3290 {
3291 struct its_node *its = data;
3292
3293
3294
3295
3296
3297 its->vlpi_redist_offset = SZ_128K;
3298 return true;
3299 }
3300
3301 static const struct gic_quirk its_quirks[] = {
3302 #ifdef CONFIG_CAVIUM_ERRATUM_22375
3303 {
3304 .desc = "ITS: Cavium errata 22375, 24313",
3305 .iidr = 0xa100034c,
3306 .mask = 0xffff0fff,
3307 .init = its_enable_quirk_cavium_22375,
3308 },
3309 #endif
3310 #ifdef CONFIG_CAVIUM_ERRATUM_23144
3311 {
3312 .desc = "ITS: Cavium erratum 23144",
3313 .iidr = 0xa100034c,
3314 .mask = 0xffff0fff,
3315 .init = its_enable_quirk_cavium_23144,
3316 },
3317 #endif
3318 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
3319 {
3320 .desc = "ITS: QDF2400 erratum 0065",
3321 .iidr = 0x00001070,
3322 .mask = 0xffffffff,
3323 .init = its_enable_quirk_qdf2400_e0065,
3324 },
3325 #endif
3326 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
3327 {
3328
3329
3330
3331
3332
3333 .desc = "ITS: Socionext Synquacer pre-ITS",
3334 .iidr = 0x0001143b,
3335 .mask = 0xffffffff,
3336 .init = its_enable_quirk_socionext_synquacer,
3337 },
3338 #endif
3339 #ifdef CONFIG_HISILICON_ERRATUM_161600802
3340 {
3341 .desc = "ITS: Hip07 erratum 161600802",
3342 .iidr = 0x00000004,
3343 .mask = 0xffffffff,
3344 .init = its_enable_quirk_hip07_161600802,
3345 },
3346 #endif
3347 {
3348 }
3349 };
3350
3351 static void its_enable_quirks(struct its_node *its)
3352 {
3353 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
3354
3355 gic_enable_quirks(iidr, its_quirks, its);
3356 }
3357
3358 static int its_save_disable(void)
3359 {
3360 struct its_node *its;
3361 int err = 0;
3362
3363 raw_spin_lock(&its_lock);
3364 list_for_each_entry(its, &its_nodes, entry) {
3365 void __iomem *base;
3366
3367 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3368 continue;
3369
3370 base = its->base;
3371 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
3372 err = its_force_quiescent(base);
3373 if (err) {
3374 pr_err("ITS@%pa: failed to quiesce: %d\n",
3375 &its->phys_base, err);
3376 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3377 goto err;
3378 }
3379
3380 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
3381 }
3382
3383 err:
3384 if (err) {
3385 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
3386 void __iomem *base;
3387
3388 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3389 continue;
3390
3391 base = its->base;
3392 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3393 }
3394 }
3395 raw_spin_unlock(&its_lock);
3396
3397 return err;
3398 }
3399
3400 static void its_restore_enable(void)
3401 {
3402 struct its_node *its;
3403 int ret;
3404
3405 raw_spin_lock(&its_lock);
3406 list_for_each_entry(its, &its_nodes, entry) {
3407 void __iomem *base;
3408 int i;
3409
3410 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3411 continue;
3412
3413 base = its->base;
3414
3415
3416
3417
3418
3419
3420
3421 ret = its_force_quiescent(base);
3422 if (ret) {
3423 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
3424 &its->phys_base, ret);
3425 continue;
3426 }
3427
3428 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
3429
3430
3431
3432
3433
3434 its->cmd_write = its->cmd_base;
3435 gits_write_cwriter(0, base + GITS_CWRITER);
3436
3437
3438 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3439 struct its_baser *baser = &its->tables[i];
3440
3441 if (!(baser->val & GITS_BASER_VALID))
3442 continue;
3443
3444 its_write_baser(its, baser, baser->val);
3445 }
3446 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3447
3448
3449
3450
3451
3452
3453 if (its->collections[smp_processor_id()].col_id <
3454 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
3455 its_cpu_init_collection(its);
3456 }
3457 raw_spin_unlock(&its_lock);
3458 }
3459
3460 static struct syscore_ops its_syscore_ops = {
3461 .suspend = its_save_disable,
3462 .resume = its_restore_enable,
3463 };
3464
3465 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
3466 {
3467 struct irq_domain *inner_domain;
3468 struct msi_domain_info *info;
3469
3470 info = kzalloc(sizeof(*info), GFP_KERNEL);
3471 if (!info)
3472 return -ENOMEM;
3473
3474 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
3475 if (!inner_domain) {
3476 kfree(info);
3477 return -ENOMEM;
3478 }
3479
3480 inner_domain->parent = its_parent;
3481 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
3482 inner_domain->flags |= its->msi_domain_flags;
3483 info->ops = &its_msi_domain_ops;
3484 info->data = its;
3485 inner_domain->host_data = info;
3486
3487 return 0;
3488 }
3489
3490 static int its_init_vpe_domain(void)
3491 {
3492 struct its_node *its;
3493 u32 devid;
3494 int entries;
3495
3496 if (gic_rdists->has_direct_lpi) {
3497 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
3498 return 0;
3499 }
3500
3501
3502 its = list_first_entry(&its_nodes, struct its_node, entry);
3503
3504 entries = roundup_pow_of_two(nr_cpu_ids);
3505 vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
3506 GFP_KERNEL);
3507 if (!vpe_proxy.vpes) {
3508 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
3509 return -ENOMEM;
3510 }
3511
3512
3513 devid = GENMASK(its->device_ids - 1, 0);
3514 vpe_proxy.dev = its_create_device(its, devid, entries, false);
3515 if (!vpe_proxy.dev) {
3516 kfree(vpe_proxy.vpes);
3517 pr_err("ITS: Can't allocate GICv4 proxy device\n");
3518 return -ENOMEM;
3519 }
3520
3521 BUG_ON(entries > vpe_proxy.dev->nr_ites);
3522
3523 raw_spin_lock_init(&vpe_proxy.lock);
3524 vpe_proxy.next_victim = 0;
3525 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
3526 devid, vpe_proxy.dev->nr_ites);
3527
3528 return 0;
3529 }
3530
3531 static int __init its_compute_its_list_map(struct resource *res,
3532 void __iomem *its_base)
3533 {
3534 int its_number;
3535 u32 ctlr;
3536
3537
3538
3539
3540
3541
3542
3543 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
3544 if (its_number >= GICv4_ITS_LIST_MAX) {
3545 pr_err("ITS@%pa: No ITSList entry available!\n",
3546 &res->start);
3547 return -EINVAL;
3548 }
3549
3550 ctlr = readl_relaxed(its_base + GITS_CTLR);
3551 ctlr &= ~GITS_CTLR_ITS_NUMBER;
3552 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
3553 writel_relaxed(ctlr, its_base + GITS_CTLR);
3554 ctlr = readl_relaxed(its_base + GITS_CTLR);
3555 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
3556 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
3557 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
3558 }
3559
3560 if (test_and_set_bit(its_number, &its_list_map)) {
3561 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
3562 &res->start, its_number);
3563 return -EINVAL;
3564 }
3565
3566 return its_number;
3567 }
3568
3569 static int __init its_probe_one(struct resource *res,
3570 struct fwnode_handle *handle, int numa_node)
3571 {
3572 struct its_node *its;
3573 void __iomem *its_base;
3574 u32 val, ctlr;
3575 u64 baser, tmp, typer;
3576 struct page *page;
3577 int err;
3578
3579 its_base = ioremap(res->start, resource_size(res));
3580 if (!its_base) {
3581 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
3582 return -ENOMEM;
3583 }
3584
3585 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
3586 if (val != 0x30 && val != 0x40) {
3587 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
3588 err = -ENODEV;
3589 goto out_unmap;
3590 }
3591
3592 err = its_force_quiescent(its_base);
3593 if (err) {
3594 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
3595 goto out_unmap;
3596 }
3597
3598 pr_info("ITS %pR\n", res);
3599
3600 its = kzalloc(sizeof(*its), GFP_KERNEL);
3601 if (!its) {
3602 err = -ENOMEM;
3603 goto out_unmap;
3604 }
3605
3606 raw_spin_lock_init(&its->lock);
3607 mutex_init(&its->dev_alloc_lock);
3608 INIT_LIST_HEAD(&its->entry);
3609 INIT_LIST_HEAD(&its->its_device_list);
3610 typer = gic_read_typer(its_base + GITS_TYPER);
3611 its->base = its_base;
3612 its->phys_base = res->start;
3613 its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer);
3614 its->device_ids = GITS_TYPER_DEVBITS(typer);
3615 its->is_v4 = !!(typer & GITS_TYPER_VLPIS);
3616 if (its->is_v4) {
3617 if (!(typer & GITS_TYPER_VMOVP)) {
3618 err = its_compute_its_list_map(res, its_base);
3619 if (err < 0)
3620 goto out_free_its;
3621
3622 its->list_nr = err;
3623
3624 pr_info("ITS@%pa: Using ITS number %d\n",
3625 &res->start, err);
3626 } else {
3627 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
3628 }
3629 }
3630
3631 its->numa_node = numa_node;
3632
3633 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3634 get_order(ITS_CMD_QUEUE_SZ));
3635 if (!page) {
3636 err = -ENOMEM;
3637 goto out_free_its;
3638 }
3639 its->cmd_base = (void *)page_address(page);
3640 its->cmd_write = its->cmd_base;
3641 its->fwnode_handle = handle;
3642 its->get_msi_base = its_irq_get_msi_base;
3643 its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
3644
3645 its_enable_quirks(its);
3646
3647 err = its_alloc_tables(its);
3648 if (err)
3649 goto out_free_cmd;
3650
3651 err = its_alloc_collections(its);
3652 if (err)
3653 goto out_free_tables;
3654
3655 baser = (virt_to_phys(its->cmd_base) |
3656 GITS_CBASER_RaWaWb |
3657 GITS_CBASER_InnerShareable |
3658 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
3659 GITS_CBASER_VALID);
3660
3661 gits_write_cbaser(baser, its->base + GITS_CBASER);
3662 tmp = gits_read_cbaser(its->base + GITS_CBASER);
3663
3664 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
3665 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
3666
3667
3668
3669
3670
3671 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
3672 GITS_CBASER_CACHEABILITY_MASK);
3673 baser |= GITS_CBASER_nC;
3674 gits_write_cbaser(baser, its->base + GITS_CBASER);
3675 }
3676 pr_info("ITS: using cache flushing for cmd queue\n");
3677 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
3678 }
3679
3680 gits_write_cwriter(0, its->base + GITS_CWRITER);
3681 ctlr = readl_relaxed(its->base + GITS_CTLR);
3682 ctlr |= GITS_CTLR_ENABLE;
3683 if (its->is_v4)
3684 ctlr |= GITS_CTLR_ImDe;
3685 writel_relaxed(ctlr, its->base + GITS_CTLR);
3686
3687 if (GITS_TYPER_HCC(typer))
3688 its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE;
3689
3690 err = its_init_domain(handle, its);
3691 if (err)
3692 goto out_free_tables;
3693
3694 raw_spin_lock(&its_lock);
3695 list_add(&its->entry, &its_nodes);
3696 raw_spin_unlock(&its_lock);
3697
3698 return 0;
3699
3700 out_free_tables:
3701 its_free_tables(its);
3702 out_free_cmd:
3703 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
3704 out_free_its:
3705 kfree(its);
3706 out_unmap:
3707 iounmap(its_base);
3708 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
3709 return err;
3710 }
3711
3712 static bool gic_rdists_supports_plpis(void)
3713 {
3714 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
3715 }
3716
3717 static int redist_disable_lpis(void)
3718 {
3719 void __iomem *rbase = gic_data_rdist_rd_base();
3720 u64 timeout = USEC_PER_SEC;
3721 u64 val;
3722
3723 if (!gic_rdists_supports_plpis()) {
3724 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
3725 return -ENXIO;
3726 }
3727
3728 val = readl_relaxed(rbase + GICR_CTLR);
3729 if (!(val & GICR_CTLR_ENABLE_LPIS))
3730 return 0;
3731
3732
3733
3734
3735
3736
3737
3738
3739 if (gic_data_rdist()->lpi_enabled ||
3740 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
3741 return 0;
3742
3743
3744
3745
3746 pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
3747 smp_processor_id());
3748 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3749
3750
3751 val &= ~GICR_CTLR_ENABLE_LPIS;
3752 writel_relaxed(val, rbase + GICR_CTLR);
3753
3754
3755 dsb(sy);
3756
3757
3758
3759
3760
3761
3762 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
3763 if (!timeout) {
3764 pr_err("CPU%d: Timeout while disabling LPIs\n",
3765 smp_processor_id());
3766 return -ETIMEDOUT;
3767 }
3768 udelay(1);
3769 timeout--;
3770 }
3771
3772
3773
3774
3775
3776
3777 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
3778 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
3779 return -EBUSY;
3780 }
3781
3782 return 0;
3783 }
3784
3785 int its_cpu_init(void)
3786 {
3787 if (!list_empty(&its_nodes)) {
3788 int ret;
3789
3790 ret = redist_disable_lpis();
3791 if (ret)
3792 return ret;
3793
3794 its_cpu_init_lpis();
3795 its_cpu_init_collections();
3796 }
3797
3798 return 0;
3799 }
3800
3801 static const struct of_device_id its_device_id[] = {
3802 { .compatible = "arm,gic-v3-its", },
3803 {},
3804 };
3805
3806 static int __init its_of_probe(struct device_node *node)
3807 {
3808 struct device_node *np;
3809 struct resource res;
3810
3811 for (np = of_find_matching_node(node, its_device_id); np;
3812 np = of_find_matching_node(np, its_device_id)) {
3813 if (!of_device_is_available(np))
3814 continue;
3815 if (!of_property_read_bool(np, "msi-controller")) {
3816 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
3817 np);
3818 continue;
3819 }
3820
3821 if (of_address_to_resource(np, 0, &res)) {
3822 pr_warn("%pOF: no regs?\n", np);
3823 continue;
3824 }
3825
3826 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
3827 }
3828 return 0;
3829 }
3830
3831 #ifdef CONFIG_ACPI
3832
3833 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
3834
3835 #ifdef CONFIG_ACPI_NUMA
3836 struct its_srat_map {
3837
3838 u32 numa_node;
3839
3840 u32 its_id;
3841 };
3842
3843 static struct its_srat_map *its_srat_maps __initdata;
3844 static int its_in_srat __initdata;
3845
3846 static int __init acpi_get_its_numa_node(u32 its_id)
3847 {
3848 int i;
3849
3850 for (i = 0; i < its_in_srat; i++) {
3851 if (its_id == its_srat_maps[i].its_id)
3852 return its_srat_maps[i].numa_node;
3853 }
3854 return NUMA_NO_NODE;
3855 }
3856
3857 static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
3858 const unsigned long end)
3859 {
3860 return 0;
3861 }
3862
3863 static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
3864 const unsigned long end)
3865 {
3866 int node;
3867 struct acpi_srat_gic_its_affinity *its_affinity;
3868
3869 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
3870 if (!its_affinity)
3871 return -EINVAL;
3872
3873 if (its_affinity->header.length < sizeof(*its_affinity)) {
3874 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
3875 its_affinity->header.length);
3876 return -EINVAL;
3877 }
3878
3879 node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
3880
3881 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
3882 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
3883 return 0;
3884 }
3885
3886 its_srat_maps[its_in_srat].numa_node = node;
3887 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
3888 its_in_srat++;
3889 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
3890 its_affinity->proximity_domain, its_affinity->its_id, node);
3891
3892 return 0;
3893 }
3894
3895 static void __init acpi_table_parse_srat_its(void)
3896 {
3897 int count;
3898
3899 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
3900 sizeof(struct acpi_table_srat),
3901 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3902 gic_acpi_match_srat_its, 0);
3903 if (count <= 0)
3904 return;
3905
3906 its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
3907 GFP_KERNEL);
3908 if (!its_srat_maps) {
3909 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
3910 return;
3911 }
3912
3913 acpi_table_parse_entries(ACPI_SIG_SRAT,
3914 sizeof(struct acpi_table_srat),
3915 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3916 gic_acpi_parse_srat_its, 0);
3917 }
3918
3919
3920 static void __init acpi_its_srat_maps_free(void)
3921 {
3922 kfree(its_srat_maps);
3923 }
3924 #else
3925 static void __init acpi_table_parse_srat_its(void) { }
3926 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
3927 static void __init acpi_its_srat_maps_free(void) { }
3928 #endif
3929
3930 static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
3931 const unsigned long end)
3932 {
3933 struct acpi_madt_generic_translator *its_entry;
3934 struct fwnode_handle *dom_handle;
3935 struct resource res;
3936 int err;
3937
3938 its_entry = (struct acpi_madt_generic_translator *)header;
3939 memset(&res, 0, sizeof(res));
3940 res.start = its_entry->base_address;
3941 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
3942 res.flags = IORESOURCE_MEM;
3943
3944 dom_handle = irq_domain_alloc_fwnode(&res.start);
3945 if (!dom_handle) {
3946 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
3947 &res.start);
3948 return -ENOMEM;
3949 }
3950
3951 err = iort_register_domain_token(its_entry->translation_id, res.start,
3952 dom_handle);
3953 if (err) {
3954 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
3955 &res.start, its_entry->translation_id);
3956 goto dom_err;
3957 }
3958
3959 err = its_probe_one(&res, dom_handle,
3960 acpi_get_its_numa_node(its_entry->translation_id));
3961 if (!err)
3962 return 0;
3963
3964 iort_deregister_domain_token(its_entry->translation_id);
3965 dom_err:
3966 irq_domain_free_fwnode(dom_handle);
3967 return err;
3968 }
3969
3970 static void __init its_acpi_probe(void)
3971 {
3972 acpi_table_parse_srat_its();
3973 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
3974 gic_acpi_parse_madt_its, 0);
3975 acpi_its_srat_maps_free();
3976 }
3977 #else
3978 static void __init its_acpi_probe(void) { }
3979 #endif
3980
3981 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
3982 struct irq_domain *parent_domain)
3983 {
3984 struct device_node *of_node;
3985 struct its_node *its;
3986 bool has_v4 = false;
3987 int err;
3988
3989 its_parent = parent_domain;
3990 of_node = to_of_node(handle);
3991 if (of_node)
3992 its_of_probe(of_node);
3993 else
3994 its_acpi_probe();
3995
3996 if (list_empty(&its_nodes)) {
3997 pr_warn("ITS: No ITS available, not enabling LPIs\n");
3998 return -ENXIO;
3999 }
4000
4001 gic_rdists = rdists;
4002
4003 err = allocate_lpi_tables();
4004 if (err)
4005 return err;
4006
4007 list_for_each_entry(its, &its_nodes, entry)
4008 has_v4 |= its->is_v4;
4009
4010 if (has_v4 & rdists->has_vlpis) {
4011 if (its_init_vpe_domain() ||
4012 its_init_v4(parent_domain, &its_vpe_domain_ops)) {
4013 rdists->has_vlpis = false;
4014 pr_err("ITS: Disabling GICv4 support\n");
4015 }
4016 }
4017
4018 register_syscore_ops(&its_syscore_ops);
4019
4020 return 0;
4021 }