This source file includes following definitions.
- irq_data_to_priv
- rza1_irqc_eoi
- rza1_irqc_set_type
- rza1_irqc_alloc
- rza1_irqc_translate
- rza1_irqc_parse_map
- rza1_irqc_probe
- rza1_irqc_remove
- rza1_irqc_init
- rza1_irqc_exit
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8 #include <linux/err.h>
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/irqdomain.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
15 #include <linux/of_irq.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20
21 #define IRQC_NUM_IRQ 8
22
23 #define ICR0 0
24
25 #define ICR0_NMIL BIT(15)
26 #define ICR0_NMIE BIT(8)
27 #define ICR0_NMIF BIT(1)
28
29 #define ICR1 2
30
31 #define ICR1_IRQS(n, sense) ((sense) << ((n) * 2))
32 #define ICR1_IRQS_LEVEL_LOW 0
33 #define ICR1_IRQS_EDGE_FALLING 1
34 #define ICR1_IRQS_EDGE_RISING 2
35 #define ICR1_IRQS_EDGE_BOTH 3
36 #define ICR1_IRQS_MASK(n) ICR1_IRQS((n), 3)
37
38 #define IRQRR 4
39
40
41 struct rza1_irqc_priv {
42 struct device *dev;
43 void __iomem *base;
44 struct irq_chip chip;
45 struct irq_domain *irq_domain;
46 struct of_phandle_args map[IRQC_NUM_IRQ];
47 };
48
49 static struct rza1_irqc_priv *irq_data_to_priv(struct irq_data *data)
50 {
51 return data->domain->host_data;
52 }
53
54 static void rza1_irqc_eoi(struct irq_data *d)
55 {
56 struct rza1_irqc_priv *priv = irq_data_to_priv(d);
57 u16 bit = BIT(irqd_to_hwirq(d));
58 u16 tmp;
59
60 tmp = readw_relaxed(priv->base + IRQRR);
61 if (tmp & bit)
62 writew_relaxed(GENMASK(IRQC_NUM_IRQ - 1, 0) & ~bit,
63 priv->base + IRQRR);
64
65 irq_chip_eoi_parent(d);
66 }
67
68 static int rza1_irqc_set_type(struct irq_data *d, unsigned int type)
69 {
70 struct rza1_irqc_priv *priv = irq_data_to_priv(d);
71 unsigned int hw_irq = irqd_to_hwirq(d);
72 u16 sense, tmp;
73
74 switch (type & IRQ_TYPE_SENSE_MASK) {
75 case IRQ_TYPE_LEVEL_LOW:
76 sense = ICR1_IRQS_LEVEL_LOW;
77 break;
78
79 case IRQ_TYPE_EDGE_FALLING:
80 sense = ICR1_IRQS_EDGE_FALLING;
81 break;
82
83 case IRQ_TYPE_EDGE_RISING:
84 sense = ICR1_IRQS_EDGE_RISING;
85 break;
86
87 case IRQ_TYPE_EDGE_BOTH:
88 sense = ICR1_IRQS_EDGE_BOTH;
89 break;
90
91 default:
92 return -EINVAL;
93 }
94
95 tmp = readw_relaxed(priv->base + ICR1);
96 tmp &= ~ICR1_IRQS_MASK(hw_irq);
97 tmp |= ICR1_IRQS(hw_irq, sense);
98 writew_relaxed(tmp, priv->base + ICR1);
99 return 0;
100 }
101
102 static int rza1_irqc_alloc(struct irq_domain *domain, unsigned int virq,
103 unsigned int nr_irqs, void *arg)
104 {
105 struct rza1_irqc_priv *priv = domain->host_data;
106 struct irq_fwspec *fwspec = arg;
107 unsigned int hwirq = fwspec->param[0];
108 struct irq_fwspec spec;
109 unsigned int i;
110 int ret;
111
112 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &priv->chip,
113 priv);
114 if (ret)
115 return ret;
116
117 spec.fwnode = &priv->dev->of_node->fwnode;
118 spec.param_count = priv->map[hwirq].args_count;
119 for (i = 0; i < spec.param_count; i++)
120 spec.param[i] = priv->map[hwirq].args[i];
121
122 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &spec);
123 }
124
125 static int rza1_irqc_translate(struct irq_domain *domain,
126 struct irq_fwspec *fwspec, unsigned long *hwirq,
127 unsigned int *type)
128 {
129 if (fwspec->param_count != 2 || fwspec->param[0] >= IRQC_NUM_IRQ)
130 return -EINVAL;
131
132 *hwirq = fwspec->param[0];
133 *type = fwspec->param[1];
134 return 0;
135 }
136
137 static const struct irq_domain_ops rza1_irqc_domain_ops = {
138 .alloc = rza1_irqc_alloc,
139 .translate = rza1_irqc_translate,
140 };
141
142 static int rza1_irqc_parse_map(struct rza1_irqc_priv *priv,
143 struct device_node *gic_node)
144 {
145 unsigned int imaplen, i, j, ret;
146 struct device *dev = priv->dev;
147 struct device_node *ipar;
148 const __be32 *imap;
149 u32 intsize;
150
151 imap = of_get_property(dev->of_node, "interrupt-map", &imaplen);
152 if (!imap)
153 return -EINVAL;
154
155 for (i = 0; i < IRQC_NUM_IRQ; i++) {
156 if (imaplen < 3)
157 return -EINVAL;
158
159
160 if (be32_to_cpup(imap) != i)
161 return -EINVAL;
162
163 ipar = of_find_node_by_phandle(be32_to_cpup(imap + 2));
164 if (ipar != gic_node) {
165 of_node_put(ipar);
166 return -EINVAL;
167 }
168
169 imap += 3;
170 imaplen -= 3;
171
172 ret = of_property_read_u32(ipar, "#interrupt-cells", &intsize);
173 of_node_put(ipar);
174 if (ret)
175 return ret;
176
177 if (imaplen < intsize)
178 return -EINVAL;
179
180 priv->map[i].args_count = intsize;
181 for (j = 0; j < intsize; j++)
182 priv->map[i].args[j] = be32_to_cpup(imap++);
183
184 imaplen -= intsize;
185 }
186
187 return 0;
188 }
189
190 static int rza1_irqc_probe(struct platform_device *pdev)
191 {
192 struct device *dev = &pdev->dev;
193 struct device_node *np = dev->of_node;
194 struct irq_domain *parent = NULL;
195 struct device_node *gic_node;
196 struct rza1_irqc_priv *priv;
197 int ret;
198
199 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
200 if (!priv)
201 return -ENOMEM;
202
203 platform_set_drvdata(pdev, priv);
204 priv->dev = dev;
205
206 priv->base = devm_platform_ioremap_resource(pdev, 0);
207 if (IS_ERR(priv->base))
208 return PTR_ERR(priv->base);
209
210 gic_node = of_irq_find_parent(np);
211 if (gic_node)
212 parent = irq_find_host(gic_node);
213
214 if (!parent) {
215 dev_err(dev, "cannot find parent domain\n");
216 ret = -ENODEV;
217 goto out_put_node;
218 }
219
220 ret = rza1_irqc_parse_map(priv, gic_node);
221 if (ret) {
222 dev_err(dev, "cannot parse %s: %d\n", "interrupt-map", ret);
223 goto out_put_node;
224 }
225
226 priv->chip.name = "rza1-irqc",
227 priv->chip.irq_mask = irq_chip_mask_parent,
228 priv->chip.irq_unmask = irq_chip_unmask_parent,
229 priv->chip.irq_eoi = rza1_irqc_eoi,
230 priv->chip.irq_retrigger = irq_chip_retrigger_hierarchy,
231 priv->chip.irq_set_type = rza1_irqc_set_type,
232 priv->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
233
234 priv->irq_domain = irq_domain_add_hierarchy(parent, 0, IRQC_NUM_IRQ,
235 np, &rza1_irqc_domain_ops,
236 priv);
237 if (!priv->irq_domain) {
238 dev_err(dev, "cannot initialize irq domain\n");
239 ret = -ENOMEM;
240 }
241
242 out_put_node:
243 of_node_put(gic_node);
244 return ret;
245 }
246
247 static int rza1_irqc_remove(struct platform_device *pdev)
248 {
249 struct rza1_irqc_priv *priv = platform_get_drvdata(pdev);
250
251 irq_domain_remove(priv->irq_domain);
252 return 0;
253 }
254
255 static const struct of_device_id rza1_irqc_dt_ids[] = {
256 { .compatible = "renesas,rza1-irqc" },
257 {},
258 };
259 MODULE_DEVICE_TABLE(of, rza1_irqc_dt_ids);
260
261 static struct platform_driver rza1_irqc_device_driver = {
262 .probe = rza1_irqc_probe,
263 .remove = rza1_irqc_remove,
264 .driver = {
265 .name = "renesas_rza1_irqc",
266 .of_match_table = rza1_irqc_dt_ids,
267 }
268 };
269
270 static int __init rza1_irqc_init(void)
271 {
272 return platform_driver_register(&rza1_irqc_device_driver);
273 }
274 postcore_initcall(rza1_irqc_init);
275
276 static void __exit rza1_irqc_exit(void)
277 {
278 platform_driver_unregister(&rza1_irqc_device_driver);
279 }
280 module_exit(rza1_irqc_exit);
281
282 MODULE_AUTHOR("Geert Uytterhoeven <geert+renesas@glider.be>");
283 MODULE_DESCRIPTION("Renesas RZ/A1 IRQC Driver");
284 MODULE_LICENSE("GPL v2");