root/drivers/pinctrl/pinctrl-zynq.c

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DEFINITIONS

This source file includes following definitions.
  1. zynq_pctrl_get_groups_count
  2. zynq_pctrl_get_group_name
  3. zynq_pctrl_get_group_pins
  4. zynq_pmux_get_functions_count
  5. zynq_pmux_get_function_name
  6. zynq_pmux_get_function_groups
  7. zynq_pinmux_set_mux
  8. zynq_pinconf_iostd_get
  9. zynq_pinconf_cfg_get
  10. zynq_pinconf_cfg_set
  11. zynq_pinconf_group_set
  12. zynq_pinctrl_probe
  13. zynq_pinctrl_init

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Zynq pin controller
   4  *
   5  *  Copyright (C) 2014 Xilinx
   6  *
   7  *  Sören Brinkmann <soren.brinkmann@xilinx.com>
   8  */
   9 #include <linux/io.h>
  10 #include <linux/mfd/syscon.h>
  11 #include <linux/init.h>
  12 #include <linux/of.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pinctrl/pinctrl.h>
  15 #include <linux/pinctrl/pinmux.h>
  16 #include <linux/pinctrl/pinconf.h>
  17 #include <linux/pinctrl/pinconf-generic.h>
  18 #include <linux/regmap.h>
  19 #include "pinctrl-utils.h"
  20 #include "core.h"
  21 
  22 #define ZYNQ_NUM_MIOS   54
  23 
  24 #define ZYNQ_PCTRL_MIO_MST_TRI0 0x10c
  25 #define ZYNQ_PCTRL_MIO_MST_TRI1 0x110
  26 
  27 #define ZYNQ_PINMUX_MUX_SHIFT   1
  28 #define ZYNQ_PINMUX_MUX_MASK    (0x7f << ZYNQ_PINMUX_MUX_SHIFT)
  29 
  30 /**
  31  * struct zynq_pinctrl - driver data
  32  * @pctrl:              Pinctrl device
  33  * @syscon:             Syscon regmap
  34  * @pctrl_offset:       Offset for pinctrl into the @syscon space
  35  * @groups:             Pingroups
  36  * @ngroups:            Number of @groups
  37  * @funcs:              Pinmux functions
  38  * @nfuncs:             Number of @funcs
  39  */
  40 struct zynq_pinctrl {
  41         struct pinctrl_dev *pctrl;
  42         struct regmap *syscon;
  43         u32 pctrl_offset;
  44         const struct zynq_pctrl_group *groups;
  45         unsigned int ngroups;
  46         const struct zynq_pinmux_function *funcs;
  47         unsigned int nfuncs;
  48 };
  49 
  50 struct zynq_pctrl_group {
  51         const char *name;
  52         const unsigned int *pins;
  53         const unsigned int npins;
  54 };
  55 
  56 /**
  57  * struct zynq_pinmux_function - a pinmux function
  58  * @name:       Name of the pinmux function.
  59  * @groups:     List of pingroups for this function.
  60  * @ngroups:    Number of entries in @groups.
  61  * @mux_val:    Selector for this function
  62  * @mux:        Offset of function specific mux
  63  * @mux_mask:   Mask for function specific selector
  64  * @mux_shift:  Shift for function specific selector
  65  */
  66 struct zynq_pinmux_function {
  67         const char *name;
  68         const char * const *groups;
  69         unsigned int ngroups;
  70         unsigned int mux_val;
  71         u32 mux;
  72         u32 mux_mask;
  73         u8 mux_shift;
  74 };
  75 
  76 enum zynq_pinmux_functions {
  77         ZYNQ_PMUX_can0,
  78         ZYNQ_PMUX_can1,
  79         ZYNQ_PMUX_ethernet0,
  80         ZYNQ_PMUX_ethernet1,
  81         ZYNQ_PMUX_gpio0,
  82         ZYNQ_PMUX_i2c0,
  83         ZYNQ_PMUX_i2c1,
  84         ZYNQ_PMUX_mdio0,
  85         ZYNQ_PMUX_mdio1,
  86         ZYNQ_PMUX_qspi0,
  87         ZYNQ_PMUX_qspi1,
  88         ZYNQ_PMUX_qspi_fbclk,
  89         ZYNQ_PMUX_qspi_cs1,
  90         ZYNQ_PMUX_spi0,
  91         ZYNQ_PMUX_spi1,
  92         ZYNQ_PMUX_spi0_ss,
  93         ZYNQ_PMUX_spi1_ss,
  94         ZYNQ_PMUX_sdio0,
  95         ZYNQ_PMUX_sdio0_pc,
  96         ZYNQ_PMUX_sdio0_cd,
  97         ZYNQ_PMUX_sdio0_wp,
  98         ZYNQ_PMUX_sdio1,
  99         ZYNQ_PMUX_sdio1_pc,
 100         ZYNQ_PMUX_sdio1_cd,
 101         ZYNQ_PMUX_sdio1_wp,
 102         ZYNQ_PMUX_smc0_nor,
 103         ZYNQ_PMUX_smc0_nor_cs1,
 104         ZYNQ_PMUX_smc0_nor_addr25,
 105         ZYNQ_PMUX_smc0_nand,
 106         ZYNQ_PMUX_ttc0,
 107         ZYNQ_PMUX_ttc1,
 108         ZYNQ_PMUX_uart0,
 109         ZYNQ_PMUX_uart1,
 110         ZYNQ_PMUX_usb0,
 111         ZYNQ_PMUX_usb1,
 112         ZYNQ_PMUX_swdt0,
 113         ZYNQ_PMUX_MAX_FUNC
 114 };
 115 
 116 static const struct pinctrl_pin_desc zynq_pins[] = {
 117         PINCTRL_PIN(0,  "MIO0"),
 118         PINCTRL_PIN(1,  "MIO1"),
 119         PINCTRL_PIN(2,  "MIO2"),
 120         PINCTRL_PIN(3,  "MIO3"),
 121         PINCTRL_PIN(4,  "MIO4"),
 122         PINCTRL_PIN(5,  "MIO5"),
 123         PINCTRL_PIN(6,  "MIO6"),
 124         PINCTRL_PIN(7,  "MIO7"),
 125         PINCTRL_PIN(8,  "MIO8"),
 126         PINCTRL_PIN(9,  "MIO9"),
 127         PINCTRL_PIN(10, "MIO10"),
 128         PINCTRL_PIN(11, "MIO11"),
 129         PINCTRL_PIN(12, "MIO12"),
 130         PINCTRL_PIN(13, "MIO13"),
 131         PINCTRL_PIN(14, "MIO14"),
 132         PINCTRL_PIN(15, "MIO15"),
 133         PINCTRL_PIN(16, "MIO16"),
 134         PINCTRL_PIN(17, "MIO17"),
 135         PINCTRL_PIN(18, "MIO18"),
 136         PINCTRL_PIN(19, "MIO19"),
 137         PINCTRL_PIN(20, "MIO20"),
 138         PINCTRL_PIN(21, "MIO21"),
 139         PINCTRL_PIN(22, "MIO22"),
 140         PINCTRL_PIN(23, "MIO23"),
 141         PINCTRL_PIN(24, "MIO24"),
 142         PINCTRL_PIN(25, "MIO25"),
 143         PINCTRL_PIN(26, "MIO26"),
 144         PINCTRL_PIN(27, "MIO27"),
 145         PINCTRL_PIN(28, "MIO28"),
 146         PINCTRL_PIN(29, "MIO29"),
 147         PINCTRL_PIN(30, "MIO30"),
 148         PINCTRL_PIN(31, "MIO31"),
 149         PINCTRL_PIN(32, "MIO32"),
 150         PINCTRL_PIN(33, "MIO33"),
 151         PINCTRL_PIN(34, "MIO34"),
 152         PINCTRL_PIN(35, "MIO35"),
 153         PINCTRL_PIN(36, "MIO36"),
 154         PINCTRL_PIN(37, "MIO37"),
 155         PINCTRL_PIN(38, "MIO38"),
 156         PINCTRL_PIN(39, "MIO39"),
 157         PINCTRL_PIN(40, "MIO40"),
 158         PINCTRL_PIN(41, "MIO41"),
 159         PINCTRL_PIN(42, "MIO42"),
 160         PINCTRL_PIN(43, "MIO43"),
 161         PINCTRL_PIN(44, "MIO44"),
 162         PINCTRL_PIN(45, "MIO45"),
 163         PINCTRL_PIN(46, "MIO46"),
 164         PINCTRL_PIN(47, "MIO47"),
 165         PINCTRL_PIN(48, "MIO48"),
 166         PINCTRL_PIN(49, "MIO49"),
 167         PINCTRL_PIN(50, "MIO50"),
 168         PINCTRL_PIN(51, "MIO51"),
 169         PINCTRL_PIN(52, "MIO52"),
 170         PINCTRL_PIN(53, "MIO53"),
 171         PINCTRL_PIN(54, "EMIO_SD0_WP"),
 172         PINCTRL_PIN(55, "EMIO_SD0_CD"),
 173         PINCTRL_PIN(56, "EMIO_SD1_WP"),
 174         PINCTRL_PIN(57, "EMIO_SD1_CD"),
 175 };
 176 
 177 /* pin groups */
 178 static const unsigned int ethernet0_0_pins[] = {16, 17, 18, 19, 20, 21, 22, 23,
 179                                                 24, 25, 26, 27};
 180 static const unsigned int ethernet1_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35,
 181                                                 36, 37, 38, 39};
 182 static const unsigned int mdio0_0_pins[] = {52, 53};
 183 static const unsigned int mdio1_0_pins[] = {52, 53};
 184 static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6};
 185 
 186 static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13};
 187 static const unsigned int qspi_cs1_pins[] = {0};
 188 static const unsigned int qspi_fbclk_pins[] = {8};
 189 static const unsigned int spi0_0_pins[] = {16, 17, 21};
 190 static const unsigned int spi0_0_ss0_pins[] = {18};
 191 static const unsigned int spi0_0_ss1_pins[] = {19};
 192 static const unsigned int spi0_0_ss2_pins[] = {20,};
 193 static const unsigned int spi0_1_pins[] = {28, 29, 33};
 194 static const unsigned int spi0_1_ss0_pins[] = {30};
 195 static const unsigned int spi0_1_ss1_pins[] = {31};
 196 static const unsigned int spi0_1_ss2_pins[] = {32};
 197 static const unsigned int spi0_2_pins[] = {40, 41, 45};
 198 static const unsigned int spi0_2_ss0_pins[] = {42};
 199 static const unsigned int spi0_2_ss1_pins[] = {43};
 200 static const unsigned int spi0_2_ss2_pins[] = {44};
 201 static const unsigned int spi1_0_pins[] = {10, 11, 12};
 202 static const unsigned int spi1_0_ss0_pins[] = {13};
 203 static const unsigned int spi1_0_ss1_pins[] = {14};
 204 static const unsigned int spi1_0_ss2_pins[] = {15};
 205 static const unsigned int spi1_1_pins[] = {22, 23, 24};
 206 static const unsigned int spi1_1_ss0_pins[] = {25};
 207 static const unsigned int spi1_1_ss1_pins[] = {26};
 208 static const unsigned int spi1_1_ss2_pins[] = {27};
 209 static const unsigned int spi1_2_pins[] = {34, 35, 36};
 210 static const unsigned int spi1_2_ss0_pins[] = {37};
 211 static const unsigned int spi1_2_ss1_pins[] = {38};
 212 static const unsigned int spi1_2_ss2_pins[] = {39};
 213 static const unsigned int spi1_3_pins[] = {46, 47, 48, 49};
 214 static const unsigned int spi1_3_ss0_pins[] = {49};
 215 static const unsigned int spi1_3_ss1_pins[] = {50};
 216 static const unsigned int spi1_3_ss2_pins[] = {51};
 217 
 218 static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21};
 219 static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33};
 220 static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45};
 221 static const unsigned int sdio1_0_pins[] = {10, 11, 12, 13, 14, 15};
 222 static const unsigned int sdio1_1_pins[] = {22, 23, 24, 25, 26, 27};
 223 static const unsigned int sdio1_2_pins[] = {34, 35, 36, 37, 38, 39};
 224 static const unsigned int sdio1_3_pins[] = {46, 47, 48, 49, 50, 51};
 225 static const unsigned int sdio0_emio_wp_pins[] = {54};
 226 static const unsigned int sdio0_emio_cd_pins[] = {55};
 227 static const unsigned int sdio1_emio_wp_pins[] = {56};
 228 static const unsigned int sdio1_emio_cd_pins[] = {57};
 229 static const unsigned int smc0_nor_pins[] = {0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
 230                                              15, 16, 17, 18, 19, 20, 21, 22, 23,
 231                                              24, 25, 26, 27, 28, 29, 30, 31, 32,
 232                                              33, 34, 35, 36, 37, 38, 39};
 233 static const unsigned int smc0_nor_cs1_pins[] = {1};
 234 static const unsigned int smc0_nor_addr25_pins[] = {1};
 235 static const unsigned int smc0_nand_pins[] = {0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
 236                                               12, 13, 14, 16, 17, 18, 19, 20,
 237                                               21, 22, 23};
 238 static const unsigned int smc0_nand8_pins[] = {0, 2, 3,  4,  5,  6,  7,
 239                                                8, 9, 10, 11, 12, 13, 14};
 240 /* Note: CAN MIO clock inputs are modeled in the clock framework */
 241 static const unsigned int can0_0_pins[] = {10, 11};
 242 static const unsigned int can0_1_pins[] = {14, 15};
 243 static const unsigned int can0_2_pins[] = {18, 19};
 244 static const unsigned int can0_3_pins[] = {22, 23};
 245 static const unsigned int can0_4_pins[] = {26, 27};
 246 static const unsigned int can0_5_pins[] = {30, 31};
 247 static const unsigned int can0_6_pins[] = {34, 35};
 248 static const unsigned int can0_7_pins[] = {38, 39};
 249 static const unsigned int can0_8_pins[] = {42, 43};
 250 static const unsigned int can0_9_pins[] = {46, 47};
 251 static const unsigned int can0_10_pins[] = {50, 51};
 252 static const unsigned int can1_0_pins[] = {8, 9};
 253 static const unsigned int can1_1_pins[] = {12, 13};
 254 static const unsigned int can1_2_pins[] = {16, 17};
 255 static const unsigned int can1_3_pins[] = {20, 21};
 256 static const unsigned int can1_4_pins[] = {24, 25};
 257 static const unsigned int can1_5_pins[] = {28, 29};
 258 static const unsigned int can1_6_pins[] = {32, 33};
 259 static const unsigned int can1_7_pins[] = {36, 37};
 260 static const unsigned int can1_8_pins[] = {40, 41};
 261 static const unsigned int can1_9_pins[] = {44, 45};
 262 static const unsigned int can1_10_pins[] = {48, 49};
 263 static const unsigned int can1_11_pins[] = {52, 53};
 264 static const unsigned int uart0_0_pins[] = {10, 11};
 265 static const unsigned int uart0_1_pins[] = {14, 15};
 266 static const unsigned int uart0_2_pins[] = {18, 19};
 267 static const unsigned int uart0_3_pins[] = {22, 23};
 268 static const unsigned int uart0_4_pins[] = {26, 27};
 269 static const unsigned int uart0_5_pins[] = {30, 31};
 270 static const unsigned int uart0_6_pins[] = {34, 35};
 271 static const unsigned int uart0_7_pins[] = {38, 39};
 272 static const unsigned int uart0_8_pins[] = {42, 43};
 273 static const unsigned int uart0_9_pins[] = {46, 47};
 274 static const unsigned int uart0_10_pins[] = {50, 51};
 275 static const unsigned int uart1_0_pins[] = {8, 9};
 276 static const unsigned int uart1_1_pins[] = {12, 13};
 277 static const unsigned int uart1_2_pins[] = {16, 17};
 278 static const unsigned int uart1_3_pins[] = {20, 21};
 279 static const unsigned int uart1_4_pins[] = {24, 25};
 280 static const unsigned int uart1_5_pins[] = {28, 29};
 281 static const unsigned int uart1_6_pins[] = {32, 33};
 282 static const unsigned int uart1_7_pins[] = {36, 37};
 283 static const unsigned int uart1_8_pins[] = {40, 41};
 284 static const unsigned int uart1_9_pins[] = {44, 45};
 285 static const unsigned int uart1_10_pins[] = {48, 49};
 286 static const unsigned int uart1_11_pins[] = {52, 53};
 287 static const unsigned int i2c0_0_pins[] = {10, 11};
 288 static const unsigned int i2c0_1_pins[] = {14, 15};
 289 static const unsigned int i2c0_2_pins[] = {18, 19};
 290 static const unsigned int i2c0_3_pins[] = {22, 23};
 291 static const unsigned int i2c0_4_pins[] = {26, 27};
 292 static const unsigned int i2c0_5_pins[] = {30, 31};
 293 static const unsigned int i2c0_6_pins[] = {34, 35};
 294 static const unsigned int i2c0_7_pins[] = {38, 39};
 295 static const unsigned int i2c0_8_pins[] = {42, 43};
 296 static const unsigned int i2c0_9_pins[] = {46, 47};
 297 static const unsigned int i2c0_10_pins[] = {50, 51};
 298 static const unsigned int i2c1_0_pins[] = {12, 13};
 299 static const unsigned int i2c1_1_pins[] = {16, 17};
 300 static const unsigned int i2c1_2_pins[] = {20, 21};
 301 static const unsigned int i2c1_3_pins[] = {24, 25};
 302 static const unsigned int i2c1_4_pins[] = {28, 29};
 303 static const unsigned int i2c1_5_pins[] = {32, 33};
 304 static const unsigned int i2c1_6_pins[] = {36, 37};
 305 static const unsigned int i2c1_7_pins[] = {40, 41};
 306 static const unsigned int i2c1_8_pins[] = {44, 45};
 307 static const unsigned int i2c1_9_pins[] = {48, 49};
 308 static const unsigned int i2c1_10_pins[] = {52, 53};
 309 static const unsigned int ttc0_0_pins[] = {18, 19};
 310 static const unsigned int ttc0_1_pins[] = {30, 31};
 311 static const unsigned int ttc0_2_pins[] = {42, 43};
 312 static const unsigned int ttc1_0_pins[] = {16, 17};
 313 static const unsigned int ttc1_1_pins[] = {28, 29};
 314 static const unsigned int ttc1_2_pins[] = {40, 41};
 315 static const unsigned int swdt0_0_pins[] = {14, 15};
 316 static const unsigned int swdt0_1_pins[] = {26, 27};
 317 static const unsigned int swdt0_2_pins[] = {38, 39};
 318 static const unsigned int swdt0_3_pins[] = {50, 51};
 319 static const unsigned int swdt0_4_pins[] = {52, 53};
 320 static const unsigned int gpio0_0_pins[] = {0};
 321 static const unsigned int gpio0_1_pins[] = {1};
 322 static const unsigned int gpio0_2_pins[] = {2};
 323 static const unsigned int gpio0_3_pins[] = {3};
 324 static const unsigned int gpio0_4_pins[] = {4};
 325 static const unsigned int gpio0_5_pins[] = {5};
 326 static const unsigned int gpio0_6_pins[] = {6};
 327 static const unsigned int gpio0_7_pins[] = {7};
 328 static const unsigned int gpio0_8_pins[] = {8};
 329 static const unsigned int gpio0_9_pins[] = {9};
 330 static const unsigned int gpio0_10_pins[] = {10};
 331 static const unsigned int gpio0_11_pins[] = {11};
 332 static const unsigned int gpio0_12_pins[] = {12};
 333 static const unsigned int gpio0_13_pins[] = {13};
 334 static const unsigned int gpio0_14_pins[] = {14};
 335 static const unsigned int gpio0_15_pins[] = {15};
 336 static const unsigned int gpio0_16_pins[] = {16};
 337 static const unsigned int gpio0_17_pins[] = {17};
 338 static const unsigned int gpio0_18_pins[] = {18};
 339 static const unsigned int gpio0_19_pins[] = {19};
 340 static const unsigned int gpio0_20_pins[] = {20};
 341 static const unsigned int gpio0_21_pins[] = {21};
 342 static const unsigned int gpio0_22_pins[] = {22};
 343 static const unsigned int gpio0_23_pins[] = {23};
 344 static const unsigned int gpio0_24_pins[] = {24};
 345 static const unsigned int gpio0_25_pins[] = {25};
 346 static const unsigned int gpio0_26_pins[] = {26};
 347 static const unsigned int gpio0_27_pins[] = {27};
 348 static const unsigned int gpio0_28_pins[] = {28};
 349 static const unsigned int gpio0_29_pins[] = {29};
 350 static const unsigned int gpio0_30_pins[] = {30};
 351 static const unsigned int gpio0_31_pins[] = {31};
 352 static const unsigned int gpio0_32_pins[] = {32};
 353 static const unsigned int gpio0_33_pins[] = {33};
 354 static const unsigned int gpio0_34_pins[] = {34};
 355 static const unsigned int gpio0_35_pins[] = {35};
 356 static const unsigned int gpio0_36_pins[] = {36};
 357 static const unsigned int gpio0_37_pins[] = {37};
 358 static const unsigned int gpio0_38_pins[] = {38};
 359 static const unsigned int gpio0_39_pins[] = {39};
 360 static const unsigned int gpio0_40_pins[] = {40};
 361 static const unsigned int gpio0_41_pins[] = {41};
 362 static const unsigned int gpio0_42_pins[] = {42};
 363 static const unsigned int gpio0_43_pins[] = {43};
 364 static const unsigned int gpio0_44_pins[] = {44};
 365 static const unsigned int gpio0_45_pins[] = {45};
 366 static const unsigned int gpio0_46_pins[] = {46};
 367 static const unsigned int gpio0_47_pins[] = {47};
 368 static const unsigned int gpio0_48_pins[] = {48};
 369 static const unsigned int gpio0_49_pins[] = {49};
 370 static const unsigned int gpio0_50_pins[] = {50};
 371 static const unsigned int gpio0_51_pins[] = {51};
 372 static const unsigned int gpio0_52_pins[] = {52};
 373 static const unsigned int gpio0_53_pins[] = {53};
 374 static const unsigned int usb0_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, 36,
 375                                            37, 38, 39};
 376 static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48,
 377                                            49, 50, 51};
 378 
 379 #define DEFINE_ZYNQ_PINCTRL_GRP(nm) \
 380         { \
 381                 .name = #nm "_grp", \
 382                 .pins = nm ## _pins, \
 383                 .npins = ARRAY_SIZE(nm ## _pins), \
 384         }
 385 
 386 static const struct zynq_pctrl_group zynq_pctrl_groups[] = {
 387         DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
 388         DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
 389         DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
 390         DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
 391         DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
 392         DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
 393         DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
 394         DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
 395         DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
 396         DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0),
 397         DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1),
 398         DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2),
 399         DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
 400         DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0),
 401         DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1),
 402         DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2),
 403         DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
 404         DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0),
 405         DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1),
 406         DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2),
 407         DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
 408         DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0),
 409         DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1),
 410         DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2),
 411         DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
 412         DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0),
 413         DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1),
 414         DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2),
 415         DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
 416         DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0),
 417         DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1),
 418         DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2),
 419         DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
 420         DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0),
 421         DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1),
 422         DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2),
 423         DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
 424         DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
 425         DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
 426         DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
 427         DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
 428         DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
 429         DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
 430         DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
 431         DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
 432         DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
 433         DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
 434         DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
 435         DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
 436         DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
 437         DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
 438         DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand8),
 439         DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
 440         DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
 441         DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
 442         DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
 443         DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
 444         DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
 445         DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
 446         DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
 447         DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
 448         DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
 449         DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
 450         DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
 451         DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
 452         DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
 453         DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
 454         DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
 455         DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
 456         DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
 457         DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
 458         DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
 459         DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
 460         DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
 461         DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
 462         DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
 463         DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
 464         DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
 465         DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
 466         DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
 467         DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
 468         DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
 469         DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
 470         DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
 471         DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
 472         DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
 473         DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
 474         DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
 475         DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
 476         DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
 477         DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
 478         DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
 479         DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
 480         DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
 481         DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
 482         DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
 483         DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
 484         DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
 485         DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
 486         DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
 487         DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
 488         DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
 489         DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
 490         DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
 491         DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
 492         DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
 493         DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
 494         DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
 495         DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
 496         DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
 497         DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
 498         DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
 499         DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
 500         DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
 501         DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
 502         DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
 503         DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
 504         DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
 505         DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
 506         DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
 507         DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
 508         DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
 509         DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
 510         DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
 511         DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
 512         DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2),
 513         DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0),
 514         DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1),
 515         DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2),
 516         DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3),
 517         DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4),
 518         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_0),
 519         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_1),
 520         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_2),
 521         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_3),
 522         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_4),
 523         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_5),
 524         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_6),
 525         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_7),
 526         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_8),
 527         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_9),
 528         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_10),
 529         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_11),
 530         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_12),
 531         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_13),
 532         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_14),
 533         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_15),
 534         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_16),
 535         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_17),
 536         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_18),
 537         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_19),
 538         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_20),
 539         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_21),
 540         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_22),
 541         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_23),
 542         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_24),
 543         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_25),
 544         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_26),
 545         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_27),
 546         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_28),
 547         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_29),
 548         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_30),
 549         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_31),
 550         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_32),
 551         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_33),
 552         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_34),
 553         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_35),
 554         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_36),
 555         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_37),
 556         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_38),
 557         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_39),
 558         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_40),
 559         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_41),
 560         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_42),
 561         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_43),
 562         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_44),
 563         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_45),
 564         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_46),
 565         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_47),
 566         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_48),
 567         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_49),
 568         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_50),
 569         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_51),
 570         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_52),
 571         DEFINE_ZYNQ_PINCTRL_GRP(gpio0_53),
 572         DEFINE_ZYNQ_PINCTRL_GRP(usb0_0),
 573         DEFINE_ZYNQ_PINCTRL_GRP(usb1_0),
 574 };
 575 
 576 /* function groups */
 577 static const char * const ethernet0_groups[] = {"ethernet0_0_grp"};
 578 static const char * const ethernet1_groups[] = {"ethernet1_0_grp"};
 579 static const char * const usb0_groups[] = {"usb0_0_grp"};
 580 static const char * const usb1_groups[] = {"usb1_0_grp"};
 581 static const char * const mdio0_groups[] = {"mdio0_0_grp"};
 582 static const char * const mdio1_groups[] = {"mdio1_0_grp"};
 583 static const char * const qspi0_groups[] = {"qspi0_0_grp"};
 584 static const char * const qspi1_groups[] = {"qspi1_0_grp"};
 585 static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"};
 586 static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"};
 587 static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp",
 588                                            "spi0_2_grp"};
 589 static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp",
 590                                            "spi1_2_grp", "spi1_3_grp"};
 591 static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp",
 592                 "spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp",
 593                 "spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp",
 594                 "spi0_2_ss1_grp", "spi0_2_ss2_grp"};
 595 static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp",
 596                 "spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp",
 597                 "spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp",
 598                 "spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp",
 599                 "spi1_3_ss1_grp", "spi1_3_ss2_grp"};
 600 static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp",
 601                                             "sdio0_2_grp"};
 602 static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp",
 603                                             "sdio1_2_grp", "sdio1_3_grp"};
 604 static const char * const sdio0_pc_groups[] = {"gpio0_0_grp",
 605                 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
 606                 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
 607                 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
 608                 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
 609                 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
 610                 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
 611                 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
 612                 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
 613                 "gpio0_50_grp", "gpio0_52_grp"};
 614 static const char * const sdio1_pc_groups[] = {"gpio0_1_grp",
 615                 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
 616                 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
 617                 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
 618                 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
 619                 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
 620                 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
 621                 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
 622                 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
 623                 "gpio0_51_grp", "gpio0_53_grp"};
 624 static const char * const sdio0_cd_groups[] = {"gpio0_0_grp",
 625                 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
 626                 "gpio0_10_grp", "gpio0_12_grp",
 627                 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
 628                 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
 629                 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
 630                 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
 631                 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
 632                 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
 633                 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
 634                 "gpio0_3_grp", "gpio0_5_grp",
 635                 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
 636                 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
 637                 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
 638                 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
 639                 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
 640                 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
 641                 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
 642                 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_cd_grp"};
 643 static const char * const sdio0_wp_groups[] = {"gpio0_0_grp",
 644                 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
 645                 "gpio0_10_grp", "gpio0_12_grp",
 646                 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
 647                 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
 648                 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
 649                 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
 650                 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
 651                 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
 652                 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
 653                 "gpio0_3_grp", "gpio0_5_grp",
 654                 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
 655                 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
 656                 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
 657                 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
 658                 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
 659                 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
 660                 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
 661                 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_wp_grp"};
 662 static const char * const sdio1_cd_groups[] = {"gpio0_0_grp",
 663                 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
 664                 "gpio0_10_grp", "gpio0_12_grp",
 665                 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
 666                 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
 667                 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
 668                 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
 669                 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
 670                 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
 671                 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
 672                 "gpio0_3_grp", "gpio0_5_grp",
 673                 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
 674                 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
 675                 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
 676                 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
 677                 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
 678                 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
 679                 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
 680                 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_cd_grp"};
 681 static const char * const sdio1_wp_groups[] = {"gpio0_0_grp",
 682                 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
 683                 "gpio0_10_grp", "gpio0_12_grp",
 684                 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
 685                 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
 686                 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
 687                 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
 688                 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
 689                 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
 690                 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
 691                 "gpio0_3_grp", "gpio0_5_grp",
 692                 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
 693                 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
 694                 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
 695                 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
 696                 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
 697                 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
 698                 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
 699                 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"};
 700 static const char * const smc0_nor_groups[] = {"smc0_nor_grp"};
 701 static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"};
 702 static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"};
 703 static const char * const smc0_nand_groups[] = {"smc0_nand_grp",
 704                 "smc0_nand8_grp"};
 705 static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp",
 706                 "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp",
 707                 "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp",
 708                 "can0_10_grp"};
 709 static const char * const can1_groups[] = {"can1_0_grp", "can1_1_grp",
 710                 "can1_2_grp", "can1_3_grp", "can1_4_grp", "can1_5_grp",
 711                 "can1_6_grp", "can1_7_grp", "can1_8_grp", "can1_9_grp",
 712                 "can1_10_grp", "can1_11_grp"};
 713 static const char * const uart0_groups[] = {"uart0_0_grp", "uart0_1_grp",
 714                 "uart0_2_grp", "uart0_3_grp", "uart0_4_grp", "uart0_5_grp",
 715                 "uart0_6_grp", "uart0_7_grp", "uart0_8_grp", "uart0_9_grp",
 716                 "uart0_10_grp"};
 717 static const char * const uart1_groups[] = {"uart1_0_grp", "uart1_1_grp",
 718                 "uart1_2_grp", "uart1_3_grp", "uart1_4_grp", "uart1_5_grp",
 719                 "uart1_6_grp", "uart1_7_grp", "uart1_8_grp", "uart1_9_grp",
 720                 "uart1_10_grp", "uart1_11_grp"};
 721 static const char * const i2c0_groups[] = {"i2c0_0_grp", "i2c0_1_grp",
 722                 "i2c0_2_grp", "i2c0_3_grp", "i2c0_4_grp", "i2c0_5_grp",
 723                 "i2c0_6_grp", "i2c0_7_grp", "i2c0_8_grp", "i2c0_9_grp",
 724                 "i2c0_10_grp"};
 725 static const char * const i2c1_groups[] = {"i2c1_0_grp", "i2c1_1_grp",
 726                 "i2c1_2_grp", "i2c1_3_grp", "i2c1_4_grp", "i2c1_5_grp",
 727                 "i2c1_6_grp", "i2c1_7_grp", "i2c1_8_grp", "i2c1_9_grp",
 728                 "i2c1_10_grp"};
 729 static const char * const ttc0_groups[] = {"ttc0_0_grp", "ttc0_1_grp",
 730                                            "ttc0_2_grp"};
 731 static const char * const ttc1_groups[] = {"ttc1_0_grp", "ttc1_1_grp",
 732                                            "ttc1_2_grp"};
 733 static const char * const swdt0_groups[] = {"swdt0_0_grp", "swdt0_1_grp",
 734                 "swdt0_2_grp", "swdt0_3_grp", "swdt0_4_grp"};
 735 static const char * const gpio0_groups[] = {"gpio0_0_grp",
 736                 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
 737                 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
 738                 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
 739                 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
 740                 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
 741                 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
 742                 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
 743                 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
 744                 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
 745                 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
 746                 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
 747                 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
 748                 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
 749                 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
 750                 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
 751                 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
 752                 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
 753                 "gpio0_51_grp", "gpio0_53_grp"};
 754 
 755 #define DEFINE_ZYNQ_PINMUX_FUNCTION(fname, mval)        \
 756         [ZYNQ_PMUX_##fname] = {                         \
 757                 .name = #fname,                         \
 758                 .groups = fname##_groups,               \
 759                 .ngroups = ARRAY_SIZE(fname##_groups),  \
 760                 .mux_val = mval,                        \
 761         }
 762 
 763 #define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\
 764         [ZYNQ_PMUX_##fname] = {                         \
 765                 .name = #fname,                         \
 766                 .groups = fname##_groups,               \
 767                 .ngroups = ARRAY_SIZE(fname##_groups),  \
 768                 .mux_val = mval,                        \
 769                 .mux = offset,                          \
 770                 .mux_mask = mask,                       \
 771                 .mux_shift = shift,                     \
 772         }
 773 
 774 #define ZYNQ_SDIO_WP_SHIFT      0
 775 #define ZYNQ_SDIO_WP_MASK       (0x3f << ZYNQ_SDIO_WP_SHIFT)
 776 #define ZYNQ_SDIO_CD_SHIFT      16
 777 #define ZYNQ_SDIO_CD_MASK       (0x3f << ZYNQ_SDIO_CD_SHIFT)
 778 
 779 static const struct zynq_pinmux_function zynq_pmux_functions[] = {
 780         DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet0, 1),
 781         DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet1, 1),
 782         DEFINE_ZYNQ_PINMUX_FUNCTION(usb0, 2),
 783         DEFINE_ZYNQ_PINMUX_FUNCTION(usb1, 2),
 784         DEFINE_ZYNQ_PINMUX_FUNCTION(mdio0, 0x40),
 785         DEFINE_ZYNQ_PINMUX_FUNCTION(mdio1, 0x50),
 786         DEFINE_ZYNQ_PINMUX_FUNCTION(qspi0, 1),
 787         DEFINE_ZYNQ_PINMUX_FUNCTION(qspi1, 1),
 788         DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_fbclk, 1),
 789         DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1),
 790         DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50),
 791         DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50),
 792         DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50),
 793         DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50),
 794         DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40),
 795         DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc),
 796         DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK,
 797                                         ZYNQ_SDIO_WP_SHIFT),
 798         DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK,
 799                                         ZYNQ_SDIO_CD_SHIFT),
 800         DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40),
 801         DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc),
 802         DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK,
 803                                         ZYNQ_SDIO_WP_SHIFT),
 804         DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK,
 805                                         ZYNQ_SDIO_CD_SHIFT),
 806         DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4),
 807         DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),
 808         DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_addr25, 4),
 809         DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nand, 8),
 810         DEFINE_ZYNQ_PINMUX_FUNCTION(can0, 0x10),
 811         DEFINE_ZYNQ_PINMUX_FUNCTION(can1, 0x10),
 812         DEFINE_ZYNQ_PINMUX_FUNCTION(uart0, 0x70),
 813         DEFINE_ZYNQ_PINMUX_FUNCTION(uart1, 0x70),
 814         DEFINE_ZYNQ_PINMUX_FUNCTION(i2c0, 0x20),
 815         DEFINE_ZYNQ_PINMUX_FUNCTION(i2c1, 0x20),
 816         DEFINE_ZYNQ_PINMUX_FUNCTION(ttc0, 0x60),
 817         DEFINE_ZYNQ_PINMUX_FUNCTION(ttc1, 0x60),
 818         DEFINE_ZYNQ_PINMUX_FUNCTION(swdt0, 0x30),
 819         DEFINE_ZYNQ_PINMUX_FUNCTION(gpio0, 0),
 820 };
 821 
 822 
 823 /* pinctrl */
 824 static int zynq_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 825 {
 826         struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 827 
 828         return pctrl->ngroups;
 829 }
 830 
 831 static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 832                                              unsigned int selector)
 833 {
 834         struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 835 
 836         return pctrl->groups[selector].name;
 837 }
 838 
 839 static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 840                                      unsigned int selector,
 841                                      const unsigned int **pins,
 842                                      unsigned int *num_pins)
 843 {
 844         struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 845 
 846         *pins = pctrl->groups[selector].pins;
 847         *num_pins = pctrl->groups[selector].npins;
 848 
 849         return 0;
 850 }
 851 
 852 static const struct pinctrl_ops zynq_pctrl_ops = {
 853         .get_groups_count = zynq_pctrl_get_groups_count,
 854         .get_group_name = zynq_pctrl_get_group_name,
 855         .get_group_pins = zynq_pctrl_get_group_pins,
 856         .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
 857         .dt_free_map = pinctrl_utils_free_map,
 858 };
 859 
 860 /* pinmux */
 861 static int zynq_pmux_get_functions_count(struct pinctrl_dev *pctldev)
 862 {
 863         struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 864 
 865         return pctrl->nfuncs;
 866 }
 867 
 868 static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev,
 869                                                unsigned int selector)
 870 {
 871         struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 872 
 873         return pctrl->funcs[selector].name;
 874 }
 875 
 876 static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev,
 877                                          unsigned int selector,
 878                                          const char * const **groups,
 879                                          unsigned * const num_groups)
 880 {
 881         struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 882 
 883         *groups = pctrl->funcs[selector].groups;
 884         *num_groups = pctrl->funcs[selector].ngroups;
 885         return 0;
 886 }
 887 
 888 static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev,
 889                                unsigned int function,
 890                                unsigned int  group)
 891 {
 892         int i, ret;
 893         struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 894         const struct zynq_pctrl_group *pgrp = &pctrl->groups[group];
 895         const struct zynq_pinmux_function *func = &pctrl->funcs[function];
 896 
 897         /*
 898          * SD WP & CD are special. They have dedicated registers
 899          * to mux them in
 900          */
 901         if (function == ZYNQ_PMUX_sdio0_cd || function == ZYNQ_PMUX_sdio0_wp ||
 902                         function == ZYNQ_PMUX_sdio1_cd ||
 903                         function == ZYNQ_PMUX_sdio1_wp) {
 904                 u32 reg;
 905 
 906                 ret = regmap_read(pctrl->syscon,
 907                                   pctrl->pctrl_offset + func->mux, &reg);
 908                 if (ret)
 909                         return ret;
 910 
 911                 reg &= ~func->mux_mask;
 912                 reg |= pgrp->pins[0] << func->mux_shift;
 913                 ret = regmap_write(pctrl->syscon,
 914                                    pctrl->pctrl_offset + func->mux, reg);
 915                 if (ret)
 916                         return ret;
 917         } else {
 918                 for (i = 0; i < pgrp->npins; i++) {
 919                         unsigned int pin = pgrp->pins[i];
 920                         u32 reg, addr = pctrl->pctrl_offset + (4 * pin);
 921 
 922                         ret = regmap_read(pctrl->syscon, addr, &reg);
 923                         if (ret)
 924                                 return ret;
 925 
 926                         reg &= ~ZYNQ_PINMUX_MUX_MASK;
 927                         reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT;
 928                         ret = regmap_write(pctrl->syscon, addr, reg);
 929                         if (ret)
 930                                 return ret;
 931                 }
 932         }
 933 
 934         return 0;
 935 }
 936 
 937 static const struct pinmux_ops zynq_pinmux_ops = {
 938         .get_functions_count = zynq_pmux_get_functions_count,
 939         .get_function_name = zynq_pmux_get_function_name,
 940         .get_function_groups = zynq_pmux_get_function_groups,
 941         .set_mux = zynq_pinmux_set_mux,
 942 };
 943 
 944 /* pinconfig */
 945 #define ZYNQ_PINCONF_TRISTATE           BIT(0)
 946 #define ZYNQ_PINCONF_SPEED              BIT(8)
 947 #define ZYNQ_PINCONF_PULLUP             BIT(12)
 948 #define ZYNQ_PINCONF_DISABLE_RECVR      BIT(13)
 949 
 950 #define ZYNQ_PINCONF_IOTYPE_SHIFT       9
 951 #define ZYNQ_PINCONF_IOTYPE_MASK        (7 << ZYNQ_PINCONF_IOTYPE_SHIFT)
 952 
 953 enum zynq_io_standards {
 954         zynq_iostd_min,
 955         zynq_iostd_lvcmos18,
 956         zynq_iostd_lvcmos25,
 957         zynq_iostd_lvcmos33,
 958         zynq_iostd_hstl,
 959         zynq_iostd_max
 960 };
 961 
 962 /*
 963  * PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to
 964  *      this parameter (on a custom format) tells the driver which alternative
 965  *      IO standard to use.
 966  */
 967 #define PIN_CONFIG_IOSTANDARD           (PIN_CONFIG_END + 1)
 968 
 969 static const struct pinconf_generic_params zynq_dt_params[] = {
 970         {"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18},
 971 };
 972 
 973 #ifdef CONFIG_DEBUG_FS
 974 static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)]
 975         = { PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true),
 976 };
 977 #endif
 978 
 979 static unsigned int zynq_pinconf_iostd_get(u32 reg)
 980 {
 981         return (reg & ZYNQ_PINCONF_IOTYPE_MASK) >> ZYNQ_PINCONF_IOTYPE_SHIFT;
 982 }
 983 
 984 static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
 985                                 unsigned int pin,
 986                                 unsigned long *config)
 987 {
 988         u32 reg;
 989         int ret;
 990         unsigned int arg = 0;
 991         unsigned int param = pinconf_to_config_param(*config);
 992         struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 993 
 994         if (pin >= ZYNQ_NUM_MIOS)
 995                 return -ENOTSUPP;
 996 
 997         ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), &reg);
 998         if (ret)
 999                 return -EIO;
1000 
1001         switch (param) {
1002         case PIN_CONFIG_BIAS_PULL_UP:
1003                 if (!(reg & ZYNQ_PINCONF_PULLUP))
1004                         return -EINVAL;
1005                 arg = 1;
1006                 break;
1007         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1008                 if (!(reg & ZYNQ_PINCONF_TRISTATE))
1009                         return -EINVAL;
1010                 arg = 1;
1011                 break;
1012         case PIN_CONFIG_BIAS_DISABLE:
1013                 if (reg & ZYNQ_PINCONF_PULLUP || reg & ZYNQ_PINCONF_TRISTATE)
1014                         return -EINVAL;
1015                 break;
1016         case PIN_CONFIG_SLEW_RATE:
1017                 arg = !!(reg & ZYNQ_PINCONF_SPEED);
1018                 break;
1019         case PIN_CONFIG_LOW_POWER_MODE:
1020         {
1021                 enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg);
1022 
1023                 if (iostd != zynq_iostd_hstl)
1024                         return -EINVAL;
1025                 if (!(reg & ZYNQ_PINCONF_DISABLE_RECVR))
1026                         return -EINVAL;
1027                 arg = !!(reg & ZYNQ_PINCONF_DISABLE_RECVR);
1028                 break;
1029         }
1030         case PIN_CONFIG_IOSTANDARD:
1031                 arg = zynq_pinconf_iostd_get(reg);
1032                 break;
1033         default:
1034                 return -ENOTSUPP;
1035         }
1036 
1037         *config = pinconf_to_config_packed(param, arg);
1038         return 0;
1039 }
1040 
1041 static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
1042                                 unsigned int pin,
1043                                 unsigned long *configs,
1044                                 unsigned int num_configs)
1045 {
1046         int i, ret;
1047         u32 reg;
1048         u32 pullup = 0;
1049         u32 tristate = 0;
1050         struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1051 
1052         if (pin >= ZYNQ_NUM_MIOS)
1053                 return -ENOTSUPP;
1054 
1055         ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), &reg);
1056         if (ret)
1057                 return -EIO;
1058 
1059         for (i = 0; i < num_configs; i++) {
1060                 unsigned int param = pinconf_to_config_param(configs[i]);
1061                 unsigned int arg = pinconf_to_config_argument(configs[i]);
1062 
1063                 switch (param) {
1064                 case PIN_CONFIG_BIAS_PULL_UP:
1065                         pullup = ZYNQ_PINCONF_PULLUP;
1066                         break;
1067                 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1068                         tristate = ZYNQ_PINCONF_TRISTATE;
1069                         break;
1070                 case PIN_CONFIG_BIAS_DISABLE:
1071                         reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
1072                         break;
1073                 case PIN_CONFIG_SLEW_RATE:
1074                         if (arg)
1075                                 reg |= ZYNQ_PINCONF_SPEED;
1076                         else
1077                                 reg &= ~ZYNQ_PINCONF_SPEED;
1078 
1079                         break;
1080                 case PIN_CONFIG_IOSTANDARD:
1081                         if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) {
1082                                 dev_warn(pctldev->dev,
1083                                          "unsupported IO standard '%u'\n",
1084                                          param);
1085                                 break;
1086                         }
1087                         reg &= ~ZYNQ_PINCONF_IOTYPE_MASK;
1088                         reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT;
1089                         break;
1090                 case PIN_CONFIG_LOW_POWER_MODE:
1091                         if (arg)
1092                                 reg |= ZYNQ_PINCONF_DISABLE_RECVR;
1093                         else
1094                                 reg &= ~ZYNQ_PINCONF_DISABLE_RECVR;
1095 
1096                         break;
1097                 default:
1098                         dev_warn(pctldev->dev,
1099                                  "unsupported configuration parameter '%u'\n",
1100                                  param);
1101                         continue;
1102                 }
1103         }
1104 
1105         if (tristate || pullup) {
1106                 reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
1107                 reg |= tristate | pullup;
1108         }
1109 
1110         ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg);
1111         if (ret)
1112                 return -EIO;
1113 
1114         return 0;
1115 }
1116 
1117 static int zynq_pinconf_group_set(struct pinctrl_dev *pctldev,
1118                                   unsigned int selector,
1119                                   unsigned long *configs,
1120                                   unsigned int  num_configs)
1121 {
1122         int i, ret;
1123         struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1124         const struct zynq_pctrl_group *pgrp = &pctrl->groups[selector];
1125 
1126         for (i = 0; i < pgrp->npins; i++) {
1127                 ret = zynq_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
1128                                            num_configs);
1129                 if (ret)
1130                         return ret;
1131         }
1132 
1133         return 0;
1134 }
1135 
1136 static const struct pinconf_ops zynq_pinconf_ops = {
1137         .is_generic = true,
1138         .pin_config_get = zynq_pinconf_cfg_get,
1139         .pin_config_set = zynq_pinconf_cfg_set,
1140         .pin_config_group_set = zynq_pinconf_group_set,
1141 };
1142 
1143 static struct pinctrl_desc zynq_desc = {
1144         .name = "zynq_pinctrl",
1145         .pins = zynq_pins,
1146         .npins = ARRAY_SIZE(zynq_pins),
1147         .pctlops = &zynq_pctrl_ops,
1148         .pmxops = &zynq_pinmux_ops,
1149         .confops = &zynq_pinconf_ops,
1150         .num_custom_params = ARRAY_SIZE(zynq_dt_params),
1151         .custom_params = zynq_dt_params,
1152 #ifdef CONFIG_DEBUG_FS
1153         .custom_conf_items = zynq_conf_items,
1154 #endif
1155         .owner = THIS_MODULE,
1156 };
1157 
1158 static int zynq_pinctrl_probe(struct platform_device *pdev)
1159 
1160 {
1161         struct resource *res;
1162         struct zynq_pinctrl *pctrl;
1163 
1164         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1165         if (!pctrl)
1166                 return -ENOMEM;
1167 
1168         pctrl->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1169                                                         "syscon");
1170         if (IS_ERR(pctrl->syscon)) {
1171                 dev_err(&pdev->dev, "unable to get syscon\n");
1172                 return PTR_ERR(pctrl->syscon);
1173         }
1174 
1175         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1176         if (!res) {
1177                 dev_err(&pdev->dev, "missing IO resource\n");
1178                 return -ENODEV;
1179         }
1180         pctrl->pctrl_offset = res->start;
1181 
1182         pctrl->groups = zynq_pctrl_groups;
1183         pctrl->ngroups = ARRAY_SIZE(zynq_pctrl_groups);
1184         pctrl->funcs = zynq_pmux_functions;
1185         pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions);
1186 
1187         pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &zynq_desc, pctrl);
1188         if (IS_ERR(pctrl->pctrl))
1189                 return PTR_ERR(pctrl->pctrl);
1190 
1191         platform_set_drvdata(pdev, pctrl);
1192 
1193         dev_info(&pdev->dev, "zynq pinctrl initialized\n");
1194 
1195         return 0;
1196 }
1197 
1198 static const struct of_device_id zynq_pinctrl_of_match[] = {
1199         { .compatible = "xlnx,pinctrl-zynq" },
1200         { }
1201 };
1202 
1203 static struct platform_driver zynq_pinctrl_driver = {
1204         .driver = {
1205                 .name = "zynq-pinctrl",
1206                 .of_match_table = zynq_pinctrl_of_match,
1207         },
1208         .probe = zynq_pinctrl_probe,
1209 };
1210 
1211 static int __init zynq_pinctrl_init(void)
1212 {
1213         return platform_driver_register(&zynq_pinctrl_driver);
1214 }
1215 arch_initcall(zynq_pinctrl_init);

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