root/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c

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DEFINITIONS

This source file includes following definitions.
  1. PORT_ALL
  2. PORT_ALL
  3. PORT_ALL
  4. PORT_ALL
  5. PORT_ALL
  6. PORT_ALL
  7. PORT_ALL
  8. PORT_ALL
  9. PORT_ALL
  10. PORT_ALL
  11. PORT_ALL
  12. PORT_ALL
  13. PORT_ALL
  14. F1
  15. F3
  16. F7
  17. IRQ
  18. F1
  19. F3
  20. F7
  21. IRQ
  22. F1
  23. F3
  24. F7
  25. IRQ
  26. F1
  27. F3
  28. F7
  29. IRQ
  30. F1
  31. F3
  32. F7
  33. IRQ
  34. F1
  35. F3
  36. F7
  37. IRQ
  38. F1
  39. F3
  40. F7
  41. IRQ
  42. F1
  43. F3
  44. F7
  45. IRQ
  46. F1
  47. F3
  48. F7
  49. IRQ
  50. F1
  51. F3
  52. F7
  53. IRQ
  54. F1
  55. F3
  56. F7
  57. IRQ
  58. F1
  59. F3
  60. F7
  61. IRQ
  62. F1
  63. F3
  64. F7
  65. IRQ
  66. F1
  67. F3
  68. F4
  69. F7
  70. IRQ
  71. F1
  72. F3
  73. F4
  74. F7
  75. IRQ
  76. F1
  77. F3
  78. F7
  79. IRQ
  80. F1
  81. F4
  82. F7
  83. F1
  84. F4
  85. F7
  86. F1
  87. F4
  88. F7
  89. F1
  90. F3
  91. F7
  92. F1
  93. F3
  94. F7
  95. F1
  96. F3
  97. F7
  98. F1
  99. F3
  100. F7
  101. F1
  102. F3
  103. F7
  104. F1
  105. F2
  106. F3
  107. F7
  108. F1
  109. F3
  110. F7
  111. F1
  112. F2
  113. F3
  114. F7
  115. F1
  116. F2
  117. F3
  118. F7
  119. F1
  120. F3
  121. F7
  122. F1
  123. F4
  124. F7
  125. F1
  126. F4
  127. F7
  128. F1
  129. F5
  130. F7
  131. F1
  132. F5
  133. F7
  134. F1
  135. F5
  136. F7
  137. F1
  138. F7
  139. F1
  140. F7
  141. F1
  142. F7
  143. F1
  144. F3
  145. F4
  146. F7
  147. F1
  148. F3
  149. F4
  150. F7
  151. F1
  152. F3
  153. F4
  154. F7
  155. F1
  156. F1
  157. F1
  158. F2
  159. F3
  160. F5
  161. IRQ
  162. F1
  163. F2
  164. F5
  165. F7
  166. F1
  167. F2
  168. F3
  169. F5
  170. F1
  171. F2
  172. F3
  173. F5
  174. F1
  175. F2
  176. F5
  177. F6
  178. F7
  179. F1
  180. F2
  181. F5
  182. F6
  183. F7
  184. F1
  185. F2
  186. F5
  187. F7
  188. F1
  189. F2
  190. F3
  191. F5
  192. F1
  193. F1
  194. F1
  195. F1
  196. F1
  197. F1
  198. F1
  199. F1
  200. F1
  201. F1
  202. IRQ
  203. IRQ
  204. F1
  205. F1
  206. F1
  207. F1
  208. F1
  209. F1
  210. F1
  211. IRQ
  212. F1
  213. IRQ
  214. F2
  215. F2
  216. F2
  217. F2
  218. F2
  219. F2
  220. IRQ
  221. F2
  222. IRQ
  223. F2
  224. F5
  225. IRQ
  226. F1
  227. F2
  228. F4
  229. F1
  230. F2
  231. F4
  232. F1
  233. F2
  234. F4
  235. F1
  236. F2
  237. F4
  238. F1
  239. F7
  240. F1
  241. F7
  242. F1
  243. F7
  244. F1
  245. F7
  246. F3
  247. F4
  248. F7
  249. F3
  250. F4
  251. F1
  252. F7
  253. F1
  254. F7
  255. F3
  256. F1
  257. F2
  258. F3
  259. F5
  260. F1
  261. F2
  262. F3
  263. F1
  264. F2
  265. F3
  266. F5
  267. F1
  268. F2
  269. F3
  270. F1
  271. F2
  272. F3
  273. F5
  274. F1
  275. F5
  276. F1
  277. F2
  278. F3
  279. F1
  280. F2
  281. F3
  282. F5
  283. F1
  284. F2
  285. F3
  286. IRQ
  287. IRQ
  288. IRQ
  289. IRQ
  290. F1
  291. F1
  292. F1
  293. F1
  294. F1
  295. F1
  296. F1
  297. F1
  298. F1
  299. F1
  300. F1
  301. IRQ
  302. IRQ
  303. IRQ
  304. IRQ
  305. F1
  306. F2
  307. IRQ
  308. F1
  309. F2
  310. IRQ
  311. F1
  312. F2
  313. IRQ
  314. F1
  315. F2
  316. IRQ
  317. F1
  318. F2
  319. IRQ
  320. F1
  321. F2
  322. IRQ
  323. F1
  324. F2
  325. IRQ
  326. F1
  327. F2
  328. IRQ
  329. F1
  330. F2
  331. IRQ
  332. F1
  333. F1
  334. F2
  335. F1
  336. F2
  337. F1
  338. F5
  339. F1
  340. F5
  341. F1
  342. F2
  343. F5
  344. F1
  345. F5
  346. F1
  347. F5
  348. F1
  349. F5
  350. F1
  351. F5
  352. F1
  353. F5
  354. F1
  355. F5
  356. F1
  357. F2
  358. F5
  359. F1
  360. F2
  361. F5
  362. F1
  363. F2
  364. F5
  365. F1
  366. F2
  367. F5
  368. F1
  369. F2
  370. F5
  371. F1
  372. F2
  373. F5
  374. F1
  375. F2
  376. F5
  377. F1
  378. F2
  379. F5
  380. F1
  381. F2
  382. F5
  383. F1
  384. F2
  385. F5
  386. F1
  387. F2
  388. F5
  389. F1
  390. F1
  391. F2
  392. F5
  393. F1
  394. F2
  395. F1
  396. F5
  397. F1
  398. F2
  399. F1
  400. F2
  401. F1
  402. F2
  403. F2
  404. F4
  405. F2
  406. F4
  407. F1
  408. F2
  409. F3
  410. F1
  411. F2
  412. F1
  413. F2
  414. F3
  415. F1
  416. F2
  417. F1
  418. F2
  419. F1
  420. F2
  421. F1
  422. F1
  423. F2
  424. F1
  425. F3
  426. F1
  427. F2
  428. F1
  429. F2
  430. F1
  431. F3
  432. F1
  433. F1
  434. F1
  435. F1
  436. F1
  437. F1
  438. F1
  439. F1
  440. F1
  441. F3
  442. F1
  443. F2
  444. F7
  445. F2
  446. F1
  447. F4
  448. F1
  449. F4
  450. F1
  451. F4
  452. F1
  453. F4
  454. F1
  455. F1
  456. F4
  457. F1
  458. F4
  459. F1
  460. F3
  461. F1
  462. F3
  463. F1
  464. F3
  465. F1
  466. F1
  467. F1
  468. F1
  469. F1
  470. F1
  471. F1
  472. F1
  473. F1
  474. F2
  475. F1
  476. F2
  477. F1
  478. F1
  479. F3
  480. F1
  481. F3
  482. IRQ
  483. F1
  484. F3
  485. F1
  486. F3
  487. F1
  488. F3
  489. F1
  490. F3
  491. F1
  492. F2
  493. F3
  494. F1
  495. F4
  496. IRQ
  497. F1
  498. F2
  499. F3
  500. F1
  501. F2
  502. F3
  503. F1
  504. F2
  505. F3
  506. F1
  507. F2
  508. F3
  509. F4
  510. F1
  511. IRQ
  512. F1
  513. F3
  514. F1
  515. F3
  516. F1
  517. F3
  518. F1
  519. F3
  520. F1
  521. F3
  522. F1
  523. F1
  524. F3
  525. IRQ
  526. IRQ
  527. IRQ
  528. IRQ
  529. IRQ
  530. IRQ
  531. IRQ
  532. IRQ
  533. IRQ
  534. IRQ
  535. r8a73a4_pinmux_get_bias
  536. r8a73a4_pinmux_set_bias
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2012-2013  Renesas Solutions Corp.
   4  * Copyright (C) 2013  Magnus Damm
   5  * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  */
   7 #include <linux/io.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pinctrl/pinconf-generic.h>
  10 
  11 #include "sh_pfc.h"
  12 
  13 #define CPU_ALL_PORT(fn, pfx, sfx)                                      \
  14         /*  Port0 - Port30 */                                           \
  15         PORT_10(0, fn, pfx, sfx),                                       \
  16         PORT_10(10, fn, pfx##1, sfx),                                   \
  17         PORT_10(20, fn, pfx##2, sfx),                                   \
  18         PORT_1(30, fn, pfx##30, sfx),                                   \
  19         /* Port32 - Port40 */                                           \
  20         PORT_1(32, fn, pfx##32, sfx),   PORT_1(33, fn, pfx##33, sfx),   \
  21         PORT_1(34, fn, pfx##34, sfx),   PORT_1(35, fn, pfx##35, sfx),   \
  22         PORT_1(36, fn, pfx##36, sfx),   PORT_1(37, fn, pfx##37, sfx),   \
  23         PORT_1(38, fn, pfx##38, sfx),   PORT_1(39, fn, pfx##39, sfx),   \
  24         PORT_1(40, fn, pfx##40, sfx),                                   \
  25         /* Port64  - Port85 */                                          \
  26         PORT_1(64, fn, pfx##64, sfx),   PORT_1(65, fn, pfx##65, sfx),   \
  27         PORT_1(66, fn, pfx##66, sfx),   PORT_1(67, fn, pfx##67, sfx),   \
  28         PORT_1(68, fn, pfx##68, sfx),   PORT_1(69, fn, pfx##69, sfx),   \
  29         PORT_10(70, fn, pfx##7, sfx),                                   \
  30         PORT_1(80, fn, pfx##80, sfx),   PORT_1(81, fn, pfx##81, sfx),   \
  31         PORT_1(82, fn, pfx##82, sfx),   PORT_1(83, fn, pfx##83, sfx),   \
  32         PORT_1(84, fn, pfx##84, sfx),   PORT_1(85, fn, pfx##85, sfx),   \
  33         /* Port96  - Port126 */                                         \
  34         PORT_1(96, fn, pfx##96, sfx),   PORT_1(97, fn, pfx##97, sfx),   \
  35         PORT_1(98, fn, pfx##98, sfx),   PORT_1(99, fn, pfx##99, sfx),   \
  36         PORT_10(100, fn, pfx##10, sfx),                                 \
  37         PORT_10(110, fn, pfx##11, sfx),                                 \
  38         PORT_1(120, fn, pfx##120, sfx), PORT_1(121, fn, pfx##121, sfx), \
  39         PORT_1(122, fn, pfx##122, sfx), PORT_1(123, fn, pfx##123, sfx), \
  40         PORT_1(124, fn, pfx##124, sfx), PORT_1(125, fn, pfx##125, sfx), \
  41         PORT_1(126, fn, pfx##126, sfx),                                 \
  42         /* Port128 - Port134 */                                         \
  43         PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
  44         PORT_1(130, fn, pfx##130, sfx), PORT_1(131, fn, pfx##131, sfx), \
  45         PORT_1(132, fn, pfx##132, sfx), PORT_1(133, fn, pfx##133, sfx), \
  46         PORT_1(134, fn, pfx##134, sfx),                                 \
  47         /* Port160 - Port178 */                                         \
  48         PORT_10(160, fn, pfx##16, sfx),                                 \
  49         PORT_1(170, fn, pfx##170, sfx), PORT_1(171, fn, pfx##171, sfx), \
  50         PORT_1(172, fn, pfx##172, sfx), PORT_1(173, fn, pfx##173, sfx), \
  51         PORT_1(174, fn, pfx##174, sfx), PORT_1(175, fn, pfx##175, sfx), \
  52         PORT_1(176, fn, pfx##176, sfx), PORT_1(177, fn, pfx##177, sfx), \
  53         PORT_1(178, fn, pfx##178, sfx),                                 \
  54         /* Port192 - Port222 */                                         \
  55         PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
  56         PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
  57         PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
  58         PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
  59         PORT_10(200, fn, pfx##20, sfx),                                 \
  60         PORT_10(210, fn, pfx##21, sfx),                                 \
  61         PORT_1(220, fn, pfx##220, sfx), PORT_1(221, fn, pfx##221, sfx), \
  62         PORT_1(222, fn, pfx##222, sfx),                                 \
  63         /* Port224 - Port250 */                                         \
  64         PORT_1(224, fn, pfx##224, sfx), PORT_1(225, fn, pfx##225, sfx), \
  65         PORT_1(226, fn, pfx##226, sfx), PORT_1(227, fn, pfx##227, sfx), \
  66         PORT_1(228, fn, pfx##228, sfx), PORT_1(229, fn, pfx##229, sfx), \
  67         PORT_10(230, fn, pfx##23, sfx),                                 \
  68         PORT_10(240, fn, pfx##24, sfx),                                 \
  69         PORT_1(250, fn, pfx##250, sfx),                                 \
  70         /* Port256 - Port283 */                                         \
  71         PORT_1(256, fn, pfx##256, sfx), PORT_1(257, fn, pfx##257, sfx), \
  72         PORT_1(258, fn, pfx##258, sfx), PORT_1(259, fn, pfx##259, sfx), \
  73         PORT_10(260, fn, pfx##26, sfx),                                 \
  74         PORT_10(270, fn, pfx##27, sfx),                                 \
  75         PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
  76         PORT_1(282, fn, pfx##282, sfx), PORT_1(283, fn, pfx##283, sfx), \
  77         /* Port288 - Port308 */                                         \
  78         PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
  79         PORT_10(290, fn, pfx##29, sfx),                                 \
  80         PORT_1(300, fn, pfx##300, sfx), PORT_1(301, fn, pfx##301, sfx), \
  81         PORT_1(302, fn, pfx##302, sfx), PORT_1(303, fn, pfx##303, sfx), \
  82         PORT_1(304, fn, pfx##304, sfx), PORT_1(305, fn, pfx##305, sfx), \
  83         PORT_1(306, fn, pfx##306, sfx), PORT_1(307, fn, pfx##307, sfx), \
  84         PORT_1(308, fn, pfx##308, sfx),                                 \
  85         /* Port320 - Port329 */                                         \
  86         PORT_10(320, fn, pfx##32, sfx)
  87 
  88 
  89 enum {
  90         PINMUX_RESERVED = 0,
  91 
  92         /* PORT0_DATA -> PORT329_DATA */
  93         PINMUX_DATA_BEGIN,
  94         PORT_ALL(DATA),
  95         PINMUX_DATA_END,
  96 
  97         /* PORT0_IN -> PORT329_IN */
  98         PINMUX_INPUT_BEGIN,
  99         PORT_ALL(IN),
 100         PINMUX_INPUT_END,
 101 
 102         /* PORT0_OUT -> PORT329_OUT */
 103         PINMUX_OUTPUT_BEGIN,
 104         PORT_ALL(OUT),
 105         PINMUX_OUTPUT_END,
 106 
 107         PINMUX_FUNCTION_BEGIN,
 108         PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
 109         PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
 110         PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
 111         PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
 112         PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
 113         PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
 114         PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
 115         PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
 116         PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
 117         PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
 118 
 119         MSEL1CR_31_0, MSEL1CR_31_1,
 120         MSEL1CR_27_0, MSEL1CR_27_1,
 121         MSEL1CR_25_0, MSEL1CR_25_1,
 122         MSEL1CR_24_0, MSEL1CR_24_1,
 123         MSEL1CR_22_0, MSEL1CR_22_1,
 124         MSEL1CR_21_0, MSEL1CR_21_1,
 125         MSEL1CR_20_0, MSEL1CR_20_1,
 126         MSEL1CR_19_0, MSEL1CR_19_1,
 127         MSEL1CR_18_0, MSEL1CR_18_1,
 128         MSEL1CR_17_0, MSEL1CR_17_1,
 129         MSEL1CR_16_0, MSEL1CR_16_1,
 130         MSEL1CR_15_0, MSEL1CR_15_1,
 131         MSEL1CR_14_0, MSEL1CR_14_1,
 132         MSEL1CR_13_0, MSEL1CR_13_1,
 133         MSEL1CR_12_0, MSEL1CR_12_1,
 134         MSEL1CR_11_0, MSEL1CR_11_1,
 135         MSEL1CR_10_0, MSEL1CR_10_1,
 136         MSEL1CR_09_0, MSEL1CR_09_1,
 137         MSEL1CR_08_0, MSEL1CR_08_1,
 138         MSEL1CR_07_0, MSEL1CR_07_1,
 139         MSEL1CR_06_0, MSEL1CR_06_1,
 140         MSEL1CR_05_0, MSEL1CR_05_1,
 141         MSEL1CR_04_0, MSEL1CR_04_1,
 142         MSEL1CR_03_0, MSEL1CR_03_1,
 143         MSEL1CR_02_0, MSEL1CR_02_1,
 144         MSEL1CR_01_0, MSEL1CR_01_1,
 145         MSEL1CR_00_0, MSEL1CR_00_1,
 146 
 147         MSEL3CR_31_0, MSEL3CR_31_1,
 148         MSEL3CR_28_0, MSEL3CR_28_1,
 149         MSEL3CR_27_0, MSEL3CR_27_1,
 150         MSEL3CR_26_0, MSEL3CR_26_1,
 151         MSEL3CR_23_0, MSEL3CR_23_1,
 152         MSEL3CR_22_0, MSEL3CR_22_1,
 153         MSEL3CR_21_0, MSEL3CR_21_1,
 154         MSEL3CR_20_0, MSEL3CR_20_1,
 155         MSEL3CR_19_0, MSEL3CR_19_1,
 156         MSEL3CR_18_0, MSEL3CR_18_1,
 157         MSEL3CR_17_0, MSEL3CR_17_1,
 158         MSEL3CR_16_0, MSEL3CR_16_1,
 159         MSEL3CR_15_0, MSEL3CR_15_1,
 160         MSEL3CR_12_0, MSEL3CR_12_1,
 161         MSEL3CR_11_0, MSEL3CR_11_1,
 162         MSEL3CR_10_0, MSEL3CR_10_1,
 163         MSEL3CR_09_0, MSEL3CR_09_1,
 164         MSEL3CR_06_0, MSEL3CR_06_1,
 165         MSEL3CR_03_0, MSEL3CR_03_1,
 166         MSEL3CR_01_0, MSEL3CR_01_1,
 167         MSEL3CR_00_0, MSEL3CR_00_1,
 168 
 169         MSEL4CR_30_0, MSEL4CR_30_1,
 170         MSEL4CR_29_0, MSEL4CR_29_1,
 171         MSEL4CR_28_0, MSEL4CR_28_1,
 172         MSEL4CR_27_0, MSEL4CR_27_1,
 173         MSEL4CR_26_0, MSEL4CR_26_1,
 174         MSEL4CR_25_0, MSEL4CR_25_1,
 175         MSEL4CR_24_0, MSEL4CR_24_1,
 176         MSEL4CR_23_0, MSEL4CR_23_1,
 177         MSEL4CR_22_0, MSEL4CR_22_1,
 178         MSEL4CR_21_0, MSEL4CR_21_1,
 179         MSEL4CR_20_0, MSEL4CR_20_1,
 180         MSEL4CR_19_0, MSEL4CR_19_1,
 181         MSEL4CR_18_0, MSEL4CR_18_1,
 182         MSEL4CR_17_0, MSEL4CR_17_1,
 183         MSEL4CR_16_0, MSEL4CR_16_1,
 184         MSEL4CR_15_0, MSEL4CR_15_1,
 185         MSEL4CR_14_0, MSEL4CR_14_1,
 186         MSEL4CR_13_0, MSEL4CR_13_1,
 187         MSEL4CR_12_0, MSEL4CR_12_1,
 188         MSEL4CR_11_0, MSEL4CR_11_1,
 189         MSEL4CR_10_0, MSEL4CR_10_1,
 190         MSEL4CR_09_0, MSEL4CR_09_1,
 191         MSEL4CR_07_0, MSEL4CR_07_1,
 192         MSEL4CR_04_0, MSEL4CR_04_1,
 193         MSEL4CR_01_0, MSEL4CR_01_1,
 194 
 195         MSEL5CR_31_0, MSEL5CR_31_1,
 196         MSEL5CR_30_0, MSEL5CR_30_1,
 197         MSEL5CR_29_0, MSEL5CR_29_1,
 198         MSEL5CR_28_0, MSEL5CR_28_1,
 199         MSEL5CR_27_0, MSEL5CR_27_1,
 200         MSEL5CR_26_0, MSEL5CR_26_1,
 201         MSEL5CR_25_0, MSEL5CR_25_1,
 202         MSEL5CR_24_0, MSEL5CR_24_1,
 203         MSEL5CR_23_0, MSEL5CR_23_1,
 204         MSEL5CR_22_0, MSEL5CR_22_1,
 205         MSEL5CR_21_0, MSEL5CR_21_1,
 206         MSEL5CR_20_0, MSEL5CR_20_1,
 207         MSEL5CR_19_0, MSEL5CR_19_1,
 208         MSEL5CR_18_0, MSEL5CR_18_1,
 209         MSEL5CR_17_0, MSEL5CR_17_1,
 210         MSEL5CR_16_0, MSEL5CR_16_1,
 211         MSEL5CR_15_0, MSEL5CR_15_1,
 212         MSEL5CR_14_0, MSEL5CR_14_1,
 213         MSEL5CR_13_0, MSEL5CR_13_1,
 214         MSEL5CR_12_0, MSEL5CR_12_1,
 215         MSEL5CR_11_0, MSEL5CR_11_1,
 216         MSEL5CR_10_0, MSEL5CR_10_1,
 217         MSEL5CR_09_0, MSEL5CR_09_1,
 218         MSEL5CR_08_0, MSEL5CR_08_1,
 219         MSEL5CR_07_0, MSEL5CR_07_1,
 220         MSEL5CR_06_0, MSEL5CR_06_1,
 221 
 222         MSEL8CR_16_0, MSEL8CR_16_1,
 223         MSEL8CR_01_0, MSEL8CR_01_1,
 224         MSEL8CR_00_0, MSEL8CR_00_1,
 225 
 226         PINMUX_FUNCTION_END,
 227 
 228         PINMUX_MARK_BEGIN,
 229 
 230 
 231 #define F1(a)   a##_MARK
 232 #define F2(a)   a##_MARK
 233 #define F3(a)   a##_MARK
 234 #define F4(a)   a##_MARK
 235 #define F5(a)   a##_MARK
 236 #define F6(a)   a##_MARK
 237 #define F7(a)   a##_MARK
 238 #define IRQ(a)  IRQ##a##_MARK
 239 
 240         F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
 241         F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
 242         F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
 243         F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
 244         F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
 245         F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
 246         F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
 247         F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
 248         F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
 249         F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
 250         F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
 251         F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
 252         F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
 253         F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
 254         F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
 255         F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
 256         F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
 257         F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
 258         F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
 259         F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
 260         F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
 261         F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
 262         F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
 263         F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
 264         F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
 265         F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
 266         F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
 267         F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
 268         F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
 269         F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
 270         F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
 271         F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
 272 
 273         F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
 274         F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
 275         F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
 276         F1(SCIFA1_RTS), F7(CSCIF1_RTS),
 277         F1(SCIFA1_CTS), F7(CSCIF1_CTS),
 278         F1(SCIFA1_SCK), F7(CSCIF1_SCK),
 279         F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
 280         F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
 281         F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
 282         F7(CHSCIF0_HSCK), /* Port40 */
 283 
 284         F1(PDM0_DATA), /* Port64 */
 285         F1(PDM1_DATA),
 286         F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
 287         IRQ(40),
 288         F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
 289         F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
 290         F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
 291         F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
 292         F7(CHSCIF1_HRTS), /* Port70 */
 293         F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
 294         F7(CHSCIF1_HCTS),
 295         F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
 296         F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
 297         F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
 298         F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
 299         F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
 300 
 301         F1(KEYIN0), /* Port96 */
 302         F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
 303         F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
 304         F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
 305         F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
 306         F2(KEYOUT7), F5(RFANAEN), IRQ(45),
 307         F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
 308         F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
 309         F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
 310         F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
 311         F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
 312         F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
 313         F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
 314         F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
 315         F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
 316         F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
 317         F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
 318         F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
 319         F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
 320         F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
 321         F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
 322         F5(SIM0_VOLTSEL1), /* Port130 */
 323         F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
 324         F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
 325         F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
 326         IRQ(20), /* Port160 */
 327         IRQ(21), IRQ(22), IRQ(23),
 328         F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
 329         F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
 330         F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
 331         IRQ(24), IRQ(25), IRQ(26), IRQ(27),
 332         F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
 333         F1(A9), F2(MMCD1_6), IRQ(32),
 334         F1(A8), F2(MMCD1_5), IRQ(33),
 335         F1(A7), F2(MMCD1_4), IRQ(34),
 336         F1(A6), F2(MMCD1_3), IRQ(35),
 337         F1(A5), F2(MMCD1_2), IRQ(36),
 338         F1(A4), F2(MMCD1_1), IRQ(37),
 339         F1(A3), F2(MMCD1_0), IRQ(38),
 340         F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
 341         F1(A1),
 342         F1(A0), F2(BS),
 343         F1(CKO), F2(MMCCLK1),
 344         F1(CS0_N), F5(SIM0_GPO1),
 345         F1(CS2_N), F5(SIM0_GPO2),
 346         F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
 347         F1(D15), F5(GIO_OUT15),
 348         F1(D14), F5(GIO_OUT14),
 349         F1(D13), F5(GIO_OUT13),
 350         F1(D12), F5(GIO_OUT12), /* Port210 */
 351         F1(D11), F5(WGM_TXP2),
 352         F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
 353         F1(D9), F2(VIO_D9), F5(GIO_OUT9),
 354         F1(D8), F2(VIO_D8), F5(GIO_OUT8),
 355         F1(D7), F2(VIO_D7), F5(GIO_OUT7),
 356         F1(D6), F2(VIO_D6), F5(GIO_OUT6),
 357         F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
 358         F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
 359         F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
 360         F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
 361         F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
 362         F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
 363         F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
 364         F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
 365         F1(WE0_N), F2(RDWR_227),
 366         F1(WE1_N), F5(SIM0_GPO0),
 367         F1(PWMO), F2(VIO_CKO1_229),
 368         F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
 369         F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
 370         F2(VIO_CKO3_233), F4(SF_PORT_1_233),
 371         F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
 372         F1(FSIAISLD), F2(PDM3_DATA_235),
 373         F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
 374         F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
 375         F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
 376         F1(FSIBISLD), /* Port240 */
 377         F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
 378         F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
 379         F1(FSIBCK), F3(ISP_SHUTTER0_245),
 380         F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
 381         F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
 382         F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
 383         F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
 384         F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
 385         F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
 386         F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
 387         F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
 388         F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
 389         F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
 390         F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
 391         F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
 392         F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
 393         F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
 394         F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
 395         F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
 396         F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
 397         F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
 398         F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
 399         F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
 400         F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
 401         F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
 402         F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
 403         F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
 404         F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
 405         F4(MSIOF6_SS1), /* Port300 */
 406         F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
 407         F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
 408         F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
 409         F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
 410         IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
 411         IRQ(55), IRQ(56), IRQ(57),
 412         PINMUX_MARK_END,
 413 };
 414 
 415 static const u16 pinmux_data[] = {
 416         /* specify valid pin states for each pin in GPIO mode */
 417         PINMUX_DATA_ALL(),
 418 
 419         /* Port0 */
 420         PINMUX_DATA(LCDD0_MARK,         PORT0_FN1),
 421         PINMUX_DATA(PDM2_CLK_0_MARK,    PORT0_FN3),
 422         PINMUX_DATA(DU0_DR0_MARK,       PORT0_FN7),
 423         PINMUX_DATA(IRQ0_MARK,          PORT0_FN0),
 424 
 425         /* Port1 */
 426         PINMUX_DATA(LCDD1_MARK,         PORT1_FN1),
 427         PINMUX_DATA(PDM2_DATA_1_MARK,   PORT1_FN3,      MSEL3CR_12_0),
 428         PINMUX_DATA(DU0_DR19_MARK,      PORT1_FN7),
 429         PINMUX_DATA(IRQ1_MARK,          PORT1_FN0),
 430 
 431         /* Port2 */
 432         PINMUX_DATA(LCDD2_MARK,         PORT2_FN1),
 433         PINMUX_DATA(PDM3_CLK_2_MARK,    PORT2_FN3),
 434         PINMUX_DATA(DU0_DR2_MARK,       PORT2_FN7),
 435         PINMUX_DATA(IRQ2_MARK,          PORT2_FN0),
 436 
 437         /* Port3 */
 438         PINMUX_DATA(LCDD3_MARK,         PORT3_FN1),
 439         PINMUX_DATA(PDM3_DATA_3_MARK,   PORT3_FN3,      MSEL3CR_12_0),
 440         PINMUX_DATA(DU0_DR3_MARK,       PORT3_FN7),
 441         PINMUX_DATA(IRQ3_MARK,          PORT3_FN0),
 442 
 443         /* Port4 */
 444         PINMUX_DATA(LCDD4_MARK,         PORT4_FN1),
 445         PINMUX_DATA(PDM4_CLK_4_MARK,    PORT4_FN3),
 446         PINMUX_DATA(DU0_DR4_MARK,       PORT4_FN7),
 447         PINMUX_DATA(IRQ4_MARK,          PORT4_FN0),
 448 
 449         /* Port5 */
 450         PINMUX_DATA(LCDD5_MARK,         PORT5_FN1),
 451         PINMUX_DATA(PDM4_DATA_5_MARK,   PORT5_FN3,      MSEL3CR_12_0),
 452         PINMUX_DATA(DU0_DR5_MARK,       PORT5_FN7),
 453         PINMUX_DATA(IRQ5_MARK,          PORT5_FN0),
 454 
 455         /* Port6 */
 456         PINMUX_DATA(LCDD6_MARK,         PORT6_FN1),
 457         PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
 458         PINMUX_DATA(DU0_DR6_MARK,       PORT6_FN7),
 459         PINMUX_DATA(IRQ6_MARK,          PORT6_FN0),
 460 
 461         /* Port7 */
 462         PINMUX_DATA(LCDD7_MARK,                 PORT7_FN1),
 463         PINMUX_DATA(PDM0_OUTDATA_7_MARK,        PORT7_FN3),
 464         PINMUX_DATA(DU0_DR7_MARK,               PORT7_FN7),
 465         PINMUX_DATA(IRQ7_MARK,                  PORT7_FN0),
 466 
 467         /* Port8 */
 468         PINMUX_DATA(LCDD8_MARK,         PORT8_FN1),
 469         PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
 470         PINMUX_DATA(DU0_DG0_MARK,       PORT8_FN7),
 471         PINMUX_DATA(IRQ8_MARK,          PORT8_FN0),
 472 
 473         /* Port9 */
 474         PINMUX_DATA(LCDD9_MARK,         PORT9_FN1),
 475         PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
 476         PINMUX_DATA(DU0_DG1_MARK,       PORT9_FN7),
 477         PINMUX_DATA(IRQ9_MARK,          PORT9_FN0),
 478 
 479         /* Port10 */
 480         PINMUX_DATA(LCDD10_MARK,                PORT10_FN1),
 481         PINMUX_DATA(FSICCK_MARK,                PORT10_FN3),
 482         PINMUX_DATA(DU0_DG2_MARK,               PORT10_FN7),
 483         PINMUX_DATA(IRQ10_MARK,                 PORT10_FN0),
 484 
 485         /* Port11 */
 486         PINMUX_DATA(LCDD11_MARK,                PORT11_FN1),
 487         PINMUX_DATA(FSICISLD_MARK,              PORT11_FN3),
 488         PINMUX_DATA(DU0_DG3_MARK,               PORT11_FN7),
 489         PINMUX_DATA(IRQ11_MARK,                 PORT11_FN0),
 490 
 491         /* Port12 */
 492         PINMUX_DATA(LCDD12_MARK,                PORT12_FN1),
 493         PINMUX_DATA(FSICOMC_MARK,               PORT12_FN3),
 494         PINMUX_DATA(DU0_DG4_MARK,               PORT12_FN7),
 495         PINMUX_DATA(IRQ12_MARK,                 PORT12_FN0),
 496 
 497         /* Port13 */
 498         PINMUX_DATA(LCDD13_MARK,                PORT13_FN1),
 499         PINMUX_DATA(FSICOLR_MARK,               PORT13_FN3),
 500         PINMUX_DATA(FSICILR_MARK,               PORT13_FN4),
 501         PINMUX_DATA(DU0_DG5_MARK,               PORT13_FN7),
 502         PINMUX_DATA(IRQ13_MARK,                 PORT13_FN0),
 503 
 504         /* Port14 */
 505         PINMUX_DATA(LCDD14_MARK,                PORT14_FN1),
 506         PINMUX_DATA(FSICOBT_MARK,               PORT14_FN3),
 507         PINMUX_DATA(FSICIBT_MARK,               PORT14_FN4),
 508         PINMUX_DATA(DU0_DG6_MARK,               PORT14_FN7),
 509         PINMUX_DATA(IRQ14_MARK,                 PORT14_FN0),
 510 
 511         /* Port15 */
 512         PINMUX_DATA(LCDD15_MARK,                PORT15_FN1),
 513         PINMUX_DATA(FSICOSLD_MARK,              PORT15_FN3),
 514         PINMUX_DATA(DU0_DG7_MARK,               PORT15_FN7),
 515         PINMUX_DATA(IRQ15_MARK,                 PORT15_FN0),
 516 
 517         /* Port16 */
 518         PINMUX_DATA(LCDD16_MARK,                PORT16_FN1),
 519         PINMUX_DATA(TPU1TO1_MARK,               PORT16_FN4),
 520         PINMUX_DATA(DU0_DB0_MARK,               PORT16_FN7),
 521 
 522         /* Port17 */
 523         PINMUX_DATA(LCDD17_MARK,                PORT17_FN1),
 524         PINMUX_DATA(SF_IRQ_00_MARK,             PORT17_FN4),
 525         PINMUX_DATA(DU0_DB1_MARK,               PORT17_FN7),
 526 
 527         /* Port18 */
 528         PINMUX_DATA(LCDD18_MARK,                PORT18_FN1),
 529         PINMUX_DATA(SF_IRQ_01_MARK,             PORT18_FN4),
 530         PINMUX_DATA(DU0_DB2_MARK,               PORT18_FN7),
 531 
 532         /* Port19 */
 533         PINMUX_DATA(LCDD19_MARK,                PORT19_FN1),
 534         PINMUX_DATA(SCIFB3_RTS_19_MARK,         PORT19_FN3),
 535         PINMUX_DATA(DU0_DB3_MARK,               PORT19_FN7),
 536 
 537         /* Port20 */
 538         PINMUX_DATA(LCDD20_MARK,                PORT20_FN1),
 539         PINMUX_DATA(SCIFB3_CTS_20_MARK,         PORT20_FN3,     MSEL3CR_09_0),
 540         PINMUX_DATA(DU0_DB4_MARK,               PORT20_FN7),
 541 
 542         /* Port21 */
 543         PINMUX_DATA(LCDD21_MARK,                PORT21_FN1),
 544         PINMUX_DATA(SCIFB3_TXD_21_MARK,         PORT21_FN3,     MSEL3CR_09_0),
 545         PINMUX_DATA(DU0_DB5_MARK,               PORT21_FN7),
 546 
 547         /* Port22 */
 548         PINMUX_DATA(LCDD22_MARK,                PORT22_FN1),
 549         PINMUX_DATA(SCIFB3_RXD_22_MARK,         PORT22_FN3,     MSEL3CR_09_0),
 550         PINMUX_DATA(DU0_DB6_MARK,               PORT22_FN7),
 551 
 552         /* Port23 */
 553         PINMUX_DATA(LCDD23_MARK,                PORT23_FN1),
 554         PINMUX_DATA(SCIFB3_SCK_23_MARK,         PORT23_FN3),
 555         PINMUX_DATA(DU0_DB7_MARK,               PORT23_FN7),
 556 
 557         /* Port24 */
 558         PINMUX_DATA(LCDHSYN_MARK,                       PORT24_FN1),
 559         PINMUX_DATA(LCDCS_MARK,                         PORT24_FN2),
 560         PINMUX_DATA(SCIFB1_RTS_24_MARK,                 PORT24_FN3),
 561         PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
 562 
 563         /* Port25 */
 564         PINMUX_DATA(LCDVSYN_MARK,                       PORT25_FN1),
 565         PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
 566         PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
 567 
 568         /* Port26 */
 569         PINMUX_DATA(LCDDCK_MARK,                PORT26_FN1),
 570         PINMUX_DATA(LCDWR_MARK,                 PORT26_FN2),
 571         PINMUX_DATA(SCIFB1_TXD_26_MARK,         PORT26_FN3,     MSEL3CR_11_0),
 572         PINMUX_DATA(DU0_DOTCLKIN_MARK,          PORT26_FN7),
 573 
 574         /* Port27 */
 575         PINMUX_DATA(LCDDISP_MARK,               PORT27_FN1),
 576         PINMUX_DATA(LCDRS_MARK,                 PORT27_FN2),
 577         PINMUX_DATA(SCIFB1_RXD_27_MARK,         PORT27_FN3,     MSEL3CR_11_0),
 578         PINMUX_DATA(DU0_DOTCLKOUT_MARK,         PORT27_FN7),
 579 
 580         /* Port28 */
 581         PINMUX_DATA(LCDRD_N_MARK,               PORT28_FN1),
 582         PINMUX_DATA(SCIFB1_SCK_28_MARK,         PORT28_FN3),
 583         PINMUX_DATA(DU0_DOTCLKOUTB_MARK,        PORT28_FN7),
 584 
 585         /* Port29 */
 586         PINMUX_DATA(LCDLCLK_MARK,               PORT29_FN1),
 587         PINMUX_DATA(SF_IRQ_02_MARK,             PORT29_FN4),
 588         PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK,   PORT29_FN7),
 589 
 590         /* Port30 */
 591         PINMUX_DATA(LCDDON_MARK,                PORT30_FN1),
 592         PINMUX_DATA(SF_IRQ_03_MARK,             PORT30_FN4),
 593         PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK,      PORT30_FN7),
 594 
 595         /* Port32 */
 596         PINMUX_DATA(SCIFA0_RTS_MARK,            PORT32_FN1),
 597         PINMUX_DATA(SIM0_DET_MARK,              PORT32_FN5),
 598         PINMUX_DATA(CSCIF0_RTS_MARK,            PORT32_FN7),
 599 
 600         /* Port33 */
 601         PINMUX_DATA(SCIFA0_CTS_MARK,            PORT33_FN1),
 602         PINMUX_DATA(SIM1_DET_MARK,              PORT33_FN5),
 603         PINMUX_DATA(CSCIF0_CTS_MARK,            PORT33_FN7),
 604 
 605         /* Port34 */
 606         PINMUX_DATA(SCIFA0_SCK_MARK,            PORT34_FN1),
 607         PINMUX_DATA(SIM0_PWRON_MARK,            PORT34_FN5),
 608         PINMUX_DATA(CSCIF0_SCK_MARK,            PORT34_FN7),
 609 
 610         /* Port35 */
 611         PINMUX_DATA(SCIFA1_RTS_MARK,            PORT35_FN1),
 612         PINMUX_DATA(CSCIF1_RTS_MARK,            PORT35_FN7),
 613 
 614         /* Port36 */
 615         PINMUX_DATA(SCIFA1_CTS_MARK,            PORT36_FN1),
 616         PINMUX_DATA(CSCIF1_CTS_MARK,            PORT36_FN7),
 617 
 618         /* Port37 */
 619         PINMUX_DATA(SCIFA1_SCK_MARK,            PORT37_FN1),
 620         PINMUX_DATA(CSCIF1_SCK_MARK,            PORT37_FN7),
 621 
 622         /* Port38 */
 623         PINMUX_DATA(SCIFB0_RTS_MARK,            PORT38_FN1),
 624         PINMUX_DATA(TPU0TO1_MARK,               PORT38_FN3),
 625         PINMUX_DATA(SCIFB3_RTS_38_MARK,         PORT38_FN4),
 626         PINMUX_DATA(CHSCIF0_HRTS_MARK,          PORT38_FN7),
 627 
 628         /* Port39 */
 629         PINMUX_DATA(SCIFB0_CTS_MARK,            PORT39_FN1),
 630         PINMUX_DATA(TPU0TO2_MARK,               PORT39_FN3),
 631         PINMUX_DATA(SCIFB3_CTS_39_MARK,         PORT39_FN4,     MSEL3CR_09_1),
 632         PINMUX_DATA(CHSCIF0_HCTS_MARK,          PORT39_FN7),
 633 
 634         /* Port40 */
 635         PINMUX_DATA(SCIFB0_SCK_MARK,            PORT40_FN1),
 636         PINMUX_DATA(TPU0TO3_MARK,               PORT40_FN3),
 637         PINMUX_DATA(SCIFB3_SCK_40_MARK,         PORT40_FN4),
 638         PINMUX_DATA(CHSCIF0_HSCK_MARK,          PORT40_FN7),
 639 
 640         /* Port64 */
 641         PINMUX_DATA(PDM0_DATA_MARK,             PORT64_FN1),
 642 
 643         /* Port65 */
 644         PINMUX_DATA(PDM1_DATA_MARK,             PORT65_FN1),
 645 
 646         /* Port66 */
 647         PINMUX_DATA(HSI_RX_WAKE_MARK,           PORT66_FN1),
 648         PINMUX_DATA(SCIFB2_CTS_66_MARK,         PORT66_FN2,     MSEL3CR_10_0),
 649         PINMUX_DATA(MSIOF3_SYNC_MARK,           PORT66_FN3),
 650         PINMUX_DATA(GenIO4_MARK,                PORT66_FN5),
 651         PINMUX_DATA(IRQ40_MARK,                 PORT66_FN0),
 652 
 653         /* Port67 */
 654         PINMUX_DATA(HSI_RX_READY_MARK,          PORT67_FN1),
 655         PINMUX_DATA(SCIFB1_TXD_67_MARK,         PORT67_FN2,     MSEL3CR_11_1),
 656         PINMUX_DATA(GIO_OUT3_67_MARK,           PORT67_FN5),
 657         PINMUX_DATA(CHSCIF1_HTX_MARK,           PORT67_FN7),
 658 
 659         /* Port68 */
 660         PINMUX_DATA(HSI_RX_FLAG_MARK,           PORT68_FN1),
 661         PINMUX_DATA(SCIFB2_TXD_68_MARK,         PORT68_FN2,     MSEL3CR_10_0),
 662         PINMUX_DATA(MSIOF3_TXD_MARK,            PORT68_FN3),
 663         PINMUX_DATA(GIO_OUT4_68_MARK,           PORT68_FN5),
 664 
 665         /* Port69 */
 666         PINMUX_DATA(HSI_RX_DATA_MARK,           PORT69_FN1),
 667         PINMUX_DATA(SCIFB2_RXD_69_MARK,         PORT69_FN2,     MSEL3CR_10_0),
 668         PINMUX_DATA(MSIOF3_RXD_MARK,            PORT69_FN3),
 669         PINMUX_DATA(GIO_OUT5_69_MARK,           PORT69_FN5),
 670 
 671         /* Port70 */
 672         PINMUX_DATA(HSI_TX_FLAG_MARK,           PORT70_FN1),
 673         PINMUX_DATA(SCIFB1_RTS_70_MARK,         PORT70_FN2),
 674         PINMUX_DATA(GIO_OUT1_70_MARK,           PORT70_FN5),
 675         PINMUX_DATA(HSIC_TSTCLK0_MARK,          PORT70_FN6),
 676         PINMUX_DATA(CHSCIF1_HRTS_MARK,          PORT70_FN7),
 677 
 678         /* Port71 */
 679         PINMUX_DATA(HSI_TX_DATA_MARK,           PORT71_FN1),
 680         PINMUX_DATA(SCIFB1_CTS_71_MARK,         PORT71_FN2,     MSEL3CR_11_1),
 681         PINMUX_DATA(GIO_OUT2_71_MARK,           PORT71_FN5),
 682         PINMUX_DATA(HSIC_TSTCLK1_MARK,          PORT71_FN6),
 683         PINMUX_DATA(CHSCIF1_HCTS_MARK,          PORT71_FN7),
 684 
 685         /* Port72 */
 686         PINMUX_DATA(HSI_TX_WAKE_MARK,           PORT72_FN1),
 687         PINMUX_DATA(SCIFB1_RXD_72_MARK,         PORT72_FN2,     MSEL3CR_11_1),
 688         PINMUX_DATA(GenIO8_MARK,                PORT72_FN5),
 689         PINMUX_DATA(CHSCIF1_HRX_MARK,           PORT72_FN7),
 690 
 691         /* Port73 */
 692         PINMUX_DATA(HSI_TX_READY_MARK,          PORT73_FN1),
 693         PINMUX_DATA(SCIFB2_RTS_73_MARK,         PORT73_FN2),
 694         PINMUX_DATA(MSIOF3_SCK_MARK,            PORT73_FN3),
 695         PINMUX_DATA(GIO_OUT0_73_MARK,           PORT73_FN5),
 696 
 697         /* Port74 - Port85 */
 698         PINMUX_DATA(IRDA_OUT_MARK,              PORT74_FN1),
 699         PINMUX_DATA(IRDA_IN_MARK,               PORT75_FN1),
 700         PINMUX_DATA(IRDA_FIRSEL_MARK,           PORT76_FN1),
 701         PINMUX_DATA(TPU0TO0_MARK,               PORT77_FN1),
 702         PINMUX_DATA(DIGRFEN_MARK,               PORT78_FN1),
 703         PINMUX_DATA(GPS_TIMESTAMP_MARK,         PORT79_FN1),
 704         PINMUX_DATA(TXP_MARK,                   PORT80_FN1),
 705         PINMUX_DATA(TXP2_MARK,                  PORT81_FN1),
 706         PINMUX_DATA(COEX_0_MARK,                PORT82_FN1),
 707         PINMUX_DATA(COEX_1_MARK,                PORT83_FN1),
 708         PINMUX_DATA(IRQ19_MARK,                 PORT84_FN0),
 709         PINMUX_DATA(IRQ18_MARK,                 PORT85_FN0),
 710 
 711         /* Port96 - Port101 */
 712         PINMUX_DATA(KEYIN0_MARK,                PORT96_FN1),
 713         PINMUX_DATA(KEYIN1_MARK,                PORT97_FN1),
 714         PINMUX_DATA(KEYIN2_MARK,                PORT98_FN1),
 715         PINMUX_DATA(KEYIN3_MARK,                PORT99_FN1),
 716         PINMUX_DATA(KEYIN4_MARK,                PORT100_FN1),
 717         PINMUX_DATA(KEYIN5_MARK,                PORT101_FN1),
 718 
 719         /* Port102 */
 720         PINMUX_DATA(KEYIN6_MARK,                PORT102_FN1),
 721         PINMUX_DATA(IRQ41_MARK,                 PORT102_FN0),
 722 
 723         /* Port103 */
 724         PINMUX_DATA(KEYIN7_MARK,                PORT103_FN1),
 725         PINMUX_DATA(IRQ42_MARK,                 PORT103_FN0),
 726 
 727         /* Port104 - Port108 */
 728         PINMUX_DATA(KEYOUT0_MARK,               PORT104_FN2),
 729         PINMUX_DATA(KEYOUT1_MARK,               PORT105_FN2),
 730         PINMUX_DATA(KEYOUT2_MARK,               PORT106_FN2),
 731         PINMUX_DATA(KEYOUT3_MARK,               PORT107_FN2),
 732         PINMUX_DATA(KEYOUT4_MARK,               PORT108_FN2),
 733 
 734         /* Port109 */
 735         PINMUX_DATA(KEYOUT5_MARK,               PORT109_FN2),
 736         PINMUX_DATA(IRQ43_MARK,                 PORT109_FN0),
 737 
 738         /* Port110 */
 739         PINMUX_DATA(KEYOUT6_MARK,               PORT110_FN2),
 740         PINMUX_DATA(IRQ44_MARK,                 PORT110_FN0),
 741 
 742         /* Port111 */
 743         PINMUX_DATA(KEYOUT7_MARK,               PORT111_FN2),
 744         PINMUX_DATA(RFANAEN_MARK,               PORT111_FN5),
 745         PINMUX_DATA(IRQ45_MARK,                 PORT111_FN0),
 746 
 747         /* Port112 */
 748         PINMUX_DATA(KEYIN8_MARK,                PORT112_FN1),
 749         PINMUX_DATA(KEYOUT8_MARK,               PORT112_FN2),
 750         PINMUX_DATA(SF_IRQ_04_MARK,             PORT112_FN4),
 751         PINMUX_DATA(IRQ46_MARK,                 PORT112_FN0),
 752 
 753         /* Port113 */
 754         PINMUX_DATA(KEYIN9_MARK,                PORT113_FN1),
 755         PINMUX_DATA(KEYOUT9_MARK,               PORT113_FN2),
 756         PINMUX_DATA(SF_IRQ_05_MARK,             PORT113_FN4),
 757         PINMUX_DATA(IRQ47_MARK,                 PORT113_FN0),
 758 
 759         /* Port114 */
 760         PINMUX_DATA(KEYIN10_MARK,               PORT114_FN1),
 761         PINMUX_DATA(KEYOUT10_MARK,              PORT114_FN2),
 762         PINMUX_DATA(SF_IRQ_06_MARK,             PORT114_FN4),
 763         PINMUX_DATA(IRQ48_MARK,                 PORT114_FN0),
 764 
 765         /* Port115 */
 766         PINMUX_DATA(KEYIN11_MARK,               PORT115_FN1),
 767         PINMUX_DATA(KEYOUT11_MARK,              PORT115_FN2),
 768         PINMUX_DATA(SF_IRQ_07_MARK,             PORT115_FN4),
 769         PINMUX_DATA(IRQ49_MARK,                 PORT115_FN0),
 770 
 771         /* Port116 */
 772         PINMUX_DATA(SCIFA0_TXD_MARK,            PORT116_FN1),
 773         PINMUX_DATA(CSCIF0_TX_MARK,             PORT116_FN7),
 774 
 775         /* Port117 */
 776         PINMUX_DATA(SCIFA0_RXD_MARK,            PORT117_FN1),
 777         PINMUX_DATA(CSCIF0_RX_MARK,             PORT117_FN7),
 778 
 779         /* Port118 */
 780         PINMUX_DATA(SCIFA1_TXD_MARK,            PORT118_FN1),
 781         PINMUX_DATA(CSCIF1_TX_MARK,             PORT118_FN7),
 782 
 783         /* Port119 */
 784         PINMUX_DATA(SCIFA1_RXD_MARK,            PORT119_FN1),
 785         PINMUX_DATA(CSCIF1_RX_MARK,             PORT119_FN7),
 786 
 787         /* Port120 */
 788         PINMUX_DATA(SF_PORT_1_120_MARK,         PORT120_FN3),
 789         PINMUX_DATA(SCIFB3_RXD_120_MARK,        PORT120_FN4,    MSEL3CR_09_1),
 790         PINMUX_DATA(DU0_CDE_MARK,               PORT120_FN7),
 791 
 792         /* Port121 */
 793         PINMUX_DATA(SF_PORT_0_121_MARK,         PORT121_FN3),
 794         PINMUX_DATA(SCIFB3_TXD_121_MARK,        PORT121_FN4,    MSEL3CR_09_1),
 795 
 796         /* Port122 */
 797         PINMUX_DATA(SCIFB0_TXD_MARK,            PORT122_FN1),
 798         PINMUX_DATA(CHSCIF0_HTX_MARK,           PORT122_FN7),
 799 
 800         /* Port123 */
 801         PINMUX_DATA(SCIFB0_RXD_MARK,            PORT123_FN1),
 802         PINMUX_DATA(CHSCIF0_HRX_MARK,           PORT123_FN7),
 803 
 804         /* Port124 */
 805         PINMUX_DATA(ISP_STROBE_124_MARK,        PORT124_FN3),
 806 
 807         /* Port125 */
 808         PINMUX_DATA(STP_ISD_0_MARK,             PORT125_FN1),
 809         PINMUX_DATA(PDM4_CLK_125_MARK,          PORT125_FN2),
 810         PINMUX_DATA(MSIOF2_TXD_MARK,            PORT125_FN3),
 811         PINMUX_DATA(SIM0_VOLTSEL0_MARK,         PORT125_FN5),
 812 
 813         /* Port126 */
 814         PINMUX_DATA(TS_SDEN_MARK,               PORT126_FN1),
 815         PINMUX_DATA(MSIOF7_SYNC_MARK,           PORT126_FN2),
 816         PINMUX_DATA(STP_ISEN_1_MARK,            PORT126_FN3),
 817 
 818         /* Port128 */
 819         PINMUX_DATA(STP_ISEN_0_MARK,            PORT128_FN1),
 820         PINMUX_DATA(PDM1_OUTDATA_128_MARK,      PORT128_FN2),
 821         PINMUX_DATA(MSIOF2_SYNC_MARK,           PORT128_FN3),
 822         PINMUX_DATA(SIM1_VOLTSEL1_MARK,         PORT128_FN5),
 823 
 824         /* Port129 */
 825         PINMUX_DATA(TS_SPSYNC_MARK,             PORT129_FN1),
 826         PINMUX_DATA(MSIOF7_RXD_MARK,            PORT129_FN2),
 827         PINMUX_DATA(STP_ISSYNC_1_MARK,          PORT129_FN3),
 828 
 829         /* Port130 */
 830         PINMUX_DATA(STP_ISSYNC_0_MARK,          PORT130_FN1),
 831         PINMUX_DATA(PDM4_DATA_130_MARK,         PORT130_FN2,    MSEL3CR_12_1),
 832         PINMUX_DATA(MSIOF2_RXD_MARK,            PORT130_FN3),
 833         PINMUX_DATA(SIM0_VOLTSEL1_MARK,         PORT130_FN5),
 834 
 835         /* Port131 */
 836         PINMUX_DATA(STP_OPWM_0_MARK,            PORT131_FN1),
 837         PINMUX_DATA(SIM1_PWRON_MARK,            PORT131_FN5),
 838 
 839         /* Port132 */
 840         PINMUX_DATA(TS_SCK_MARK,                PORT132_FN1),
 841         PINMUX_DATA(MSIOF7_SCK_MARK,            PORT132_FN2),
 842         PINMUX_DATA(STP_ISCLK_1_MARK,           PORT132_FN3),
 843 
 844         /* Port133 */
 845         PINMUX_DATA(STP_ISCLK_0_MARK,           PORT133_FN1),
 846         PINMUX_DATA(PDM1_OUTCLK_133_MARK,       PORT133_FN2),
 847         PINMUX_DATA(MSIOF2_SCK_MARK,            PORT133_FN3),
 848         PINMUX_DATA(SIM1_VOLTSEL0_MARK,         PORT133_FN5),
 849 
 850         /* Port134 */
 851         PINMUX_DATA(TS_SDAT_MARK,               PORT134_FN1),
 852         PINMUX_DATA(MSIOF7_TXD_MARK,            PORT134_FN2),
 853         PINMUX_DATA(STP_ISD_1_MARK,             PORT134_FN3),
 854 
 855         /* Port160 - Port178 */
 856         PINMUX_DATA(IRQ20_MARK,                 PORT160_FN0),
 857         PINMUX_DATA(IRQ21_MARK,                 PORT161_FN0),
 858         PINMUX_DATA(IRQ22_MARK,                 PORT162_FN0),
 859         PINMUX_DATA(IRQ23_MARK,                 PORT163_FN0),
 860         PINMUX_DATA(MMCD0_0_MARK,               PORT164_FN1),
 861         PINMUX_DATA(MMCD0_1_MARK,               PORT165_FN1),
 862         PINMUX_DATA(MMCD0_2_MARK,               PORT166_FN1),
 863         PINMUX_DATA(MMCD0_3_MARK,               PORT167_FN1),
 864         PINMUX_DATA(MMCD0_4_MARK,               PORT168_FN1),
 865         PINMUX_DATA(MMCD0_5_MARK,               PORT169_FN1),
 866         PINMUX_DATA(MMCD0_6_MARK,               PORT170_FN1),
 867         PINMUX_DATA(MMCD0_7_MARK,               PORT171_FN1),
 868         PINMUX_DATA(MMCCMD0_MARK,               PORT172_FN1),
 869         PINMUX_DATA(MMCCLK0_MARK,               PORT173_FN1),
 870         PINMUX_DATA(MMCRST_MARK,                PORT174_FN1),
 871         PINMUX_DATA(IRQ24_MARK,                 PORT175_FN0),
 872         PINMUX_DATA(IRQ25_MARK,                 PORT176_FN0),
 873         PINMUX_DATA(IRQ26_MARK,                 PORT177_FN0),
 874         PINMUX_DATA(IRQ27_MARK,                 PORT178_FN0),
 875 
 876         /* Port192 - Port200 FN1 */
 877         PINMUX_DATA(A10_MARK,           PORT192_FN1),
 878         PINMUX_DATA(A9_MARK,            PORT193_FN1),
 879         PINMUX_DATA(A8_MARK,            PORT194_FN1),
 880         PINMUX_DATA(A7_MARK,            PORT195_FN1),
 881         PINMUX_DATA(A6_MARK,            PORT196_FN1),
 882         PINMUX_DATA(A5_MARK,            PORT197_FN1),
 883         PINMUX_DATA(A4_MARK,            PORT198_FN1),
 884         PINMUX_DATA(A3_MARK,            PORT199_FN1),
 885         PINMUX_DATA(A2_MARK,            PORT200_FN1),
 886 
 887         /* Port192 - Port200 FN2 */
 888         PINMUX_DATA(MMCD1_7_MARK,               PORT192_FN2),
 889         PINMUX_DATA(MMCD1_6_MARK,               PORT193_FN2),
 890         PINMUX_DATA(MMCD1_5_MARK,               PORT194_FN2),
 891         PINMUX_DATA(MMCD1_4_MARK,               PORT195_FN2),
 892         PINMUX_DATA(MMCD1_3_MARK,               PORT196_FN2),
 893         PINMUX_DATA(MMCD1_2_MARK,               PORT197_FN2),
 894         PINMUX_DATA(MMCD1_1_MARK,               PORT198_FN2),
 895         PINMUX_DATA(MMCD1_0_MARK,               PORT199_FN2),
 896         PINMUX_DATA(MMCCMD1_MARK,               PORT200_FN2),
 897 
 898         /* Port192 - Port200 IRQ */
 899         PINMUX_DATA(IRQ31_MARK,                 PORT192_FN0),
 900         PINMUX_DATA(IRQ32_MARK,                 PORT193_FN0),
 901         PINMUX_DATA(IRQ33_MARK,                 PORT194_FN0),
 902         PINMUX_DATA(IRQ34_MARK,                 PORT195_FN0),
 903         PINMUX_DATA(IRQ35_MARK,                 PORT196_FN0),
 904         PINMUX_DATA(IRQ36_MARK,                 PORT197_FN0),
 905         PINMUX_DATA(IRQ37_MARK,                 PORT198_FN0),
 906         PINMUX_DATA(IRQ38_MARK,                 PORT199_FN0),
 907         PINMUX_DATA(IRQ39_MARK,                 PORT200_FN0),
 908 
 909         /* Port201 */
 910         PINMUX_DATA(A1_MARK,            PORT201_FN1),
 911 
 912         /* Port202 */
 913         PINMUX_DATA(A0_MARK,            PORT202_FN1),
 914         PINMUX_DATA(BS_MARK,            PORT202_FN2),
 915 
 916         /* Port203 */
 917         PINMUX_DATA(CKO_MARK,           PORT203_FN1),
 918         PINMUX_DATA(MMCCLK1_MARK,       PORT203_FN2),
 919 
 920         /* Port204 */
 921         PINMUX_DATA(CS0_N_MARK,         PORT204_FN1),
 922         PINMUX_DATA(SIM0_GPO1_MARK,     PORT204_FN5),
 923 
 924         /* Port205 */
 925         PINMUX_DATA(CS2_N_MARK,         PORT205_FN1),
 926         PINMUX_DATA(SIM0_GPO2_MARK,     PORT205_FN5),
 927 
 928         /* Port206 */
 929         PINMUX_DATA(CS4_N_MARK,         PORT206_FN1),
 930         PINMUX_DATA(VIO_VD_MARK,        PORT206_FN2),
 931         PINMUX_DATA(SIM1_GPO0_MARK,     PORT206_FN5),
 932 
 933         /* Port207 - Port212 FN1 */
 934         PINMUX_DATA(D15_MARK,           PORT207_FN1),
 935         PINMUX_DATA(D14_MARK,           PORT208_FN1),
 936         PINMUX_DATA(D13_MARK,           PORT209_FN1),
 937         PINMUX_DATA(D12_MARK,           PORT210_FN1),
 938         PINMUX_DATA(D11_MARK,           PORT211_FN1),
 939         PINMUX_DATA(D10_MARK,           PORT212_FN1),
 940 
 941         /* Port207 - Port212 FN5 */
 942         PINMUX_DATA(GIO_OUT15_MARK,                     PORT207_FN5),
 943         PINMUX_DATA(GIO_OUT14_MARK,                     PORT208_FN5),
 944         PINMUX_DATA(GIO_OUT13_MARK,                     PORT209_FN5),
 945         PINMUX_DATA(GIO_OUT12_MARK,                     PORT210_FN5),
 946         PINMUX_DATA(WGM_TXP2_MARK,                      PORT211_FN5),
 947         PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK,       PORT212_FN5),
 948 
 949         /* Port213 - Port222 FN1 */
 950         PINMUX_DATA(D9_MARK,            PORT213_FN1),
 951         PINMUX_DATA(D8_MARK,            PORT214_FN1),
 952         PINMUX_DATA(D7_MARK,            PORT215_FN1),
 953         PINMUX_DATA(D6_MARK,            PORT216_FN1),
 954         PINMUX_DATA(D5_MARK,            PORT217_FN1),
 955         PINMUX_DATA(D4_MARK,            PORT218_FN1),
 956         PINMUX_DATA(D3_MARK,            PORT219_FN1),
 957         PINMUX_DATA(D2_MARK,            PORT220_FN1),
 958         PINMUX_DATA(D1_MARK,            PORT221_FN1),
 959         PINMUX_DATA(D0_MARK,            PORT222_FN1),
 960 
 961         /* Port213 - Port222 FN2 */
 962         PINMUX_DATA(VIO_D9_MARK,        PORT213_FN2),
 963         PINMUX_DATA(VIO_D8_MARK,        PORT214_FN2),
 964         PINMUX_DATA(VIO_D7_MARK,        PORT215_FN2),
 965         PINMUX_DATA(VIO_D6_MARK,        PORT216_FN2),
 966         PINMUX_DATA(VIO_D5_MARK,        PORT217_FN2),
 967         PINMUX_DATA(VIO_D4_MARK,        PORT218_FN2),
 968         PINMUX_DATA(VIO_D3_MARK,        PORT219_FN2),
 969         PINMUX_DATA(VIO_D2_MARK,        PORT220_FN2),
 970         PINMUX_DATA(VIO_D1_MARK,        PORT221_FN2),
 971         PINMUX_DATA(VIO_D0_MARK,        PORT222_FN2),
 972 
 973         /* Port213 - Port222 FN5 */
 974         PINMUX_DATA(GIO_OUT9_MARK,      PORT213_FN5),
 975         PINMUX_DATA(GIO_OUT8_MARK,      PORT214_FN5),
 976         PINMUX_DATA(GIO_OUT7_MARK,      PORT215_FN5),
 977         PINMUX_DATA(GIO_OUT6_MARK,      PORT216_FN5),
 978         PINMUX_DATA(GIO_OUT5_217_MARK,  PORT217_FN5),
 979         PINMUX_DATA(GIO_OUT4_218_MARK,  PORT218_FN5),
 980         PINMUX_DATA(GIO_OUT3_219_MARK,  PORT219_FN5),
 981         PINMUX_DATA(GIO_OUT2_220_MARK,  PORT220_FN5),
 982         PINMUX_DATA(GIO_OUT1_221_MARK,  PORT221_FN5),
 983         PINMUX_DATA(GIO_OUT0_222_MARK,  PORT222_FN5),
 984 
 985         /* Port224 */
 986         PINMUX_DATA(RDWR_224_MARK,      PORT224_FN1),
 987         PINMUX_DATA(VIO_HD_MARK,        PORT224_FN2),
 988         PINMUX_DATA(SIM1_GPO2_MARK,     PORT224_FN5),
 989 
 990         /* Port225 */
 991         PINMUX_DATA(RD_N_MARK,          PORT225_FN1),
 992 
 993         /* Port226 */
 994         PINMUX_DATA(WAIT_N_MARK,        PORT226_FN1),
 995         PINMUX_DATA(VIO_CLK_MARK,       PORT226_FN2),
 996         PINMUX_DATA(SIM1_GPO1_MARK,     PORT226_FN5),
 997 
 998         /* Port227 */
 999         PINMUX_DATA(WE0_N_MARK,         PORT227_FN1),
1000         PINMUX_DATA(RDWR_227_MARK,      PORT227_FN2),
1001 
1002         /* Port228 */
1003         PINMUX_DATA(WE1_N_MARK,         PORT228_FN1),
1004         PINMUX_DATA(SIM0_GPO0_MARK,     PORT228_FN5),
1005 
1006         /* Port229 */
1007         PINMUX_DATA(PWMO_MARK,          PORT229_FN1),
1008         PINMUX_DATA(VIO_CKO1_229_MARK,  PORT229_FN2),
1009 
1010         /* Port230 */
1011         PINMUX_DATA(SLIM_CLK_MARK,      PORT230_FN1),
1012         PINMUX_DATA(VIO_CKO4_230_MARK,  PORT230_FN2),
1013 
1014         /* Port231 */
1015         PINMUX_DATA(SLIM_DATA_MARK,     PORT231_FN1),
1016         PINMUX_DATA(VIO_CKO5_231_MARK,  PORT231_FN2),
1017 
1018         /* Port232 */
1019         PINMUX_DATA(VIO_CKO2_232_MARK,  PORT232_FN2),
1020         PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
1021 
1022         /* Port233 */
1023         PINMUX_DATA(VIO_CKO3_233_MARK,  PORT233_FN2),
1024         PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
1025 
1026         /* Port234 */
1027         PINMUX_DATA(FSIACK_MARK,        PORT234_FN1),
1028         PINMUX_DATA(PDM3_CLK_234_MARK,  PORT234_FN2),
1029         PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
1030 
1031         /* Port235 */
1032         PINMUX_DATA(FSIAISLD_MARK,      PORT235_FN1),
1033         PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2,    MSEL3CR_12_1),
1034 
1035         /* Port236 */
1036         PINMUX_DATA(FSIAOMC_MARK,               PORT236_FN1),
1037         PINMUX_DATA(PDM0_OUTCLK_236_MARK,       PORT236_FN2),
1038         PINMUX_DATA(ISP_IRIS0_236_MARK,         PORT236_FN3),
1039 
1040         /* Port237 */
1041         PINMUX_DATA(FSIAOLR_MARK,       PORT237_FN1),
1042         PINMUX_DATA(FSIAILR_MARK,       PORT237_FN2),
1043 
1044         /* Port238 */
1045         PINMUX_DATA(FSIAOBT_MARK,       PORT238_FN1),
1046         PINMUX_DATA(FSIAIBT_MARK,       PORT238_FN2),
1047 
1048         /* Port239 */
1049         PINMUX_DATA(FSIAOSLD_MARK,              PORT239_FN1),
1050         PINMUX_DATA(PDM0_OUTDATA_239_MARK,      PORT239_FN2),
1051 
1052         /* Port240 */
1053         PINMUX_DATA(FSIBISLD_MARK,      PORT240_FN1),
1054 
1055         /* Port241 */
1056         PINMUX_DATA(FSIBOLR_MARK,       PORT241_FN1),
1057         PINMUX_DATA(FSIBILR_MARK,       PORT241_FN2),
1058 
1059         /* Port242 */
1060         PINMUX_DATA(FSIBOMC_MARK,               PORT242_FN1),
1061         PINMUX_DATA(ISP_SHUTTER1_242_MARK,      PORT242_FN3),
1062 
1063         /* Port243 */
1064         PINMUX_DATA(FSIBOBT_MARK,       PORT243_FN1),
1065         PINMUX_DATA(FSIBIBT_MARK,       PORT243_FN2),
1066 
1067         /* Port244 */
1068         PINMUX_DATA(FSIBOSLD_MARK,      PORT244_FN1),
1069         PINMUX_DATA(FSIASPDIF_MARK,     PORT244_FN2),
1070 
1071         /* Port245 */
1072         PINMUX_DATA(FSIBCK_MARK,                PORT245_FN1),
1073         PINMUX_DATA(ISP_SHUTTER0_245_MARK,      PORT245_FN3),
1074 
1075         /* Port246 - Port250 FN1 */
1076         PINMUX_DATA(ISP_IRIS1_246_MARK,         PORT246_FN1),
1077         PINMUX_DATA(ISP_IRIS0_247_MARK,         PORT247_FN1),
1078         PINMUX_DATA(ISP_SHUTTER1_248_MARK,      PORT248_FN1),
1079         PINMUX_DATA(ISP_SHUTTER0_249_MARK,      PORT249_FN1),
1080         PINMUX_DATA(ISP_STROBE_250_MARK,        PORT250_FN1),
1081 
1082         /* Port256 - Port258 */
1083         PINMUX_DATA(MSIOF0_SYNC_MARK,           PORT256_FN1),
1084         PINMUX_DATA(MSIOF0_RXD_MARK,            PORT257_FN1),
1085         PINMUX_DATA(MSIOF0_SCK_MARK,            PORT258_FN1),
1086 
1087         /* Port259 */
1088         PINMUX_DATA(MSIOF0_SS2_MARK,            PORT259_FN1),
1089         PINMUX_DATA(VIO_CKO3_259_MARK,          PORT259_FN3),
1090 
1091         /* Port260 */
1092         PINMUX_DATA(MSIOF0_TXD_MARK,            PORT260_FN1),
1093 
1094         /* Port261 */
1095         PINMUX_DATA(SCIFB1_SCK_261_MARK,        PORT261_FN2),
1096         PINMUX_DATA(CHSCIF1_HSCK_MARK,          PORT261_FN7),
1097 
1098         /* Port262 */
1099         PINMUX_DATA(SCIFB2_SCK_262_MARK,        PORT262_FN2),
1100 
1101         /* Port263 - Port266 FN1 */
1102         PINMUX_DATA(MSIOF1_SS2_MARK,            PORT263_FN1),
1103         PINMUX_DATA(MSIOF1_TXD_MARK,            PORT264_FN1),
1104         PINMUX_DATA(MSIOF1_RXD_MARK,            PORT265_FN1),
1105         PINMUX_DATA(MSIOF1_SS1_MARK,            PORT266_FN1),
1106 
1107         /* Port263 - Port266 FN4 */
1108         PINMUX_DATA(MSIOF5_SS2_MARK,            PORT263_FN4),
1109         PINMUX_DATA(MSIOF5_TXD_MARK,            PORT264_FN4),
1110         PINMUX_DATA(MSIOF5_RXD_MARK,            PORT265_FN4),
1111         PINMUX_DATA(MSIOF5_SS1_MARK,            PORT266_FN4),
1112 
1113         /* Port267 */
1114         PINMUX_DATA(MSIOF0_SS1_MARK,            PORT267_FN1),
1115 
1116         /* Port268 */
1117         PINMUX_DATA(MSIOF1_SCK_MARK,            PORT268_FN1),
1118         PINMUX_DATA(MSIOF5_SCK_MARK,            PORT268_FN4),
1119 
1120         /* Port269 */
1121         PINMUX_DATA(MSIOF1_SYNC_MARK,           PORT269_FN1),
1122         PINMUX_DATA(MSIOF5_SYNC_MARK,           PORT269_FN4),
1123 
1124         /* Port270 - Port273 FN1 */
1125         PINMUX_DATA(MSIOF2_SS1_MARK,            PORT270_FN1),
1126         PINMUX_DATA(MSIOF2_SS2_MARK,            PORT271_FN1),
1127         PINMUX_DATA(MSIOF3_SS2_MARK,            PORT272_FN1),
1128         PINMUX_DATA(MSIOF3_SS1_MARK,            PORT273_FN1),
1129 
1130         /* Port270 - Port273 FN3 */
1131         PINMUX_DATA(VIO_CKO5_270_MARK,          PORT270_FN3),
1132         PINMUX_DATA(VIO_CKO2_271_MARK,          PORT271_FN3),
1133         PINMUX_DATA(VIO_CKO1_272_MARK,          PORT272_FN3),
1134         PINMUX_DATA(VIO_CKO4_273_MARK,          PORT273_FN3),
1135 
1136         /* Port274 */
1137         PINMUX_DATA(MSIOF4_SS2_MARK,            PORT274_FN1),
1138         PINMUX_DATA(TPU1TO0_MARK,               PORT274_FN4),
1139 
1140         /* Port275 - Port280 */
1141         PINMUX_DATA(IC_DP_MARK,                 PORT275_FN1),
1142         PINMUX_DATA(SIM0_RST_MARK,              PORT276_FN1),
1143         PINMUX_DATA(IC_DM_MARK,                 PORT277_FN1),
1144         PINMUX_DATA(SIM0_BSICOMP_MARK,          PORT278_FN1),
1145         PINMUX_DATA(SIM0_CLK_MARK,              PORT279_FN1),
1146         PINMUX_DATA(SIM0_IO_MARK,               PORT280_FN1),
1147 
1148         /* Port281 */
1149         PINMUX_DATA(SIM1_IO_MARK,               PORT281_FN1),
1150         PINMUX_DATA(PDM2_DATA_281_MARK,         PORT281_FN2,    MSEL3CR_12_1),
1151 
1152         /* Port282 */
1153         PINMUX_DATA(SIM1_CLK_MARK,              PORT282_FN1),
1154         PINMUX_DATA(PDM2_CLK_282_MARK,          PORT282_FN2),
1155 
1156         /* Port283 */
1157         PINMUX_DATA(SIM1_RST_MARK,              PORT283_FN1),
1158 
1159         /* Port289 */
1160         PINMUX_DATA(SDHID1_0_MARK,              PORT289_FN1),
1161         PINMUX_DATA(STMDATA0_2_MARK,            PORT289_FN3),
1162 
1163         /* Port290 */
1164         PINMUX_DATA(SDHID1_1_MARK,              PORT290_FN1),
1165         PINMUX_DATA(STMDATA1_2_MARK,            PORT290_FN3),
1166         PINMUX_DATA(IRQ51_MARK,                 PORT290_FN0),
1167 
1168         /* Port291 - Port294 FN1 */
1169         PINMUX_DATA(SDHID1_2_MARK,              PORT291_FN1),
1170         PINMUX_DATA(SDHID1_3_MARK,              PORT292_FN1),
1171         PINMUX_DATA(SDHICLK1_MARK,              PORT293_FN1),
1172         PINMUX_DATA(SDHICMD1_MARK,              PORT294_FN1),
1173 
1174         /* Port291 - Port294 FN3 */
1175         PINMUX_DATA(STMDATA2_2_MARK,            PORT291_FN3),
1176         PINMUX_DATA(STMDATA3_2_MARK,            PORT292_FN3),
1177         PINMUX_DATA(STMCLK_2_MARK,              PORT293_FN3),
1178         PINMUX_DATA(STMSIDI_2_MARK,             PORT294_FN3),
1179 
1180         /* Port295 */
1181         PINMUX_DATA(SDHID2_0_MARK,              PORT295_FN1),
1182         PINMUX_DATA(MSIOF4_TXD_MARK,            PORT295_FN2),
1183         PINMUX_DATA(SCIFB2_TXD_295_MARK,        PORT295_FN3,    MSEL3CR_10_1),
1184         PINMUX_DATA(MSIOF6_TXD_MARK,            PORT295_FN4),
1185 
1186         /* Port296 */
1187         PINMUX_DATA(SDHID2_1_MARK,              PORT296_FN1),
1188         PINMUX_DATA(MSIOF6_SS2_MARK,            PORT296_FN4),
1189         PINMUX_DATA(IRQ52_MARK,                 PORT296_FN0),
1190 
1191         /* Port297 - Port300 FN1 */
1192         PINMUX_DATA(SDHID2_2_MARK,              PORT297_FN1),
1193         PINMUX_DATA(SDHID2_3_MARK,              PORT298_FN1),
1194         PINMUX_DATA(SDHICLK2_MARK,              PORT299_FN1),
1195         PINMUX_DATA(SDHICMD2_MARK,              PORT300_FN1),
1196 
1197         /* Port297 - Port300 FN2 */
1198         PINMUX_DATA(MSIOF4_RXD_MARK,            PORT297_FN2),
1199         PINMUX_DATA(MSIOF4_SYNC_MARK,           PORT298_FN2),
1200         PINMUX_DATA(MSIOF4_SCK_MARK,            PORT299_FN2),
1201         PINMUX_DATA(MSIOF4_SS1_MARK,            PORT300_FN2),
1202 
1203         /* Port297 - Port300 FN3 */
1204         PINMUX_DATA(SCIFB2_RXD_297_MARK,        PORT297_FN3,    MSEL3CR_10_1),
1205         PINMUX_DATA(SCIFB2_CTS_298_MARK,        PORT298_FN3,    MSEL3CR_10_1),
1206         PINMUX_DATA(SCIFB2_SCK_299_MARK,        PORT299_FN3),
1207         PINMUX_DATA(SCIFB2_RTS_300_MARK,        PORT300_FN3),
1208 
1209         /* Port297 - Port300 FN4 */
1210         PINMUX_DATA(MSIOF6_RXD_MARK,            PORT297_FN4),
1211         PINMUX_DATA(MSIOF6_SYNC_MARK,           PORT298_FN4),
1212         PINMUX_DATA(MSIOF6_SCK_MARK,            PORT299_FN4),
1213         PINMUX_DATA(MSIOF6_SS1_MARK,            PORT300_FN4),
1214 
1215         /* Port301 */
1216         PINMUX_DATA(SDHICD0_MARK,               PORT301_FN1),
1217         PINMUX_DATA(IRQ50_MARK,                 PORT301_FN0),
1218 
1219         /* Port302 - Port306 FN1 */
1220         PINMUX_DATA(SDHID0_0_MARK,              PORT302_FN1),
1221         PINMUX_DATA(SDHID0_1_MARK,              PORT303_FN1),
1222         PINMUX_DATA(SDHID0_2_MARK,              PORT304_FN1),
1223         PINMUX_DATA(SDHID0_3_MARK,              PORT305_FN1),
1224         PINMUX_DATA(SDHICMD0_MARK,              PORT306_FN1),
1225 
1226         /* Port302 - Port306 FN3 */
1227         PINMUX_DATA(STMDATA0_1_MARK,            PORT302_FN3),
1228         PINMUX_DATA(STMDATA1_1_MARK,            PORT303_FN3),
1229         PINMUX_DATA(STMDATA2_1_MARK,            PORT304_FN3),
1230         PINMUX_DATA(STMDATA3_1_MARK,            PORT305_FN3),
1231         PINMUX_DATA(STMSIDI_1_MARK,             PORT306_FN3),
1232 
1233         /* Port307 */
1234         PINMUX_DATA(SDHIWP0_MARK,               PORT307_FN1),
1235 
1236         /* Port308 */
1237         PINMUX_DATA(SDHICLK0_MARK,              PORT308_FN1),
1238         PINMUX_DATA(STMCLK_1_MARK,              PORT308_FN3),
1239 
1240         /* Port320 - Port329 */
1241         PINMUX_DATA(IRQ16_MARK,                 PORT320_FN0),
1242         PINMUX_DATA(IRQ17_MARK,                 PORT321_FN0),
1243         PINMUX_DATA(IRQ28_MARK,                 PORT322_FN0),
1244         PINMUX_DATA(IRQ29_MARK,                 PORT323_FN0),
1245         PINMUX_DATA(IRQ30_MARK,                 PORT324_FN0),
1246         PINMUX_DATA(IRQ53_MARK,                 PORT325_FN0),
1247         PINMUX_DATA(IRQ54_MARK,                 PORT326_FN0),
1248         PINMUX_DATA(IRQ55_MARK,                 PORT327_FN0),
1249         PINMUX_DATA(IRQ56_MARK,                 PORT328_FN0),
1250         PINMUX_DATA(IRQ57_MARK,                 PORT329_FN0),
1251 };
1252 
1253 #define __O     (SH_PFC_PIN_CFG_OUTPUT)
1254 #define __IO    (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1255 #define __PUD   (SH_PFC_PIN_CFG_PULL_UP_DOWN)
1256 
1257 #define R8A73A4_PIN_IO_PU_PD(pin)       SH_PFC_PIN_CFG(pin, __IO | __PUD)
1258 #define R8A73A4_PIN_O(pin)              SH_PFC_PIN_CFG(pin, __O)
1259 
1260 static const struct sh_pfc_pin pinmux_pins[] = {
1261         R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1262         R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1263         R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1264         R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1265         R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1266         R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1267         R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1268         R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1269         R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1270         R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1271         R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1272         R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1273         R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1274         R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1275         R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1276         R8A73A4_PIN_IO_PU_PD(30),
1277         R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1278         R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1279         R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1280         R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1281         R8A73A4_PIN_IO_PU_PD(40),
1282         R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1283         R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1284         R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1285         R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1286         R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1287         R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1288         R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1289         R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1290         R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1291         R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1292         R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1293         R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1294         R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1295         R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1296         R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1297         R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1298         R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1299         R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1300         R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1301         R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1302         R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1303         R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1304         R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1305         R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1306         R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1307         R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1308         R8A73A4_PIN_IO_PU_PD(126),
1309         R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1310         R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1311         R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1312         R8A73A4_PIN_IO_PU_PD(134),
1313         R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1314         R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1315         R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1316         R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1317         R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1318         R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1319         R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1320         R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1321         R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1322         R8A73A4_PIN_IO_PU_PD(178),
1323         R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1324         R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1325         R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1326         R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1327         R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1328         R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1329         R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1330         R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1331         R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1332         R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1333         R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1334         R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1335         R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1336         R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1337         R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1338         R8A73A4_PIN_IO_PU_PD(222),
1339         R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1340         R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1341         R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1342         R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1343         R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1344         R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1345         R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1346         R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1347         R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1348         R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1349         R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1350         R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1351         R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1352         R8A73A4_PIN_IO_PU_PD(250),
1353         R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1354         R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1355         R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1356         R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1357         R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1358         R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1359         R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1360         R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1361         R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1362         R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1363         R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1364         R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1365         R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1366         R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1367         R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1368         R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1369         R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1370         R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1371         R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1372         R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1373         R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1374         R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1375         R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1376         R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1377         R8A73A4_PIN_IO_PU_PD(308),
1378         R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1379         R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1380         R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1381         R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1382         R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
1383 };
1384 
1385 /* - IRQC ------------------------------------------------------------------- */
1386 #define IRQC_PINS_MUX(pin, irq_mark)                            \
1387 static const unsigned int irqc_irq##irq_mark##_pins[] = {       \
1388         pin,                                                    \
1389 };                                                              \
1390 static const unsigned int irqc_irq##irq_mark##_mux[] = {        \
1391         IRQ##irq_mark##_MARK,                                   \
1392 }
1393 IRQC_PINS_MUX(0, 0);
1394 IRQC_PINS_MUX(1, 1);
1395 IRQC_PINS_MUX(2, 2);
1396 IRQC_PINS_MUX(3, 3);
1397 IRQC_PINS_MUX(4, 4);
1398 IRQC_PINS_MUX(5, 5);
1399 IRQC_PINS_MUX(6, 6);
1400 IRQC_PINS_MUX(7, 7);
1401 IRQC_PINS_MUX(8, 8);
1402 IRQC_PINS_MUX(9, 9);
1403 IRQC_PINS_MUX(10, 10);
1404 IRQC_PINS_MUX(11, 11);
1405 IRQC_PINS_MUX(12, 12);
1406 IRQC_PINS_MUX(13, 13);
1407 IRQC_PINS_MUX(14, 14);
1408 IRQC_PINS_MUX(15, 15);
1409 IRQC_PINS_MUX(66, 40);
1410 IRQC_PINS_MUX(84, 19);
1411 IRQC_PINS_MUX(85, 18);
1412 IRQC_PINS_MUX(102, 41);
1413 IRQC_PINS_MUX(103, 42);
1414 IRQC_PINS_MUX(109, 43);
1415 IRQC_PINS_MUX(110, 44);
1416 IRQC_PINS_MUX(111, 45);
1417 IRQC_PINS_MUX(112, 46);
1418 IRQC_PINS_MUX(113, 47);
1419 IRQC_PINS_MUX(114, 48);
1420 IRQC_PINS_MUX(115, 49);
1421 IRQC_PINS_MUX(160, 20);
1422 IRQC_PINS_MUX(161, 21);
1423 IRQC_PINS_MUX(162, 22);
1424 IRQC_PINS_MUX(163, 23);
1425 IRQC_PINS_MUX(175, 24);
1426 IRQC_PINS_MUX(176, 25);
1427 IRQC_PINS_MUX(177, 26);
1428 IRQC_PINS_MUX(178, 27);
1429 IRQC_PINS_MUX(192, 31);
1430 IRQC_PINS_MUX(193, 32);
1431 IRQC_PINS_MUX(194, 33);
1432 IRQC_PINS_MUX(195, 34);
1433 IRQC_PINS_MUX(196, 35);
1434 IRQC_PINS_MUX(197, 36);
1435 IRQC_PINS_MUX(198, 37);
1436 IRQC_PINS_MUX(199, 38);
1437 IRQC_PINS_MUX(200, 39);
1438 IRQC_PINS_MUX(290, 51);
1439 IRQC_PINS_MUX(296, 52);
1440 IRQC_PINS_MUX(301, 50);
1441 IRQC_PINS_MUX(320, 16);
1442 IRQC_PINS_MUX(321, 17);
1443 IRQC_PINS_MUX(322, 28);
1444 IRQC_PINS_MUX(323, 29);
1445 IRQC_PINS_MUX(324, 30);
1446 IRQC_PINS_MUX(325, 53);
1447 IRQC_PINS_MUX(326, 54);
1448 IRQC_PINS_MUX(327, 55);
1449 IRQC_PINS_MUX(328, 56);
1450 IRQC_PINS_MUX(329, 57);
1451 /* - MMCIF0 ----------------------------------------------------------------- */
1452 static const unsigned int mmc0_data1_pins[] = {
1453         /* D[0] */
1454         164,
1455 };
1456 static const unsigned int mmc0_data1_mux[] = {
1457         MMCD0_0_MARK,
1458 };
1459 static const unsigned int mmc0_data4_pins[] = {
1460         /* D[0:3] */
1461         164, 165, 166, 167,
1462 };
1463 static const unsigned int mmc0_data4_mux[] = {
1464         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1465 };
1466 static const unsigned int mmc0_data8_pins[] = {
1467         /* D[0:7] */
1468         164, 165, 166, 167, 168, 169, 170, 171,
1469 };
1470 static const unsigned int mmc0_data8_mux[] = {
1471         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1472         MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
1473 };
1474 static const unsigned int mmc0_ctrl_pins[] = {
1475         /* CMD, CLK */
1476         172, 173,
1477 };
1478 static const unsigned int mmc0_ctrl_mux[] = {
1479         MMCCMD0_MARK, MMCCLK0_MARK,
1480 };
1481 /* - MMCIF1 ----------------------------------------------------------------- */
1482 static const unsigned int mmc1_data1_pins[] = {
1483         /* D[0] */
1484         199,
1485 };
1486 static const unsigned int mmc1_data1_mux[] = {
1487         MMCD1_0_MARK,
1488 };
1489 static const unsigned int mmc1_data4_pins[] = {
1490         /* D[0:3] */
1491         199, 198, 197, 196,
1492 };
1493 static const unsigned int mmc1_data4_mux[] = {
1494         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1495 };
1496 static const unsigned int mmc1_data8_pins[] = {
1497         /* D[0:7] */
1498         199, 198, 197, 196, 195, 194, 193, 192,
1499 };
1500 static const unsigned int mmc1_data8_mux[] = {
1501         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1502         MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1503 };
1504 static const unsigned int mmc1_ctrl_pins[] = {
1505         /* CMD, CLK */
1506         200, 203,
1507 };
1508 static const unsigned int mmc1_ctrl_mux[] = {
1509         MMCCMD1_MARK, MMCCLK1_MARK,
1510 };
1511 /* - SCIFA0 ----------------------------------------------------------------- */
1512 static const unsigned int scifa0_data_pins[] = {
1513         /* SCIFA0_RXD, SCIFA0_TXD */
1514         117, 116,
1515 };
1516 static const unsigned int scifa0_data_mux[] = {
1517         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1518 };
1519 static const unsigned int scifa0_clk_pins[] = {
1520         /* SCIFA0_SCK */
1521         34,
1522 };
1523 static const unsigned int scifa0_clk_mux[] = {
1524         SCIFA0_SCK_MARK,
1525 };
1526 static const unsigned int scifa0_ctrl_pins[] = {
1527         /* SCIFA0_RTS, SCIFA0_CTS */
1528         32, 33,
1529 };
1530 static const unsigned int scifa0_ctrl_mux[] = {
1531         SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1532 };
1533 /* - SCIFA1 ----------------------------------------------------------------- */
1534 static const unsigned int scifa1_data_pins[] = {
1535         /* SCIFA1_RXD, SCIFA1_TXD */
1536         119, 118,
1537 };
1538 static const unsigned int scifa1_data_mux[] = {
1539         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1540 };
1541 static const unsigned int scifa1_clk_pins[] = {
1542         /* SCIFA1_SCK */
1543         37,
1544 };
1545 static const unsigned int scifa1_clk_mux[] = {
1546         SCIFA1_SCK_MARK,
1547 };
1548 static const unsigned int scifa1_ctrl_pins[] = {
1549         /* SCIFA1_RTS, SCIFA1_CTS */
1550         35, 36,
1551 };
1552 static const unsigned int scifa1_ctrl_mux[] = {
1553         SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1554 };
1555 /* - SCIFB0 ----------------------------------------------------------------- */
1556 static const unsigned int scifb0_data_pins[] = {
1557         /* SCIFB0_RXD, SCIFB0_TXD */
1558         123, 122,
1559 };
1560 static const unsigned int scifb0_data_mux[] = {
1561         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1562 };
1563 static const unsigned int scifb0_clk_pins[] = {
1564         /* SCIFB0_SCK */
1565         40,
1566 };
1567 static const unsigned int scifb0_clk_mux[] = {
1568         SCIFB0_SCK_MARK,
1569 };
1570 static const unsigned int scifb0_ctrl_pins[] = {
1571         /* SCIFB0_RTS, SCIFB0_CTS */
1572         38, 39,
1573 };
1574 static const unsigned int scifb0_ctrl_mux[] = {
1575         SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1576 };
1577 /* - SCIFB1 ----------------------------------------------------------------- */
1578 static const unsigned int scifb1_data_pins[] = {
1579         /* SCIFB1_RXD, SCIFB1_TXD */
1580         27, 26,
1581 };
1582 static const unsigned int scifb1_data_mux[] = {
1583         SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1584 };
1585 static const unsigned int scifb1_clk_pins[] = {
1586         /* SCIFB1_SCK */
1587         28,
1588 };
1589 static const unsigned int scifb1_clk_mux[] = {
1590         SCIFB1_SCK_28_MARK,
1591 };
1592 static const unsigned int scifb1_ctrl_pins[] = {
1593         /* SCIFB1_RTS, SCIFB1_CTS */
1594         24, 25,
1595 };
1596 static const unsigned int scifb1_ctrl_mux[] = {
1597         SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1598 };
1599 static const unsigned int scifb1_data_b_pins[] = {
1600         /* SCIFB1_RXD, SCIFB1_TXD */
1601         72, 67,
1602 };
1603 static const unsigned int scifb1_data_b_mux[] = {
1604         SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1605 };
1606 static const unsigned int scifb1_clk_b_pins[] = {
1607         /* SCIFB1_SCK */
1608         261,
1609 };
1610 static const unsigned int scifb1_clk_b_mux[] = {
1611         SCIFB1_SCK_261_MARK,
1612 };
1613 static const unsigned int scifb1_ctrl_b_pins[] = {
1614         /* SCIFB1_RTS, SCIFB1_CTS */
1615         70, 71,
1616 };
1617 static const unsigned int scifb1_ctrl_b_mux[] = {
1618         SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1619 };
1620 /* - SCIFB2 ----------------------------------------------------------------- */
1621 static const unsigned int scifb2_data_pins[] = {
1622         /* SCIFB2_RXD, SCIFB2_TXD */
1623         69, 68,
1624 };
1625 static const unsigned int scifb2_data_mux[] = {
1626         SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1627 };
1628 static const unsigned int scifb2_clk_pins[] = {
1629         /* SCIFB2_SCK */
1630         262,
1631 };
1632 static const unsigned int scifb2_clk_mux[] = {
1633         SCIFB2_SCK_262_MARK,
1634 };
1635 static const unsigned int scifb2_ctrl_pins[] = {
1636         /* SCIFB2_RTS, SCIFB2_CTS */
1637         73, 66,
1638 };
1639 static const unsigned int scifb2_ctrl_mux[] = {
1640         SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1641 };
1642 static const unsigned int scifb2_data_b_pins[] = {
1643         /* SCIFB2_RXD, SCIFB2_TXD */
1644         297, 295,
1645 };
1646 static const unsigned int scifb2_data_b_mux[] = {
1647         SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1648 };
1649 static const unsigned int scifb2_clk_b_pins[] = {
1650         /* SCIFB2_SCK */
1651         299,
1652 };
1653 static const unsigned int scifb2_clk_b_mux[] = {
1654         SCIFB2_SCK_299_MARK,
1655 };
1656 static const unsigned int scifb2_ctrl_b_pins[] = {
1657         /* SCIFB2_RTS, SCIFB2_CTS */
1658         300, 298,
1659 };
1660 static const unsigned int scifb2_ctrl_b_mux[] = {
1661         SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1662 };
1663 /* - SCIFB3 ----------------------------------------------------------------- */
1664 static const unsigned int scifb3_data_pins[] = {
1665         /* SCIFB3_RXD, SCIFB3_TXD */
1666         22, 21,
1667 };
1668 static const unsigned int scifb3_data_mux[] = {
1669         SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1670 };
1671 static const unsigned int scifb3_clk_pins[] = {
1672         /* SCIFB3_SCK */
1673         23,
1674 };
1675 static const unsigned int scifb3_clk_mux[] = {
1676         SCIFB3_SCK_23_MARK,
1677 };
1678 static const unsigned int scifb3_ctrl_pins[] = {
1679         /* SCIFB3_RTS, SCIFB3_CTS */
1680         19, 20,
1681 };
1682 static const unsigned int scifb3_ctrl_mux[] = {
1683         SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1684 };
1685 static const unsigned int scifb3_data_b_pins[] = {
1686         /* SCIFB3_RXD, SCIFB3_TXD */
1687         120, 121,
1688 };
1689 static const unsigned int scifb3_data_b_mux[] = {
1690         SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1691 };
1692 static const unsigned int scifb3_clk_b_pins[] = {
1693         /* SCIFB3_SCK */
1694         40,
1695 };
1696 static const unsigned int scifb3_clk_b_mux[] = {
1697         SCIFB3_SCK_40_MARK,
1698 };
1699 static const unsigned int scifb3_ctrl_b_pins[] = {
1700         /* SCIFB3_RTS, SCIFB3_CTS */
1701         38, 39,
1702 };
1703 static const unsigned int scifb3_ctrl_b_mux[] = {
1704         SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1705 };
1706 /* - SDHI0 ------------------------------------------------------------------ */
1707 static const unsigned int sdhi0_data1_pins[] = {
1708         /* D0 */
1709         302,
1710 };
1711 static const unsigned int sdhi0_data1_mux[] = {
1712         SDHID0_0_MARK,
1713 };
1714 static const unsigned int sdhi0_data4_pins[] = {
1715         /* D[0:3] */
1716         302, 303, 304, 305,
1717 };
1718 static const unsigned int sdhi0_data4_mux[] = {
1719         SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1720 };
1721 static const unsigned int sdhi0_ctrl_pins[] = {
1722         /* CLK, CMD */
1723         308, 306,
1724 };
1725 static const unsigned int sdhi0_ctrl_mux[] = {
1726         SDHICLK0_MARK, SDHICMD0_MARK,
1727 };
1728 static const unsigned int sdhi0_cd_pins[] = {
1729         /* CD */
1730         301,
1731 };
1732 static const unsigned int sdhi0_cd_mux[] = {
1733         SDHICD0_MARK,
1734 };
1735 static const unsigned int sdhi0_wp_pins[] = {
1736         /* WP */
1737         307,
1738 };
1739 static const unsigned int sdhi0_wp_mux[] = {
1740         SDHIWP0_MARK,
1741 };
1742 /* - SDHI1 ------------------------------------------------------------------ */
1743 static const unsigned int sdhi1_data1_pins[] = {
1744         /* D0 */
1745         289,
1746 };
1747 static const unsigned int sdhi1_data1_mux[] = {
1748         SDHID1_0_MARK,
1749 };
1750 static const unsigned int sdhi1_data4_pins[] = {
1751         /* D[0:3] */
1752         289, 290, 291, 292,
1753 };
1754 static const unsigned int sdhi1_data4_mux[] = {
1755         SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1756 };
1757 static const unsigned int sdhi1_ctrl_pins[] = {
1758         /* CLK, CMD */
1759         293, 294,
1760 };
1761 static const unsigned int sdhi1_ctrl_mux[] = {
1762         SDHICLK1_MARK, SDHICMD1_MARK,
1763 };
1764 /* - SDHI2 ------------------------------------------------------------------ */
1765 static const unsigned int sdhi2_data1_pins[] = {
1766         /* D0 */
1767         295,
1768 };
1769 static const unsigned int sdhi2_data1_mux[] = {
1770         SDHID2_0_MARK,
1771 };
1772 static const unsigned int sdhi2_data4_pins[] = {
1773         /* D[0:3] */
1774         295, 296, 297, 298,
1775 };
1776 static const unsigned int sdhi2_data4_mux[] = {
1777         SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1778 };
1779 static const unsigned int sdhi2_ctrl_pins[] = {
1780         /* CLK, CMD */
1781         299, 300,
1782 };
1783 static const unsigned int sdhi2_ctrl_mux[] = {
1784         SDHICLK2_MARK, SDHICMD2_MARK,
1785 };
1786 
1787 static const struct sh_pfc_pin_group pinmux_groups[] = {
1788         SH_PFC_PIN_GROUP(irqc_irq0),
1789         SH_PFC_PIN_GROUP(irqc_irq1),
1790         SH_PFC_PIN_GROUP(irqc_irq2),
1791         SH_PFC_PIN_GROUP(irqc_irq3),
1792         SH_PFC_PIN_GROUP(irqc_irq4),
1793         SH_PFC_PIN_GROUP(irqc_irq5),
1794         SH_PFC_PIN_GROUP(irqc_irq6),
1795         SH_PFC_PIN_GROUP(irqc_irq7),
1796         SH_PFC_PIN_GROUP(irqc_irq8),
1797         SH_PFC_PIN_GROUP(irqc_irq9),
1798         SH_PFC_PIN_GROUP(irqc_irq10),
1799         SH_PFC_PIN_GROUP(irqc_irq11),
1800         SH_PFC_PIN_GROUP(irqc_irq12),
1801         SH_PFC_PIN_GROUP(irqc_irq13),
1802         SH_PFC_PIN_GROUP(irqc_irq14),
1803         SH_PFC_PIN_GROUP(irqc_irq15),
1804         SH_PFC_PIN_GROUP(irqc_irq16),
1805         SH_PFC_PIN_GROUP(irqc_irq17),
1806         SH_PFC_PIN_GROUP(irqc_irq18),
1807         SH_PFC_PIN_GROUP(irqc_irq19),
1808         SH_PFC_PIN_GROUP(irqc_irq20),
1809         SH_PFC_PIN_GROUP(irqc_irq21),
1810         SH_PFC_PIN_GROUP(irqc_irq22),
1811         SH_PFC_PIN_GROUP(irqc_irq23),
1812         SH_PFC_PIN_GROUP(irqc_irq24),
1813         SH_PFC_PIN_GROUP(irqc_irq25),
1814         SH_PFC_PIN_GROUP(irqc_irq26),
1815         SH_PFC_PIN_GROUP(irqc_irq27),
1816         SH_PFC_PIN_GROUP(irqc_irq28),
1817         SH_PFC_PIN_GROUP(irqc_irq29),
1818         SH_PFC_PIN_GROUP(irqc_irq30),
1819         SH_PFC_PIN_GROUP(irqc_irq31),
1820         SH_PFC_PIN_GROUP(irqc_irq32),
1821         SH_PFC_PIN_GROUP(irqc_irq33),
1822         SH_PFC_PIN_GROUP(irqc_irq34),
1823         SH_PFC_PIN_GROUP(irqc_irq35),
1824         SH_PFC_PIN_GROUP(irqc_irq36),
1825         SH_PFC_PIN_GROUP(irqc_irq37),
1826         SH_PFC_PIN_GROUP(irqc_irq38),
1827         SH_PFC_PIN_GROUP(irqc_irq39),
1828         SH_PFC_PIN_GROUP(irqc_irq40),
1829         SH_PFC_PIN_GROUP(irqc_irq41),
1830         SH_PFC_PIN_GROUP(irqc_irq42),
1831         SH_PFC_PIN_GROUP(irqc_irq43),
1832         SH_PFC_PIN_GROUP(irqc_irq44),
1833         SH_PFC_PIN_GROUP(irqc_irq45),
1834         SH_PFC_PIN_GROUP(irqc_irq46),
1835         SH_PFC_PIN_GROUP(irqc_irq47),
1836         SH_PFC_PIN_GROUP(irqc_irq48),
1837         SH_PFC_PIN_GROUP(irqc_irq49),
1838         SH_PFC_PIN_GROUP(irqc_irq50),
1839         SH_PFC_PIN_GROUP(irqc_irq51),
1840         SH_PFC_PIN_GROUP(irqc_irq52),
1841         SH_PFC_PIN_GROUP(irqc_irq53),
1842         SH_PFC_PIN_GROUP(irqc_irq54),
1843         SH_PFC_PIN_GROUP(irqc_irq55),
1844         SH_PFC_PIN_GROUP(irqc_irq56),
1845         SH_PFC_PIN_GROUP(irqc_irq57),
1846         SH_PFC_PIN_GROUP(mmc0_data1),
1847         SH_PFC_PIN_GROUP(mmc0_data4),
1848         SH_PFC_PIN_GROUP(mmc0_data8),
1849         SH_PFC_PIN_GROUP(mmc0_ctrl),
1850         SH_PFC_PIN_GROUP(mmc1_data1),
1851         SH_PFC_PIN_GROUP(mmc1_data4),
1852         SH_PFC_PIN_GROUP(mmc1_data8),
1853         SH_PFC_PIN_GROUP(mmc1_ctrl),
1854         SH_PFC_PIN_GROUP(scifa0_data),
1855         SH_PFC_PIN_GROUP(scifa0_clk),
1856         SH_PFC_PIN_GROUP(scifa0_ctrl),
1857         SH_PFC_PIN_GROUP(scifa1_data),
1858         SH_PFC_PIN_GROUP(scifa1_clk),
1859         SH_PFC_PIN_GROUP(scifa1_ctrl),
1860         SH_PFC_PIN_GROUP(scifb0_data),
1861         SH_PFC_PIN_GROUP(scifb0_clk),
1862         SH_PFC_PIN_GROUP(scifb0_ctrl),
1863         SH_PFC_PIN_GROUP(scifb1_data),
1864         SH_PFC_PIN_GROUP(scifb1_clk),
1865         SH_PFC_PIN_GROUP(scifb1_ctrl),
1866         SH_PFC_PIN_GROUP(scifb1_data_b),
1867         SH_PFC_PIN_GROUP(scifb1_clk_b),
1868         SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1869         SH_PFC_PIN_GROUP(scifb2_data),
1870         SH_PFC_PIN_GROUP(scifb2_clk),
1871         SH_PFC_PIN_GROUP(scifb2_ctrl),
1872         SH_PFC_PIN_GROUP(scifb2_data_b),
1873         SH_PFC_PIN_GROUP(scifb2_clk_b),
1874         SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1875         SH_PFC_PIN_GROUP(scifb3_data),
1876         SH_PFC_PIN_GROUP(scifb3_clk),
1877         SH_PFC_PIN_GROUP(scifb3_ctrl),
1878         SH_PFC_PIN_GROUP(scifb3_data_b),
1879         SH_PFC_PIN_GROUP(scifb3_clk_b),
1880         SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1881         SH_PFC_PIN_GROUP(sdhi0_data1),
1882         SH_PFC_PIN_GROUP(sdhi0_data4),
1883         SH_PFC_PIN_GROUP(sdhi0_ctrl),
1884         SH_PFC_PIN_GROUP(sdhi0_cd),
1885         SH_PFC_PIN_GROUP(sdhi0_wp),
1886         SH_PFC_PIN_GROUP(sdhi1_data1),
1887         SH_PFC_PIN_GROUP(sdhi1_data4),
1888         SH_PFC_PIN_GROUP(sdhi1_ctrl),
1889         SH_PFC_PIN_GROUP(sdhi2_data1),
1890         SH_PFC_PIN_GROUP(sdhi2_data4),
1891         SH_PFC_PIN_GROUP(sdhi2_ctrl),
1892 };
1893 
1894 static const char * const irqc_groups[] = {
1895         "irqc_irq0",
1896         "irqc_irq1",
1897         "irqc_irq2",
1898         "irqc_irq3",
1899         "irqc_irq4",
1900         "irqc_irq5",
1901         "irqc_irq6",
1902         "irqc_irq7",
1903         "irqc_irq8",
1904         "irqc_irq9",
1905         "irqc_irq10",
1906         "irqc_irq11",
1907         "irqc_irq12",
1908         "irqc_irq13",
1909         "irqc_irq14",
1910         "irqc_irq15",
1911         "irqc_irq16",
1912         "irqc_irq17",
1913         "irqc_irq18",
1914         "irqc_irq19",
1915         "irqc_irq20",
1916         "irqc_irq21",
1917         "irqc_irq22",
1918         "irqc_irq23",
1919         "irqc_irq24",
1920         "irqc_irq25",
1921         "irqc_irq26",
1922         "irqc_irq27",
1923         "irqc_irq28",
1924         "irqc_irq29",
1925         "irqc_irq30",
1926         "irqc_irq31",
1927         "irqc_irq32",
1928         "irqc_irq33",
1929         "irqc_irq34",
1930         "irqc_irq35",
1931         "irqc_irq36",
1932         "irqc_irq37",
1933         "irqc_irq38",
1934         "irqc_irq39",
1935         "irqc_irq40",
1936         "irqc_irq41",
1937         "irqc_irq42",
1938         "irqc_irq43",
1939         "irqc_irq44",
1940         "irqc_irq45",
1941         "irqc_irq46",
1942         "irqc_irq47",
1943         "irqc_irq48",
1944         "irqc_irq49",
1945         "irqc_irq50",
1946         "irqc_irq51",
1947         "irqc_irq52",
1948         "irqc_irq53",
1949         "irqc_irq54",
1950         "irqc_irq55",
1951         "irqc_irq56",
1952         "irqc_irq57",
1953 };
1954 
1955 static const char * const mmc0_groups[] = {
1956         "mmc0_data1",
1957         "mmc0_data4",
1958         "mmc0_data8",
1959         "mmc0_ctrl",
1960 };
1961 
1962 static const char * const mmc1_groups[] = {
1963         "mmc1_data1",
1964         "mmc1_data4",
1965         "mmc1_data8",
1966         "mmc1_ctrl",
1967 };
1968 
1969 static const char * const scifa0_groups[] = {
1970         "scifa0_data",
1971         "scifa0_clk",
1972         "scifa0_ctrl",
1973 };
1974 
1975 static const char * const scifa1_groups[] = {
1976         "scifa1_data",
1977         "scifa1_clk",
1978         "scifa1_ctrl",
1979 };
1980 
1981 static const char * const scifb0_groups[] = {
1982         "scifb0_data",
1983         "scifb0_clk",
1984         "scifb0_ctrl",
1985 };
1986 
1987 static const char * const scifb1_groups[] = {
1988         "scifb1_data",
1989         "scifb1_clk",
1990         "scifb1_ctrl",
1991         "scifb1_data_b",
1992         "scifb1_clk_b",
1993         "scifb1_ctrl_b",
1994 };
1995 
1996 static const char * const scifb2_groups[] = {
1997         "scifb2_data",
1998         "scifb2_clk",
1999         "scifb2_ctrl",
2000         "scifb2_data_b",
2001         "scifb2_clk_b",
2002         "scifb2_ctrl_b",
2003 };
2004 
2005 static const char * const scifb3_groups[] = {
2006         "scifb3_data",
2007         "scifb3_clk",
2008         "scifb3_ctrl",
2009         "scifb3_data_b",
2010         "scifb3_clk_b",
2011         "scifb3_ctrl_b",
2012 };
2013 
2014 static const char * const sdhi0_groups[] = {
2015         "sdhi0_data1",
2016         "sdhi0_data4",
2017         "sdhi0_ctrl",
2018         "sdhi0_cd",
2019         "sdhi0_wp",
2020 };
2021 
2022 static const char * const sdhi1_groups[] = {
2023         "sdhi1_data1",
2024         "sdhi1_data4",
2025         "sdhi1_ctrl",
2026 };
2027 
2028 static const char * const sdhi2_groups[] = {
2029         "sdhi2_data1",
2030         "sdhi2_data4",
2031         "sdhi2_ctrl",
2032 };
2033 
2034 static const struct sh_pfc_function pinmux_functions[] = {
2035         SH_PFC_FUNCTION(irqc),
2036         SH_PFC_FUNCTION(mmc0),
2037         SH_PFC_FUNCTION(mmc1),
2038         SH_PFC_FUNCTION(scifa0),
2039         SH_PFC_FUNCTION(scifa1),
2040         SH_PFC_FUNCTION(scifb0),
2041         SH_PFC_FUNCTION(scifb1),
2042         SH_PFC_FUNCTION(scifb2),
2043         SH_PFC_FUNCTION(scifb3),
2044         SH_PFC_FUNCTION(sdhi0),
2045         SH_PFC_FUNCTION(sdhi1),
2046         SH_PFC_FUNCTION(sdhi2),
2047 };
2048 
2049 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2050         PORTCR(0, 0xe6050000),
2051         PORTCR(1, 0xe6050001),
2052         PORTCR(2, 0xe6050002),
2053         PORTCR(3, 0xe6050003),
2054         PORTCR(4, 0xe6050004),
2055         PORTCR(5, 0xe6050005),
2056         PORTCR(6, 0xe6050006),
2057         PORTCR(7, 0xe6050007),
2058         PORTCR(8, 0xe6050008),
2059         PORTCR(9, 0xe6050009),
2060         PORTCR(10, 0xe605000A),
2061         PORTCR(11, 0xe605000B),
2062         PORTCR(12, 0xe605000C),
2063         PORTCR(13, 0xe605000D),
2064         PORTCR(14, 0xe605000E),
2065         PORTCR(15, 0xe605000F),
2066         PORTCR(16, 0xe6050010),
2067         PORTCR(17, 0xe6050011),
2068         PORTCR(18, 0xe6050012),
2069         PORTCR(19, 0xe6050013),
2070         PORTCR(20, 0xe6050014),
2071         PORTCR(21, 0xe6050015),
2072         PORTCR(22, 0xe6050016),
2073         PORTCR(23, 0xe6050017),
2074         PORTCR(24, 0xe6050018),
2075         PORTCR(25, 0xe6050019),
2076         PORTCR(26, 0xe605001A),
2077         PORTCR(27, 0xe605001B),
2078         PORTCR(28, 0xe605001C),
2079         PORTCR(29, 0xe605001D),
2080         PORTCR(30, 0xe605001E),
2081         PORTCR(32, 0xe6051020),
2082         PORTCR(33, 0xe6051021),
2083         PORTCR(34, 0xe6051022),
2084         PORTCR(35, 0xe6051023),
2085         PORTCR(36, 0xe6051024),
2086         PORTCR(37, 0xe6051025),
2087         PORTCR(38, 0xe6051026),
2088         PORTCR(39, 0xe6051027),
2089         PORTCR(40, 0xe6051028),
2090         PORTCR(64, 0xe6050040),
2091         PORTCR(65, 0xe6050041),
2092         PORTCR(66, 0xe6050042),
2093         PORTCR(67, 0xe6050043),
2094         PORTCR(68, 0xe6050044),
2095         PORTCR(69, 0xe6050045),
2096         PORTCR(70, 0xe6050046),
2097         PORTCR(71, 0xe6050047),
2098         PORTCR(72, 0xe6050048),
2099         PORTCR(73, 0xe6050049),
2100         PORTCR(74, 0xe605004A),
2101         PORTCR(75, 0xe605004B),
2102         PORTCR(76, 0xe605004C),
2103         PORTCR(77, 0xe605004D),
2104         PORTCR(78, 0xe605004E),
2105         PORTCR(79, 0xe605004F),
2106         PORTCR(80, 0xe6050050),
2107         PORTCR(81, 0xe6050051),
2108         PORTCR(82, 0xe6050052),
2109         PORTCR(83, 0xe6050053),
2110         PORTCR(84, 0xe6050054),
2111         PORTCR(85, 0xe6050055),
2112         PORTCR(96, 0xe6051060),
2113         PORTCR(97, 0xe6051061),
2114         PORTCR(98, 0xe6051062),
2115         PORTCR(99, 0xe6051063),
2116         PORTCR(100, 0xe6051064),
2117         PORTCR(101, 0xe6051065),
2118         PORTCR(102, 0xe6051066),
2119         PORTCR(103, 0xe6051067),
2120         PORTCR(104, 0xe6051068),
2121         PORTCR(105, 0xe6051069),
2122         PORTCR(106, 0xe605106A),
2123         PORTCR(107, 0xe605106B),
2124         PORTCR(108, 0xe605106C),
2125         PORTCR(109, 0xe605106D),
2126         PORTCR(110, 0xe605106E),
2127         PORTCR(111, 0xe605106F),
2128         PORTCR(112, 0xe6051070),
2129         PORTCR(113, 0xe6051071),
2130         PORTCR(114, 0xe6051072),
2131         PORTCR(115, 0xe6051073),
2132         PORTCR(116, 0xe6051074),
2133         PORTCR(117, 0xe6051075),
2134         PORTCR(118, 0xe6051076),
2135         PORTCR(119, 0xe6051077),
2136         PORTCR(120, 0xe6051078),
2137         PORTCR(121, 0xe6051079),
2138         PORTCR(122, 0xe605107A),
2139         PORTCR(123, 0xe605107B),
2140         PORTCR(124, 0xe605107C),
2141         PORTCR(125, 0xe605107D),
2142         PORTCR(126, 0xe605107E),
2143         PORTCR(128, 0xe6051080),
2144         PORTCR(129, 0xe6051081),
2145         PORTCR(130, 0xe6051082),
2146         PORTCR(131, 0xe6051083),
2147         PORTCR(132, 0xe6051084),
2148         PORTCR(133, 0xe6051085),
2149         PORTCR(134, 0xe6051086),
2150         PORTCR(160, 0xe60520A0),
2151         PORTCR(161, 0xe60520A1),
2152         PORTCR(162, 0xe60520A2),
2153         PORTCR(163, 0xe60520A3),
2154         PORTCR(164, 0xe60520A4),
2155         PORTCR(165, 0xe60520A5),
2156         PORTCR(166, 0xe60520A6),
2157         PORTCR(167, 0xe60520A7),
2158         PORTCR(168, 0xe60520A8),
2159         PORTCR(169, 0xe60520A9),
2160         PORTCR(170, 0xe60520AA),
2161         PORTCR(171, 0xe60520AB),
2162         PORTCR(172, 0xe60520AC),
2163         PORTCR(173, 0xe60520AD),
2164         PORTCR(174, 0xe60520AE),
2165         PORTCR(175, 0xe60520AF),
2166         PORTCR(176, 0xe60520B0),
2167         PORTCR(177, 0xe60520B1),
2168         PORTCR(178, 0xe60520B2),
2169         PORTCR(192, 0xe60520C0),
2170         PORTCR(193, 0xe60520C1),
2171         PORTCR(194, 0xe60520C2),
2172         PORTCR(195, 0xe60520C3),
2173         PORTCR(196, 0xe60520C4),
2174         PORTCR(197, 0xe60520C5),
2175         PORTCR(198, 0xe60520C6),
2176         PORTCR(199, 0xe60520C7),
2177         PORTCR(200, 0xe60520C8),
2178         PORTCR(201, 0xe60520C9),
2179         PORTCR(202, 0xe60520CA),
2180         PORTCR(203, 0xe60520CB),
2181         PORTCR(204, 0xe60520CC),
2182         PORTCR(205, 0xe60520CD),
2183         PORTCR(206, 0xe60520CE),
2184         PORTCR(207, 0xe60520CF),
2185         PORTCR(208, 0xe60520D0),
2186         PORTCR(209, 0xe60520D1),
2187         PORTCR(210, 0xe60520D2),
2188         PORTCR(211, 0xe60520D3),
2189         PORTCR(212, 0xe60520D4),
2190         PORTCR(213, 0xe60520D5),
2191         PORTCR(214, 0xe60520D6),
2192         PORTCR(215, 0xe60520D7),
2193         PORTCR(216, 0xe60520D8),
2194         PORTCR(217, 0xe60520D9),
2195         PORTCR(218, 0xe60520DA),
2196         PORTCR(219, 0xe60520DB),
2197         PORTCR(220, 0xe60520DC),
2198         PORTCR(221, 0xe60520DD),
2199         PORTCR(222, 0xe60520DE),
2200         PORTCR(224, 0xe60520E0),
2201         PORTCR(225, 0xe60520E1),
2202         PORTCR(226, 0xe60520E2),
2203         PORTCR(227, 0xe60520E3),
2204         PORTCR(228, 0xe60520E4),
2205         PORTCR(229, 0xe60520E5),
2206         PORTCR(230, 0xe60520e6),
2207         PORTCR(231, 0xe60520E7),
2208         PORTCR(232, 0xe60520E8),
2209         PORTCR(233, 0xe60520E9),
2210         PORTCR(234, 0xe60520EA),
2211         PORTCR(235, 0xe60520EB),
2212         PORTCR(236, 0xe60520EC),
2213         PORTCR(237, 0xe60520ED),
2214         PORTCR(238, 0xe60520EE),
2215         PORTCR(239, 0xe60520EF),
2216         PORTCR(240, 0xe60520F0),
2217         PORTCR(241, 0xe60520F1),
2218         PORTCR(242, 0xe60520F2),
2219         PORTCR(243, 0xe60520F3),
2220         PORTCR(244, 0xe60520F4),
2221         PORTCR(245, 0xe60520F5),
2222         PORTCR(246, 0xe60520F6),
2223         PORTCR(247, 0xe60520F7),
2224         PORTCR(248, 0xe60520F8),
2225         PORTCR(249, 0xe60520F9),
2226         PORTCR(250, 0xe60520FA),
2227         PORTCR(256, 0xe6052100),
2228         PORTCR(257, 0xe6052101),
2229         PORTCR(258, 0xe6052102),
2230         PORTCR(259, 0xe6052103),
2231         PORTCR(260, 0xe6052104),
2232         PORTCR(261, 0xe6052105),
2233         PORTCR(262, 0xe6052106),
2234         PORTCR(263, 0xe6052107),
2235         PORTCR(264, 0xe6052108),
2236         PORTCR(265, 0xe6052109),
2237         PORTCR(266, 0xe605210A),
2238         PORTCR(267, 0xe605210B),
2239         PORTCR(268, 0xe605210C),
2240         PORTCR(269, 0xe605210D),
2241         PORTCR(270, 0xe605210E),
2242         PORTCR(271, 0xe605210F),
2243         PORTCR(272, 0xe6052110),
2244         PORTCR(273, 0xe6052111),
2245         PORTCR(274, 0xe6052112),
2246         PORTCR(275, 0xe6052113),
2247         PORTCR(276, 0xe6052114),
2248         PORTCR(277, 0xe6052115),
2249         PORTCR(278, 0xe6052116),
2250         PORTCR(279, 0xe6052117),
2251         PORTCR(280, 0xe6052118),
2252         PORTCR(281, 0xe6052119),
2253         PORTCR(282, 0xe605211A),
2254         PORTCR(283, 0xe605211B),
2255         PORTCR(288, 0xe6053120),
2256         PORTCR(289, 0xe6053121),
2257         PORTCR(290, 0xe6053122),
2258         PORTCR(291, 0xe6053123),
2259         PORTCR(292, 0xe6053124),
2260         PORTCR(293, 0xe6053125),
2261         PORTCR(294, 0xe6053126),
2262         PORTCR(295, 0xe6053127),
2263         PORTCR(296, 0xe6053128),
2264         PORTCR(297, 0xe6053129),
2265         PORTCR(298, 0xe605312A),
2266         PORTCR(299, 0xe605312B),
2267         PORTCR(300, 0xe605312C),
2268         PORTCR(301, 0xe605312D),
2269         PORTCR(302, 0xe605312E),
2270         PORTCR(303, 0xe605312F),
2271         PORTCR(304, 0xe6053130),
2272         PORTCR(305, 0xe6053131),
2273         PORTCR(306, 0xe6053132),
2274         PORTCR(307, 0xe6053133),
2275         PORTCR(308, 0xe6053134),
2276         PORTCR(320, 0xe6053140),
2277         PORTCR(321, 0xe6053141),
2278         PORTCR(322, 0xe6053142),
2279         PORTCR(323, 0xe6053143),
2280         PORTCR(324, 0xe6053144),
2281         PORTCR(325, 0xe6053145),
2282         PORTCR(326, 0xe6053146),
2283         PORTCR(327, 0xe6053147),
2284         PORTCR(328, 0xe6053148),
2285         PORTCR(329, 0xe6053149),
2286 
2287         { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
2288                         MSEL1CR_31_0, MSEL1CR_31_1,
2289                         0, 0,
2290                         0, 0,
2291                         0, 0,
2292                         MSEL1CR_27_0, MSEL1CR_27_1,
2293                         0, 0,
2294                         MSEL1CR_25_0, MSEL1CR_25_1,
2295                         MSEL1CR_24_0, MSEL1CR_24_1,
2296                         0, 0,
2297                         MSEL1CR_22_0, MSEL1CR_22_1,
2298                         MSEL1CR_21_0, MSEL1CR_21_1,
2299                         MSEL1CR_20_0, MSEL1CR_20_1,
2300                         MSEL1CR_19_0, MSEL1CR_19_1,
2301                         MSEL1CR_18_0, MSEL1CR_18_1,
2302                         MSEL1CR_17_0, MSEL1CR_17_1,
2303                         MSEL1CR_16_0, MSEL1CR_16_1,
2304                         MSEL1CR_15_0, MSEL1CR_15_1,
2305                         MSEL1CR_14_0, MSEL1CR_14_1,
2306                         MSEL1CR_13_0, MSEL1CR_13_1,
2307                         MSEL1CR_12_0, MSEL1CR_12_1,
2308                         MSEL1CR_11_0, MSEL1CR_11_1,
2309                         MSEL1CR_10_0, MSEL1CR_10_1,
2310                         MSEL1CR_09_0, MSEL1CR_09_1,
2311                         MSEL1CR_08_0, MSEL1CR_08_1,
2312                         MSEL1CR_07_0, MSEL1CR_07_1,
2313                         MSEL1CR_06_0, MSEL1CR_06_1,
2314                         MSEL1CR_05_0, MSEL1CR_05_1,
2315                         MSEL1CR_04_0, MSEL1CR_04_1,
2316                         MSEL1CR_03_0, MSEL1CR_03_1,
2317                         MSEL1CR_02_0, MSEL1CR_02_1,
2318                         MSEL1CR_01_0, MSEL1CR_01_1,
2319                         MSEL1CR_00_0, MSEL1CR_00_1,
2320                 ))
2321         },
2322         { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
2323                         MSEL3CR_31_0, MSEL3CR_31_1,
2324                         0, 0,
2325                         0, 0,
2326                         MSEL3CR_28_0, MSEL3CR_28_1,
2327                         MSEL3CR_27_0, MSEL3CR_27_1,
2328                         MSEL3CR_26_0, MSEL3CR_26_1,
2329                         0, 0,
2330                         0, 0,
2331                         MSEL3CR_23_0, MSEL3CR_23_1,
2332                         MSEL3CR_22_0, MSEL3CR_22_1,
2333                         MSEL3CR_21_0, MSEL3CR_21_1,
2334                         MSEL3CR_20_0, MSEL3CR_20_1,
2335                         MSEL3CR_19_0, MSEL3CR_19_1,
2336                         MSEL3CR_18_0, MSEL3CR_18_1,
2337                         MSEL3CR_17_0, MSEL3CR_17_1,
2338                         MSEL3CR_16_0, MSEL3CR_16_1,
2339                         MSEL3CR_15_0, MSEL3CR_15_1,
2340                         0, 0,
2341                         0, 0,
2342                         MSEL3CR_12_0, MSEL3CR_12_1,
2343                         MSEL3CR_11_0, MSEL3CR_11_1,
2344                         MSEL3CR_10_0, MSEL3CR_10_1,
2345                         MSEL3CR_09_0, MSEL3CR_09_1,
2346                         0, 0,
2347                         0, 0,
2348                         MSEL3CR_06_0, MSEL3CR_06_1,
2349                         0, 0,
2350                         0, 0,
2351                         MSEL3CR_03_0, MSEL3CR_03_1,
2352                         0, 0,
2353                         MSEL3CR_01_0, MSEL3CR_01_1,
2354                         MSEL3CR_00_0, MSEL3CR_00_1,
2355                         ))
2356         },
2357         { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
2358                         0, 0,
2359                         MSEL4CR_30_0, MSEL4CR_30_1,
2360                         MSEL4CR_29_0, MSEL4CR_29_1,
2361                         MSEL4CR_28_0, MSEL4CR_28_1,
2362                         MSEL4CR_27_0, MSEL4CR_27_1,
2363                         MSEL4CR_26_0, MSEL4CR_26_1,
2364                         MSEL4CR_25_0, MSEL4CR_25_1,
2365                         MSEL4CR_24_0, MSEL4CR_24_1,
2366                         MSEL4CR_23_0, MSEL4CR_23_1,
2367                         MSEL4CR_22_0, MSEL4CR_22_1,
2368                         MSEL4CR_21_0, MSEL4CR_21_1,
2369                         MSEL4CR_20_0, MSEL4CR_20_1,
2370                         MSEL4CR_19_0, MSEL4CR_19_1,
2371                         MSEL4CR_18_0, MSEL4CR_18_1,
2372                         MSEL4CR_17_0, MSEL4CR_17_1,
2373                         MSEL4CR_16_0, MSEL4CR_16_1,
2374                         MSEL4CR_15_0, MSEL4CR_15_1,
2375                         MSEL4CR_14_0, MSEL4CR_14_1,
2376                         MSEL4CR_13_0, MSEL4CR_13_1,
2377                         MSEL4CR_12_0, MSEL4CR_12_1,
2378                         MSEL4CR_11_0, MSEL4CR_11_1,
2379                         MSEL4CR_10_0, MSEL4CR_10_1,
2380                         MSEL4CR_09_0, MSEL4CR_09_1,
2381                         0, 0,
2382                         MSEL4CR_07_0, MSEL4CR_07_1,
2383                         0, 0,
2384                         0, 0,
2385                         MSEL4CR_04_0, MSEL4CR_04_1,
2386                         0, 0,
2387                         0, 0,
2388                         MSEL4CR_01_0, MSEL4CR_01_1,
2389                         0, 0,
2390                 ))
2391         },
2392         { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1, GROUP(
2393                         MSEL5CR_31_0, MSEL5CR_31_1,
2394                         MSEL5CR_30_0, MSEL5CR_30_1,
2395                         MSEL5CR_29_0, MSEL5CR_29_1,
2396                         MSEL5CR_28_0, MSEL5CR_28_1,
2397                         MSEL5CR_27_0, MSEL5CR_27_1,
2398                         MSEL5CR_26_0, MSEL5CR_26_1,
2399                         MSEL5CR_25_0, MSEL5CR_25_1,
2400                         MSEL5CR_24_0, MSEL5CR_24_1,
2401                         MSEL5CR_23_0, MSEL5CR_23_1,
2402                         MSEL5CR_22_0, MSEL5CR_22_1,
2403                         MSEL5CR_21_0, MSEL5CR_21_1,
2404                         MSEL5CR_20_0, MSEL5CR_20_1,
2405                         MSEL5CR_19_0, MSEL5CR_19_1,
2406                         MSEL5CR_18_0, MSEL5CR_18_1,
2407                         MSEL5CR_17_0, MSEL5CR_17_1,
2408                         MSEL5CR_16_0, MSEL5CR_16_1,
2409                         MSEL5CR_15_0, MSEL5CR_15_1,
2410                         MSEL5CR_14_0, MSEL5CR_14_1,
2411                         MSEL5CR_13_0, MSEL5CR_13_1,
2412                         MSEL5CR_12_0, MSEL5CR_12_1,
2413                         MSEL5CR_11_0, MSEL5CR_11_1,
2414                         MSEL5CR_10_0, MSEL5CR_10_1,
2415                         MSEL5CR_09_0, MSEL5CR_09_1,
2416                         MSEL5CR_08_0, MSEL5CR_08_1,
2417                         MSEL5CR_07_0, MSEL5CR_07_1,
2418                         MSEL5CR_06_0, MSEL5CR_06_1,
2419                         0, 0,
2420                         0, 0,
2421                         0, 0,
2422                         0, 0,
2423                         0, 0,
2424                         0, 0,
2425                 ))
2426         },
2427         { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1, GROUP(
2428                         0, 0,
2429                         0, 0,
2430                         0, 0,
2431                         0, 0,
2432                         0, 0,
2433                         0, 0,
2434                         0, 0,
2435                         0, 0,
2436                         0, 0,
2437                         0, 0,
2438                         0, 0,
2439                         0, 0,
2440                         0, 0,
2441                         0, 0,
2442                         0, 0,
2443                         MSEL8CR_16_0, MSEL8CR_16_1,
2444                         0, 0,
2445                         0, 0,
2446                         0, 0,
2447                         0, 0,
2448                         0, 0,
2449                         0, 0,
2450                         0, 0,
2451                         0, 0,
2452                         0, 0,
2453                         0, 0,
2454                         0, 0,
2455                         0, 0,
2456                         0, 0,
2457                         0, 0,
2458                         MSEL8CR_01_0, MSEL8CR_01_1,
2459                         MSEL8CR_00_0, MSEL8CR_00_1,
2460                 ))
2461         },
2462         { },
2463 };
2464 
2465 static const struct pinmux_data_reg pinmux_data_regs[] = {
2466 
2467         { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
2468                         0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2469                         PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2470                         PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2471                         PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2472                         PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2473                         PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2474                         PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2475                         PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2476                 ))
2477         },
2478         { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
2479                         0, 0, 0, 0,
2480                         0, 0, 0, 0,
2481                         0, 0, 0, 0,
2482                         0, 0, 0, 0,
2483                         0, 0, 0, 0,
2484                         0, 0, 0, PORT40_DATA,
2485                         PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2486                         PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2487                 ))
2488         },
2489         { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32, GROUP(
2490                         0, 0, 0, 0,
2491                         0, 0, 0, 0,
2492                         0, 0, PORT85_DATA, PORT84_DATA,
2493                         PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2494                         PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2495                         PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2496                         PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2497                         PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2498                 ))
2499         },
2500         { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32, GROUP(
2501                         0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2502                         PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2503                         PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2504                         PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2505                         PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2506                         PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2507                         PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2508                         PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2509                 ))
2510         },
2511         { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32, GROUP(
2512                         0, 0, 0, 0,
2513                         0, 0, 0, 0,
2514                         0, 0, 0, 0,
2515                         0, 0, 0, 0,
2516                         0, 0, 0, 0,
2517                         0, 0, 0, 0,
2518                         0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2519                         PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2520                 ))
2521         },
2522         { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32, GROUP(
2523                         0, 0, 0, 0,
2524                         0, 0, 0, 0,
2525                         0, 0, 0, 0,
2526                         0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2527                         PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2528                         PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2529                         PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2530                         PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2531                 ))
2532         },
2533         { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32, GROUP(
2534                         0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
2535                         PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
2536                         PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
2537                         PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
2538                         PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2539                         PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2540                         PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2541                         PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
2542                 ))
2543         },
2544         { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32, GROUP(
2545                         0, 0, 0, 0,
2546                         0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
2547                         PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
2548                         PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
2549                         PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
2550                         PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
2551                         PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
2552                         PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
2553                 ))
2554         },
2555         { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32, GROUP(
2556                         0, 0, 0, 0,
2557                         PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
2558                         PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
2559                         PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
2560                         PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
2561                         PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
2562                         PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
2563                         PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
2564                 ))
2565         },
2566         { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32, GROUP(
2567                         0, 0, 0, 0,
2568                         0, 0, 0, 0,
2569                         0, 0, 0, PORT308_DATA,
2570                         PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
2571                         PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
2572                         PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
2573                         PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
2574                         PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
2575                 ))
2576         },
2577         { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32, GROUP(
2578                         0, 0, 0, 0,
2579                         0, 0, 0, 0,
2580                         0, 0, 0, 0,
2581                         0, 0, 0, 0,
2582                         0, 0, 0, 0,
2583                         0, 0, PORT329_DATA, PORT328_DATA,
2584                         PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
2585                         PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
2586                 ))
2587         },
2588         { },
2589 };
2590 
2591 static const struct pinmux_irq pinmux_irqs[] = {
2592         PINMUX_IRQ(0),          /* IRQ0 */
2593         PINMUX_IRQ(1),          /* IRQ1 */
2594         PINMUX_IRQ(2),          /* IRQ2 */
2595         PINMUX_IRQ(3),          /* IRQ3 */
2596         PINMUX_IRQ(4),          /* IRQ4 */
2597         PINMUX_IRQ(5),          /* IRQ5 */
2598         PINMUX_IRQ(6),          /* IRQ6 */
2599         PINMUX_IRQ(7),          /* IRQ7 */
2600         PINMUX_IRQ(8),          /* IRQ8 */
2601         PINMUX_IRQ(9),          /* IRQ9 */
2602         PINMUX_IRQ(10),         /* IRQ10 */
2603         PINMUX_IRQ(11),         /* IRQ11 */
2604         PINMUX_IRQ(12),         /* IRQ12 */
2605         PINMUX_IRQ(13),         /* IRQ13 */
2606         PINMUX_IRQ(14),         /* IRQ14 */
2607         PINMUX_IRQ(15),         /* IRQ15 */
2608         PINMUX_IRQ(320),        /* IRQ16 */
2609         PINMUX_IRQ(321),        /* IRQ17 */
2610         PINMUX_IRQ(85),         /* IRQ18 */
2611         PINMUX_IRQ(84),         /* IRQ19 */
2612         PINMUX_IRQ(160),        /* IRQ20 */
2613         PINMUX_IRQ(161),        /* IRQ21 */
2614         PINMUX_IRQ(162),        /* IRQ22 */
2615         PINMUX_IRQ(163),        /* IRQ23 */
2616         PINMUX_IRQ(175),        /* IRQ24 */
2617         PINMUX_IRQ(176),        /* IRQ25 */
2618         PINMUX_IRQ(177),        /* IRQ26 */
2619         PINMUX_IRQ(178),        /* IRQ27 */
2620         PINMUX_IRQ(322),        /* IRQ28 */
2621         PINMUX_IRQ(323),        /* IRQ29 */
2622         PINMUX_IRQ(324),        /* IRQ30 */
2623         PINMUX_IRQ(192),        /* IRQ31 */
2624         PINMUX_IRQ(193),        /* IRQ32 */
2625         PINMUX_IRQ(194),        /* IRQ33 */
2626         PINMUX_IRQ(195),        /* IRQ34 */
2627         PINMUX_IRQ(196),        /* IRQ35 */
2628         PINMUX_IRQ(197),        /* IRQ36 */
2629         PINMUX_IRQ(198),        /* IRQ37 */
2630         PINMUX_IRQ(199),        /* IRQ38 */
2631         PINMUX_IRQ(200),        /* IRQ39 */
2632         PINMUX_IRQ(66),         /* IRQ40 */
2633         PINMUX_IRQ(102),        /* IRQ41 */
2634         PINMUX_IRQ(103),        /* IRQ42 */
2635         PINMUX_IRQ(109),        /* IRQ43 */
2636         PINMUX_IRQ(110),        /* IRQ44 */
2637         PINMUX_IRQ(111),        /* IRQ45 */
2638         PINMUX_IRQ(112),        /* IRQ46 */
2639         PINMUX_IRQ(113),        /* IRQ47 */
2640         PINMUX_IRQ(114),        /* IRQ48 */
2641         PINMUX_IRQ(115),        /* IRQ49 */
2642         PINMUX_IRQ(301),        /* IRQ50 */
2643         PINMUX_IRQ(290),        /* IRQ51 */
2644         PINMUX_IRQ(296),        /* IRQ52 */
2645         PINMUX_IRQ(325),        /* IRQ53 */
2646         PINMUX_IRQ(326),        /* IRQ54 */
2647         PINMUX_IRQ(327),        /* IRQ55 */
2648         PINMUX_IRQ(328),        /* IRQ56 */
2649         PINMUX_IRQ(329),        /* IRQ57 */
2650 };
2651 
2652 #define PORTCR_PULMD_OFF (0 << 6)
2653 #define PORTCR_PULMD_DOWN (2 << 6)
2654 #define PORTCR_PULMD_UP (3 << 6)
2655 #define PORTCR_PULMD_MASK (3 << 6)
2656 
2657 static const unsigned int r8a73a4_portcr_offsets[] = {
2658         0x00000000, 0x00001000, 0x00000000, 0x00001000,
2659         0x00001000, 0x00002000, 0x00002000, 0x00002000,
2660         0x00002000, 0x00003000, 0x00003000,
2661 };
2662 
2663 static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
2664                                             unsigned int pin)
2665 {
2666         void __iomem *addr;
2667 
2668         addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2669 
2670         switch (ioread8(addr) & PORTCR_PULMD_MASK) {
2671         case PORTCR_PULMD_UP:
2672                 return PIN_CONFIG_BIAS_PULL_UP;
2673         case PORTCR_PULMD_DOWN:
2674                 return PIN_CONFIG_BIAS_PULL_DOWN;
2675         case PORTCR_PULMD_OFF:
2676         default:
2677                 return PIN_CONFIG_BIAS_DISABLE;
2678         }
2679 }
2680 
2681 static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2682                                    unsigned int bias)
2683 {
2684         void __iomem *addr;
2685         u32 value;
2686 
2687         addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2688         value = ioread8(addr) & ~PORTCR_PULMD_MASK;
2689 
2690         switch (bias) {
2691         case PIN_CONFIG_BIAS_PULL_UP:
2692                 value |= PORTCR_PULMD_UP;
2693                 break;
2694         case PIN_CONFIG_BIAS_PULL_DOWN:
2695                 value |= PORTCR_PULMD_DOWN;
2696                 break;
2697         }
2698 
2699         iowrite8(value, addr);
2700 }
2701 
2702 static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
2703         .get_bias = r8a73a4_pinmux_get_bias,
2704         .set_bias = r8a73a4_pinmux_set_bias,
2705 };
2706 
2707 const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2708         .name           = "r8a73a4_pfc",
2709         .ops            = &r8a73a4_pfc_ops,
2710 
2711         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2712         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2713         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2714 
2715         .pins = pinmux_pins,
2716         .nr_pins = ARRAY_SIZE(pinmux_pins),
2717 
2718         .groups = pinmux_groups,
2719         .nr_groups = ARRAY_SIZE(pinmux_groups),
2720         .functions = pinmux_functions,
2721         .nr_functions = ARRAY_SIZE(pinmux_functions),
2722 
2723         .cfg_regs = pinmux_config_regs,
2724         .data_regs = pinmux_data_regs,
2725 
2726         .pinmux_data = pinmux_data,
2727         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2728 
2729         .gpio_irq = pinmux_irqs,
2730         .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2731 };
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