This source file includes following definitions.
- sh_pfc_map_resources
- sh_pfc_phys_to_virt
- sh_pfc_get_pin_index
- sh_pfc_enum_in_range
- sh_pfc_read_raw_reg
- sh_pfc_write_raw_reg
- sh_pfc_read
- sh_pfc_write
- sh_pfc_config_reg_helper
- sh_pfc_write_config_reg
- sh_pfc_get_config_reg
- sh_pfc_mark_to_enum
- sh_pfc_config_mux
- sh_pfc_pin_to_bias_reg
- sh_pfc_init_ranges
- sh_pfc_nop_reg
- sh_pfc_save_reg
- sh_pfc_restore_reg
- sh_pfc_walk_regs
- sh_pfc_suspend_init
- sh_pfc_suspend_noirq
- sh_pfc_resume_noirq
- sh_pfc_suspend_init
- is0s
- sh_pfc_check_cfg_reg
- sh_pfc_check_info
- sh_pfc_check_driver
- sh_pfc_check_driver
- sh_pfc_probe
- sh_pfc_init
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11 #define DRV_NAME "sh-pfc"
12
13 #include <linux/bitops.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/pinctrl/machine.h>
23 #include <linux/platform_device.h>
24 #include <linux/psci.h>
25 #include <linux/slab.h>
26
27 #include "core.h"
28
29 static int sh_pfc_map_resources(struct sh_pfc *pfc,
30 struct platform_device *pdev)
31 {
32 struct sh_pfc_window *windows;
33 unsigned int *irqs = NULL;
34 unsigned int num_windows;
35 struct resource *res;
36 unsigned int i;
37 int num_irqs;
38
39
40 for (num_windows = 0;; num_windows++) {
41 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
42 if (!res)
43 break;
44 }
45 if (num_windows == 0)
46 return -EINVAL;
47
48 num_irqs = platform_irq_count(pdev);
49 if (num_irqs < 0)
50 return num_irqs;
51
52
53 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
54 GFP_KERNEL);
55 if (windows == NULL)
56 return -ENOMEM;
57
58 pfc->num_windows = num_windows;
59 pfc->windows = windows;
60
61 if (num_irqs) {
62 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
63 GFP_KERNEL);
64 if (irqs == NULL)
65 return -ENOMEM;
66
67 pfc->num_irqs = num_irqs;
68 pfc->irqs = irqs;
69 }
70
71
72 for (i = 0; i < num_windows; i++) {
73 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
74 windows->phys = res->start;
75 windows->size = resource_size(res);
76 windows->virt = devm_ioremap_resource(pfc->dev, res);
77 if (IS_ERR(windows->virt))
78 return -ENOMEM;
79 windows++;
80 }
81 for (i = 0; i < num_irqs; i++)
82 *irqs++ = platform_get_irq(pdev, i);
83
84 return 0;
85 }
86
87 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
88 {
89 struct sh_pfc_window *window;
90 phys_addr_t address = reg;
91 unsigned int i;
92
93
94 for (i = 0; i < pfc->num_windows; i++) {
95 window = pfc->windows + i;
96
97 if (address < window->phys)
98 continue;
99
100 if (address >= (window->phys + window->size))
101 continue;
102
103 return window->virt + (address - window->phys);
104 }
105
106 BUG();
107 return NULL;
108 }
109
110 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
111 {
112 unsigned int offset;
113 unsigned int i;
114
115 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
116 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
117
118 if (pin <= range->end)
119 return pin >= range->start
120 ? offset + pin - range->start : -1;
121
122 offset += range->end - range->start + 1;
123 }
124
125 return -EINVAL;
126 }
127
128 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
129 {
130 if (enum_id < r->begin)
131 return 0;
132
133 if (enum_id > r->end)
134 return 0;
135
136 return 1;
137 }
138
139 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
140 {
141 switch (reg_width) {
142 case 8:
143 return ioread8(mapped_reg);
144 case 16:
145 return ioread16(mapped_reg);
146 case 32:
147 return ioread32(mapped_reg);
148 }
149
150 BUG();
151 return 0;
152 }
153
154 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
155 u32 data)
156 {
157 switch (reg_width) {
158 case 8:
159 iowrite8(data, mapped_reg);
160 return;
161 case 16:
162 iowrite16(data, mapped_reg);
163 return;
164 case 32:
165 iowrite32(data, mapped_reg);
166 return;
167 }
168
169 BUG();
170 }
171
172 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
173 {
174 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
175 }
176
177 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
178 {
179 if (pfc->info->unlock_reg)
180 sh_pfc_write_raw_reg(
181 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
182 ~data);
183
184 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
185 }
186
187 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
188 const struct pinmux_cfg_reg *crp,
189 unsigned int in_pos,
190 void __iomem **mapped_regp, u32 *maskp,
191 unsigned int *posp)
192 {
193 unsigned int k;
194
195 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
196
197 if (crp->field_width) {
198 *maskp = (1 << crp->field_width) - 1;
199 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
200 } else {
201 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
202 *posp = crp->reg_width;
203 for (k = 0; k <= in_pos; k++)
204 *posp -= crp->var_field_width[k];
205 }
206 }
207
208 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
209 const struct pinmux_cfg_reg *crp,
210 unsigned int field, u32 value)
211 {
212 void __iomem *mapped_reg;
213 unsigned int pos;
214 u32 mask, data;
215
216 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
217
218 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
219 "r_width = %u, f_width = %u\n",
220 crp->reg, value, field, crp->reg_width, hweight32(mask));
221
222 mask = ~(mask << pos);
223 value = value << pos;
224
225 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
226 data &= mask;
227 data |= value;
228
229 if (pfc->info->unlock_reg)
230 sh_pfc_write_raw_reg(
231 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
232 ~data);
233
234 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
235 }
236
237 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
238 const struct pinmux_cfg_reg **crp,
239 unsigned int *fieldp, u32 *valuep)
240 {
241 unsigned int k = 0;
242
243 while (1) {
244 const struct pinmux_cfg_reg *config_reg =
245 pfc->info->cfg_regs + k;
246 unsigned int r_width = config_reg->reg_width;
247 unsigned int f_width = config_reg->field_width;
248 unsigned int curr_width;
249 unsigned int bit_pos;
250 unsigned int pos = 0;
251 unsigned int m = 0;
252
253 if (!r_width)
254 break;
255
256 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
257 u32 ncomb;
258 u32 n;
259
260 if (f_width)
261 curr_width = f_width;
262 else
263 curr_width = config_reg->var_field_width[m];
264
265 ncomb = 1 << curr_width;
266 for (n = 0; n < ncomb; n++) {
267 if (config_reg->enum_ids[pos + n] == enum_id) {
268 *crp = config_reg;
269 *fieldp = m;
270 *valuep = n;
271 return 0;
272 }
273 }
274 pos += ncomb;
275 m++;
276 }
277 k++;
278 }
279
280 return -EINVAL;
281 }
282
283 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
284 u16 *enum_idp)
285 {
286 const u16 *data = pfc->info->pinmux_data;
287 unsigned int k;
288
289 if (pos) {
290 *enum_idp = data[pos + 1];
291 return pos + 1;
292 }
293
294 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
295 if (data[k] == mark) {
296 *enum_idp = data[k + 1];
297 return k + 1;
298 }
299 }
300
301 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
302 mark);
303 return -EINVAL;
304 }
305
306 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
307 {
308 const struct pinmux_range *range;
309 int pos = 0;
310
311 switch (pinmux_type) {
312 case PINMUX_TYPE_GPIO:
313 case PINMUX_TYPE_FUNCTION:
314 range = NULL;
315 break;
316
317 case PINMUX_TYPE_OUTPUT:
318 range = &pfc->info->output;
319 break;
320
321 case PINMUX_TYPE_INPUT:
322 range = &pfc->info->input;
323 break;
324
325 default:
326 return -EINVAL;
327 }
328
329
330 while (1) {
331 const struct pinmux_cfg_reg *cr;
332 unsigned int field;
333 u16 enum_id;
334 u32 value;
335 int in_range;
336 int ret;
337
338 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
339 if (pos < 0)
340 return pos;
341
342 if (!enum_id)
343 break;
344
345
346
347
348
349 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
350 if (!in_range) {
351 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
352
353
354
355 in_range = 1;
356 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
357
358
359
360 in_range = sh_pfc_enum_in_range(enum_id, range);
361
362
363
364
365
366
367 if (in_range && enum_id == range->force)
368 continue;
369 }
370
371 }
372
373 if (!in_range)
374 continue;
375
376 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
377 if (ret < 0)
378 return ret;
379
380 sh_pfc_write_config_reg(pfc, cr, field, value);
381 }
382
383 return 0;
384 }
385
386 const struct pinmux_bias_reg *
387 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
388 unsigned int *bit)
389 {
390 unsigned int i, j;
391
392 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
393 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
394 if (pfc->info->bias_regs[i].pins[j] == pin) {
395 *bit = j;
396 return &pfc->info->bias_regs[i];
397 }
398 }
399 }
400
401 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
402
403 return NULL;
404 }
405
406 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
407 {
408 struct sh_pfc_pin_range *range;
409 unsigned int nr_ranges;
410 unsigned int i;
411
412 if (pfc->info->pins[0].pin == (u16)-1) {
413
414
415
416
417 pfc->nr_ranges = 1;
418 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
419 GFP_KERNEL);
420 if (pfc->ranges == NULL)
421 return -ENOMEM;
422
423 pfc->ranges->start = 0;
424 pfc->ranges->end = pfc->info->nr_pins - 1;
425 pfc->nr_gpio_pins = pfc->info->nr_pins;
426
427 return 0;
428 }
429
430
431
432
433
434 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
435 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
436 nr_ranges++;
437 }
438
439 pfc->nr_ranges = nr_ranges;
440 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
441 GFP_KERNEL);
442 if (pfc->ranges == NULL)
443 return -ENOMEM;
444
445 range = pfc->ranges;
446 range->start = pfc->info->pins[0].pin;
447
448 for (i = 1; i < pfc->info->nr_pins; ++i) {
449 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
450 continue;
451
452 range->end = pfc->info->pins[i-1].pin;
453 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
454 pfc->nr_gpio_pins = range->end + 1;
455
456 range++;
457 range->start = pfc->info->pins[i].pin;
458 }
459
460 range->end = pfc->info->pins[i-1].pin;
461 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
462 pfc->nr_gpio_pins = range->end + 1;
463
464 return 0;
465 }
466
467 #ifdef CONFIG_OF
468 static const struct of_device_id sh_pfc_of_table[] = {
469 #ifdef CONFIG_PINCTRL_PFC_EMEV2
470 {
471 .compatible = "renesas,pfc-emev2",
472 .data = &emev2_pinmux_info,
473 },
474 #endif
475 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
476 {
477 .compatible = "renesas,pfc-r8a73a4",
478 .data = &r8a73a4_pinmux_info,
479 },
480 #endif
481 #ifdef CONFIG_PINCTRL_PFC_R8A7740
482 {
483 .compatible = "renesas,pfc-r8a7740",
484 .data = &r8a7740_pinmux_info,
485 },
486 #endif
487 #ifdef CONFIG_PINCTRL_PFC_R8A7743
488 {
489 .compatible = "renesas,pfc-r8a7743",
490 .data = &r8a7743_pinmux_info,
491 },
492 #endif
493 #ifdef CONFIG_PINCTRL_PFC_R8A7744
494 {
495 .compatible = "renesas,pfc-r8a7744",
496 .data = &r8a7744_pinmux_info,
497 },
498 #endif
499 #ifdef CONFIG_PINCTRL_PFC_R8A7745
500 {
501 .compatible = "renesas,pfc-r8a7745",
502 .data = &r8a7745_pinmux_info,
503 },
504 #endif
505 #ifdef CONFIG_PINCTRL_PFC_R8A77470
506 {
507 .compatible = "renesas,pfc-r8a77470",
508 .data = &r8a77470_pinmux_info,
509 },
510 #endif
511 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
512 {
513 .compatible = "renesas,pfc-r8a774a1",
514 .data = &r8a774a1_pinmux_info,
515 },
516 #endif
517 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
518 {
519 .compatible = "renesas,pfc-r8a774c0",
520 .data = &r8a774c0_pinmux_info,
521 },
522 #endif
523 #ifdef CONFIG_PINCTRL_PFC_R8A7778
524 {
525 .compatible = "renesas,pfc-r8a7778",
526 .data = &r8a7778_pinmux_info,
527 },
528 #endif
529 #ifdef CONFIG_PINCTRL_PFC_R8A7779
530 {
531 .compatible = "renesas,pfc-r8a7779",
532 .data = &r8a7779_pinmux_info,
533 },
534 #endif
535 #ifdef CONFIG_PINCTRL_PFC_R8A7790
536 {
537 .compatible = "renesas,pfc-r8a7790",
538 .data = &r8a7790_pinmux_info,
539 },
540 #endif
541 #ifdef CONFIG_PINCTRL_PFC_R8A7791
542 {
543 .compatible = "renesas,pfc-r8a7791",
544 .data = &r8a7791_pinmux_info,
545 },
546 #endif
547 #ifdef CONFIG_PINCTRL_PFC_R8A7792
548 {
549 .compatible = "renesas,pfc-r8a7792",
550 .data = &r8a7792_pinmux_info,
551 },
552 #endif
553 #ifdef CONFIG_PINCTRL_PFC_R8A7793
554 {
555 .compatible = "renesas,pfc-r8a7793",
556 .data = &r8a7793_pinmux_info,
557 },
558 #endif
559 #ifdef CONFIG_PINCTRL_PFC_R8A7794
560 {
561 .compatible = "renesas,pfc-r8a7794",
562 .data = &r8a7794_pinmux_info,
563 },
564 #endif
565 #ifdef CONFIG_PINCTRL_PFC_R8A7795
566 {
567 .compatible = "renesas,pfc-r8a7795",
568 .data = &r8a7795_pinmux_info,
569 },
570 #ifdef DEBUG
571 {
572
573 .compatible = "renesas,pfc-r8a77950",
574 .data = &r8a7795es1_pinmux_info,
575 },
576 #endif
577 #endif
578 #ifdef CONFIG_PINCTRL_PFC_R8A7796
579 {
580 .compatible = "renesas,pfc-r8a7796",
581 .data = &r8a7796_pinmux_info,
582 },
583 #endif
584 #ifdef CONFIG_PINCTRL_PFC_R8A77965
585 {
586 .compatible = "renesas,pfc-r8a77965",
587 .data = &r8a77965_pinmux_info,
588 },
589 #endif
590 #ifdef CONFIG_PINCTRL_PFC_R8A77970
591 {
592 .compatible = "renesas,pfc-r8a77970",
593 .data = &r8a77970_pinmux_info,
594 },
595 #endif
596 #ifdef CONFIG_PINCTRL_PFC_R8A77980
597 {
598 .compatible = "renesas,pfc-r8a77980",
599 .data = &r8a77980_pinmux_info,
600 },
601 #endif
602 #ifdef CONFIG_PINCTRL_PFC_R8A77990
603 {
604 .compatible = "renesas,pfc-r8a77990",
605 .data = &r8a77990_pinmux_info,
606 },
607 #endif
608 #ifdef CONFIG_PINCTRL_PFC_R8A77995
609 {
610 .compatible = "renesas,pfc-r8a77995",
611 .data = &r8a77995_pinmux_info,
612 },
613 #endif
614 #ifdef CONFIG_PINCTRL_PFC_SH73A0
615 {
616 .compatible = "renesas,pfc-sh73a0",
617 .data = &sh73a0_pinmux_info,
618 },
619 #endif
620 { },
621 };
622 #endif
623
624 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
625 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
626 {
627 }
628
629 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
630 {
631 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
632 }
633
634 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
635 {
636 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
637 }
638
639 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
640 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
641 {
642 unsigned int i, n = 0;
643
644 if (pfc->info->cfg_regs)
645 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
646 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
647
648 if (pfc->info->drive_regs)
649 for (i = 0; pfc->info->drive_regs[i].reg; i++)
650 do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
651
652 if (pfc->info->bias_regs)
653 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
654 do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
655 if (pfc->info->bias_regs[i].pud)
656 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
657 }
658
659 if (pfc->info->ioctrl_regs)
660 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
661 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
662
663 return n;
664 }
665
666 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
667 {
668 unsigned int n;
669
670
671 if (!psci_ops.cpu_suspend)
672 return 0;
673
674 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
675 if (!n)
676 return 0;
677
678 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
679 sizeof(*pfc->saved_regs),
680 GFP_KERNEL);
681 if (!pfc->saved_regs)
682 return -ENOMEM;
683
684 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
685 return 0;
686 }
687
688 static int sh_pfc_suspend_noirq(struct device *dev)
689 {
690 struct sh_pfc *pfc = dev_get_drvdata(dev);
691
692 if (pfc->saved_regs)
693 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
694 return 0;
695 }
696
697 static int sh_pfc_resume_noirq(struct device *dev)
698 {
699 struct sh_pfc *pfc = dev_get_drvdata(dev);
700
701 if (pfc->saved_regs)
702 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
703 return 0;
704 }
705
706 static const struct dev_pm_ops sh_pfc_pm = {
707 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
708 };
709 #define DEV_PM_OPS &sh_pfc_pm
710 #else
711 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
712 #define DEV_PM_OPS NULL
713 #endif
714
715 #ifdef DEBUG
716 static bool __init is0s(const u16 *enum_ids, unsigned int n)
717 {
718 unsigned int i;
719
720 for (i = 0; i < n; i++)
721 if (enum_ids[i])
722 return false;
723
724 return true;
725 }
726
727 static unsigned int sh_pfc_errors __initdata = 0;
728 static unsigned int sh_pfc_warnings __initdata = 0;
729
730 static void __init sh_pfc_check_cfg_reg(const char *drvname,
731 const struct pinmux_cfg_reg *cfg_reg)
732 {
733 unsigned int i, n, rw, fw;
734
735 if (cfg_reg->field_width) {
736
737 return;
738 }
739
740 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
741 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) {
742 pr_warn("%s: reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
743 drvname, cfg_reg->reg, rw, rw + fw - 1);
744 sh_pfc_warnings++;
745 }
746 n += 1 << fw;
747 rw += fw;
748 }
749
750 if (rw != cfg_reg->reg_width) {
751 pr_err("%s: reg 0x%x: var_field_width declares %u instead of %u bits\n",
752 drvname, cfg_reg->reg, rw, cfg_reg->reg_width);
753 sh_pfc_errors++;
754 }
755
756 if (n != cfg_reg->nr_enum_ids) {
757 pr_err("%s: reg 0x%x: enum_ids[] has %u instead of %u values\n",
758 drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n);
759 sh_pfc_errors++;
760 }
761 }
762
763 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
764 {
765 const struct sh_pfc_function *func;
766 const char *drvname = info->name;
767 unsigned int *refcnts;
768 unsigned int i, j, k;
769
770 pr_info("Checking %s\n", drvname);
771
772
773 for (i = 0; i < info->nr_pins; i++) {
774 for (j = 0; j < i; j++) {
775 if (!strcmp(info->pins[i].name, info->pins[j].name)) {
776 pr_err("%s: pin %s/%s: name conflict\n",
777 drvname, info->pins[i].name,
778 info->pins[j].name);
779 sh_pfc_errors++;
780 }
781
782 if (info->pins[i].pin != (u16)-1 &&
783 info->pins[i].pin == info->pins[j].pin) {
784 pr_err("%s: pin %s/%s: pin %u conflict\n",
785 drvname, info->pins[i].name,
786 info->pins[j].name, info->pins[i].pin);
787 sh_pfc_errors++;
788 }
789
790 if (info->pins[i].enum_id &&
791 info->pins[i].enum_id == info->pins[j].enum_id) {
792 pr_err("%s: pin %s/%s: enum_id %u conflict\n",
793 drvname, info->pins[i].name,
794 info->pins[j].name,
795 info->pins[i].enum_id);
796 sh_pfc_errors++;
797 }
798 }
799 }
800
801
802 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
803 if (!refcnts)
804 return;
805
806 for (i = 0; i < info->nr_functions; i++) {
807 func = &info->functions[i];
808 if (!func->name) {
809 pr_err("%s: empty function %u\n", drvname, i);
810 sh_pfc_errors++;
811 continue;
812 }
813 for (j = 0; j < func->nr_groups; j++) {
814 for (k = 0; k < info->nr_groups; k++) {
815 if (info->groups[k].name &&
816 !strcmp(func->groups[j],
817 info->groups[k].name)) {
818 refcnts[k]++;
819 break;
820 }
821 }
822
823 if (k == info->nr_groups) {
824 pr_err("%s: function %s: group %s not found\n",
825 drvname, func->name, func->groups[j]);
826 sh_pfc_errors++;
827 }
828 }
829 }
830
831 for (i = 0; i < info->nr_groups; i++) {
832 if (!info->groups[i].name) {
833 pr_err("%s: empty group %u\n", drvname, i);
834 sh_pfc_errors++;
835 continue;
836 }
837 if (!refcnts[i]) {
838 pr_err("%s: orphan group %s\n", drvname,
839 info->groups[i].name);
840 sh_pfc_errors++;
841 } else if (refcnts[i] > 1) {
842 pr_warn("%s: group %s referenced by %u functions\n",
843 drvname, info->groups[i].name, refcnts[i]);
844 sh_pfc_warnings++;
845 }
846 }
847
848 kfree(refcnts);
849
850
851 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
852 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
853 }
854
855 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
856 {
857 unsigned int i;
858
859 pr_warn("Checking builtin pinmux tables\n");
860
861 for (i = 0; pdrv->id_table[i].name[0]; i++)
862 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
863
864 #ifdef CONFIG_OF
865 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
866 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
867 #endif
868
869 pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
870 sh_pfc_warnings);
871 }
872
873 #else
874 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
875 #endif
876
877 static int sh_pfc_probe(struct platform_device *pdev)
878 {
879 #ifdef CONFIG_OF
880 struct device_node *np = pdev->dev.of_node;
881 #endif
882 const struct sh_pfc_soc_info *info;
883 struct sh_pfc *pfc;
884 int ret;
885
886 #ifdef CONFIG_OF
887 if (np)
888 info = of_device_get_match_data(&pdev->dev);
889 else
890 #endif
891 info = (const void *)platform_get_device_id(pdev)->driver_data;
892
893 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
894 if (pfc == NULL)
895 return -ENOMEM;
896
897 pfc->info = info;
898 pfc->dev = &pdev->dev;
899
900 ret = sh_pfc_map_resources(pfc, pdev);
901 if (unlikely(ret < 0))
902 return ret;
903
904 spin_lock_init(&pfc->lock);
905
906 if (info->ops && info->ops->init) {
907 ret = info->ops->init(pfc);
908 if (ret < 0)
909 return ret;
910
911
912 info = pfc->info;
913 }
914
915 ret = sh_pfc_suspend_init(pfc);
916 if (ret)
917 return ret;
918
919
920 if (!of_have_populated_dt())
921 pinctrl_provide_dummies();
922
923 ret = sh_pfc_init_ranges(pfc);
924 if (ret < 0)
925 return ret;
926
927
928
929
930 ret = sh_pfc_register_pinctrl(pfc);
931 if (unlikely(ret != 0))
932 return ret;
933
934 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
935
936
937
938 ret = sh_pfc_register_gpiochip(pfc);
939 if (unlikely(ret != 0)) {
940
941
942
943
944
945 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
946 }
947 #endif
948
949 platform_set_drvdata(pdev, pfc);
950
951 dev_info(pfc->dev, "%s support registered\n", info->name);
952
953 return 0;
954 }
955
956 static const struct platform_device_id sh_pfc_id_table[] = {
957 #ifdef CONFIG_PINCTRL_PFC_SH7203
958 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
959 #endif
960 #ifdef CONFIG_PINCTRL_PFC_SH7264
961 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
962 #endif
963 #ifdef CONFIG_PINCTRL_PFC_SH7269
964 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
965 #endif
966 #ifdef CONFIG_PINCTRL_PFC_SH7720
967 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
968 #endif
969 #ifdef CONFIG_PINCTRL_PFC_SH7722
970 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
971 #endif
972 #ifdef CONFIG_PINCTRL_PFC_SH7723
973 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
974 #endif
975 #ifdef CONFIG_PINCTRL_PFC_SH7724
976 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
977 #endif
978 #ifdef CONFIG_PINCTRL_PFC_SH7734
979 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
980 #endif
981 #ifdef CONFIG_PINCTRL_PFC_SH7757
982 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
983 #endif
984 #ifdef CONFIG_PINCTRL_PFC_SH7785
985 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
986 #endif
987 #ifdef CONFIG_PINCTRL_PFC_SH7786
988 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
989 #endif
990 #ifdef CONFIG_PINCTRL_PFC_SHX3
991 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
992 #endif
993 { },
994 };
995
996 static struct platform_driver sh_pfc_driver = {
997 .probe = sh_pfc_probe,
998 .id_table = sh_pfc_id_table,
999 .driver = {
1000 .name = DRV_NAME,
1001 .of_match_table = of_match_ptr(sh_pfc_of_table),
1002 .pm = DEV_PM_OPS,
1003 },
1004 };
1005
1006 static int __init sh_pfc_init(void)
1007 {
1008 sh_pfc_check_driver(&sh_pfc_driver);
1009 return platform_driver_register(&sh_pfc_driver);
1010 }
1011 postcore_initcall(sh_pfc_init);