root/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

/* [<][>][^][v][top][bottom][index][help] */ 
   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver
   4 // with eint support.
   5 //
   6 // Copyright (c) 2012 Samsung Electronics Co., Ltd.
   7 //              http://www.samsung.com
   8 // Copyright (c) 2012 Linaro Ltd
   9 //              http://www.linaro.org
  10 // Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
  11 //
  12 // This file contains the Samsung Exynos specific information required by the
  13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of
  14 // external gpio and wakeup interrupt support.
  15 
  16 #include <linux/slab.h>
  17 #include <linux/soc/samsung/exynos-regs-pmu.h>
  18 
  19 #include "pinctrl-samsung.h"
  20 #include "pinctrl-exynos.h"
  21 
  22 static const struct samsung_pin_bank_type bank_type_off = {
  23         .fld_width = { 4, 1, 2, 2, 2, 2, },
  24         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
  25 };
  26 
  27 static const struct samsung_pin_bank_type bank_type_alive = {
  28         .fld_width = { 4, 1, 2, 2, },
  29         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
  30 };
  31 
  32 /* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */
  33 static const struct samsung_pin_bank_type exynos5433_bank_type_off = {
  34         .fld_width = { 4, 1, 2, 4, 2, 2, },
  35         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
  36 };
  37 
  38 static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
  39         .fld_width = { 4, 1, 2, 4, },
  40         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
  41 };
  42 
  43 /* Pad retention control code for accessing PMU regmap */
  44 static atomic_t exynos_shared_retention_refcnt;
  45 
  46 /* pin banks of exynos5433 pin-controller - ALIVE */
  47 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = {
  48         /* Must start with EINTG banks, ordered by EINT group number. */
  49         EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
  50         EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
  51         EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
  52         EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
  53         EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
  54         EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
  55         EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
  56         EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
  57         EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
  58 };
  59 
  60 /* pin banks of exynos5433 pin-controller - AUD */
  61 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = {
  62         /* Must start with EINTG banks, ordered by EINT group number. */
  63         EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
  64         EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
  65 };
  66 
  67 /* pin banks of exynos5433 pin-controller - CPIF */
  68 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = {
  69         /* Must start with EINTG banks, ordered by EINT group number. */
  70         EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
  71 };
  72 
  73 /* pin banks of exynos5433 pin-controller - eSE */
  74 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = {
  75         /* Must start with EINTG banks, ordered by EINT group number. */
  76         EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
  77 };
  78 
  79 /* pin banks of exynos5433 pin-controller - FINGER */
  80 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = {
  81         /* Must start with EINTG banks, ordered by EINT group number. */
  82         EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
  83 };
  84 
  85 /* pin banks of exynos5433 pin-controller - FSYS */
  86 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = {
  87         /* Must start with EINTG banks, ordered by EINT group number. */
  88         EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
  89         EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
  90         EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
  91         EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
  92         EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
  93         EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
  94 };
  95 
  96 /* pin banks of exynos5433 pin-controller - IMEM */
  97 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = {
  98         /* Must start with EINTG banks, ordered by EINT group number. */
  99         EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
 100 };
 101 
 102 /* pin banks of exynos5433 pin-controller - NFC */
 103 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = {
 104         /* Must start with EINTG banks, ordered by EINT group number. */
 105         EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
 106 };
 107 
 108 /* pin banks of exynos5433 pin-controller - PERIC */
 109 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = {
 110         /* Must start with EINTG banks, ordered by EINT group number. */
 111         EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
 112         EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
 113         EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
 114         EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
 115         EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
 116         EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
 117         EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
 118         EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
 119         EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
 120         EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
 121         EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
 122         EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
 123         EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
 124         EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
 125         EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
 126         EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
 127         EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
 128 };
 129 
 130 /* pin banks of exynos5433 pin-controller - TOUCH */
 131 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = {
 132         /* Must start with EINTG banks, ordered by EINT group number. */
 133         EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
 134 };
 135 
 136 /* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */
 137 static const u32 exynos5433_retention_regs[] = {
 138         EXYNOS5433_PAD_RETENTION_TOP_OPTION,
 139         EXYNOS5433_PAD_RETENTION_UART_OPTION,
 140         EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
 141         EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
 142         EXYNOS5433_PAD_RETENTION_SPI_OPTION,
 143         EXYNOS5433_PAD_RETENTION_MIF_OPTION,
 144         EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
 145         EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
 146         EXYNOS5433_PAD_RETENTION_UFS_OPTION,
 147         EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,
 148 };
 149 
 150 static const struct samsung_retention_data exynos5433_retention_data __initconst = {
 151         .regs    = exynos5433_retention_regs,
 152         .nr_regs = ARRAY_SIZE(exynos5433_retention_regs),
 153         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 154         .refcnt  = &exynos_shared_retention_refcnt,
 155         .init    = exynos_retention_init,
 156 };
 157 
 158 /* PMU retention control for audio pins can be tied to audio pin bank */
 159 static const u32 exynos5433_audio_retention_regs[] = {
 160         EXYNOS5433_PAD_RETENTION_AUD_OPTION,
 161 };
 162 
 163 static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = {
 164         .regs    = exynos5433_audio_retention_regs,
 165         .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs),
 166         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 167         .init    = exynos_retention_init,
 168 };
 169 
 170 /* PMU retention control for mmc pins can be tied to fsys pin bank */
 171 static const u32 exynos5433_fsys_retention_regs[] = {
 172         EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
 173         EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
 174         EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
 175 };
 176 
 177 static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = {
 178         .regs    = exynos5433_fsys_retention_regs,
 179         .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs),
 180         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 181         .init    = exynos_retention_init,
 182 };
 183 
 184 /*
 185  * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
 186  * ten gpio/pin-mux/pinconfig controllers.
 187  */
 188 static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
 189         {
 190                 /* pin-controller instance 0 data */
 191                 .pin_banks      = exynos5433_pin_banks0,
 192                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks0),
 193                 .eint_wkup_init = exynos_eint_wkup_init,
 194                 .suspend        = exynos_pinctrl_suspend,
 195                 .resume         = exynos_pinctrl_resume,
 196                 .nr_ext_resources = 1,
 197                 .retention_data = &exynos5433_retention_data,
 198         }, {
 199                 /* pin-controller instance 1 data */
 200                 .pin_banks      = exynos5433_pin_banks1,
 201                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks1),
 202                 .eint_gpio_init = exynos_eint_gpio_init,
 203                 .suspend        = exynos_pinctrl_suspend,
 204                 .resume         = exynos_pinctrl_resume,
 205                 .retention_data = &exynos5433_audio_retention_data,
 206         }, {
 207                 /* pin-controller instance 2 data */
 208                 .pin_banks      = exynos5433_pin_banks2,
 209                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks2),
 210                 .eint_gpio_init = exynos_eint_gpio_init,
 211                 .suspend        = exynos_pinctrl_suspend,
 212                 .resume         = exynos_pinctrl_resume,
 213                 .retention_data = &exynos5433_retention_data,
 214         }, {
 215                 /* pin-controller instance 3 data */
 216                 .pin_banks      = exynos5433_pin_banks3,
 217                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks3),
 218                 .eint_gpio_init = exynos_eint_gpio_init,
 219                 .suspend        = exynos_pinctrl_suspend,
 220                 .resume         = exynos_pinctrl_resume,
 221                 .retention_data = &exynos5433_retention_data,
 222         }, {
 223                 /* pin-controller instance 4 data */
 224                 .pin_banks      = exynos5433_pin_banks4,
 225                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks4),
 226                 .eint_gpio_init = exynos_eint_gpio_init,
 227                 .suspend        = exynos_pinctrl_suspend,
 228                 .resume         = exynos_pinctrl_resume,
 229                 .retention_data = &exynos5433_retention_data,
 230         }, {
 231                 /* pin-controller instance 5 data */
 232                 .pin_banks      = exynos5433_pin_banks5,
 233                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks5),
 234                 .eint_gpio_init = exynos_eint_gpio_init,
 235                 .suspend        = exynos_pinctrl_suspend,
 236                 .resume         = exynos_pinctrl_resume,
 237                 .retention_data = &exynos5433_fsys_retention_data,
 238         }, {
 239                 /* pin-controller instance 6 data */
 240                 .pin_banks      = exynos5433_pin_banks6,
 241                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks6),
 242                 .eint_gpio_init = exynos_eint_gpio_init,
 243                 .suspend        = exynos_pinctrl_suspend,
 244                 .resume         = exynos_pinctrl_resume,
 245                 .retention_data = &exynos5433_retention_data,
 246         }, {
 247                 /* pin-controller instance 7 data */
 248                 .pin_banks      = exynos5433_pin_banks7,
 249                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks7),
 250                 .eint_gpio_init = exynos_eint_gpio_init,
 251                 .suspend        = exynos_pinctrl_suspend,
 252                 .resume         = exynos_pinctrl_resume,
 253                 .retention_data = &exynos5433_retention_data,
 254         }, {
 255                 /* pin-controller instance 8 data */
 256                 .pin_banks      = exynos5433_pin_banks8,
 257                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks8),
 258                 .eint_gpio_init = exynos_eint_gpio_init,
 259                 .suspend        = exynos_pinctrl_suspend,
 260                 .resume         = exynos_pinctrl_resume,
 261                 .retention_data = &exynos5433_retention_data,
 262         }, {
 263                 /* pin-controller instance 9 data */
 264                 .pin_banks      = exynos5433_pin_banks9,
 265                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks9),
 266                 .eint_gpio_init = exynos_eint_gpio_init,
 267                 .suspend        = exynos_pinctrl_suspend,
 268                 .resume         = exynos_pinctrl_resume,
 269                 .retention_data = &exynos5433_retention_data,
 270         },
 271 };
 272 
 273 const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = {
 274         .ctrl           = exynos5433_pin_ctrl,
 275         .num_ctrl       = ARRAY_SIZE(exynos5433_pin_ctrl),
 276 };
 277 
 278 /* pin banks of exynos7 pin-controller - ALIVE */
 279 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
 280         /* Must start with EINTG banks, ordered by EINT group number. */
 281         EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
 282         EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
 283         EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
 284         EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
 285 };
 286 
 287 /* pin banks of exynos7 pin-controller - BUS0 */
 288 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
 289         /* Must start with EINTG banks, ordered by EINT group number. */
 290         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
 291         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
 292         EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
 293         EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
 294         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
 295         EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
 296         EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
 297         EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
 298         EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
 299         EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
 300         EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
 301         EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
 302         EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
 303         EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
 304         EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
 305 };
 306 
 307 /* pin banks of exynos7 pin-controller - NFC */
 308 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
 309         /* Must start with EINTG banks, ordered by EINT group number. */
 310         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
 311 };
 312 
 313 /* pin banks of exynos7 pin-controller - TOUCH */
 314 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
 315         /* Must start with EINTG banks, ordered by EINT group number. */
 316         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
 317 };
 318 
 319 /* pin banks of exynos7 pin-controller - FF */
 320 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
 321         /* Must start with EINTG banks, ordered by EINT group number. */
 322         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
 323 };
 324 
 325 /* pin banks of exynos7 pin-controller - ESE */
 326 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
 327         /* Must start with EINTG banks, ordered by EINT group number. */
 328         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
 329 };
 330 
 331 /* pin banks of exynos7 pin-controller - FSYS0 */
 332 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
 333         /* Must start with EINTG banks, ordered by EINT group number. */
 334         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
 335 };
 336 
 337 /* pin banks of exynos7 pin-controller - FSYS1 */
 338 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
 339         /* Must start with EINTG banks, ordered by EINT group number. */
 340         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
 341         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
 342         EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
 343         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
 344 };
 345 
 346 /* pin banks of exynos7 pin-controller - BUS1 */
 347 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
 348         /* Must start with EINTG banks, ordered by EINT group number. */
 349         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
 350         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
 351         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
 352         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
 353         EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
 354         EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
 355         EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
 356         EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
 357         EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
 358         EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
 359 };
 360 
 361 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
 362         /* Must start with EINTG banks, ordered by EINT group number. */
 363         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
 364         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
 365 };
 366 
 367 static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
 368         {
 369                 /* pin-controller instance 0 Alive data */
 370                 .pin_banks      = exynos7_pin_banks0,
 371                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks0),
 372                 .eint_wkup_init = exynos_eint_wkup_init,
 373         }, {
 374                 /* pin-controller instance 1 BUS0 data */
 375                 .pin_banks      = exynos7_pin_banks1,
 376                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks1),
 377                 .eint_gpio_init = exynos_eint_gpio_init,
 378         }, {
 379                 /* pin-controller instance 2 NFC data */
 380                 .pin_banks      = exynos7_pin_banks2,
 381                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks2),
 382                 .eint_gpio_init = exynos_eint_gpio_init,
 383         }, {
 384                 /* pin-controller instance 3 TOUCH data */
 385                 .pin_banks      = exynos7_pin_banks3,
 386                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks3),
 387                 .eint_gpio_init = exynos_eint_gpio_init,
 388         }, {
 389                 /* pin-controller instance 4 FF data */
 390                 .pin_banks      = exynos7_pin_banks4,
 391                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks4),
 392                 .eint_gpio_init = exynos_eint_gpio_init,
 393         }, {
 394                 /* pin-controller instance 5 ESE data */
 395                 .pin_banks      = exynos7_pin_banks5,
 396                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks5),
 397                 .eint_gpio_init = exynos_eint_gpio_init,
 398         }, {
 399                 /* pin-controller instance 6 FSYS0 data */
 400                 .pin_banks      = exynos7_pin_banks6,
 401                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks6),
 402                 .eint_gpio_init = exynos_eint_gpio_init,
 403         }, {
 404                 /* pin-controller instance 7 FSYS1 data */
 405                 .pin_banks      = exynos7_pin_banks7,
 406                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
 407                 .eint_gpio_init = exynos_eint_gpio_init,
 408         }, {
 409                 /* pin-controller instance 8 BUS1 data */
 410                 .pin_banks      = exynos7_pin_banks8,
 411                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
 412                 .eint_gpio_init = exynos_eint_gpio_init,
 413         }, {
 414                 /* pin-controller instance 9 AUD data */
 415                 .pin_banks      = exynos7_pin_banks9,
 416                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks9),
 417                 .eint_gpio_init = exynos_eint_gpio_init,
 418         },
 419 };
 420 
 421 const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
 422         .ctrl           = exynos7_pin_ctrl,
 423         .num_ctrl       = ARRAY_SIZE(exynos7_pin_ctrl),
 424 };
/* [<][>][^][v][top][bottom][index][help] */