This source file includes following definitions.
- pmx_readl
- pmx_writel
- tegra_pinctrl_get_groups_count
- tegra_pinctrl_get_group_name
- tegra_pinctrl_get_group_pins
- tegra_pinctrl_pin_dbg_show
- tegra_pinctrl_dt_subnode_to_map
- tegra_pinctrl_dt_node_to_map
- tegra_pinctrl_get_funcs_count
- tegra_pinctrl_get_func_name
- tegra_pinctrl_get_func_groups
- tegra_pinctrl_set_mux
- tegra_pinconf_reg
- tegra_pinconf_get
- tegra_pinconf_set
- tegra_pinconf_group_get
- tegra_pinconf_group_set
- tegra_pinconf_dbg_show
- strip_prefix
- tegra_pinconf_group_dbg_show
- tegra_pinconf_config_dbg_show
- tegra_pinctrl_clear_parked_bits
- tegra_pinctrl_get_bank_size
- tegra_pinctrl_suspend
- tegra_pinctrl_resume
- gpio_node_has_range
- tegra_pinctrl_probe
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13 #include <linux/err.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/machine.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/slab.h>
23
24 #include "../core.h"
25 #include "../pinctrl-utils.h"
26 #include "pinctrl-tegra.h"
27
28 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
29 {
30 return readl(pmx->regs[bank] + reg);
31 }
32
33 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
34 {
35 writel_relaxed(val, pmx->regs[bank] + reg);
36
37 pmx_readl(pmx, bank, reg);
38 }
39
40 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
41 {
42 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
43
44 return pmx->soc->ngroups;
45 }
46
47 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
48 unsigned group)
49 {
50 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
51
52 return pmx->soc->groups[group].name;
53 }
54
55 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
56 unsigned group,
57 const unsigned **pins,
58 unsigned *num_pins)
59 {
60 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
61
62 *pins = pmx->soc->groups[group].pins;
63 *num_pins = pmx->soc->groups[group].npins;
64
65 return 0;
66 }
67
68 #ifdef CONFIG_DEBUG_FS
69 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
70 struct seq_file *s,
71 unsigned offset)
72 {
73 seq_printf(s, " %s", dev_name(pctldev->dev));
74 }
75 #endif
76
77 static const struct cfg_param {
78 const char *property;
79 enum tegra_pinconf_param param;
80 } cfg_params[] = {
81 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
82 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
83 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
84 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
85 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
86 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
87 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
88 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
89 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
90 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
91 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
92 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
93 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
94 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
95 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
96 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
97 };
98
99 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
100 struct device_node *np,
101 struct pinctrl_map **map,
102 unsigned *reserved_maps,
103 unsigned *num_maps)
104 {
105 struct device *dev = pctldev->dev;
106 int ret, i;
107 const char *function;
108 u32 val;
109 unsigned long config;
110 unsigned long *configs = NULL;
111 unsigned num_configs = 0;
112 unsigned reserve;
113 struct property *prop;
114 const char *group;
115
116 ret = of_property_read_string(np, "nvidia,function", &function);
117 if (ret < 0) {
118
119 if (ret != -EINVAL)
120 dev_err(dev,
121 "could not parse property nvidia,function\n");
122 function = NULL;
123 }
124
125 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
126 ret = of_property_read_u32(np, cfg_params[i].property, &val);
127 if (!ret) {
128 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
129 ret = pinctrl_utils_add_config(pctldev, &configs,
130 &num_configs, config);
131 if (ret < 0)
132 goto exit;
133
134 } else if (ret != -EINVAL) {
135 dev_err(dev, "could not parse property %s\n",
136 cfg_params[i].property);
137 }
138 }
139
140 reserve = 0;
141 if (function != NULL)
142 reserve++;
143 if (num_configs)
144 reserve++;
145 ret = of_property_count_strings(np, "nvidia,pins");
146 if (ret < 0) {
147 dev_err(dev, "could not parse property nvidia,pins\n");
148 goto exit;
149 }
150 reserve *= ret;
151
152 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
153 num_maps, reserve);
154 if (ret < 0)
155 goto exit;
156
157 of_property_for_each_string(np, "nvidia,pins", prop, group) {
158 if (function) {
159 ret = pinctrl_utils_add_map_mux(pctldev, map,
160 reserved_maps, num_maps, group,
161 function);
162 if (ret < 0)
163 goto exit;
164 }
165
166 if (num_configs) {
167 ret = pinctrl_utils_add_map_configs(pctldev, map,
168 reserved_maps, num_maps, group,
169 configs, num_configs,
170 PIN_MAP_TYPE_CONFIGS_GROUP);
171 if (ret < 0)
172 goto exit;
173 }
174 }
175
176 ret = 0;
177
178 exit:
179 kfree(configs);
180 return ret;
181 }
182
183 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
184 struct device_node *np_config,
185 struct pinctrl_map **map,
186 unsigned *num_maps)
187 {
188 unsigned reserved_maps;
189 struct device_node *np;
190 int ret;
191
192 reserved_maps = 0;
193 *map = NULL;
194 *num_maps = 0;
195
196 for_each_child_of_node(np_config, np) {
197 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
198 &reserved_maps, num_maps);
199 if (ret < 0) {
200 pinctrl_utils_free_map(pctldev, *map,
201 *num_maps);
202 of_node_put(np);
203 return ret;
204 }
205 }
206
207 return 0;
208 }
209
210 static const struct pinctrl_ops tegra_pinctrl_ops = {
211 .get_groups_count = tegra_pinctrl_get_groups_count,
212 .get_group_name = tegra_pinctrl_get_group_name,
213 .get_group_pins = tegra_pinctrl_get_group_pins,
214 #ifdef CONFIG_DEBUG_FS
215 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
216 #endif
217 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
218 .dt_free_map = pinctrl_utils_free_map,
219 };
220
221 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
222 {
223 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
224
225 return pmx->soc->nfunctions;
226 }
227
228 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
229 unsigned function)
230 {
231 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
232
233 return pmx->soc->functions[function].name;
234 }
235
236 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
237 unsigned function,
238 const char * const **groups,
239 unsigned * const num_groups)
240 {
241 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
242
243 *groups = pmx->soc->functions[function].groups;
244 *num_groups = pmx->soc->functions[function].ngroups;
245
246 return 0;
247 }
248
249 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
250 unsigned function,
251 unsigned group)
252 {
253 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
254 const struct tegra_pingroup *g;
255 int i;
256 u32 val;
257
258 g = &pmx->soc->groups[group];
259
260 if (WARN_ON(g->mux_reg < 0))
261 return -EINVAL;
262
263 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
264 if (g->funcs[i] == function)
265 break;
266 }
267 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
268 return -EINVAL;
269
270 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
271 val &= ~(0x3 << g->mux_bit);
272 val |= i << g->mux_bit;
273 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
274
275 return 0;
276 }
277
278 static const struct pinmux_ops tegra_pinmux_ops = {
279 .get_functions_count = tegra_pinctrl_get_funcs_count,
280 .get_function_name = tegra_pinctrl_get_func_name,
281 .get_function_groups = tegra_pinctrl_get_func_groups,
282 .set_mux = tegra_pinctrl_set_mux,
283 };
284
285 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
286 const struct tegra_pingroup *g,
287 enum tegra_pinconf_param param,
288 bool report_err,
289 s8 *bank, s32 *reg, s8 *bit, s8 *width)
290 {
291 switch (param) {
292 case TEGRA_PINCONF_PARAM_PULL:
293 *bank = g->pupd_bank;
294 *reg = g->pupd_reg;
295 *bit = g->pupd_bit;
296 *width = 2;
297 break;
298 case TEGRA_PINCONF_PARAM_TRISTATE:
299 *bank = g->tri_bank;
300 *reg = g->tri_reg;
301 *bit = g->tri_bit;
302 *width = 1;
303 break;
304 case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
305 *bank = g->mux_bank;
306 *reg = g->mux_reg;
307 *bit = g->einput_bit;
308 *width = 1;
309 break;
310 case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
311 *bank = g->mux_bank;
312 *reg = g->mux_reg;
313 *bit = g->odrain_bit;
314 *width = 1;
315 break;
316 case TEGRA_PINCONF_PARAM_LOCK:
317 *bank = g->mux_bank;
318 *reg = g->mux_reg;
319 *bit = g->lock_bit;
320 *width = 1;
321 break;
322 case TEGRA_PINCONF_PARAM_IORESET:
323 *bank = g->mux_bank;
324 *reg = g->mux_reg;
325 *bit = g->ioreset_bit;
326 *width = 1;
327 break;
328 case TEGRA_PINCONF_PARAM_RCV_SEL:
329 *bank = g->mux_bank;
330 *reg = g->mux_reg;
331 *bit = g->rcv_sel_bit;
332 *width = 1;
333 break;
334 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
335 if (pmx->soc->hsm_in_mux) {
336 *bank = g->mux_bank;
337 *reg = g->mux_reg;
338 } else {
339 *bank = g->drv_bank;
340 *reg = g->drv_reg;
341 }
342 *bit = g->hsm_bit;
343 *width = 1;
344 break;
345 case TEGRA_PINCONF_PARAM_SCHMITT:
346 if (pmx->soc->schmitt_in_mux) {
347 *bank = g->mux_bank;
348 *reg = g->mux_reg;
349 } else {
350 *bank = g->drv_bank;
351 *reg = g->drv_reg;
352 }
353 *bit = g->schmitt_bit;
354 *width = 1;
355 break;
356 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
357 *bank = g->drv_bank;
358 *reg = g->drv_reg;
359 *bit = g->lpmd_bit;
360 *width = 2;
361 break;
362 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
363 *bank = g->drv_bank;
364 *reg = g->drv_reg;
365 *bit = g->drvdn_bit;
366 *width = g->drvdn_width;
367 break;
368 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
369 *bank = g->drv_bank;
370 *reg = g->drv_reg;
371 *bit = g->drvup_bit;
372 *width = g->drvup_width;
373 break;
374 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
375 *bank = g->drv_bank;
376 *reg = g->drv_reg;
377 *bit = g->slwf_bit;
378 *width = g->slwf_width;
379 break;
380 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
381 *bank = g->drv_bank;
382 *reg = g->drv_reg;
383 *bit = g->slwr_bit;
384 *width = g->slwr_width;
385 break;
386 case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
387 if (pmx->soc->drvtype_in_mux) {
388 *bank = g->mux_bank;
389 *reg = g->mux_reg;
390 } else {
391 *bank = g->drv_bank;
392 *reg = g->drv_reg;
393 }
394 *bit = g->drvtype_bit;
395 *width = 2;
396 break;
397 default:
398 dev_err(pmx->dev, "Invalid config param %04x\n", param);
399 return -ENOTSUPP;
400 }
401
402 if (*reg < 0 || *bit < 0) {
403 if (report_err) {
404 const char *prop = "unknown";
405 int i;
406
407 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
408 if (cfg_params[i].param == param) {
409 prop = cfg_params[i].property;
410 break;
411 }
412 }
413
414 dev_err(pmx->dev,
415 "Config param %04x (%s) not supported on group %s\n",
416 param, prop, g->name);
417 }
418 return -ENOTSUPP;
419 }
420
421 return 0;
422 }
423
424 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
425 unsigned pin, unsigned long *config)
426 {
427 dev_err(pctldev->dev, "pin_config_get op not supported\n");
428 return -ENOTSUPP;
429 }
430
431 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
432 unsigned pin, unsigned long *configs,
433 unsigned num_configs)
434 {
435 dev_err(pctldev->dev, "pin_config_set op not supported\n");
436 return -ENOTSUPP;
437 }
438
439 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
440 unsigned group, unsigned long *config)
441 {
442 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
443 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
444 u16 arg;
445 const struct tegra_pingroup *g;
446 int ret;
447 s8 bank, bit, width;
448 s32 reg;
449 u32 val, mask;
450
451 g = &pmx->soc->groups[group];
452
453 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
454 &width);
455 if (ret < 0)
456 return ret;
457
458 val = pmx_readl(pmx, bank, reg);
459 mask = (1 << width) - 1;
460 arg = (val >> bit) & mask;
461
462 *config = TEGRA_PINCONF_PACK(param, arg);
463
464 return 0;
465 }
466
467 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
468 unsigned group, unsigned long *configs,
469 unsigned num_configs)
470 {
471 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
472 enum tegra_pinconf_param param;
473 u16 arg;
474 const struct tegra_pingroup *g;
475 int ret, i;
476 s8 bank, bit, width;
477 s32 reg;
478 u32 val, mask;
479
480 g = &pmx->soc->groups[group];
481
482 for (i = 0; i < num_configs; i++) {
483 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
484 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
485
486 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
487 &width);
488 if (ret < 0)
489 return ret;
490
491 val = pmx_readl(pmx, bank, reg);
492
493
494 if (param == TEGRA_PINCONF_PARAM_LOCK) {
495 if ((val & BIT(bit)) && !arg) {
496 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
497 return -EINVAL;
498 }
499 }
500
501
502 if (width == 1)
503 arg = !!arg;
504
505
506 mask = (1 << width) - 1;
507 if (arg & ~mask) {
508 dev_err(pctldev->dev,
509 "config %lx: %x too big for %d bit register\n",
510 configs[i], arg, width);
511 return -EINVAL;
512 }
513
514
515 val &= ~(mask << bit);
516 val |= arg << bit;
517 pmx_writel(pmx, val, bank, reg);
518 }
519
520 return 0;
521 }
522
523 #ifdef CONFIG_DEBUG_FS
524 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
525 struct seq_file *s, unsigned offset)
526 {
527 }
528
529 static const char *strip_prefix(const char *s)
530 {
531 const char *comma = strchr(s, ',');
532 if (!comma)
533 return s;
534
535 return comma + 1;
536 }
537
538 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
539 struct seq_file *s, unsigned group)
540 {
541 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
542 const struct tegra_pingroup *g;
543 int i, ret;
544 s8 bank, bit, width;
545 s32 reg;
546 u32 val;
547
548 g = &pmx->soc->groups[group];
549
550 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
551 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
552 &bank, ®, &bit, &width);
553 if (ret < 0)
554 continue;
555
556 val = pmx_readl(pmx, bank, reg);
557 val >>= bit;
558 val &= (1 << width) - 1;
559
560 seq_printf(s, "\n\t%s=%u",
561 strip_prefix(cfg_params[i].property), val);
562 }
563 }
564
565 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
566 struct seq_file *s,
567 unsigned long config)
568 {
569 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
570 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
571 const char *pname = "unknown";
572 int i;
573
574 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
575 if (cfg_params[i].param == param) {
576 pname = cfg_params[i].property;
577 break;
578 }
579 }
580
581 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
582 }
583 #endif
584
585 static const struct pinconf_ops tegra_pinconf_ops = {
586 .pin_config_get = tegra_pinconf_get,
587 .pin_config_set = tegra_pinconf_set,
588 .pin_config_group_get = tegra_pinconf_group_get,
589 .pin_config_group_set = tegra_pinconf_group_set,
590 #ifdef CONFIG_DEBUG_FS
591 .pin_config_dbg_show = tegra_pinconf_dbg_show,
592 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
593 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
594 #endif
595 };
596
597 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
598 .name = "Tegra GPIOs",
599 .id = 0,
600 .base = 0,
601 };
602
603 static struct pinctrl_desc tegra_pinctrl_desc = {
604 .pctlops = &tegra_pinctrl_ops,
605 .pmxops = &tegra_pinmux_ops,
606 .confops = &tegra_pinconf_ops,
607 .owner = THIS_MODULE,
608 };
609
610 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
611 {
612 int i = 0;
613 const struct tegra_pingroup *g;
614 u32 val;
615
616 for (i = 0; i < pmx->soc->ngroups; ++i) {
617 g = &pmx->soc->groups[i];
618 if (g->parked_bitmask > 0) {
619 unsigned int bank, reg;
620
621 if (g->mux_reg != -1) {
622 bank = g->mux_bank;
623 reg = g->mux_reg;
624 } else {
625 bank = g->drv_bank;
626 reg = g->drv_reg;
627 }
628
629 val = pmx_readl(pmx, bank, reg);
630 val &= ~g->parked_bitmask;
631 pmx_writel(pmx, val, bank, reg);
632 }
633 }
634 }
635
636 static size_t tegra_pinctrl_get_bank_size(struct device *dev,
637 unsigned int bank_id)
638 {
639 struct platform_device *pdev = to_platform_device(dev);
640 struct resource *res;
641
642 res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
643
644 return resource_size(res) / 4;
645 }
646
647 static int tegra_pinctrl_suspend(struct device *dev)
648 {
649 struct tegra_pmx *pmx = dev_get_drvdata(dev);
650 u32 *backup_regs = pmx->backup_regs;
651 u32 *regs;
652 size_t bank_size;
653 unsigned int i, k;
654
655 for (i = 0; i < pmx->nbanks; i++) {
656 bank_size = tegra_pinctrl_get_bank_size(dev, i);
657 regs = pmx->regs[i];
658 for (k = 0; k < bank_size; k++)
659 *backup_regs++ = readl_relaxed(regs++);
660 }
661
662 return pinctrl_force_sleep(pmx->pctl);
663 }
664
665 static int tegra_pinctrl_resume(struct device *dev)
666 {
667 struct tegra_pmx *pmx = dev_get_drvdata(dev);
668 u32 *backup_regs = pmx->backup_regs;
669 u32 *regs;
670 size_t bank_size;
671 unsigned int i, k;
672
673 for (i = 0; i < pmx->nbanks; i++) {
674 bank_size = tegra_pinctrl_get_bank_size(dev, i);
675 regs = pmx->regs[i];
676 for (k = 0; k < bank_size; k++)
677 writel_relaxed(*backup_regs++, regs++);
678 }
679
680
681 readl_relaxed(pmx->regs[0]);
682
683 rmb();
684 return 0;
685 }
686
687 const struct dev_pm_ops tegra_pinctrl_pm = {
688 .suspend = &tegra_pinctrl_suspend,
689 .resume = &tegra_pinctrl_resume
690 };
691
692 static bool gpio_node_has_range(const char *compatible)
693 {
694 struct device_node *np;
695 bool has_prop = false;
696
697 np = of_find_compatible_node(NULL, NULL, compatible);
698 if (!np)
699 return has_prop;
700
701 has_prop = of_find_property(np, "gpio-ranges", NULL);
702
703 of_node_put(np);
704
705 return has_prop;
706 }
707
708 int tegra_pinctrl_probe(struct platform_device *pdev,
709 const struct tegra_pinctrl_soc_data *soc_data)
710 {
711 struct tegra_pmx *pmx;
712 struct resource *res;
713 int i;
714 const char **group_pins;
715 int fn, gn, gfn;
716 unsigned long backup_regs_size = 0;
717
718 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
719 if (!pmx)
720 return -ENOMEM;
721
722 pmx->dev = &pdev->dev;
723 pmx->soc = soc_data;
724
725
726
727
728
729 pmx->group_pins = devm_kcalloc(&pdev->dev,
730 soc_data->ngroups * 4, sizeof(*pmx->group_pins),
731 GFP_KERNEL);
732 if (!pmx->group_pins)
733 return -ENOMEM;
734
735 group_pins = pmx->group_pins;
736 for (fn = 0; fn < soc_data->nfunctions; fn++) {
737 struct tegra_function *func = &soc_data->functions[fn];
738
739 func->groups = group_pins;
740
741 for (gn = 0; gn < soc_data->ngroups; gn++) {
742 const struct tegra_pingroup *g = &soc_data->groups[gn];
743
744 if (g->mux_reg == -1)
745 continue;
746
747 for (gfn = 0; gfn < 4; gfn++)
748 if (g->funcs[gfn] == fn)
749 break;
750 if (gfn == 4)
751 continue;
752
753 BUG_ON(group_pins - pmx->group_pins >=
754 soc_data->ngroups * 4);
755 *group_pins++ = g->name;
756 func->ngroups++;
757 }
758 }
759
760 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
761 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
762 tegra_pinctrl_desc.pins = pmx->soc->pins;
763 tegra_pinctrl_desc.npins = pmx->soc->npins;
764
765 for (i = 0; ; i++) {
766 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
767 if (!res)
768 break;
769 backup_regs_size += resource_size(res);
770 }
771 pmx->nbanks = i;
772
773 pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
774 GFP_KERNEL);
775 if (!pmx->regs)
776 return -ENOMEM;
777
778 pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
779 GFP_KERNEL);
780 if (!pmx->backup_regs)
781 return -ENOMEM;
782
783 for (i = 0; i < pmx->nbanks; i++) {
784 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
785 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
786 if (IS_ERR(pmx->regs[i]))
787 return PTR_ERR(pmx->regs[i]);
788 }
789
790 pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
791 if (IS_ERR(pmx->pctl)) {
792 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
793 return PTR_ERR(pmx->pctl);
794 }
795
796 tegra_pinctrl_clear_parked_bits(pmx);
797
798 if (!gpio_node_has_range(pmx->soc->gpio_compatible))
799 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
800
801 platform_set_drvdata(pdev, pmx);
802
803 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
804
805 return 0;
806 }