1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Driver for the NVIDIA Tegra pinmux
4 *
5 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
6 */
7
8 #ifndef __PINMUX_TEGRA_H__
9 #define __PINMUX_TEGRA_H__
10
11 struct tegra_pmx {
12 struct device *dev;
13 struct pinctrl_dev *pctl;
14
15 const struct tegra_pinctrl_soc_data *soc;
16 const char **group_pins;
17
18 int nbanks;
19 void __iomem **regs;
20 u32 *backup_regs;
21 };
22
23 enum tegra_pinconf_param {
24 /* argument: tegra_pinconf_pull */
25 TEGRA_PINCONF_PARAM_PULL,
26 /* argument: tegra_pinconf_tristate */
27 TEGRA_PINCONF_PARAM_TRISTATE,
28 /* argument: Boolean */
29 TEGRA_PINCONF_PARAM_ENABLE_INPUT,
30 /* argument: Boolean */
31 TEGRA_PINCONF_PARAM_OPEN_DRAIN,
32 /* argument: Boolean */
33 TEGRA_PINCONF_PARAM_LOCK,
34 /* argument: Boolean */
35 TEGRA_PINCONF_PARAM_IORESET,
36 /* argument: Boolean */
37 TEGRA_PINCONF_PARAM_RCV_SEL,
38 /* argument: Boolean */
39 TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
40 /* argument: Boolean */
41 TEGRA_PINCONF_PARAM_SCHMITT,
42 /* argument: Boolean */
43 TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
44 /* argument: Integer, range is HW-dependant */
45 TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
46 /* argument: Integer, range is HW-dependant */
47 TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
48 /* argument: Integer, range is HW-dependant */
49 TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
50 /* argument: Integer, range is HW-dependant */
51 TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
52 /* argument: Integer, range is HW-dependant */
53 TEGRA_PINCONF_PARAM_DRIVE_TYPE,
54 };
55
56 enum tegra_pinconf_pull {
57 TEGRA_PINCONFIG_PULL_NONE,
58 TEGRA_PINCONFIG_PULL_DOWN,
59 TEGRA_PINCONFIG_PULL_UP,
60 };
61
62 enum tegra_pinconf_tristate {
63 TEGRA_PINCONFIG_DRIVEN,
64 TEGRA_PINCONFIG_TRISTATE,
65 };
66
67 #define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
68 #define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
69 #define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
70
71 /**
72 * struct tegra_function - Tegra pinctrl mux function
73 * @name: The name of the function, exported to pinctrl core.
74 * @groups: An array of pin groups that may select this function.
75 * @ngroups: The number of entries in @groups.
76 */
77 struct tegra_function {
78 const char *name;
79 const char **groups;
80 unsigned ngroups;
81 };
82
83 /**
84 * struct tegra_pingroup - Tegra pin group
85 * @name The name of the pin group.
86 * @pins An array of pin IDs included in this pin group.
87 * @npins The number of entries in @pins.
88 * @funcs The mux functions which can be muxed onto this group.
89 * @mux_reg: Mux register offset.
90 * This register contains the mux, einput, odrain, lock,
91 * ioreset, rcv_sel parameters.
92 * @mux_bank: Mux register bank.
93 * @mux_bit: Mux register bit.
94 * @pupd_reg: Pull-up/down register offset.
95 * @pupd_bank: Pull-up/down register bank.
96 * @pupd_bit: Pull-up/down register bit.
97 * @tri_reg: Tri-state register offset.
98 * @tri_bank: Tri-state register bank.
99 * @tri_bit: Tri-state register bit.
100 * @einput_bit: Enable-input register bit.
101 * @odrain_bit: Open-drain register bit.
102 * @lock_bit: Lock register bit.
103 * @ioreset_bit: IO reset register bit.
104 * @rcv_sel_bit: Receiver select bit.
105 * @drv_reg: Drive fields register offset.
106 * This register contains hsm, schmitt, lpmd, drvdn,
107 * drvup, slwr, slwf, and drvtype parameters.
108 * @drv_bank: Drive fields register bank.
109 * @hsm_bit: High Speed Mode register bit.
110 * @schmitt_bit: Scmitt register bit.
111 * @lpmd_bit: Low Power Mode register bit.
112 * @drvdn_bit: Drive Down register bit.
113 * @drvdn_width: Drive Down field width.
114 * @drvup_bit: Drive Up register bit.
115 * @drvup_width: Drive Up field width.
116 * @slwr_bit: Slew Rising register bit.
117 * @slwr_width: Slew Rising field width.
118 * @slwf_bit: Slew Falling register bit.
119 * @slwf_width: Slew Falling field width.
120 * @drvtype_bit: Drive type register bit.
121 * @parked_bitmask: Parked register mask. 0 if unsupported.
122 *
123 * -1 in a *_reg field means that feature is unsupported for this group.
124 * *_bank and *_reg values are irrelevant when *_reg is -1.
125 * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
126 *
127 * A representation of a group of pins (possibly just one pin) in the Tegra
128 * pin controller. Each group allows some parameter or parameters to be
129 * configured. The most common is mux function selection. Many others exist
130 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
131 * certain groups may only support configuring certain parameters, hence
132 * each parameter is optional.
133 */
134 struct tegra_pingroup {
135 const char *name;
136 const unsigned *pins;
137 u8 npins;
138 u8 funcs[4];
139 s32 mux_reg;
140 s32 pupd_reg;
141 s32 tri_reg;
142 s32 drv_reg;
143 u32 mux_bank:2;
144 u32 pupd_bank:2;
145 u32 tri_bank:2;
146 u32 drv_bank:2;
147 s32 mux_bit:6;
148 s32 pupd_bit:6;
149 s32 tri_bit:6;
150 s32 einput_bit:6;
151 s32 odrain_bit:6;
152 s32 lock_bit:6;
153 s32 ioreset_bit:6;
154 s32 rcv_sel_bit:6;
155 s32 hsm_bit:6;
156 s32 schmitt_bit:6;
157 s32 lpmd_bit:6;
158 s32 drvdn_bit:6;
159 s32 drvup_bit:6;
160 s32 slwr_bit:6;
161 s32 slwf_bit:6;
162 s32 drvtype_bit:6;
163 s32 drvdn_width:6;
164 s32 drvup_width:6;
165 s32 slwr_width:6;
166 s32 slwf_width:6;
167 u32 parked_bitmask;
168 };
169
170 /**
171 * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
172 * @ngpios: The number of GPIO pins the pin controller HW affects.
173 * @pins: An array describing all pins the pin controller affects.
174 * All pins which are also GPIOs must be listed first within the
175 * array, and be numbered identically to the GPIO controller's
176 * numbering.
177 * @npins: The numbmer of entries in @pins.
178 * @functions: An array describing all mux functions the SoC supports.
179 * @nfunctions: The numbmer of entries in @functions.
180 * @groups: An array describing all pin groups the pin SoC supports.
181 * @ngroups: The numbmer of entries in @groups.
182 */
183 struct tegra_pinctrl_soc_data {
184 unsigned ngpios;
185 const char *gpio_compatible;
186 const struct pinctrl_pin_desc *pins;
187 unsigned npins;
188 struct tegra_function *functions;
189 unsigned nfunctions;
190 const struct tegra_pingroup *groups;
191 unsigned ngroups;
192 bool hsm_in_mux;
193 bool schmitt_in_mux;
194 bool drvtype_in_mux;
195 };
196
197 extern const struct dev_pm_ops tegra_pinctrl_pm;
198
199 int tegra_pinctrl_probe(struct platform_device *pdev,
200 const struct tegra_pinctrl_soc_data *soc_data);
201 #endif