This source file includes following definitions.
- spt_pinctrl_init
- spt_pinctrl_exit
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10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13
14 #include <linux/pinctrl/pinctrl.h>
15
16 #include "pinctrl-intel.h"
17
18 #define SPT_PAD_OWN 0x020
19 #define SPT_H_PADCFGLOCK 0x090
20 #define SPT_LP_PADCFGLOCK 0x0a0
21 #define SPT_HOSTSW_OWN 0x0d0
22 #define SPT_GPI_IS 0x100
23 #define SPT_GPI_IE 0x120
24
25 #define SPT_COMMUNITY(b, s, e) \
26 { \
27 .barno = (b), \
28 .padown_offset = SPT_PAD_OWN, \
29 .padcfglock_offset = SPT_LP_PADCFGLOCK, \
30 .hostown_offset = SPT_HOSTSW_OWN, \
31 .is_offset = SPT_GPI_IS, \
32 .ie_offset = SPT_GPI_IE, \
33 .gpp_size = 24, \
34 .gpp_num_padown_regs = 4, \
35 .pin_base = (s), \
36 .npins = ((e) - (s) + 1), \
37 }
38
39 #define SPTH_GPP(r, s, e, g) \
40 { \
41 .reg_num = (r), \
42 .base = (s), \
43 .size = ((e) - (s) + 1), \
44 .gpio_base = (g), \
45 }
46
47 #define SPTH_COMMUNITY(b, s, e, g) \
48 { \
49 .barno = (b), \
50 .padown_offset = SPT_PAD_OWN, \
51 .padcfglock_offset = SPT_H_PADCFGLOCK, \
52 .hostown_offset = SPT_HOSTSW_OWN, \
53 .is_offset = SPT_GPI_IS, \
54 .ie_offset = SPT_GPI_IE, \
55 .pin_base = (s), \
56 .npins = ((e) - (s) + 1), \
57 .gpps = (g), \
58 .ngpps = ARRAY_SIZE(g), \
59 }
60
61
62 static const struct pinctrl_pin_desc sptlp_pins[] = {
63
64 PINCTRL_PIN(0, "RCINB"),
65 PINCTRL_PIN(1, "LAD_0"),
66 PINCTRL_PIN(2, "LAD_1"),
67 PINCTRL_PIN(3, "LAD_2"),
68 PINCTRL_PIN(4, "LAD_3"),
69 PINCTRL_PIN(5, "LFRAMEB"),
70 PINCTRL_PIN(6, "SERIQ"),
71 PINCTRL_PIN(7, "PIRQAB"),
72 PINCTRL_PIN(8, "CLKRUNB"),
73 PINCTRL_PIN(9, "CLKOUT_LPC_0"),
74 PINCTRL_PIN(10, "CLKOUT_LPC_1"),
75 PINCTRL_PIN(11, "PMEB"),
76 PINCTRL_PIN(12, "BM_BUSYB"),
77 PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
78 PINCTRL_PIN(14, "SUS_STATB"),
79 PINCTRL_PIN(15, "SUSACKB"),
80 PINCTRL_PIN(16, "SD_1P8_SEL"),
81 PINCTRL_PIN(17, "SD_PWR_EN_B"),
82 PINCTRL_PIN(18, "ISH_GP_0"),
83 PINCTRL_PIN(19, "ISH_GP_1"),
84 PINCTRL_PIN(20, "ISH_GP_2"),
85 PINCTRL_PIN(21, "ISH_GP_3"),
86 PINCTRL_PIN(22, "ISH_GP_4"),
87 PINCTRL_PIN(23, "ISH_GP_5"),
88
89 PINCTRL_PIN(24, "CORE_VID_0"),
90 PINCTRL_PIN(25, "CORE_VID_1"),
91 PINCTRL_PIN(26, "VRALERTB"),
92 PINCTRL_PIN(27, "CPU_GP_2"),
93 PINCTRL_PIN(28, "CPU_GP_3"),
94 PINCTRL_PIN(29, "SRCCLKREQB_0"),
95 PINCTRL_PIN(30, "SRCCLKREQB_1"),
96 PINCTRL_PIN(31, "SRCCLKREQB_2"),
97 PINCTRL_PIN(32, "SRCCLKREQB_3"),
98 PINCTRL_PIN(33, "SRCCLKREQB_4"),
99 PINCTRL_PIN(34, "SRCCLKREQB_5"),
100 PINCTRL_PIN(35, "EXT_PWR_GATEB"),
101 PINCTRL_PIN(36, "SLP_S0B"),
102 PINCTRL_PIN(37, "PLTRSTB"),
103 PINCTRL_PIN(38, "SPKR"),
104 PINCTRL_PIN(39, "GSPI0_CSB"),
105 PINCTRL_PIN(40, "GSPI0_CLK"),
106 PINCTRL_PIN(41, "GSPI0_MISO"),
107 PINCTRL_PIN(42, "GSPI0_MOSI"),
108 PINCTRL_PIN(43, "GSPI1_CSB"),
109 PINCTRL_PIN(44, "GSPI1_CLK"),
110 PINCTRL_PIN(45, "GSPI1_MISO"),
111 PINCTRL_PIN(46, "GSPI1_MOSI"),
112 PINCTRL_PIN(47, "SML1ALERTB"),
113
114 PINCTRL_PIN(48, "SMBCLK"),
115 PINCTRL_PIN(49, "SMBDATA"),
116 PINCTRL_PIN(50, "SMBALERTB"),
117 PINCTRL_PIN(51, "SML0CLK"),
118 PINCTRL_PIN(52, "SML0DATA"),
119 PINCTRL_PIN(53, "SML0ALERTB"),
120 PINCTRL_PIN(54, "SML1CLK"),
121 PINCTRL_PIN(55, "SML1DATA"),
122 PINCTRL_PIN(56, "UART0_RXD"),
123 PINCTRL_PIN(57, "UART0_TXD"),
124 PINCTRL_PIN(58, "UART0_RTSB"),
125 PINCTRL_PIN(59, "UART0_CTSB"),
126 PINCTRL_PIN(60, "UART1_RXD"),
127 PINCTRL_PIN(61, "UART1_TXD"),
128 PINCTRL_PIN(62, "UART1_RTSB"),
129 PINCTRL_PIN(63, "UART1_CTSB"),
130 PINCTRL_PIN(64, "I2C0_SDA"),
131 PINCTRL_PIN(65, "I2C0_SCL"),
132 PINCTRL_PIN(66, "I2C1_SDA"),
133 PINCTRL_PIN(67, "I2C1_SCL"),
134 PINCTRL_PIN(68, "UART2_RXD"),
135 PINCTRL_PIN(69, "UART2_TXD"),
136 PINCTRL_PIN(70, "UART2_RTSB"),
137 PINCTRL_PIN(71, "UART2_CTSB"),
138
139 PINCTRL_PIN(72, "SPI1_CSB"),
140 PINCTRL_PIN(73, "SPI1_CLK"),
141 PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
142 PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
143 PINCTRL_PIN(76, "FLASHTRIG"),
144 PINCTRL_PIN(77, "ISH_I2C0_SDA"),
145 PINCTRL_PIN(78, "ISH_I2C0_SCL"),
146 PINCTRL_PIN(79, "ISH_I2C1_SDA"),
147 PINCTRL_PIN(80, "ISH_I2C1_SCL"),
148 PINCTRL_PIN(81, "ISH_SPI_CSB"),
149 PINCTRL_PIN(82, "ISH_SPI_CLK"),
150 PINCTRL_PIN(83, "ISH_SPI_MISO"),
151 PINCTRL_PIN(84, "ISH_SPI_MOSI"),
152 PINCTRL_PIN(85, "ISH_UART0_RXD"),
153 PINCTRL_PIN(86, "ISH_UART0_TXD"),
154 PINCTRL_PIN(87, "ISH_UART0_RTSB"),
155 PINCTRL_PIN(88, "ISH_UART0_CTSB"),
156 PINCTRL_PIN(89, "DMIC_CLK_1"),
157 PINCTRL_PIN(90, "DMIC_DATA_1"),
158 PINCTRL_PIN(91, "DMIC_CLK_0"),
159 PINCTRL_PIN(92, "DMIC_DATA_0"),
160 PINCTRL_PIN(93, "SPI1_IO_2"),
161 PINCTRL_PIN(94, "SPI1_IO_3"),
162 PINCTRL_PIN(95, "SSP_MCLK"),
163
164 PINCTRL_PIN(96, "SATAXPCIE_0"),
165 PINCTRL_PIN(97, "SATAXPCIE_1"),
166 PINCTRL_PIN(98, "SATAXPCIE_2"),
167 PINCTRL_PIN(99, "CPU_GP_0"),
168 PINCTRL_PIN(100, "SATA_DEVSLP_0"),
169 PINCTRL_PIN(101, "SATA_DEVSLP_1"),
170 PINCTRL_PIN(102, "SATA_DEVSLP_2"),
171 PINCTRL_PIN(103, "CPU_GP_1"),
172 PINCTRL_PIN(104, "SATA_LEDB"),
173 PINCTRL_PIN(105, "USB2_OCB_0"),
174 PINCTRL_PIN(106, "USB2_OCB_1"),
175 PINCTRL_PIN(107, "USB2_OCB_2"),
176 PINCTRL_PIN(108, "USB2_OCB_3"),
177 PINCTRL_PIN(109, "DDSP_HPD_0"),
178 PINCTRL_PIN(110, "DDSP_HPD_1"),
179 PINCTRL_PIN(111, "DDSP_HPD_2"),
180 PINCTRL_PIN(112, "DDSP_HPD_3"),
181 PINCTRL_PIN(113, "EDP_HPD"),
182 PINCTRL_PIN(114, "DDPB_CTRLCLK"),
183 PINCTRL_PIN(115, "DDPB_CTRLDATA"),
184 PINCTRL_PIN(116, "DDPC_CTRLCLK"),
185 PINCTRL_PIN(117, "DDPC_CTRLDATA"),
186 PINCTRL_PIN(118, "DDPD_CTRLCLK"),
187 PINCTRL_PIN(119, "DDPD_CTRLDATA"),
188
189 PINCTRL_PIN(120, "SSP2_SCLK"),
190 PINCTRL_PIN(121, "SSP2_SFRM"),
191 PINCTRL_PIN(122, "SSP2_TXD"),
192 PINCTRL_PIN(123, "SSP2_RXD"),
193 PINCTRL_PIN(124, "I2C2_SDA"),
194 PINCTRL_PIN(125, "I2C2_SCL"),
195 PINCTRL_PIN(126, "I2C3_SDA"),
196 PINCTRL_PIN(127, "I2C3_SCL"),
197 PINCTRL_PIN(128, "I2C4_SDA"),
198 PINCTRL_PIN(129, "I2C4_SCL"),
199 PINCTRL_PIN(130, "I2C5_SDA"),
200 PINCTRL_PIN(131, "I2C5_SCL"),
201 PINCTRL_PIN(132, "EMMC_CMD"),
202 PINCTRL_PIN(133, "EMMC_DATA_0"),
203 PINCTRL_PIN(134, "EMMC_DATA_1"),
204 PINCTRL_PIN(135, "EMMC_DATA_2"),
205 PINCTRL_PIN(136, "EMMC_DATA_3"),
206 PINCTRL_PIN(137, "EMMC_DATA_4"),
207 PINCTRL_PIN(138, "EMMC_DATA_5"),
208 PINCTRL_PIN(139, "EMMC_DATA_6"),
209 PINCTRL_PIN(140, "EMMC_DATA_7"),
210 PINCTRL_PIN(141, "EMMC_RCLK"),
211 PINCTRL_PIN(142, "EMMC_CLK"),
212 PINCTRL_PIN(143, "GPP_F_23"),
213
214 PINCTRL_PIN(144, "SD_CMD"),
215 PINCTRL_PIN(145, "SD_DATA_0"),
216 PINCTRL_PIN(146, "SD_DATA_1"),
217 PINCTRL_PIN(147, "SD_DATA_2"),
218 PINCTRL_PIN(148, "SD_DATA_3"),
219 PINCTRL_PIN(149, "SD_CDB"),
220 PINCTRL_PIN(150, "SD_CLK"),
221 PINCTRL_PIN(151, "SD_WP"),
222 };
223
224 static const unsigned sptlp_spi0_pins[] = { 39, 40, 41, 42 };
225 static const unsigned sptlp_spi1_pins[] = { 43, 44, 45, 46 };
226 static const unsigned sptlp_uart0_pins[] = { 56, 57, 58, 59 };
227 static const unsigned sptlp_uart1_pins[] = { 60, 61, 62, 63 };
228 static const unsigned sptlp_uart2_pins[] = { 68, 69, 71, 71 };
229 static const unsigned sptlp_i2c0_pins[] = { 64, 65 };
230 static const unsigned sptlp_i2c1_pins[] = { 66, 67 };
231 static const unsigned sptlp_i2c2_pins[] = { 124, 125 };
232 static const unsigned sptlp_i2c3_pins[] = { 126, 127 };
233 static const unsigned sptlp_i2c4_pins[] = { 128, 129 };
234 static const unsigned sptlp_i2c4b_pins[] = { 85, 86 };
235 static const unsigned sptlp_i2c5_pins[] = { 130, 131 };
236 static const unsigned sptlp_ssp2_pins[] = { 120, 121, 122, 123 };
237 static const unsigned sptlp_emmc_pins[] = {
238 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142,
239 };
240 static const unsigned sptlp_sd_pins[] = {
241 144, 145, 146, 147, 148, 149, 150, 151,
242 };
243
244 static const struct intel_pingroup sptlp_groups[] = {
245 PIN_GROUP("spi0_grp", sptlp_spi0_pins, 1),
246 PIN_GROUP("spi1_grp", sptlp_spi1_pins, 1),
247 PIN_GROUP("uart0_grp", sptlp_uart0_pins, 1),
248 PIN_GROUP("uart1_grp", sptlp_uart1_pins, 1),
249 PIN_GROUP("uart2_grp", sptlp_uart2_pins, 1),
250 PIN_GROUP("i2c0_grp", sptlp_i2c0_pins, 1),
251 PIN_GROUP("i2c1_grp", sptlp_i2c1_pins, 1),
252 PIN_GROUP("i2c2_grp", sptlp_i2c2_pins, 1),
253 PIN_GROUP("i2c3_grp", sptlp_i2c3_pins, 1),
254 PIN_GROUP("i2c4_grp", sptlp_i2c4_pins, 1),
255 PIN_GROUP("i2c4b_grp", sptlp_i2c4b_pins, 3),
256 PIN_GROUP("i2c5_grp", sptlp_i2c5_pins, 1),
257 PIN_GROUP("ssp2_grp", sptlp_ssp2_pins, 1),
258 PIN_GROUP("emmc_grp", sptlp_emmc_pins, 1),
259 PIN_GROUP("sd_grp", sptlp_sd_pins, 1),
260 };
261
262 static const char * const sptlp_spi0_groups[] = { "spi0_grp" };
263 static const char * const sptlp_spi1_groups[] = { "spi0_grp" };
264 static const char * const sptlp_uart0_groups[] = { "uart0_grp" };
265 static const char * const sptlp_uart1_groups[] = { "uart1_grp" };
266 static const char * const sptlp_uart2_groups[] = { "uart2_grp" };
267 static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" };
268 static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" };
269 static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" };
270 static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" };
271 static const char * const sptlp_i2c4_groups[] = { "i2c4_grp", "i2c4b_grp" };
272 static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" };
273 static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" };
274 static const char * const sptlp_emmc_groups[] = { "emmc_grp" };
275 static const char * const sptlp_sd_groups[] = { "sd_grp" };
276
277 static const struct intel_function sptlp_functions[] = {
278 FUNCTION("spi0", sptlp_spi0_groups),
279 FUNCTION("spi1", sptlp_spi1_groups),
280 FUNCTION("uart0", sptlp_uart0_groups),
281 FUNCTION("uart1", sptlp_uart1_groups),
282 FUNCTION("uart2", sptlp_uart2_groups),
283 FUNCTION("i2c0", sptlp_i2c0_groups),
284 FUNCTION("i2c1", sptlp_i2c1_groups),
285 FUNCTION("i2c2", sptlp_i2c2_groups),
286 FUNCTION("i2c3", sptlp_i2c3_groups),
287 FUNCTION("i2c4", sptlp_i2c4_groups),
288 FUNCTION("i2c5", sptlp_i2c5_groups),
289 FUNCTION("ssp2", sptlp_ssp2_groups),
290 FUNCTION("emmc", sptlp_emmc_groups),
291 FUNCTION("sd", sptlp_sd_groups),
292 };
293
294 static const struct intel_community sptlp_communities[] = {
295 SPT_COMMUNITY(0, 0, 47),
296 SPT_COMMUNITY(1, 48, 119),
297 SPT_COMMUNITY(2, 120, 151),
298 };
299
300 static const struct intel_pinctrl_soc_data sptlp_soc_data = {
301 .pins = sptlp_pins,
302 .npins = ARRAY_SIZE(sptlp_pins),
303 .groups = sptlp_groups,
304 .ngroups = ARRAY_SIZE(sptlp_groups),
305 .functions = sptlp_functions,
306 .nfunctions = ARRAY_SIZE(sptlp_functions),
307 .communities = sptlp_communities,
308 .ncommunities = ARRAY_SIZE(sptlp_communities),
309 };
310
311
312 static const struct pinctrl_pin_desc spth_pins[] = {
313
314 PINCTRL_PIN(0, "RCINB"),
315 PINCTRL_PIN(1, "LAD_0"),
316 PINCTRL_PIN(2, "LAD_1"),
317 PINCTRL_PIN(3, "LAD_2"),
318 PINCTRL_PIN(4, "LAD_3"),
319 PINCTRL_PIN(5, "LFRAMEB"),
320 PINCTRL_PIN(6, "SERIQ"),
321 PINCTRL_PIN(7, "PIRQAB"),
322 PINCTRL_PIN(8, "CLKRUNB"),
323 PINCTRL_PIN(9, "CLKOUT_LPC_0"),
324 PINCTRL_PIN(10, "CLKOUT_LPC_1"),
325 PINCTRL_PIN(11, "PMEB"),
326 PINCTRL_PIN(12, "BM_BUSYB"),
327 PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
328 PINCTRL_PIN(14, "SUS_STATB"),
329 PINCTRL_PIN(15, "SUSACKB"),
330 PINCTRL_PIN(16, "CLKOUT_48"),
331 PINCTRL_PIN(17, "ISH_GP_7"),
332 PINCTRL_PIN(18, "ISH_GP_0"),
333 PINCTRL_PIN(19, "ISH_GP_1"),
334 PINCTRL_PIN(20, "ISH_GP_2"),
335 PINCTRL_PIN(21, "ISH_GP_3"),
336 PINCTRL_PIN(22, "ISH_GP_4"),
337 PINCTRL_PIN(23, "ISH_GP_5"),
338
339 PINCTRL_PIN(24, "CORE_VID_0"),
340 PINCTRL_PIN(25, "CORE_VID_1"),
341 PINCTRL_PIN(26, "VRALERTB"),
342 PINCTRL_PIN(27, "CPU_GP_2"),
343 PINCTRL_PIN(28, "CPU_GP_3"),
344 PINCTRL_PIN(29, "SRCCLKREQB_0"),
345 PINCTRL_PIN(30, "SRCCLKREQB_1"),
346 PINCTRL_PIN(31, "SRCCLKREQB_2"),
347 PINCTRL_PIN(32, "SRCCLKREQB_3"),
348 PINCTRL_PIN(33, "SRCCLKREQB_4"),
349 PINCTRL_PIN(34, "SRCCLKREQB_5"),
350 PINCTRL_PIN(35, "EXT_PWR_GATEB"),
351 PINCTRL_PIN(36, "SLP_S0B"),
352 PINCTRL_PIN(37, "PLTRSTB"),
353 PINCTRL_PIN(38, "SPKR"),
354 PINCTRL_PIN(39, "GSPI0_CSB"),
355 PINCTRL_PIN(40, "GSPI0_CLK"),
356 PINCTRL_PIN(41, "GSPI0_MISO"),
357 PINCTRL_PIN(42, "GSPI0_MOSI"),
358 PINCTRL_PIN(43, "GSPI1_CSB"),
359 PINCTRL_PIN(44, "GSPI1_CLK"),
360 PINCTRL_PIN(45, "GSPI1_MISO"),
361 PINCTRL_PIN(46, "GSPI1_MOSI"),
362 PINCTRL_PIN(47, "SML1ALERTB"),
363
364 PINCTRL_PIN(48, "SMBCLK"),
365 PINCTRL_PIN(49, "SMBDATA"),
366 PINCTRL_PIN(50, "SMBALERTB"),
367 PINCTRL_PIN(51, "SML0CLK"),
368 PINCTRL_PIN(52, "SML0DATA"),
369 PINCTRL_PIN(53, "SML0ALERTB"),
370 PINCTRL_PIN(54, "SML1CLK"),
371 PINCTRL_PIN(55, "SML1DATA"),
372 PINCTRL_PIN(56, "UART0_RXD"),
373 PINCTRL_PIN(57, "UART0_TXD"),
374 PINCTRL_PIN(58, "UART0_RTSB"),
375 PINCTRL_PIN(59, "UART0_CTSB"),
376 PINCTRL_PIN(60, "UART1_RXD"),
377 PINCTRL_PIN(61, "UART1_TXD"),
378 PINCTRL_PIN(62, "UART1_RTSB"),
379 PINCTRL_PIN(63, "UART1_CTSB"),
380 PINCTRL_PIN(64, "I2C0_SDA"),
381 PINCTRL_PIN(65, "I2C0_SCL"),
382 PINCTRL_PIN(66, "I2C1_SDA"),
383 PINCTRL_PIN(67, "I2C1_SCL"),
384 PINCTRL_PIN(68, "UART2_RXD"),
385 PINCTRL_PIN(69, "UART2_TXD"),
386 PINCTRL_PIN(70, "UART2_RTSB"),
387 PINCTRL_PIN(71, "UART2_CTSB"),
388
389 PINCTRL_PIN(72, "SPI1_CSB"),
390 PINCTRL_PIN(73, "SPI1_CLK"),
391 PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
392 PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
393 PINCTRL_PIN(76, "ISH_I2C2_SDA"),
394 PINCTRL_PIN(77, "SSP0_SFRM"),
395 PINCTRL_PIN(78, "SSP0_TXD"),
396 PINCTRL_PIN(79, "SSP0_RXD"),
397 PINCTRL_PIN(80, "SSP0_SCLK"),
398 PINCTRL_PIN(81, "ISH_SPI_CSB"),
399 PINCTRL_PIN(82, "ISH_SPI_CLK"),
400 PINCTRL_PIN(83, "ISH_SPI_MISO"),
401 PINCTRL_PIN(84, "ISH_SPI_MOSI"),
402 PINCTRL_PIN(85, "ISH_UART0_RXD"),
403 PINCTRL_PIN(86, "ISH_UART0_TXD"),
404 PINCTRL_PIN(87, "ISH_UART0_RTSB"),
405 PINCTRL_PIN(88, "ISH_UART0_CTSB"),
406 PINCTRL_PIN(89, "DMIC_CLK_1"),
407 PINCTRL_PIN(90, "DMIC_DATA_1"),
408 PINCTRL_PIN(91, "DMIC_CLK_0"),
409 PINCTRL_PIN(92, "DMIC_DATA_0"),
410 PINCTRL_PIN(93, "SPI1_IO_2"),
411 PINCTRL_PIN(94, "SPI1_IO_3"),
412 PINCTRL_PIN(95, "ISH_I2C2_SCL"),
413
414 PINCTRL_PIN(96, "SATAXPCIE_0"),
415 PINCTRL_PIN(97, "SATAXPCIE_1"),
416 PINCTRL_PIN(98, "SATAXPCIE_2"),
417 PINCTRL_PIN(99, "CPU_GP_0"),
418 PINCTRL_PIN(100, "SATA_DEVSLP_0"),
419 PINCTRL_PIN(101, "SATA_DEVSLP_1"),
420 PINCTRL_PIN(102, "SATA_DEVSLP_2"),
421 PINCTRL_PIN(103, "CPU_GP_1"),
422 PINCTRL_PIN(104, "SATA_LEDB"),
423 PINCTRL_PIN(105, "USB2_OCB_0"),
424 PINCTRL_PIN(106, "USB2_OCB_1"),
425 PINCTRL_PIN(107, "USB2_OCB_2"),
426 PINCTRL_PIN(108, "USB2_OCB_3"),
427
428 PINCTRL_PIN(109, "SATAXPCIE_3"),
429 PINCTRL_PIN(110, "SATAXPCIE_4"),
430 PINCTRL_PIN(111, "SATAXPCIE_5"),
431 PINCTRL_PIN(112, "SATAXPCIE_6"),
432 PINCTRL_PIN(113, "SATAXPCIE_7"),
433 PINCTRL_PIN(114, "SATA_DEVSLP_3"),
434 PINCTRL_PIN(115, "SATA_DEVSLP_4"),
435 PINCTRL_PIN(116, "SATA_DEVSLP_5"),
436 PINCTRL_PIN(117, "SATA_DEVSLP_6"),
437 PINCTRL_PIN(118, "SATA_DEVSLP_7"),
438 PINCTRL_PIN(119, "SATA_SCLOCK"),
439 PINCTRL_PIN(120, "SATA_SLOAD"),
440 PINCTRL_PIN(121, "SATA_SDATAOUT1"),
441 PINCTRL_PIN(122, "SATA_SDATAOUT0"),
442 PINCTRL_PIN(123, "GPP_F_14"),
443 PINCTRL_PIN(124, "USB_OCB_4"),
444 PINCTRL_PIN(125, "USB_OCB_5"),
445 PINCTRL_PIN(126, "USB_OCB_6"),
446 PINCTRL_PIN(127, "USB_OCB_7"),
447 PINCTRL_PIN(128, "L_VDDEN"),
448 PINCTRL_PIN(129, "L_BKLTEN"),
449 PINCTRL_PIN(130, "L_BKLTCTL"),
450 PINCTRL_PIN(131, "GPP_F_22"),
451 PINCTRL_PIN(132, "GPP_F_23"),
452
453 PINCTRL_PIN(133, "FAN_TACH_0"),
454 PINCTRL_PIN(134, "FAN_TACH_1"),
455 PINCTRL_PIN(135, "FAN_TACH_2"),
456 PINCTRL_PIN(136, "FAN_TACH_3"),
457 PINCTRL_PIN(137, "FAN_TACH_4"),
458 PINCTRL_PIN(138, "FAN_TACH_5"),
459 PINCTRL_PIN(139, "FAN_TACH_6"),
460 PINCTRL_PIN(140, "FAN_TACH_7"),
461 PINCTRL_PIN(141, "FAN_PWM_0"),
462 PINCTRL_PIN(142, "FAN_PWM_1"),
463 PINCTRL_PIN(143, "FAN_PWM_2"),
464 PINCTRL_PIN(144, "FAN_PWM_3"),
465 PINCTRL_PIN(145, "GSXDOUT"),
466 PINCTRL_PIN(146, "GSXSLOAD"),
467 PINCTRL_PIN(147, "GSXDIN"),
468 PINCTRL_PIN(148, "GSXRESETB"),
469 PINCTRL_PIN(149, "GSXCLK"),
470 PINCTRL_PIN(150, "ADR_COMPLETE"),
471 PINCTRL_PIN(151, "NMIB"),
472 PINCTRL_PIN(152, "SMIB"),
473 PINCTRL_PIN(153, "GPP_G_20"),
474 PINCTRL_PIN(154, "GPP_G_21"),
475 PINCTRL_PIN(155, "GPP_G_22"),
476 PINCTRL_PIN(156, "GPP_G_23"),
477
478 PINCTRL_PIN(157, "SRCCLKREQB_6"),
479 PINCTRL_PIN(158, "SRCCLKREQB_7"),
480 PINCTRL_PIN(159, "SRCCLKREQB_8"),
481 PINCTRL_PIN(160, "SRCCLKREQB_9"),
482 PINCTRL_PIN(161, "SRCCLKREQB_10"),
483 PINCTRL_PIN(162, "SRCCLKREQB_11"),
484 PINCTRL_PIN(163, "SRCCLKREQB_12"),
485 PINCTRL_PIN(164, "SRCCLKREQB_13"),
486 PINCTRL_PIN(165, "SRCCLKREQB_14"),
487 PINCTRL_PIN(166, "SRCCLKREQB_15"),
488 PINCTRL_PIN(167, "SML2CLK"),
489 PINCTRL_PIN(168, "SML2DATA"),
490 PINCTRL_PIN(169, "SML2ALERTB"),
491 PINCTRL_PIN(170, "SML3CLK"),
492 PINCTRL_PIN(171, "SML3DATA"),
493 PINCTRL_PIN(172, "SML3ALERTB"),
494 PINCTRL_PIN(173, "SML4CLK"),
495 PINCTRL_PIN(174, "SML4DATA"),
496 PINCTRL_PIN(175, "SML4ALERTB"),
497 PINCTRL_PIN(176, "ISH_I2C0_SDA"),
498 PINCTRL_PIN(177, "ISH_I2C0_SCL"),
499 PINCTRL_PIN(178, "ISH_I2C1_SDA"),
500 PINCTRL_PIN(179, "ISH_I2C1_SCL"),
501 PINCTRL_PIN(180, "GPP_H_23"),
502
503 PINCTRL_PIN(181, "DDSP_HDP_0"),
504 PINCTRL_PIN(182, "DDSP_HDP_1"),
505 PINCTRL_PIN(183, "DDSP_HDP_2"),
506 PINCTRL_PIN(184, "DDSP_HDP_3"),
507 PINCTRL_PIN(185, "EDP_HPD"),
508 PINCTRL_PIN(186, "DDPB_CTRLCLK"),
509 PINCTRL_PIN(187, "DDPB_CTRLDATA"),
510 PINCTRL_PIN(188, "DDPC_CTRLCLK"),
511 PINCTRL_PIN(189, "DDPC_CTRLDATA"),
512 PINCTRL_PIN(190, "DDPD_CTRLCLK"),
513 PINCTRL_PIN(191, "DDPD_CTRLDATA"),
514 };
515
516 static const unsigned spth_spi0_pins[] = { 39, 40, 41, 42 };
517 static const unsigned spth_spi1_pins[] = { 43, 44, 45, 46 };
518 static const unsigned spth_uart0_pins[] = { 56, 57, 58, 59 };
519 static const unsigned spth_uart1_pins[] = { 60, 61, 62, 63 };
520 static const unsigned spth_uart2_pins[] = { 68, 69, 71, 71 };
521 static const unsigned spth_i2c0_pins[] = { 64, 65 };
522 static const unsigned spth_i2c1_pins[] = { 66, 67 };
523 static const unsigned spth_i2c2_pins[] = { 76, 95 };
524
525 static const struct intel_pingroup spth_groups[] = {
526 PIN_GROUP("spi0_grp", spth_spi0_pins, 1),
527 PIN_GROUP("spi1_grp", spth_spi1_pins, 1),
528 PIN_GROUP("uart0_grp", spth_uart0_pins, 1),
529 PIN_GROUP("uart1_grp", spth_uart1_pins, 1),
530 PIN_GROUP("uart2_grp", spth_uart2_pins, 1),
531 PIN_GROUP("i2c0_grp", spth_i2c0_pins, 1),
532 PIN_GROUP("i2c1_grp", spth_i2c1_pins, 1),
533 PIN_GROUP("i2c2_grp", spth_i2c2_pins, 2),
534 };
535
536 static const char * const spth_spi0_groups[] = { "spi0_grp" };
537 static const char * const spth_spi1_groups[] = { "spi0_grp" };
538 static const char * const spth_uart0_groups[] = { "uart0_grp" };
539 static const char * const spth_uart1_groups[] = { "uart1_grp" };
540 static const char * const spth_uart2_groups[] = { "uart2_grp" };
541 static const char * const spth_i2c0_groups[] = { "i2c0_grp" };
542 static const char * const spth_i2c1_groups[] = { "i2c1_grp" };
543 static const char * const spth_i2c2_groups[] = { "i2c2_grp" };
544
545 static const struct intel_function spth_functions[] = {
546 FUNCTION("spi0", spth_spi0_groups),
547 FUNCTION("spi1", spth_spi1_groups),
548 FUNCTION("uart0", spth_uart0_groups),
549 FUNCTION("uart1", spth_uart1_groups),
550 FUNCTION("uart2", spth_uart2_groups),
551 FUNCTION("i2c0", spth_i2c0_groups),
552 FUNCTION("i2c1", spth_i2c1_groups),
553 FUNCTION("i2c2", spth_i2c2_groups),
554 };
555
556 static const struct intel_padgroup spth_community0_gpps[] = {
557 SPTH_GPP(0, 0, 23, 0),
558 SPTH_GPP(1, 24, 47, 24),
559 };
560
561 static const struct intel_padgroup spth_community1_gpps[] = {
562 SPTH_GPP(0, 48, 71, 48),
563 SPTH_GPP(1, 72, 95, 72),
564 SPTH_GPP(2, 96, 108, 96),
565 SPTH_GPP(3, 109, 132, 120),
566 SPTH_GPP(4, 133, 156, 144),
567 SPTH_GPP(5, 157, 180, 168),
568 };
569
570 static const struct intel_padgroup spth_community3_gpps[] = {
571 SPTH_GPP(0, 181, 191, 192),
572 };
573
574 static const struct intel_community spth_communities[] = {
575 SPTH_COMMUNITY(0, 0, 47, spth_community0_gpps),
576 SPTH_COMMUNITY(1, 48, 180, spth_community1_gpps),
577 SPTH_COMMUNITY(2, 181, 191, spth_community3_gpps),
578 };
579
580 static const struct intel_pinctrl_soc_data spth_soc_data = {
581 .pins = spth_pins,
582 .npins = ARRAY_SIZE(spth_pins),
583 .groups = spth_groups,
584 .ngroups = ARRAY_SIZE(spth_groups),
585 .functions = spth_functions,
586 .nfunctions = ARRAY_SIZE(spth_functions),
587 .communities = spth_communities,
588 .ncommunities = ARRAY_SIZE(spth_communities),
589 };
590
591 static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
592 { "INT344B", (kernel_ulong_t)&sptlp_soc_data },
593 { "INT345D", (kernel_ulong_t)&spth_soc_data },
594 { }
595 };
596 MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
597
598 static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops);
599
600 static struct platform_driver spt_pinctrl_driver = {
601 .probe = intel_pinctrl_probe_by_hid,
602 .driver = {
603 .name = "sunrisepoint-pinctrl",
604 .acpi_match_table = spt_pinctrl_acpi_match,
605 .pm = &spt_pinctrl_pm_ops,
606 },
607 };
608
609 static int __init spt_pinctrl_init(void)
610 {
611 return platform_driver_register(&spt_pinctrl_driver);
612 }
613 subsys_initcall(spt_pinctrl_init);
614
615 static void __exit spt_pinctrl_exit(void)
616 {
617 platform_driver_unregister(&spt_pinctrl_driver);
618 }
619 module_exit(spt_pinctrl_exit);
620
621 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
622 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
623 MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver");
624 MODULE_LICENSE("GPL v2");