This source file includes following definitions.
- byt_get_community
- byt_gpio_reg
- byt_get_groups_count
- byt_get_group_name
- byt_get_group_pins
- byt_get_functions_count
- byt_get_function_name
- byt_get_function_groups
- byt_set_group_simple_mux
- byt_set_group_mixed_mux
- byt_set_mux
- byt_get_gpio_mux
- byt_gpio_clear_triggering
- byt_gpio_request_enable
- byt_gpio_disable_free
- byt_gpio_set_direction
- byt_get_pull_strength
- byt_set_pull_strength
- byt_pin_config_get
- byt_pin_config_set
- byt_gpio_get
- byt_gpio_set
- byt_gpio_get_direction
- byt_gpio_direction_input
- byt_gpio_direction_output
- byt_gpio_dbg_show
- byt_irq_ack
- byt_irq_mask
- byt_irq_unmask
- byt_irq_type
- byt_gpio_irq_handler
- byt_init_irq_valid_mask
- byt_gpio_irq_init_hw
- byt_gpio_probe
- byt_set_soc_data
- byt_pinctrl_probe
- byt_gpio_suspend
- byt_gpio_resume
- byt_gpio_runtime_suspend
- byt_gpio_runtime_resume
- byt_gpio_init
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9 #include <linux/acpi.h>
10 #include <linux/bitops.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/property.h>
20 #include <linux/seq_file.h>
21
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26
27 #include "pinctrl-intel.h"
28
29
30 #define BYT_CONF0_REG 0x000
31 #define BYT_CONF1_REG 0x004
32 #define BYT_VAL_REG 0x008
33 #define BYT_DFT_REG 0x00c
34 #define BYT_INT_STAT_REG 0x800
35 #define BYT_DEBOUNCE_REG 0x9d0
36
37
38 #define BYT_IODEN BIT(31)
39 #define BYT_DIRECT_IRQ_EN BIT(27)
40 #define BYT_TRIG_MASK GENMASK(26, 24)
41 #define BYT_TRIG_NEG BIT(26)
42 #define BYT_TRIG_POS BIT(25)
43 #define BYT_TRIG_LVL BIT(24)
44 #define BYT_DEBOUNCE_EN BIT(20)
45 #define BYT_GLITCH_FILTER_EN BIT(19)
46 #define BYT_GLITCH_F_SLOW_CLK BIT(17)
47 #define BYT_GLITCH_F_FAST_CLK BIT(16)
48 #define BYT_PULL_STR_SHIFT 9
49 #define BYT_PULL_STR_MASK GENMASK(10, 9)
50 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
51 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
52 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
53 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
54 #define BYT_PULL_ASSIGN_SHIFT 7
55 #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7)
56 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
57 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
58 #define BYT_PIN_MUX GENMASK(2, 0)
59
60
61 #define BYT_DIR_MASK GENMASK(2, 1)
62 #define BYT_INPUT_EN BIT(2)
63 #define BYT_OUTPUT_EN BIT(1)
64 #define BYT_LEVEL BIT(0)
65
66 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
67 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
68
69
70 #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0)
71 #define BYT_DEBOUNCE_PULSE_375US 1
72 #define BYT_DEBOUNCE_PULSE_750US 2
73 #define BYT_DEBOUNCE_PULSE_1500US 3
74 #define BYT_DEBOUNCE_PULSE_3MS 4
75 #define BYT_DEBOUNCE_PULSE_6MS 5
76 #define BYT_DEBOUNCE_PULSE_12MS 6
77 #define BYT_DEBOUNCE_PULSE_24MS 7
78
79 #define BYT_NGPIO_SCORE 102
80 #define BYT_NGPIO_NCORE 28
81 #define BYT_NGPIO_SUS 44
82
83 #define BYT_SCORE_ACPI_UID "1"
84 #define BYT_NCORE_ACPI_UID "2"
85 #define BYT_SUS_ACPI_UID "3"
86
87
88
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90
91
92
93 #define BYT_DEFAULT_GPIO_MUX 0
94 #define BYT_ALTER_GPIO_MUX 1
95
96 struct byt_gpio_pin_context {
97 u32 conf0;
98 u32 val;
99 };
100
101 #define COMMUNITY(p, n, map) \
102 { \
103 .pin_base = (p), \
104 .npins = (n), \
105 .pad_map = (map),\
106 }
107
108 struct byt_gpio {
109 struct gpio_chip chip;
110 struct platform_device *pdev;
111 struct pinctrl_dev *pctl_dev;
112 struct pinctrl_desc pctl_desc;
113 const struct intel_pinctrl_soc_data *soc_data;
114 struct intel_community *communities_copy;
115 struct byt_gpio_pin_context *saved_context;
116 };
117
118
119 static const struct pinctrl_pin_desc byt_score_pins[] = {
120 PINCTRL_PIN(0, "SATA_GP0"),
121 PINCTRL_PIN(1, "SATA_GP1"),
122 PINCTRL_PIN(2, "SATA_LED#"),
123 PINCTRL_PIN(3, "PCIE_CLKREQ0"),
124 PINCTRL_PIN(4, "PCIE_CLKREQ1"),
125 PINCTRL_PIN(5, "PCIE_CLKREQ2"),
126 PINCTRL_PIN(6, "PCIE_CLKREQ3"),
127 PINCTRL_PIN(7, "SD3_WP"),
128 PINCTRL_PIN(8, "HDA_RST"),
129 PINCTRL_PIN(9, "HDA_SYNC"),
130 PINCTRL_PIN(10, "HDA_CLK"),
131 PINCTRL_PIN(11, "HDA_SDO"),
132 PINCTRL_PIN(12, "HDA_SDI0"),
133 PINCTRL_PIN(13, "HDA_SDI1"),
134 PINCTRL_PIN(14, "GPIO_S0_SC14"),
135 PINCTRL_PIN(15, "GPIO_S0_SC15"),
136 PINCTRL_PIN(16, "MMC1_CLK"),
137 PINCTRL_PIN(17, "MMC1_D0"),
138 PINCTRL_PIN(18, "MMC1_D1"),
139 PINCTRL_PIN(19, "MMC1_D2"),
140 PINCTRL_PIN(20, "MMC1_D3"),
141 PINCTRL_PIN(21, "MMC1_D4"),
142 PINCTRL_PIN(22, "MMC1_D5"),
143 PINCTRL_PIN(23, "MMC1_D6"),
144 PINCTRL_PIN(24, "MMC1_D7"),
145 PINCTRL_PIN(25, "MMC1_CMD"),
146 PINCTRL_PIN(26, "MMC1_RST"),
147 PINCTRL_PIN(27, "SD2_CLK"),
148 PINCTRL_PIN(28, "SD2_D0"),
149 PINCTRL_PIN(29, "SD2_D1"),
150 PINCTRL_PIN(30, "SD2_D2"),
151 PINCTRL_PIN(31, "SD2_D3_CD"),
152 PINCTRL_PIN(32, "SD2_CMD"),
153 PINCTRL_PIN(33, "SD3_CLK"),
154 PINCTRL_PIN(34, "SD3_D0"),
155 PINCTRL_PIN(35, "SD3_D1"),
156 PINCTRL_PIN(36, "SD3_D2"),
157 PINCTRL_PIN(37, "SD3_D3"),
158 PINCTRL_PIN(38, "SD3_CD"),
159 PINCTRL_PIN(39, "SD3_CMD"),
160 PINCTRL_PIN(40, "SD3_1P8EN"),
161 PINCTRL_PIN(41, "SD3_PWREN#"),
162 PINCTRL_PIN(42, "ILB_LPC_AD0"),
163 PINCTRL_PIN(43, "ILB_LPC_AD1"),
164 PINCTRL_PIN(44, "ILB_LPC_AD2"),
165 PINCTRL_PIN(45, "ILB_LPC_AD3"),
166 PINCTRL_PIN(46, "ILB_LPC_FRAME"),
167 PINCTRL_PIN(47, "ILB_LPC_CLK0"),
168 PINCTRL_PIN(48, "ILB_LPC_CLK1"),
169 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
170 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
171 PINCTRL_PIN(51, "PCU_SMB_DATA"),
172 PINCTRL_PIN(52, "PCU_SMB_CLK"),
173 PINCTRL_PIN(53, "PCU_SMB_ALERT"),
174 PINCTRL_PIN(54, "ILB_8254_SPKR"),
175 PINCTRL_PIN(55, "GPIO_S0_SC55"),
176 PINCTRL_PIN(56, "GPIO_S0_SC56"),
177 PINCTRL_PIN(57, "GPIO_S0_SC57"),
178 PINCTRL_PIN(58, "GPIO_S0_SC58"),
179 PINCTRL_PIN(59, "GPIO_S0_SC59"),
180 PINCTRL_PIN(60, "GPIO_S0_SC60"),
181 PINCTRL_PIN(61, "GPIO_S0_SC61"),
182 PINCTRL_PIN(62, "LPE_I2S2_CLK"),
183 PINCTRL_PIN(63, "LPE_I2S2_FRM"),
184 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
185 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
186 PINCTRL_PIN(66, "SIO_SPI_CS"),
187 PINCTRL_PIN(67, "SIO_SPI_MISO"),
188 PINCTRL_PIN(68, "SIO_SPI_MOSI"),
189 PINCTRL_PIN(69, "SIO_SPI_CLK"),
190 PINCTRL_PIN(70, "SIO_UART1_RXD"),
191 PINCTRL_PIN(71, "SIO_UART1_TXD"),
192 PINCTRL_PIN(72, "SIO_UART1_RTS"),
193 PINCTRL_PIN(73, "SIO_UART1_CTS"),
194 PINCTRL_PIN(74, "SIO_UART2_RXD"),
195 PINCTRL_PIN(75, "SIO_UART2_TXD"),
196 PINCTRL_PIN(76, "SIO_UART2_RTS"),
197 PINCTRL_PIN(77, "SIO_UART2_CTS"),
198 PINCTRL_PIN(78, "SIO_I2C0_DATA"),
199 PINCTRL_PIN(79, "SIO_I2C0_CLK"),
200 PINCTRL_PIN(80, "SIO_I2C1_DATA"),
201 PINCTRL_PIN(81, "SIO_I2C1_CLK"),
202 PINCTRL_PIN(82, "SIO_I2C2_DATA"),
203 PINCTRL_PIN(83, "SIO_I2C2_CLK"),
204 PINCTRL_PIN(84, "SIO_I2C3_DATA"),
205 PINCTRL_PIN(85, "SIO_I2C3_CLK"),
206 PINCTRL_PIN(86, "SIO_I2C4_DATA"),
207 PINCTRL_PIN(87, "SIO_I2C4_CLK"),
208 PINCTRL_PIN(88, "SIO_I2C5_DATA"),
209 PINCTRL_PIN(89, "SIO_I2C5_CLK"),
210 PINCTRL_PIN(90, "SIO_I2C6_DATA"),
211 PINCTRL_PIN(91, "SIO_I2C6_CLK"),
212 PINCTRL_PIN(92, "GPIO_S0_SC92"),
213 PINCTRL_PIN(93, "GPIO_S0_SC93"),
214 PINCTRL_PIN(94, "SIO_PWM0"),
215 PINCTRL_PIN(95, "SIO_PWM1"),
216 PINCTRL_PIN(96, "PMC_PLT_CLK0"),
217 PINCTRL_PIN(97, "PMC_PLT_CLK1"),
218 PINCTRL_PIN(98, "PMC_PLT_CLK2"),
219 PINCTRL_PIN(99, "PMC_PLT_CLK3"),
220 PINCTRL_PIN(100, "PMC_PLT_CLK4"),
221 PINCTRL_PIN(101, "PMC_PLT_CLK5"),
222 };
223
224 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
225 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
226 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
227 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
228 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
229 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
230 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
231 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
232 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
233 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
234 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
235 97, 100,
236 };
237
238
239 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
240 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
241
242 static const unsigned int byt_score_pwm0_pins[] = { 94 };
243 static const unsigned int byt_score_pwm1_pins[] = { 95 };
244
245 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
246
247 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
248 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
249 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
250 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
251 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
252 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
253 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
254
255 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
256 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
257 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
258
259 static const unsigned int byt_score_sdcard_pins[] = {
260 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
261 };
262 static const unsigned int byt_score_sdcard_mux_values[] = {
263 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
264 };
265
266 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
267
268 static const unsigned int byt_score_emmc_pins[] = {
269 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
270 };
271
272 static const unsigned int byt_score_ilb_lpc_pins[] = {
273 42, 43, 44, 45, 46, 47, 48, 49, 50,
274 };
275
276 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
277
278 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
279 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
280 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
281 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
282 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
283 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
284
285 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
286
287 static const struct intel_pingroup byt_score_groups[] = {
288 PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
289 PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
290 PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
291 PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
292 PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
293 PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
294 PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
295 PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
296 PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
297 PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
298 PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
299 PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
300 PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
301 PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
302 PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
303 PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
304 PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
305 PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
306 PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
307 PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
308 PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
309 PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
310 PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
311 PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
312 PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
313 PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
314 PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
315 };
316
317 static const char * const byt_score_uart_groups[] = {
318 "uart1_grp", "uart2_grp",
319 };
320 static const char * const byt_score_pwm_groups[] = {
321 "pwm0_grp", "pwm1_grp",
322 };
323 static const char * const byt_score_ssp_groups[] = {
324 "ssp0_grp", "ssp1_grp", "ssp2_grp",
325 };
326 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
327 static const char * const byt_score_i2c_groups[] = {
328 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
329 "i2c6_grp",
330 };
331 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
332 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
333 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
334 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
335 static const char * const byt_score_sata_groups[] = { "sata_grp" };
336 static const char * const byt_score_plt_clk_groups[] = {
337 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
338 "plt_clk4_grp", "plt_clk5_grp",
339 };
340 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
341 static const char * const byt_score_gpio_groups[] = {
342 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
343 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
344 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
345 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
346 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
347 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
348 };
349
350 static const struct intel_function byt_score_functions[] = {
351 FUNCTION("uart", byt_score_uart_groups),
352 FUNCTION("pwm", byt_score_pwm_groups),
353 FUNCTION("ssp", byt_score_ssp_groups),
354 FUNCTION("spi", byt_score_spi_groups),
355 FUNCTION("i2c", byt_score_i2c_groups),
356 FUNCTION("sdcard", byt_score_sdcard_groups),
357 FUNCTION("sdio", byt_score_sdio_groups),
358 FUNCTION("emmc", byt_score_emmc_groups),
359 FUNCTION("lpc", byt_score_lpc_groups),
360 FUNCTION("sata", byt_score_sata_groups),
361 FUNCTION("plt_clk", byt_score_plt_clk_groups),
362 FUNCTION("smbus", byt_score_smbus_groups),
363 FUNCTION("gpio", byt_score_gpio_groups),
364 };
365
366 static const struct intel_community byt_score_communities[] = {
367 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
368 };
369
370 static const struct intel_pinctrl_soc_data byt_score_soc_data = {
371 .uid = BYT_SCORE_ACPI_UID,
372 .pins = byt_score_pins,
373 .npins = ARRAY_SIZE(byt_score_pins),
374 .groups = byt_score_groups,
375 .ngroups = ARRAY_SIZE(byt_score_groups),
376 .functions = byt_score_functions,
377 .nfunctions = ARRAY_SIZE(byt_score_functions),
378 .communities = byt_score_communities,
379 .ncommunities = ARRAY_SIZE(byt_score_communities),
380 };
381
382
383 static const struct pinctrl_pin_desc byt_sus_pins[] = {
384 PINCTRL_PIN(0, "GPIO_S50"),
385 PINCTRL_PIN(1, "GPIO_S51"),
386 PINCTRL_PIN(2, "GPIO_S52"),
387 PINCTRL_PIN(3, "GPIO_S53"),
388 PINCTRL_PIN(4, "GPIO_S54"),
389 PINCTRL_PIN(5, "GPIO_S55"),
390 PINCTRL_PIN(6, "GPIO_S56"),
391 PINCTRL_PIN(7, "GPIO_S57"),
392 PINCTRL_PIN(8, "GPIO_S58"),
393 PINCTRL_PIN(9, "GPIO_S59"),
394 PINCTRL_PIN(10, "GPIO_S510"),
395 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
396 PINCTRL_PIN(12, "PMC_SUSCLK0"),
397 PINCTRL_PIN(13, "GPIO_S513"),
398 PINCTRL_PIN(14, "USB_ULPI_RST"),
399 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
400 PINCTRL_PIN(16, "PMC_PWRBTN"),
401 PINCTRL_PIN(17, "GPIO_S517"),
402 PINCTRL_PIN(18, "PMC_SUS_STAT"),
403 PINCTRL_PIN(19, "USB_OC0"),
404 PINCTRL_PIN(20, "USB_OC1"),
405 PINCTRL_PIN(21, "PCU_SPI_CS1"),
406 PINCTRL_PIN(22, "GPIO_S522"),
407 PINCTRL_PIN(23, "GPIO_S523"),
408 PINCTRL_PIN(24, "GPIO_S524"),
409 PINCTRL_PIN(25, "GPIO_S525"),
410 PINCTRL_PIN(26, "GPIO_S526"),
411 PINCTRL_PIN(27, "GPIO_S527"),
412 PINCTRL_PIN(28, "GPIO_S528"),
413 PINCTRL_PIN(29, "GPIO_S529"),
414 PINCTRL_PIN(30, "GPIO_S530"),
415 PINCTRL_PIN(31, "USB_ULPI_CLK"),
416 PINCTRL_PIN(32, "USB_ULPI_DATA0"),
417 PINCTRL_PIN(33, "USB_ULPI_DATA1"),
418 PINCTRL_PIN(34, "USB_ULPI_DATA2"),
419 PINCTRL_PIN(35, "USB_ULPI_DATA3"),
420 PINCTRL_PIN(36, "USB_ULPI_DATA4"),
421 PINCTRL_PIN(37, "USB_ULPI_DATA5"),
422 PINCTRL_PIN(38, "USB_ULPI_DATA6"),
423 PINCTRL_PIN(39, "USB_ULPI_DATA7"),
424 PINCTRL_PIN(40, "USB_ULPI_DIR"),
425 PINCTRL_PIN(41, "USB_ULPI_NXT"),
426 PINCTRL_PIN(42, "USB_ULPI_STP"),
427 PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
428 };
429
430 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
431 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
432 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
433 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
434 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
435 52, 53, 59, 40,
436 };
437
438 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
439 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
440 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
441
442 static const unsigned int byt_sus_usb_ulpi_pins[] = {
443 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
444 };
445 static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
446 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
447 };
448 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
449 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
450 };
451
452 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
453 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
454 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
455
456 static const struct intel_pingroup byt_sus_groups[] = {
457 PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
458 PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
459 PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
460 PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
461 PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
462 PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
463 };
464
465 static const char * const byt_sus_usb_groups[] = {
466 "usb_oc_grp", "usb_ulpi_grp",
467 };
468 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
469 static const char * const byt_sus_gpio_groups[] = {
470 "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
471 };
472
473 static const struct intel_function byt_sus_functions[] = {
474 FUNCTION("usb", byt_sus_usb_groups),
475 FUNCTION("spi", byt_sus_spi_groups),
476 FUNCTION("gpio", byt_sus_gpio_groups),
477 };
478
479 static const struct intel_community byt_sus_communities[] = {
480 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
481 };
482
483 static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
484 .uid = BYT_SUS_ACPI_UID,
485 .pins = byt_sus_pins,
486 .npins = ARRAY_SIZE(byt_sus_pins),
487 .groups = byt_sus_groups,
488 .ngroups = ARRAY_SIZE(byt_sus_groups),
489 .functions = byt_sus_functions,
490 .nfunctions = ARRAY_SIZE(byt_sus_functions),
491 .communities = byt_sus_communities,
492 .ncommunities = ARRAY_SIZE(byt_sus_communities),
493 };
494
495 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
496 PINCTRL_PIN(0, "GPIO_NCORE0"),
497 PINCTRL_PIN(1, "GPIO_NCORE1"),
498 PINCTRL_PIN(2, "GPIO_NCORE2"),
499 PINCTRL_PIN(3, "GPIO_NCORE3"),
500 PINCTRL_PIN(4, "GPIO_NCORE4"),
501 PINCTRL_PIN(5, "GPIO_NCORE5"),
502 PINCTRL_PIN(6, "GPIO_NCORE6"),
503 PINCTRL_PIN(7, "GPIO_NCORE7"),
504 PINCTRL_PIN(8, "GPIO_NCORE8"),
505 PINCTRL_PIN(9, "GPIO_NCORE9"),
506 PINCTRL_PIN(10, "GPIO_NCORE10"),
507 PINCTRL_PIN(11, "GPIO_NCORE11"),
508 PINCTRL_PIN(12, "GPIO_NCORE12"),
509 PINCTRL_PIN(13, "GPIO_NCORE13"),
510 PINCTRL_PIN(14, "GPIO_NCORE14"),
511 PINCTRL_PIN(15, "GPIO_NCORE15"),
512 PINCTRL_PIN(16, "GPIO_NCORE16"),
513 PINCTRL_PIN(17, "GPIO_NCORE17"),
514 PINCTRL_PIN(18, "GPIO_NCORE18"),
515 PINCTRL_PIN(19, "GPIO_NCORE19"),
516 PINCTRL_PIN(20, "GPIO_NCORE20"),
517 PINCTRL_PIN(21, "GPIO_NCORE21"),
518 PINCTRL_PIN(22, "GPIO_NCORE22"),
519 PINCTRL_PIN(23, "GPIO_NCORE23"),
520 PINCTRL_PIN(24, "GPIO_NCORE24"),
521 PINCTRL_PIN(25, "GPIO_NCORE25"),
522 PINCTRL_PIN(26, "GPIO_NCORE26"),
523 PINCTRL_PIN(27, "GPIO_NCORE27"),
524 };
525
526 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
527 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
528 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
529 3, 6, 10, 13, 2, 5, 9, 7,
530 };
531
532 static const struct intel_community byt_ncore_communities[] = {
533 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
534 };
535
536 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
537 .uid = BYT_NCORE_ACPI_UID,
538 .pins = byt_ncore_pins,
539 .npins = ARRAY_SIZE(byt_ncore_pins),
540 .communities = byt_ncore_communities,
541 .ncommunities = ARRAY_SIZE(byt_ncore_communities),
542 };
543
544 static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
545 &byt_score_soc_data,
546 &byt_sus_soc_data,
547 &byt_ncore_soc_data,
548 NULL
549 };
550
551 static DEFINE_RAW_SPINLOCK(byt_lock);
552
553 static struct intel_community *byt_get_community(struct byt_gpio *vg,
554 unsigned int pin)
555 {
556 struct intel_community *comm;
557 int i;
558
559 for (i = 0; i < vg->soc_data->ncommunities; i++) {
560 comm = vg->communities_copy + i;
561 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
562 return comm;
563 }
564
565 return NULL;
566 }
567
568 static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
569 int reg)
570 {
571 struct intel_community *comm = byt_get_community(vg, offset);
572 u32 reg_offset;
573
574 if (!comm)
575 return NULL;
576
577 offset -= comm->pin_base;
578 switch (reg) {
579 case BYT_INT_STAT_REG:
580 reg_offset = (offset / 32) * 4;
581 break;
582 case BYT_DEBOUNCE_REG:
583 reg_offset = 0;
584 break;
585 default:
586 reg_offset = comm->pad_map[offset] * 16;
587 break;
588 }
589
590 return comm->pad_regs + reg_offset + reg;
591 }
592
593 static int byt_get_groups_count(struct pinctrl_dev *pctldev)
594 {
595 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
596
597 return vg->soc_data->ngroups;
598 }
599
600 static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
601 unsigned int selector)
602 {
603 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
604
605 return vg->soc_data->groups[selector].name;
606 }
607
608 static int byt_get_group_pins(struct pinctrl_dev *pctldev,
609 unsigned int selector,
610 const unsigned int **pins,
611 unsigned int *num_pins)
612 {
613 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
614
615 *pins = vg->soc_data->groups[selector].pins;
616 *num_pins = vg->soc_data->groups[selector].npins;
617
618 return 0;
619 }
620
621 static const struct pinctrl_ops byt_pinctrl_ops = {
622 .get_groups_count = byt_get_groups_count,
623 .get_group_name = byt_get_group_name,
624 .get_group_pins = byt_get_group_pins,
625 };
626
627 static int byt_get_functions_count(struct pinctrl_dev *pctldev)
628 {
629 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
630
631 return vg->soc_data->nfunctions;
632 }
633
634 static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
635 unsigned int selector)
636 {
637 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
638
639 return vg->soc_data->functions[selector].name;
640 }
641
642 static int byt_get_function_groups(struct pinctrl_dev *pctldev,
643 unsigned int selector,
644 const char * const **groups,
645 unsigned int *num_groups)
646 {
647 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
648
649 *groups = vg->soc_data->functions[selector].groups;
650 *num_groups = vg->soc_data->functions[selector].ngroups;
651
652 return 0;
653 }
654
655 static void byt_set_group_simple_mux(struct byt_gpio *vg,
656 const struct intel_pingroup group,
657 unsigned int func)
658 {
659 unsigned long flags;
660 int i;
661
662 raw_spin_lock_irqsave(&byt_lock, flags);
663
664 for (i = 0; i < group.npins; i++) {
665 void __iomem *padcfg0;
666 u32 value;
667
668 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
669 if (!padcfg0) {
670 dev_warn(&vg->pdev->dev,
671 "Group %s, pin %i not muxed (no padcfg0)\n",
672 group.name, i);
673 continue;
674 }
675
676 value = readl(padcfg0);
677 value &= ~BYT_PIN_MUX;
678 value |= func;
679 writel(value, padcfg0);
680 }
681
682 raw_spin_unlock_irqrestore(&byt_lock, flags);
683 }
684
685 static void byt_set_group_mixed_mux(struct byt_gpio *vg,
686 const struct intel_pingroup group,
687 const unsigned int *func)
688 {
689 unsigned long flags;
690 int i;
691
692 raw_spin_lock_irqsave(&byt_lock, flags);
693
694 for (i = 0; i < group.npins; i++) {
695 void __iomem *padcfg0;
696 u32 value;
697
698 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
699 if (!padcfg0) {
700 dev_warn(&vg->pdev->dev,
701 "Group %s, pin %i not muxed (no padcfg0)\n",
702 group.name, i);
703 continue;
704 }
705
706 value = readl(padcfg0);
707 value &= ~BYT_PIN_MUX;
708 value |= func[i];
709 writel(value, padcfg0);
710 }
711
712 raw_spin_unlock_irqrestore(&byt_lock, flags);
713 }
714
715 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
716 unsigned int group_selector)
717 {
718 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
719 const struct intel_function func = vg->soc_data->functions[func_selector];
720 const struct intel_pingroup group = vg->soc_data->groups[group_selector];
721
722 if (group.modes)
723 byt_set_group_mixed_mux(vg, group, group.modes);
724 else if (!strcmp(func.name, "gpio"))
725 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
726 else
727 byt_set_group_simple_mux(vg, group, group.mode);
728
729 return 0;
730 }
731
732 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned int offset)
733 {
734
735 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
736 offset >= 92 && offset <= 93)
737 return BYT_ALTER_GPIO_MUX;
738
739
740 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
741 offset >= 11 && offset <= 21)
742 return BYT_ALTER_GPIO_MUX;
743
744 return BYT_DEFAULT_GPIO_MUX;
745 }
746
747 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
748 {
749 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
750 unsigned long flags;
751 u32 value;
752
753 raw_spin_lock_irqsave(&byt_lock, flags);
754 value = readl(reg);
755
756
757 if (value & BYT_DIRECT_IRQ_EN)
758 ;
759 else
760 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
761
762 writel(value, reg);
763 raw_spin_unlock_irqrestore(&byt_lock, flags);
764 }
765
766 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
767 struct pinctrl_gpio_range *range,
768 unsigned int offset)
769 {
770 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
771 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
772 u32 value, gpio_mux;
773 unsigned long flags;
774
775 raw_spin_lock_irqsave(&byt_lock, flags);
776
777
778
779
780
781
782
783
784
785
786 value = readl(reg) & BYT_PIN_MUX;
787 gpio_mux = byt_get_gpio_mux(vg, offset);
788 if (gpio_mux != value) {
789 value = readl(reg) & ~BYT_PIN_MUX;
790 value |= gpio_mux;
791 writel(value, reg);
792
793 dev_warn(&vg->pdev->dev, FW_BUG
794 "pin %u forcibly re-configured as GPIO\n", offset);
795 }
796
797 raw_spin_unlock_irqrestore(&byt_lock, flags);
798
799 pm_runtime_get(&vg->pdev->dev);
800
801 return 0;
802 }
803
804 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
805 struct pinctrl_gpio_range *range,
806 unsigned int offset)
807 {
808 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
809
810 byt_gpio_clear_triggering(vg, offset);
811 pm_runtime_put(&vg->pdev->dev);
812 }
813
814 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
815 struct pinctrl_gpio_range *range,
816 unsigned int offset,
817 bool input)
818 {
819 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
820 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
821 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
822 unsigned long flags;
823 u32 value;
824
825 raw_spin_lock_irqsave(&byt_lock, flags);
826
827 value = readl(val_reg);
828 value &= ~BYT_DIR_MASK;
829 if (input)
830 value |= BYT_OUTPUT_EN;
831 else
832
833
834
835
836
837
838 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
839 "Potential Error: Setting GPIO with direct_irq_en to output");
840 writel(value, val_reg);
841
842 raw_spin_unlock_irqrestore(&byt_lock, flags);
843
844 return 0;
845 }
846
847 static const struct pinmux_ops byt_pinmux_ops = {
848 .get_functions_count = byt_get_functions_count,
849 .get_function_name = byt_get_function_name,
850 .get_function_groups = byt_get_function_groups,
851 .set_mux = byt_set_mux,
852 .gpio_request_enable = byt_gpio_request_enable,
853 .gpio_disable_free = byt_gpio_disable_free,
854 .gpio_set_direction = byt_gpio_set_direction,
855 };
856
857 static void byt_get_pull_strength(u32 reg, u16 *strength)
858 {
859 switch (reg & BYT_PULL_STR_MASK) {
860 case BYT_PULL_STR_2K:
861 *strength = 2000;
862 break;
863 case BYT_PULL_STR_10K:
864 *strength = 10000;
865 break;
866 case BYT_PULL_STR_20K:
867 *strength = 20000;
868 break;
869 case BYT_PULL_STR_40K:
870 *strength = 40000;
871 break;
872 }
873 }
874
875 static int byt_set_pull_strength(u32 *reg, u16 strength)
876 {
877 *reg &= ~BYT_PULL_STR_MASK;
878
879 switch (strength) {
880 case 2000:
881 *reg |= BYT_PULL_STR_2K;
882 break;
883 case 10000:
884 *reg |= BYT_PULL_STR_10K;
885 break;
886 case 20000:
887 *reg |= BYT_PULL_STR_20K;
888 break;
889 case 40000:
890 *reg |= BYT_PULL_STR_40K;
891 break;
892 default:
893 return -EINVAL;
894 }
895
896 return 0;
897 }
898
899 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
900 unsigned long *config)
901 {
902 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
903 enum pin_config_param param = pinconf_to_config_param(*config);
904 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
905 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
906 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
907 unsigned long flags;
908 u32 conf, pull, val, debounce;
909 u16 arg = 0;
910
911 raw_spin_lock_irqsave(&byt_lock, flags);
912 conf = readl(conf_reg);
913 pull = conf & BYT_PULL_ASSIGN_MASK;
914 val = readl(val_reg);
915 raw_spin_unlock_irqrestore(&byt_lock, flags);
916
917 switch (param) {
918 case PIN_CONFIG_BIAS_DISABLE:
919 if (pull)
920 return -EINVAL;
921 break;
922 case PIN_CONFIG_BIAS_PULL_DOWN:
923
924 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
925 return -EINVAL;
926
927 byt_get_pull_strength(conf, &arg);
928
929 break;
930 case PIN_CONFIG_BIAS_PULL_UP:
931
932 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
933 return -EINVAL;
934
935 byt_get_pull_strength(conf, &arg);
936
937 break;
938 case PIN_CONFIG_INPUT_DEBOUNCE:
939 if (!(conf & BYT_DEBOUNCE_EN))
940 return -EINVAL;
941
942 raw_spin_lock_irqsave(&byt_lock, flags);
943 debounce = readl(db_reg);
944 raw_spin_unlock_irqrestore(&byt_lock, flags);
945
946 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
947 case BYT_DEBOUNCE_PULSE_375US:
948 arg = 375;
949 break;
950 case BYT_DEBOUNCE_PULSE_750US:
951 arg = 750;
952 break;
953 case BYT_DEBOUNCE_PULSE_1500US:
954 arg = 1500;
955 break;
956 case BYT_DEBOUNCE_PULSE_3MS:
957 arg = 3000;
958 break;
959 case BYT_DEBOUNCE_PULSE_6MS:
960 arg = 6000;
961 break;
962 case BYT_DEBOUNCE_PULSE_12MS:
963 arg = 12000;
964 break;
965 case BYT_DEBOUNCE_PULSE_24MS:
966 arg = 24000;
967 break;
968 default:
969 return -EINVAL;
970 }
971
972 break;
973 default:
974 return -ENOTSUPP;
975 }
976
977 *config = pinconf_to_config_packed(param, arg);
978
979 return 0;
980 }
981
982 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
983 unsigned int offset,
984 unsigned long *configs,
985 unsigned int num_configs)
986 {
987 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
988 unsigned int param, arg;
989 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
990 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
991 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
992 unsigned long flags;
993 u32 conf, val, debounce;
994 int i, ret = 0;
995
996 raw_spin_lock_irqsave(&byt_lock, flags);
997
998 conf = readl(conf_reg);
999 val = readl(val_reg);
1000
1001 for (i = 0; i < num_configs; i++) {
1002 param = pinconf_to_config_param(configs[i]);
1003 arg = pinconf_to_config_argument(configs[i]);
1004
1005 switch (param) {
1006 case PIN_CONFIG_BIAS_DISABLE:
1007 conf &= ~BYT_PULL_ASSIGN_MASK;
1008 break;
1009 case PIN_CONFIG_BIAS_PULL_DOWN:
1010
1011 if (arg == 1)
1012 arg = 2000;
1013
1014
1015
1016
1017
1018 if (val & BYT_INPUT_EN) {
1019 val &= ~BYT_INPUT_EN;
1020 writel(val, val_reg);
1021 dev_warn(&vg->pdev->dev,
1022 "pin %u forcibly set to input mode\n",
1023 offset);
1024 }
1025
1026 conf &= ~BYT_PULL_ASSIGN_MASK;
1027 conf |= BYT_PULL_ASSIGN_DOWN;
1028 ret = byt_set_pull_strength(&conf, arg);
1029
1030 break;
1031 case PIN_CONFIG_BIAS_PULL_UP:
1032
1033 if (arg == 1)
1034 arg = 2000;
1035
1036
1037
1038
1039
1040 if (val & BYT_INPUT_EN) {
1041 val &= ~BYT_INPUT_EN;
1042 writel(val, val_reg);
1043 dev_warn(&vg->pdev->dev,
1044 "pin %u forcibly set to input mode\n",
1045 offset);
1046 }
1047
1048 conf &= ~BYT_PULL_ASSIGN_MASK;
1049 conf |= BYT_PULL_ASSIGN_UP;
1050 ret = byt_set_pull_strength(&conf, arg);
1051
1052 break;
1053 case PIN_CONFIG_INPUT_DEBOUNCE:
1054 debounce = readl(db_reg);
1055 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1056
1057 if (arg)
1058 conf |= BYT_DEBOUNCE_EN;
1059 else
1060 conf &= ~BYT_DEBOUNCE_EN;
1061
1062 switch (arg) {
1063 case 375:
1064 debounce |= BYT_DEBOUNCE_PULSE_375US;
1065 break;
1066 case 750:
1067 debounce |= BYT_DEBOUNCE_PULSE_750US;
1068 break;
1069 case 1500:
1070 debounce |= BYT_DEBOUNCE_PULSE_1500US;
1071 break;
1072 case 3000:
1073 debounce |= BYT_DEBOUNCE_PULSE_3MS;
1074 break;
1075 case 6000:
1076 debounce |= BYT_DEBOUNCE_PULSE_6MS;
1077 break;
1078 case 12000:
1079 debounce |= BYT_DEBOUNCE_PULSE_12MS;
1080 break;
1081 case 24000:
1082 debounce |= BYT_DEBOUNCE_PULSE_24MS;
1083 break;
1084 default:
1085 if (arg)
1086 ret = -EINVAL;
1087 break;
1088 }
1089
1090 if (!ret)
1091 writel(debounce, db_reg);
1092 break;
1093 default:
1094 ret = -ENOTSUPP;
1095 }
1096
1097 if (ret)
1098 break;
1099 }
1100
1101 if (!ret)
1102 writel(conf, conf_reg);
1103
1104 raw_spin_unlock_irqrestore(&byt_lock, flags);
1105
1106 return ret;
1107 }
1108
1109 static const struct pinconf_ops byt_pinconf_ops = {
1110 .is_generic = true,
1111 .pin_config_get = byt_pin_config_get,
1112 .pin_config_set = byt_pin_config_set,
1113 };
1114
1115 static const struct pinctrl_desc byt_pinctrl_desc = {
1116 .pctlops = &byt_pinctrl_ops,
1117 .pmxops = &byt_pinmux_ops,
1118 .confops = &byt_pinconf_ops,
1119 .owner = THIS_MODULE,
1120 };
1121
1122 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1123 {
1124 struct byt_gpio *vg = gpiochip_get_data(chip);
1125 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1126 unsigned long flags;
1127 u32 val;
1128
1129 raw_spin_lock_irqsave(&byt_lock, flags);
1130 val = readl(reg);
1131 raw_spin_unlock_irqrestore(&byt_lock, flags);
1132
1133 return !!(val & BYT_LEVEL);
1134 }
1135
1136 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1137 {
1138 struct byt_gpio *vg = gpiochip_get_data(chip);
1139 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1140 unsigned long flags;
1141 u32 old_val;
1142
1143 if (!reg)
1144 return;
1145
1146 raw_spin_lock_irqsave(&byt_lock, flags);
1147 old_val = readl(reg);
1148 if (value)
1149 writel(old_val | BYT_LEVEL, reg);
1150 else
1151 writel(old_val & ~BYT_LEVEL, reg);
1152 raw_spin_unlock_irqrestore(&byt_lock, flags);
1153 }
1154
1155 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1156 {
1157 struct byt_gpio *vg = gpiochip_get_data(chip);
1158 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1159 unsigned long flags;
1160 u32 value;
1161
1162 if (!reg)
1163 return -EINVAL;
1164
1165 raw_spin_lock_irqsave(&byt_lock, flags);
1166 value = readl(reg);
1167 raw_spin_unlock_irqrestore(&byt_lock, flags);
1168
1169 if (!(value & BYT_OUTPUT_EN))
1170 return 0;
1171 if (!(value & BYT_INPUT_EN))
1172 return 1;
1173
1174 return -EINVAL;
1175 }
1176
1177 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1178 {
1179 return pinctrl_gpio_direction_input(chip->base + offset);
1180 }
1181
1182 static int byt_gpio_direction_output(struct gpio_chip *chip,
1183 unsigned int offset, int value)
1184 {
1185 int ret = pinctrl_gpio_direction_output(chip->base + offset);
1186
1187 if (ret)
1188 return ret;
1189
1190 byt_gpio_set(chip, offset, value);
1191
1192 return 0;
1193 }
1194
1195 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1196 {
1197 struct byt_gpio *vg = gpiochip_get_data(chip);
1198 int i;
1199 u32 conf0, val;
1200
1201 for (i = 0; i < vg->soc_data->npins; i++) {
1202 const struct intel_community *comm;
1203 const char *pull_str = NULL;
1204 const char *pull = NULL;
1205 void __iomem *reg;
1206 unsigned long flags;
1207 const char *label;
1208 unsigned int pin;
1209
1210 raw_spin_lock_irqsave(&byt_lock, flags);
1211 pin = vg->soc_data->pins[i].number;
1212 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1213 if (!reg) {
1214 seq_printf(s,
1215 "Could not retrieve pin %i conf0 reg\n",
1216 pin);
1217 raw_spin_unlock_irqrestore(&byt_lock, flags);
1218 continue;
1219 }
1220 conf0 = readl(reg);
1221
1222 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1223 if (!reg) {
1224 seq_printf(s,
1225 "Could not retrieve pin %i val reg\n", pin);
1226 raw_spin_unlock_irqrestore(&byt_lock, flags);
1227 continue;
1228 }
1229 val = readl(reg);
1230 raw_spin_unlock_irqrestore(&byt_lock, flags);
1231
1232 comm = byt_get_community(vg, pin);
1233 if (!comm) {
1234 seq_printf(s,
1235 "Could not get community for pin %i\n", pin);
1236 continue;
1237 }
1238 label = gpiochip_is_requested(chip, i);
1239 if (!label)
1240 label = "Unrequested";
1241
1242 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1243 case BYT_PULL_ASSIGN_UP:
1244 pull = "up";
1245 break;
1246 case BYT_PULL_ASSIGN_DOWN:
1247 pull = "down";
1248 break;
1249 }
1250
1251 switch (conf0 & BYT_PULL_STR_MASK) {
1252 case BYT_PULL_STR_2K:
1253 pull_str = "2k";
1254 break;
1255 case BYT_PULL_STR_10K:
1256 pull_str = "10k";
1257 break;
1258 case BYT_PULL_STR_20K:
1259 pull_str = "20k";
1260 break;
1261 case BYT_PULL_STR_40K:
1262 pull_str = "40k";
1263 break;
1264 }
1265
1266 seq_printf(s,
1267 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1268 pin,
1269 label,
1270 val & BYT_INPUT_EN ? " " : "in",
1271 val & BYT_OUTPUT_EN ? " " : "out",
1272 val & BYT_LEVEL ? "hi" : "lo",
1273 comm->pad_map[i], comm->pad_map[i] * 16,
1274 conf0 & 0x7,
1275 conf0 & BYT_TRIG_NEG ? " fall" : " ",
1276 conf0 & BYT_TRIG_POS ? " rise" : " ",
1277 conf0 & BYT_TRIG_LVL ? " level" : " ");
1278
1279 if (pull && pull_str)
1280 seq_printf(s, " %-4s %-3s", pull, pull_str);
1281 else
1282 seq_puts(s, " ");
1283
1284 if (conf0 & BYT_IODEN)
1285 seq_puts(s, " open-drain");
1286
1287 seq_puts(s, "\n");
1288 }
1289 }
1290
1291 static const struct gpio_chip byt_gpio_chip = {
1292 .owner = THIS_MODULE,
1293 .request = gpiochip_generic_request,
1294 .free = gpiochip_generic_free,
1295 .get_direction = byt_gpio_get_direction,
1296 .direction_input = byt_gpio_direction_input,
1297 .direction_output = byt_gpio_direction_output,
1298 .get = byt_gpio_get,
1299 .set = byt_gpio_set,
1300 .set_config = gpiochip_generic_config,
1301 .dbg_show = byt_gpio_dbg_show,
1302 };
1303
1304 static void byt_irq_ack(struct irq_data *d)
1305 {
1306 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1307 struct byt_gpio *vg = gpiochip_get_data(gc);
1308 unsigned int offset = irqd_to_hwirq(d);
1309 void __iomem *reg;
1310
1311 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1312 if (!reg)
1313 return;
1314
1315 raw_spin_lock(&byt_lock);
1316 writel(BIT(offset % 32), reg);
1317 raw_spin_unlock(&byt_lock);
1318 }
1319
1320 static void byt_irq_mask(struct irq_data *d)
1321 {
1322 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1323 struct byt_gpio *vg = gpiochip_get_data(gc);
1324
1325 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1326 }
1327
1328 static void byt_irq_unmask(struct irq_data *d)
1329 {
1330 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1331 struct byt_gpio *vg = gpiochip_get_data(gc);
1332 unsigned int offset = irqd_to_hwirq(d);
1333 unsigned long flags;
1334 void __iomem *reg;
1335 u32 value;
1336
1337 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1338 if (!reg)
1339 return;
1340
1341 raw_spin_lock_irqsave(&byt_lock, flags);
1342 value = readl(reg);
1343
1344 switch (irqd_get_trigger_type(d)) {
1345 case IRQ_TYPE_LEVEL_HIGH:
1346 value |= BYT_TRIG_LVL;
1347
1348 case IRQ_TYPE_EDGE_RISING:
1349 value |= BYT_TRIG_POS;
1350 break;
1351 case IRQ_TYPE_LEVEL_LOW:
1352 value |= BYT_TRIG_LVL;
1353
1354 case IRQ_TYPE_EDGE_FALLING:
1355 value |= BYT_TRIG_NEG;
1356 break;
1357 case IRQ_TYPE_EDGE_BOTH:
1358 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1359 break;
1360 }
1361
1362 writel(value, reg);
1363
1364 raw_spin_unlock_irqrestore(&byt_lock, flags);
1365 }
1366
1367 static int byt_irq_type(struct irq_data *d, unsigned int type)
1368 {
1369 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1370 u32 offset = irqd_to_hwirq(d);
1371 u32 value;
1372 unsigned long flags;
1373 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1374
1375 if (!reg || offset >= vg->chip.ngpio)
1376 return -EINVAL;
1377
1378 raw_spin_lock_irqsave(&byt_lock, flags);
1379 value = readl(reg);
1380
1381 WARN(value & BYT_DIRECT_IRQ_EN,
1382 "Bad pad config for io mode, force direct_irq_en bit clearing");
1383
1384
1385
1386
1387 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1388 BYT_TRIG_LVL);
1389
1390 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1391 BYT_GLITCH_F_FAST_CLK;
1392
1393 writel(value, reg);
1394
1395 if (type & IRQ_TYPE_EDGE_BOTH)
1396 irq_set_handler_locked(d, handle_edge_irq);
1397 else if (type & IRQ_TYPE_LEVEL_MASK)
1398 irq_set_handler_locked(d, handle_level_irq);
1399
1400 raw_spin_unlock_irqrestore(&byt_lock, flags);
1401
1402 return 0;
1403 }
1404
1405 static struct irq_chip byt_irqchip = {
1406 .name = "BYT-GPIO",
1407 .irq_ack = byt_irq_ack,
1408 .irq_mask = byt_irq_mask,
1409 .irq_unmask = byt_irq_unmask,
1410 .irq_set_type = byt_irq_type,
1411 .flags = IRQCHIP_SKIP_SET_WAKE,
1412 };
1413
1414 static void byt_gpio_irq_handler(struct irq_desc *desc)
1415 {
1416 struct irq_data *data = irq_desc_get_irq_data(desc);
1417 struct byt_gpio *vg = gpiochip_get_data(
1418 irq_desc_get_handler_data(desc));
1419 struct irq_chip *chip = irq_data_get_irq_chip(data);
1420 u32 base, pin;
1421 void __iomem *reg;
1422 unsigned long pending;
1423 unsigned int virq;
1424
1425
1426 for (base = 0; base < vg->chip.ngpio; base += 32) {
1427 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1428
1429 if (!reg) {
1430 dev_warn(&vg->pdev->dev,
1431 "Pin %i: could not retrieve interrupt status register\n",
1432 base);
1433 continue;
1434 }
1435
1436 raw_spin_lock(&byt_lock);
1437 pending = readl(reg);
1438 raw_spin_unlock(&byt_lock);
1439 for_each_set_bit(pin, &pending, 32) {
1440 virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
1441 generic_handle_irq(virq);
1442 }
1443 }
1444 chip->irq_eoi(data);
1445 }
1446
1447 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
1448 unsigned long *valid_mask,
1449 unsigned int ngpios)
1450 {
1451
1452
1453
1454
1455
1456
1457
1458
1459 }
1460
1461 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
1462 {
1463 struct gpio_chip *gc = &vg->chip;
1464 struct device *dev = &vg->pdev->dev;
1465 void __iomem *reg;
1466 u32 base, value;
1467 int i;
1468
1469
1470
1471
1472
1473
1474 for (i = 0; i < vg->soc_data->npins; i++) {
1475 unsigned int pin = vg->soc_data->pins[i].number;
1476
1477 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1478 if (!reg) {
1479 dev_warn(&vg->pdev->dev,
1480 "Pin %i: could not retrieve conf0 register\n",
1481 i);
1482 continue;
1483 }
1484
1485 value = readl(reg);
1486 if (value & BYT_DIRECT_IRQ_EN) {
1487 clear_bit(i, gc->irq.valid_mask);
1488 dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
1489 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1490 byt_gpio_clear_triggering(vg, i);
1491 dev_dbg(dev, "disabling GPIO %d\n", i);
1492 }
1493 }
1494
1495
1496 for (base = 0; base < vg->soc_data->npins; base += 32) {
1497 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1498
1499 if (!reg) {
1500 dev_warn(&vg->pdev->dev,
1501 "Pin %i: could not retrieve irq status reg\n",
1502 base);
1503 continue;
1504 }
1505
1506 writel(0xffffffff, reg);
1507
1508
1509 value = readl(reg);
1510 if (value)
1511 dev_err(&vg->pdev->dev,
1512 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
1513 base / 32, value);
1514 }
1515 }
1516
1517 static int byt_gpio_probe(struct byt_gpio *vg)
1518 {
1519 struct gpio_chip *gc;
1520 struct resource *irq_rc;
1521 int ret;
1522
1523
1524 vg->chip = byt_gpio_chip;
1525 gc = &vg->chip;
1526 gc->label = dev_name(&vg->pdev->dev);
1527 gc->base = -1;
1528 gc->can_sleep = false;
1529 gc->parent = &vg->pdev->dev;
1530 gc->ngpio = vg->soc_data->npins;
1531 gc->irq.init_valid_mask = byt_init_irq_valid_mask;
1532
1533 #ifdef CONFIG_PM_SLEEP
1534 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
1535 sizeof(*vg->saved_context), GFP_KERNEL);
1536 if (!vg->saved_context)
1537 return -ENOMEM;
1538 #endif
1539 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
1540 if (ret) {
1541 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
1542 return ret;
1543 }
1544
1545 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
1546 0, 0, vg->soc_data->npins);
1547 if (ret) {
1548 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
1549 return ret;
1550 }
1551
1552
1553 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
1554 if (irq_rc && irq_rc->start) {
1555 byt_gpio_irq_init_hw(vg);
1556 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
1557 handle_bad_irq, IRQ_TYPE_NONE);
1558 if (ret) {
1559 dev_err(&vg->pdev->dev, "failed to add irqchip\n");
1560 return ret;
1561 }
1562
1563 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
1564 (unsigned)irq_rc->start,
1565 byt_gpio_irq_handler);
1566 }
1567
1568 return ret;
1569 }
1570
1571 static int byt_set_soc_data(struct byt_gpio *vg,
1572 const struct intel_pinctrl_soc_data *soc_data)
1573 {
1574 int i;
1575
1576 vg->soc_data = soc_data;
1577 vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
1578 soc_data->ncommunities,
1579 sizeof(*vg->communities_copy),
1580 GFP_KERNEL);
1581 if (!vg->communities_copy)
1582 return -ENOMEM;
1583
1584 for (i = 0; i < soc_data->ncommunities; i++) {
1585 struct intel_community *comm = vg->communities_copy + i;
1586
1587 *comm = vg->soc_data->communities[i];
1588
1589 comm->pad_regs = devm_platform_ioremap_resource(vg->pdev, 0);
1590 if (IS_ERR(comm->pad_regs))
1591 return PTR_ERR(comm->pad_regs);
1592 }
1593
1594 return 0;
1595 }
1596
1597 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1598 { "INT33B2", (kernel_ulong_t)byt_soc_data },
1599 { "INT33FC", (kernel_ulong_t)byt_soc_data },
1600 { }
1601 };
1602
1603 static int byt_pinctrl_probe(struct platform_device *pdev)
1604 {
1605 const struct intel_pinctrl_soc_data *soc_data = NULL;
1606 const struct intel_pinctrl_soc_data **soc_table;
1607 struct acpi_device *acpi_dev;
1608 struct byt_gpio *vg;
1609 int i, ret;
1610
1611 acpi_dev = ACPI_COMPANION(&pdev->dev);
1612 if (!acpi_dev)
1613 return -ENODEV;
1614
1615 soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(&pdev->dev);
1616
1617 for (i = 0; soc_table[i]; i++) {
1618 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
1619 soc_data = soc_table[i];
1620 break;
1621 }
1622 }
1623
1624 if (!soc_data)
1625 return -ENODEV;
1626
1627 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
1628 if (!vg)
1629 return -ENOMEM;
1630
1631 vg->pdev = pdev;
1632 ret = byt_set_soc_data(vg, soc_data);
1633 if (ret) {
1634 dev_err(&pdev->dev, "failed to set soc data\n");
1635 return ret;
1636 }
1637
1638 vg->pctl_desc = byt_pinctrl_desc;
1639 vg->pctl_desc.name = dev_name(&pdev->dev);
1640 vg->pctl_desc.pins = vg->soc_data->pins;
1641 vg->pctl_desc.npins = vg->soc_data->npins;
1642
1643 vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg);
1644 if (IS_ERR(vg->pctl_dev)) {
1645 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1646 return PTR_ERR(vg->pctl_dev);
1647 }
1648
1649 ret = byt_gpio_probe(vg);
1650 if (ret)
1651 return ret;
1652
1653 platform_set_drvdata(pdev, vg);
1654 pm_runtime_enable(&pdev->dev);
1655
1656 return 0;
1657 }
1658
1659 #ifdef CONFIG_PM_SLEEP
1660 static int byt_gpio_suspend(struct device *dev)
1661 {
1662 struct byt_gpio *vg = dev_get_drvdata(dev);
1663 unsigned long flags;
1664 int i;
1665
1666 raw_spin_lock_irqsave(&byt_lock, flags);
1667
1668 for (i = 0; i < vg->soc_data->npins; i++) {
1669 void __iomem *reg;
1670 u32 value;
1671 unsigned int pin = vg->soc_data->pins[i].number;
1672
1673 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1674 if (!reg) {
1675 dev_warn(&vg->pdev->dev,
1676 "Pin %i: could not retrieve conf0 register\n",
1677 i);
1678 continue;
1679 }
1680 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1681 vg->saved_context[i].conf0 = value;
1682
1683 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1684 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1685 vg->saved_context[i].val = value;
1686 }
1687
1688 raw_spin_unlock_irqrestore(&byt_lock, flags);
1689 return 0;
1690 }
1691
1692 static int byt_gpio_resume(struct device *dev)
1693 {
1694 struct byt_gpio *vg = dev_get_drvdata(dev);
1695 unsigned long flags;
1696 int i;
1697
1698 raw_spin_lock_irqsave(&byt_lock, flags);
1699
1700 for (i = 0; i < vg->soc_data->npins; i++) {
1701 void __iomem *reg;
1702 u32 value;
1703 unsigned int pin = vg->soc_data->pins[i].number;
1704
1705 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1706 if (!reg) {
1707 dev_warn(&vg->pdev->dev,
1708 "Pin %i: could not retrieve conf0 register\n",
1709 i);
1710 continue;
1711 }
1712 value = readl(reg);
1713 if ((value & BYT_CONF0_RESTORE_MASK) !=
1714 vg->saved_context[i].conf0) {
1715 value &= ~BYT_CONF0_RESTORE_MASK;
1716 value |= vg->saved_context[i].conf0;
1717 writel(value, reg);
1718 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1719 }
1720
1721 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1722 value = readl(reg);
1723 if ((value & BYT_VAL_RESTORE_MASK) !=
1724 vg->saved_context[i].val) {
1725 u32 v;
1726
1727 v = value & ~BYT_VAL_RESTORE_MASK;
1728 v |= vg->saved_context[i].val;
1729 if (v != value) {
1730 writel(v, reg);
1731 dev_dbg(dev, "restored pin %d val %#08x\n",
1732 i, v);
1733 }
1734 }
1735 }
1736
1737 raw_spin_unlock_irqrestore(&byt_lock, flags);
1738 return 0;
1739 }
1740 #endif
1741
1742 #ifdef CONFIG_PM
1743 static int byt_gpio_runtime_suspend(struct device *dev)
1744 {
1745 return 0;
1746 }
1747
1748 static int byt_gpio_runtime_resume(struct device *dev)
1749 {
1750 return 0;
1751 }
1752 #endif
1753
1754 static const struct dev_pm_ops byt_gpio_pm_ops = {
1755 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1756 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1757 NULL)
1758 };
1759
1760 static struct platform_driver byt_gpio_driver = {
1761 .probe = byt_pinctrl_probe,
1762 .driver = {
1763 .name = "byt_gpio",
1764 .pm = &byt_gpio_pm_ops,
1765 .suppress_bind_attrs = true,
1766
1767 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
1768 },
1769 };
1770
1771 static int __init byt_gpio_init(void)
1772 {
1773 return platform_driver_register(&byt_gpio_driver);
1774 }
1775 subsys_initcall(byt_gpio_init);