drivers/pinctrl/meson/pinctrl-meson.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
meson_get_bank
meson_calc_reg_and_bit
meson_get_groups_count
meson_get_group_name
meson_get_group_pins
meson_pin_dbg_show
meson_pmx_get_funcs_count
meson_pmx_get_func_name
meson_pmx_get_groups
meson_pinconf_set_gpio_bit
meson_pinconf_get_gpio_bit
meson_pinconf_set_output
meson_pinconf_get_output
meson_pinconf_set_drive
meson_pinconf_get_drive
meson_pinconf_set_output_drive
meson_pinconf_disable_bias
meson_pinconf_enable_bias
meson_pinconf_set_drive_strength
meson_pinconf_set
meson_pinconf_get_pull
meson_pinconf_get_drive_strength
meson_pinconf_get
meson_pinconf_group_set
meson_pinconf_group_get
meson_gpio_direction_input
meson_gpio_direction_output
meson_gpio_set
meson_gpio_get
meson_gpiolib_register
meson_map_resource
meson_pinctrl_parse_dt
meson_pinctrl_probe
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Pin controller and GPIO driver for Amlogic Meson SoCs
   4  *
   5  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
   6  */
   7 
   8 /*
   9  * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
  10  * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
  11  * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
  12  * variable number of pins.
  13  *
  14  * The AO bank is special because it belongs to the Always-On power
  15  * domain which can't be powered off; the bank also uses a set of
  16  * registers different from the other banks.
  17  *
  18  * For each pin controller there are 4 different register ranges that
  19  * control the following properties of the pins:
  20  *  1) pin muxing
  21  *  2) pull enable/disable
  22  *  3) pull up/down
  23  *  4) GPIO direction, output value, input value
  24  *
  25  * In some cases the register ranges for pull enable and pull
  26  * direction are the same and thus there are only 3 register ranges.
  27  *
  28  * Since Meson G12A SoC, the ao register ranges for gpio, pull enable
  29  * and pull direction are the same, so there are only 2 register ranges.
  30  *
  31  * For the pull and GPIO configuration every bank uses a contiguous
  32  * set of bits in the register sets described above; the same register
  33  * can be shared by more banks with different offsets.
  34  *
  35  * In addition to this there are some registers shared between all
  36  * banks that control the IRQ functionality. This feature is not
  37  * supported at the moment by the driver.
  38  */
  39 
  40 #include <linux/device.h>
  41 #include <linux/gpio/driver.h>
  42 #include <linux/init.h>
  43 #include <linux/io.h>
  44 #include <linux/of.h>
  45 #include <linux/of_address.h>
  46 #include <linux/of_device.h>
  47 #include <linux/pinctrl/pinconf-generic.h>
  48 #include <linux/pinctrl/pinconf.h>
  49 #include <linux/pinctrl/pinctrl.h>
  50 #include <linux/pinctrl/pinmux.h>
  51 #include <linux/platform_device.h>
  52 #include <linux/regmap.h>
  53 #include <linux/seq_file.h>
  54 
  55 #include "../core.h"
  56 #include "../pinctrl-utils.h"
  57 #include "pinctrl-meson.h"
  58 
  59 /**
  60  * meson_get_bank() - find the bank containing a given pin
  61  *
  62  * @pc:         the pinctrl instance
  63  * @pin:        the pin number
  64  * @bank:       the found bank
  65  *
  66  * Return:      0 on success, a negative value on error
  67  */
  68 static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin,
  69                           struct meson_bank **bank)
  70 {
  71         int i;
  72 
  73         for (i = 0; i < pc->data->num_banks; i++) {
  74                 if (pin >= pc->data->banks[i].first &&
  75                     pin <= pc->data->banks[i].last) {
  76                         *bank = &pc->data->banks[i];
  77                         return 0;
  78                 }
  79         }
  80 
  81         return -EINVAL;
  82 }
  83 
  84 /**
  85  * meson_calc_reg_and_bit() - calculate register and bit for a pin
  86  *
  87  * @bank:       the bank containing the pin
  88  * @pin:        the pin number
  89  * @reg_type:   the type of register needed (pull-enable, pull, etc...)
  90  * @reg:        the computed register offset
  91  * @bit:        the computed bit
  92  */
  93 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
  94                                    enum meson_reg_type reg_type,
  95                                    unsigned int *reg, unsigned int *bit)
  96 {
  97         struct meson_reg_desc *desc = &bank->regs[reg_type];
  98 
  99         *reg = desc->reg * 4;
 100         *bit = desc->bit + pin - bank->first;
 101 }
 102 
 103 static int meson_get_groups_count(struct pinctrl_dev *pcdev)
 104 {
 105         struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
 106 
 107         return pc->data->num_groups;
 108 }
 109 
 110 static const char *meson_get_group_name(struct pinctrl_dev *pcdev,
 111                                         unsigned selector)
 112 {
 113         struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
 114 
 115         return pc->data->groups[selector].name;
 116 }
 117 
 118 static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector,
 119                                 const unsigned **pins, unsigned *num_pins)
 120 {
 121         struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
 122 
 123         *pins = pc->data->groups[selector].pins;
 124         *num_pins = pc->data->groups[selector].num_pins;
 125 
 126         return 0;
 127 }
 128 
 129 static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
 130                                unsigned offset)
 131 {
 132         seq_printf(s, " %s", dev_name(pcdev->dev));
 133 }
 134 
 135 static const struct pinctrl_ops meson_pctrl_ops = {
 136         .get_groups_count       = meson_get_groups_count,
 137         .get_group_name         = meson_get_group_name,
 138         .get_group_pins         = meson_get_group_pins,
 139         .dt_node_to_map         = pinconf_generic_dt_node_to_map_all,
 140         .dt_free_map            = pinctrl_utils_free_map,
 141         .pin_dbg_show           = meson_pin_dbg_show,
 142 };
 143 
 144 int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
 145 {
 146         struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
 147 
 148         return pc->data->num_funcs;
 149 }
 150 
 151 const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
 152                                     unsigned selector)
 153 {
 154         struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
 155 
 156         return pc->data->funcs[selector].name;
 157 }
 158 
 159 int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
 160                          const char * const **groups,
 161                          unsigned * const num_groups)
 162 {
 163         struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
 164 
 165         *groups = pc->data->funcs[selector].groups;
 166         *num_groups = pc->data->funcs[selector].num_groups;
 167 
 168         return 0;
 169 }
 170 
 171 static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc,
 172                                       unsigned int pin,
 173                                       unsigned int reg_type,
 174                                       bool arg)
 175 {
 176         struct meson_bank *bank;
 177         unsigned int reg, bit;
 178         int ret;
 179 
 180         ret = meson_get_bank(pc, pin, &bank);
 181         if (ret)
 182                 return ret;
 183 
 184         meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit);
 185         return regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
 186                                   arg ? BIT(bit) : 0);
 187 }
 188 
 189 static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc,
 190                                       unsigned int pin,
 191                                       unsigned int reg_type)
 192 {
 193         struct meson_bank *bank;
 194         unsigned int reg, bit, val;
 195         int ret;
 196 
 197         ret = meson_get_bank(pc, pin, &bank);
 198         if (ret)
 199                 return ret;
 200 
 201         meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit);
 202         ret = regmap_read(pc->reg_gpio, reg, &val);
 203         if (ret)
 204                 return ret;
 205 
 206         return BIT(bit) & val ? 1 : 0;
 207 }
 208 
 209 static int meson_pinconf_set_output(struct meson_pinctrl *pc,
 210                                     unsigned int pin,
 211                                     bool out)
 212 {
 213         return meson_pinconf_set_gpio_bit(pc, pin, REG_DIR, !out);
 214 }
 215 
 216 static int meson_pinconf_get_output(struct meson_pinctrl *pc,
 217                                     unsigned int pin)
 218 {
 219         int ret = meson_pinconf_get_gpio_bit(pc, pin, REG_DIR);
 220 
 221         if (ret < 0)
 222                 return ret;
 223 
 224         return !ret;
 225 }
 226 
 227 static int meson_pinconf_set_drive(struct meson_pinctrl *pc,
 228                                    unsigned int pin,
 229                                    bool high)
 230 {
 231         return meson_pinconf_set_gpio_bit(pc, pin, REG_OUT, high);
 232 }
 233 
 234 static int meson_pinconf_get_drive(struct meson_pinctrl *pc,
 235                                    unsigned int pin)
 236 {
 237         return meson_pinconf_get_gpio_bit(pc, pin, REG_OUT);
 238 }
 239 
 240 static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc,
 241                                           unsigned int pin,
 242                                           bool high)
 243 {
 244         int ret;
 245 
 246         ret = meson_pinconf_set_output(pc, pin, true);
 247         if (ret)
 248                 return ret;
 249 
 250         return meson_pinconf_set_drive(pc, pin, high);
 251 }
 252 
 253 static int meson_pinconf_disable_bias(struct meson_pinctrl *pc,
 254                                       unsigned int pin)
 255 {
 256         struct meson_bank *bank;
 257         unsigned int reg, bit = 0;
 258         int ret;
 259 
 260         ret = meson_get_bank(pc, pin, &bank);
 261         if (ret)
 262                 return ret;
 263 
 264         meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
 265         ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0);
 266         if (ret)
 267                 return ret;
 268 
 269         return 0;
 270 }
 271 
 272 static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin,
 273                                      bool pull_up)
 274 {
 275         struct meson_bank *bank;
 276         unsigned int reg, bit, val = 0;
 277         int ret;
 278 
 279         ret = meson_get_bank(pc, pin, &bank);
 280         if (ret)
 281                 return ret;
 282 
 283         meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
 284         if (pull_up)
 285                 val = BIT(bit);
 286 
 287         ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val);
 288         if (ret)
 289                 return ret;
 290 
 291         meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
 292         ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit));
 293         if (ret)
 294                 return ret;
 295 
 296         return 0;
 297 }
 298 
 299 static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc,
 300                                             unsigned int pin,
 301                                             u16 drive_strength_ua)
 302 {
 303         struct meson_bank *bank;
 304         unsigned int reg, bit, ds_val;
 305         int ret;
 306 
 307         if (!pc->reg_ds) {
 308                 dev_err(pc->dev, "drive-strength not supported\n");
 309                 return -ENOTSUPP;
 310         }
 311 
 312         ret = meson_get_bank(pc, pin, &bank);
 313         if (ret)
 314                 return ret;
 315 
 316         meson_calc_reg_and_bit(bank, pin, REG_DS, &reg, &bit);
 317         bit = bit << 1;
 318 
 319         if (drive_strength_ua <= 500) {
 320                 ds_val = MESON_PINCONF_DRV_500UA;
 321         } else if (drive_strength_ua <= 2500) {
 322                 ds_val = MESON_PINCONF_DRV_2500UA;
 323         } else if (drive_strength_ua <= 3000) {
 324                 ds_val = MESON_PINCONF_DRV_3000UA;
 325         } else if (drive_strength_ua <= 4000) {
 326                 ds_val = MESON_PINCONF_DRV_4000UA;
 327         } else {
 328                 dev_warn_once(pc->dev,
 329                               "pin %u: invalid drive-strength : %d , default to 4mA\n",
 330                               pin, drive_strength_ua);
 331                 ds_val = MESON_PINCONF_DRV_4000UA;
 332         }
 333 
 334         ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit);
 335         if (ret)
 336                 return ret;
 337 
 338         return 0;
 339 }
 340 
 341 static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
 342                              unsigned long *configs, unsigned num_configs)
 343 {
 344         struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
 345         enum pin_config_param param;
 346         unsigned int arg = 0;
 347         int i, ret;
 348 
 349         for (i = 0; i < num_configs; i++) {
 350                 param = pinconf_to_config_param(configs[i]);
 351 
 352                 switch (param) {
 353                 case PIN_CONFIG_DRIVE_STRENGTH_UA:
 354                 case PIN_CONFIG_OUTPUT_ENABLE:
 355                 case PIN_CONFIG_OUTPUT:
 356                         arg = pinconf_to_config_argument(configs[i]);
 357                         break;
 358 
 359                 default:
 360                         break;
 361                 }
 362 
 363                 switch (param) {
 364                 case PIN_CONFIG_BIAS_DISABLE:
 365                         ret = meson_pinconf_disable_bias(pc, pin);
 366                         break;
 367                 case PIN_CONFIG_BIAS_PULL_UP:
 368                         ret = meson_pinconf_enable_bias(pc, pin, true);
 369                         break;
 370                 case PIN_CONFIG_BIAS_PULL_DOWN:
 371                         ret = meson_pinconf_enable_bias(pc, pin, false);
 372                         break;
 373                 case PIN_CONFIG_DRIVE_STRENGTH_UA:
 374                         ret = meson_pinconf_set_drive_strength(pc, pin, arg);
 375                         break;
 376                 case PIN_CONFIG_OUTPUT_ENABLE:
 377                         ret = meson_pinconf_set_output(pc, pin, arg);
 378                         break;
 379                 case PIN_CONFIG_OUTPUT:
 380                         ret = meson_pinconf_set_output_drive(pc, pin, arg);
 381                         break;
 382                 default:
 383                         ret = -ENOTSUPP;
 384                 }
 385 
 386                 if (ret)
 387                         return ret;
 388         }
 389 
 390         return 0;
 391 }
 392 
 393 static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
 394 {
 395         struct meson_bank *bank;
 396         unsigned int reg, bit, val;
 397         int ret, conf;
 398 
 399         ret = meson_get_bank(pc, pin, &bank);
 400         if (ret)
 401                 return ret;
 402 
 403         meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
 404 
 405         ret = regmap_read(pc->reg_pullen, reg, &val);
 406         if (ret)
 407                 return ret;
 408 
 409         if (!(val & BIT(bit))) {
 410                 conf = PIN_CONFIG_BIAS_DISABLE;
 411         } else {
 412                 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
 413 
 414                 ret = regmap_read(pc->reg_pull, reg, &val);
 415                 if (ret)
 416                         return ret;
 417 
 418                 if (val & BIT(bit))
 419                         conf = PIN_CONFIG_BIAS_PULL_UP;
 420                 else
 421                         conf = PIN_CONFIG_BIAS_PULL_DOWN;
 422         }
 423 
 424         return conf;
 425 }
 426 
 427 static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc,
 428                                             unsigned int pin,
 429                                             u16 *drive_strength_ua)
 430 {
 431         struct meson_bank *bank;
 432         unsigned int reg, bit;
 433         unsigned int val;
 434         int ret;
 435 
 436         if (!pc->reg_ds)
 437                 return -ENOTSUPP;
 438 
 439         ret = meson_get_bank(pc, pin, &bank);
 440         if (ret)
 441                 return ret;
 442 
 443         meson_calc_reg_and_bit(bank, pin, REG_DS, &reg, &bit);
 444         bit = bit << 1;
 445 
 446         ret = regmap_read(pc->reg_ds, reg, &val);
 447         if (ret)
 448                 return ret;
 449 
 450         switch ((val >> bit) & 0x3) {
 451         case MESON_PINCONF_DRV_500UA:
 452                 *drive_strength_ua = 500;
 453                 break;
 454         case MESON_PINCONF_DRV_2500UA:
 455                 *drive_strength_ua = 2500;
 456                 break;
 457         case MESON_PINCONF_DRV_3000UA:
 458                 *drive_strength_ua = 3000;
 459                 break;
 460         case MESON_PINCONF_DRV_4000UA:
 461                 *drive_strength_ua = 4000;
 462                 break;
 463         default:
 464                 return -EINVAL;
 465         }
 466 
 467         return 0;
 468 }
 469 
 470 static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
 471                              unsigned long *config)
 472 {
 473         struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
 474         enum pin_config_param param = pinconf_to_config_param(*config);
 475         u16 arg;
 476         int ret;
 477 
 478         switch (param) {
 479         case PIN_CONFIG_BIAS_DISABLE:
 480         case PIN_CONFIG_BIAS_PULL_DOWN:
 481         case PIN_CONFIG_BIAS_PULL_UP:
 482                 if (meson_pinconf_get_pull(pc, pin) == param)
 483                         arg = 1;
 484                 else
 485                         return -EINVAL;
 486                 break;
 487         case PIN_CONFIG_DRIVE_STRENGTH_UA:
 488                 ret = meson_pinconf_get_drive_strength(pc, pin, &arg);
 489                 if (ret)
 490                         return ret;
 491                 break;
 492         case PIN_CONFIG_OUTPUT_ENABLE:
 493                 ret = meson_pinconf_get_output(pc, pin);
 494                 if (ret <= 0)
 495                         return -EINVAL;
 496                 arg = 1;
 497                 break;
 498         case PIN_CONFIG_OUTPUT:
 499                 ret = meson_pinconf_get_output(pc, pin);
 500                 if (ret <= 0)
 501                         return -EINVAL;
 502 
 503                 ret = meson_pinconf_get_drive(pc, pin);
 504                 if (ret < 0)
 505                         return -EINVAL;
 506 
 507                 arg = ret;
 508                 break;
 509 
 510         default:
 511                 return -ENOTSUPP;
 512         }
 513 
 514         *config = pinconf_to_config_packed(param, arg);
 515         dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config);
 516 
 517         return 0;
 518 }
 519 
 520 static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
 521                                    unsigned int num_group,
 522                                    unsigned long *configs, unsigned num_configs)
 523 {
 524         struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
 525         struct meson_pmx_group *group = &pc->data->groups[num_group];
 526         int i;
 527 
 528         dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
 529 
 530         for (i = 0; i < group->num_pins; i++) {
 531                 meson_pinconf_set(pcdev, group->pins[i], configs,
 532                                   num_configs);
 533         }
 534 
 535         return 0;
 536 }
 537 
 538 static int meson_pinconf_group_get(struct pinctrl_dev *pcdev,
 539                                    unsigned int group, unsigned long *config)
 540 {
 541         return -ENOTSUPP;
 542 }
 543 
 544 static const struct pinconf_ops meson_pinconf_ops = {
 545         .pin_config_get         = meson_pinconf_get,
 546         .pin_config_set         = meson_pinconf_set,
 547         .pin_config_group_get   = meson_pinconf_group_get,
 548         .pin_config_group_set   = meson_pinconf_group_set,
 549         .is_generic             = true,
 550 };
 551 
 552 static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 553 {
 554         return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false);
 555 }
 556 
 557 static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
 558                                        int value)
 559 {
 560         return meson_pinconf_set_output_drive(gpiochip_get_data(chip),
 561                                               gpio, value);
 562 }
 563 
 564 static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
 565 {
 566         meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value);
 567 }
 568 
 569 static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
 570 {
 571         struct meson_pinctrl *pc = gpiochip_get_data(chip);
 572         unsigned int reg, bit, val;
 573         struct meson_bank *bank;
 574         int ret;
 575 
 576         ret = meson_get_bank(pc, gpio, &bank);
 577         if (ret)
 578                 return ret;
 579 
 580         meson_calc_reg_and_bit(bank, gpio, REG_IN, &reg, &bit);
 581         regmap_read(pc->reg_gpio, reg, &val);
 582 
 583         return !!(val & BIT(bit));
 584 }
 585 
 586 static int meson_gpiolib_register(struct meson_pinctrl *pc)
 587 {
 588         int ret;
 589 
 590         pc->chip.label = pc->data->name;
 591         pc->chip.parent = pc->dev;
 592         pc->chip.request = gpiochip_generic_request;
 593         pc->chip.free = gpiochip_generic_free;
 594         pc->chip.direction_input = meson_gpio_direction_input;
 595         pc->chip.direction_output = meson_gpio_direction_output;
 596         pc->chip.get = meson_gpio_get;
 597         pc->chip.set = meson_gpio_set;
 598         pc->chip.base = -1;
 599         pc->chip.ngpio = pc->data->num_pins;
 600         pc->chip.can_sleep = false;
 601         pc->chip.of_node = pc->of_node;
 602         pc->chip.of_gpio_n_cells = 2;
 603 
 604         ret = gpiochip_add_data(&pc->chip, pc);
 605         if (ret) {
 606                 dev_err(pc->dev, "can't add gpio chip %s\n",
 607                         pc->data->name);
 608                 return ret;
 609         }
 610 
 611         return 0;
 612 }
 613 
 614 static struct regmap_config meson_regmap_config = {
 615         .reg_bits = 32,
 616         .val_bits = 32,
 617         .reg_stride = 4,
 618 };
 619 
 620 static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
 621                                          struct device_node *node, char *name)
 622 {
 623         struct resource res;
 624         void __iomem *base;
 625         int i;
 626 
 627         i = of_property_match_string(node, "reg-names", name);
 628         if (of_address_to_resource(node, i, &res))
 629                 return ERR_PTR(-ENOENT);
 630 
 631         base = devm_ioremap_resource(pc->dev, &res);
 632         if (IS_ERR(base))
 633                 return ERR_CAST(base);
 634 
 635         meson_regmap_config.max_register = resource_size(&res) - 4;
 636         meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
 637                                                   "%pOFn-%s", node,
 638                                                   name);
 639         if (!meson_regmap_config.name)
 640                 return ERR_PTR(-ENOMEM);
 641 
 642         return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
 643 }
 644 
 645 static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
 646                                   struct device_node *node)
 647 {
 648         struct device_node *np, *gpio_np = NULL;
 649 
 650         for_each_child_of_node(node, np) {
 651                 if (!of_find_property(np, "gpio-controller", NULL))
 652                         continue;
 653                 if (gpio_np) {
 654                         dev_err(pc->dev, "multiple gpio nodes\n");
 655                         of_node_put(np);
 656                         return -EINVAL;
 657                 }
 658                 gpio_np = np;
 659         }
 660 
 661         if (!gpio_np) {
 662                 dev_err(pc->dev, "no gpio node found\n");
 663                 return -EINVAL;
 664         }
 665 
 666         pc->of_node = gpio_np;
 667 
 668         pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
 669         if (IS_ERR(pc->reg_mux)) {
 670                 dev_err(pc->dev, "mux registers not found\n");
 671                 return PTR_ERR(pc->reg_mux);
 672         }
 673 
 674         pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
 675         if (IS_ERR(pc->reg_gpio)) {
 676                 dev_err(pc->dev, "gpio registers not found\n");
 677                 return PTR_ERR(pc->reg_gpio);
 678         }
 679 
 680         pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
 681         /* Use gpio region if pull one is not present */
 682         if (IS_ERR(pc->reg_pull))
 683                 pc->reg_pull = pc->reg_gpio;
 684 
 685         pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
 686         /* Use pull region if pull-enable one is not present */
 687         if (IS_ERR(pc->reg_pullen))
 688                 pc->reg_pullen = pc->reg_pull;
 689 
 690         pc->reg_ds = meson_map_resource(pc, gpio_np, "ds");
 691         if (IS_ERR(pc->reg_ds)) {
 692                 dev_dbg(pc->dev, "ds registers not found - skipping\n");
 693                 pc->reg_ds = NULL;
 694         }
 695 
 696         return 0;
 697 }
 698 
 699 int meson_pinctrl_probe(struct platform_device *pdev)
 700 {
 701         struct device *dev = &pdev->dev;
 702         struct meson_pinctrl *pc;
 703         int ret;
 704 
 705         pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL);
 706         if (!pc)
 707                 return -ENOMEM;
 708 
 709         pc->dev = dev;
 710         pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev);
 711 
 712         ret = meson_pinctrl_parse_dt(pc, dev->of_node);
 713         if (ret)
 714                 return ret;
 715 
 716         pc->desc.name           = "pinctrl-meson";
 717         pc->desc.owner          = THIS_MODULE;
 718         pc->desc.pctlops        = &meson_pctrl_ops;
 719         pc->desc.pmxops         = pc->data->pmx_ops;
 720         pc->desc.confops        = &meson_pinconf_ops;
 721         pc->desc.pins           = pc->data->pins;
 722         pc->desc.npins          = pc->data->num_pins;
 723 
 724         pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc);
 725         if (IS_ERR(pc->pcdev)) {
 726                 dev_err(pc->dev, "can't register pinctrl device");
 727                 return PTR_ERR(pc->pcdev);
 728         }
 729 
 730         return meson_gpiolib_register(pc);
 731 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/pinctrl/meson/pinctrl-meson.c

DEFINITIONS
