This source file includes following definitions.
- ingenic_gpio_read_reg
- ingenic_gpio_set_bit
- ingenic_gpio_shadow_set_bit
- ingenic_gpio_shadow_set_bit_load
- ingenic_gpio_get_value
- ingenic_gpio_set_value
- irq_set_type
- ingenic_gpio_irq_mask
- ingenic_gpio_irq_unmask
- ingenic_gpio_irq_enable
- ingenic_gpio_irq_disable
- ingenic_gpio_irq_ack
- ingenic_gpio_irq_set_type
- ingenic_gpio_irq_set_wake
- ingenic_gpio_irq_handler
- ingenic_gpio_set
- ingenic_gpio_get
- ingenic_gpio_direction_input
- ingenic_gpio_direction_output
- ingenic_config_pin
- ingenic_shadow_config_pin
- ingenic_shadow_config_pin_load
- ingenic_get_pin_config
- ingenic_gpio_get_direction
- ingenic_pinmux_set_pin_fn
- ingenic_pinmux_set_mux
- ingenic_pinmux_gpio_set_direction
- ingenic_pinconf_get
- ingenic_set_bias
- ingenic_pinconf_set
- ingenic_pinconf_group_get
- ingenic_pinconf_group_set
- ingenic_gpio_probe
- ingenic_pinctrl_probe
- ingenic_pinctrl_drv_register
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8
9 #include <linux/compiler.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/of_device.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <linux/pinctrl/pinctrl.h>
17 #include <linux/pinctrl/pinmux.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23
24 #include "core.h"
25 #include "pinconf.h"
26 #include "pinmux.h"
27
28 #define GPIO_PIN 0x00
29 #define GPIO_MSK 0x20
30
31 #define JZ4740_GPIO_DATA 0x10
32 #define JZ4740_GPIO_PULL_DIS 0x30
33 #define JZ4740_GPIO_FUNC 0x40
34 #define JZ4740_GPIO_SELECT 0x50
35 #define JZ4740_GPIO_DIR 0x60
36 #define JZ4740_GPIO_TRIG 0x70
37 #define JZ4740_GPIO_FLAG 0x80
38
39 #define JZ4760_GPIO_INT 0x10
40 #define JZ4760_GPIO_PAT1 0x30
41 #define JZ4760_GPIO_PAT0 0x40
42 #define JZ4760_GPIO_FLAG 0x50
43 #define JZ4760_GPIO_PEN 0x70
44
45 #define X1000_GPIO_PZ_BASE 0x700
46 #define X1000_GPIO_PZ_GID2LD 0x7f0
47
48 #define REG_SET(x) ((x) + 0x4)
49 #define REG_CLEAR(x) ((x) + 0x8)
50
51 #define PINS_PER_GPIO_CHIP 32
52
53 enum jz_version {
54 ID_JZ4740,
55 ID_JZ4725B,
56 ID_JZ4760,
57 ID_JZ4760B,
58 ID_JZ4770,
59 ID_JZ4780,
60 ID_X1000,
61 ID_X1000E,
62 ID_X1500,
63 };
64
65 struct ingenic_chip_info {
66 unsigned int num_chips;
67
68 const struct group_desc *groups;
69 unsigned int num_groups;
70
71 const struct function_desc *functions;
72 unsigned int num_functions;
73
74 const u32 *pull_ups, *pull_downs;
75 };
76
77 struct ingenic_pinctrl {
78 struct device *dev;
79 struct regmap *map;
80 struct pinctrl_dev *pctl;
81 struct pinctrl_pin_desc *pdesc;
82 enum jz_version version;
83
84 const struct ingenic_chip_info *info;
85 };
86
87 struct ingenic_gpio_chip {
88 struct ingenic_pinctrl *jzpc;
89 struct gpio_chip gc;
90 struct irq_chip irq_chip;
91 unsigned int irq, reg_base;
92 };
93
94 static const u32 jz4740_pull_ups[4] = {
95 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
96 };
97
98 static const u32 jz4740_pull_downs[4] = {
99 0x00000000, 0x00000000, 0x00000000, 0x00000000,
100 };
101
102 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
103 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
104 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
105 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
106 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
107 static int jz4740_lcd_8bit_pins[] = {
108 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54,
109 };
110 static int jz4740_lcd_16bit_pins[] = {
111 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55,
112 };
113 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
114 static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, };
115 static int jz4740_nand_cs1_pins[] = { 0x39, };
116 static int jz4740_nand_cs2_pins[] = { 0x3a, };
117 static int jz4740_nand_cs3_pins[] = { 0x3b, };
118 static int jz4740_nand_cs4_pins[] = { 0x3c, };
119 static int jz4740_pwm_pwm0_pins[] = { 0x77, };
120 static int jz4740_pwm_pwm1_pins[] = { 0x78, };
121 static int jz4740_pwm_pwm2_pins[] = { 0x79, };
122 static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
123 static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
124 static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
125 static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
126 static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
127
128 static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, };
129 static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, };
130 static int jz4740_uart0_data_funcs[] = { 1, 1, };
131 static int jz4740_uart0_hwflow_funcs[] = { 1, 1, };
132 static int jz4740_uart1_data_funcs[] = { 2, 2, };
133 static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
134 static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, };
135 static int jz4740_lcd_18bit_funcs[] = { 0, 0, };
136 static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, };
137 static int jz4740_nand_cs1_funcs[] = { 0, };
138 static int jz4740_nand_cs2_funcs[] = { 0, };
139 static int jz4740_nand_cs3_funcs[] = { 0, };
140 static int jz4740_nand_cs4_funcs[] = { 0, };
141 static int jz4740_pwm_pwm0_funcs[] = { 0, };
142 static int jz4740_pwm_pwm1_funcs[] = { 0, };
143 static int jz4740_pwm_pwm2_funcs[] = { 0, };
144 static int jz4740_pwm_pwm3_funcs[] = { 0, };
145 static int jz4740_pwm_pwm4_funcs[] = { 0, };
146 static int jz4740_pwm_pwm5_funcs[] = { 0, };
147 static int jz4740_pwm_pwm6_funcs[] = { 0, };
148 static int jz4740_pwm_pwm7_funcs[] = { 0, };
149
150 #define INGENIC_PIN_GROUP(name, id) \
151 { \
152 name, \
153 id##_pins, \
154 ARRAY_SIZE(id##_pins), \
155 id##_funcs, \
156 }
157
158 static const struct group_desc jz4740_groups[] = {
159 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit),
160 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit),
161 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data),
162 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow),
163 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data),
164 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit),
165 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit),
166 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit),
167 INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft),
168 { "lcd-no-pins", },
169 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1),
170 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2),
171 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3),
172 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4),
173 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0),
174 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1),
175 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2),
176 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3),
177 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4),
178 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5),
179 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6),
180 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7),
181 };
182
183 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
184 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
185 static const char *jz4740_uart1_groups[] = { "uart1-data", };
186 static const char *jz4740_lcd_groups[] = {
187 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
188 };
189 static const char *jz4740_nand_groups[] = {
190 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
191 };
192 static const char *jz4740_pwm0_groups[] = { "pwm0", };
193 static const char *jz4740_pwm1_groups[] = { "pwm1", };
194 static const char *jz4740_pwm2_groups[] = { "pwm2", };
195 static const char *jz4740_pwm3_groups[] = { "pwm3", };
196 static const char *jz4740_pwm4_groups[] = { "pwm4", };
197 static const char *jz4740_pwm5_groups[] = { "pwm5", };
198 static const char *jz4740_pwm6_groups[] = { "pwm6", };
199 static const char *jz4740_pwm7_groups[] = { "pwm7", };
200
201 static const struct function_desc jz4740_functions[] = {
202 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
203 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
204 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
205 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
206 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
207 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
208 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
209 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
210 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
211 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
212 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
213 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
214 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
215 };
216
217 static const struct ingenic_chip_info jz4740_chip_info = {
218 .num_chips = 4,
219 .groups = jz4740_groups,
220 .num_groups = ARRAY_SIZE(jz4740_groups),
221 .functions = jz4740_functions,
222 .num_functions = ARRAY_SIZE(jz4740_functions),
223 .pull_ups = jz4740_pull_ups,
224 .pull_downs = jz4740_pull_downs,
225 };
226
227 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
228 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
229 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
230 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
231 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
232 static int jz4725b_nand_cs1_pins[] = { 0x55, };
233 static int jz4725b_nand_cs2_pins[] = { 0x56, };
234 static int jz4725b_nand_cs3_pins[] = { 0x57, };
235 static int jz4725b_nand_cs4_pins[] = { 0x58, };
236 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
237 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
238 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
239 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
240 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
241 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
242 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
243 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
244 static int jz4725b_lcd_8bit_pins[] = {
245 0x72, 0x73, 0x74,
246 0x60, 0x61, 0x62, 0x63,
247 0x64, 0x65, 0x66, 0x67,
248 };
249 static int jz4725b_lcd_16bit_pins[] = {
250 0x68, 0x69, 0x6a, 0x6b,
251 0x6c, 0x6d, 0x6e, 0x6f,
252 };
253 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
254 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
255 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
256 static int jz4725b_lcd_generic_pins[] = { 0x75, };
257
258 static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, };
259 static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
260 static int jz4725b_mmc1_1bit_funcs[] = { 0, 0, 0, };
261 static int jz4725b_mmc1_4bit_funcs[] = { 0, 0, 0, };
262 static int jz4725b_uart_data_funcs[] = { 1, 1, };
263 static int jz4725b_nand_cs1_funcs[] = { 0, };
264 static int jz4725b_nand_cs2_funcs[] = { 0, };
265 static int jz4725b_nand_cs3_funcs[] = { 0, };
266 static int jz4725b_nand_cs4_funcs[] = { 0, };
267 static int jz4725b_nand_cle_ale_funcs[] = { 0, 0, };
268 static int jz4725b_nand_fre_fwe_funcs[] = { 0, 0, };
269 static int jz4725b_pwm_pwm0_funcs[] = { 0, };
270 static int jz4725b_pwm_pwm1_funcs[] = { 0, };
271 static int jz4725b_pwm_pwm2_funcs[] = { 0, };
272 static int jz4725b_pwm_pwm3_funcs[] = { 0, };
273 static int jz4725b_pwm_pwm4_funcs[] = { 0, };
274 static int jz4725b_pwm_pwm5_funcs[] = { 0, };
275 static int jz4725b_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
276 static int jz4725b_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
277 static int jz4725b_lcd_18bit_funcs[] = { 0, 0, };
278 static int jz4725b_lcd_24bit_funcs[] = { 1, 1, 1, 1, };
279 static int jz4725b_lcd_special_funcs[] = { 0, 0, 0, 0, };
280 static int jz4725b_lcd_generic_funcs[] = { 0, };
281
282 static const struct group_desc jz4725b_groups[] = {
283 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit),
284 INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit),
285 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit),
286 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit),
287 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data),
288 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1),
289 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2),
290 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3),
291 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4),
292 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale),
293 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe),
294 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0),
295 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1),
296 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2),
297 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3),
298 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4),
299 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5),
300 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit),
301 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit),
302 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit),
303 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit),
304 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special),
305 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic),
306 };
307
308 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
309 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
310 static const char *jz4725b_uart_groups[] = { "uart-data", };
311 static const char *jz4725b_nand_groups[] = {
312 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
313 "nand-cle-ale", "nand-fre-fwe",
314 };
315 static const char *jz4725b_pwm0_groups[] = { "pwm0", };
316 static const char *jz4725b_pwm1_groups[] = { "pwm1", };
317 static const char *jz4725b_pwm2_groups[] = { "pwm2", };
318 static const char *jz4725b_pwm3_groups[] = { "pwm3", };
319 static const char *jz4725b_pwm4_groups[] = { "pwm4", };
320 static const char *jz4725b_pwm5_groups[] = { "pwm5", };
321 static const char *jz4725b_lcd_groups[] = {
322 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
323 "lcd-special", "lcd-generic",
324 };
325
326 static const struct function_desc jz4725b_functions[] = {
327 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
328 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
329 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
330 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
331 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
332 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
333 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
334 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
335 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
336 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
337 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
338 };
339
340 static const struct ingenic_chip_info jz4725b_chip_info = {
341 .num_chips = 4,
342 .groups = jz4725b_groups,
343 .num_groups = ARRAY_SIZE(jz4725b_groups),
344 .functions = jz4725b_functions,
345 .num_functions = ARRAY_SIZE(jz4725b_functions),
346 .pull_ups = jz4740_pull_ups,
347 .pull_downs = jz4740_pull_downs,
348 };
349
350 static const u32 jz4760_pull_ups[6] = {
351 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f,
352 };
353
354 static const u32 jz4760_pull_downs[6] = {
355 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
356 };
357
358 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
359 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
360 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
361 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
362 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
363 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
364 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
365 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
366 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
367 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
368 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
369 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
370 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
371 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
372 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
373 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
374 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
375 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
376 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
377 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
378 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
379 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
380 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
381 static int jz4760_nemc_8bit_data_pins[] = {
382 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
383 };
384 static int jz4760_nemc_16bit_data_pins[] = {
385 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
386 };
387 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
388 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
389 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
390 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
391 static int jz4760_nemc_wait_pins[] = { 0x1b, };
392 static int jz4760_nemc_cs1_pins[] = { 0x15, };
393 static int jz4760_nemc_cs2_pins[] = { 0x16, };
394 static int jz4760_nemc_cs3_pins[] = { 0x17, };
395 static int jz4760_nemc_cs4_pins[] = { 0x18, };
396 static int jz4760_nemc_cs5_pins[] = { 0x19, };
397 static int jz4760_nemc_cs6_pins[] = { 0x1a, };
398 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
399 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
400 static int jz4760_cim_pins[] = {
401 0x26, 0x27, 0x28, 0x29,
402 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
403 };
404 static int jz4760_lcd_24bit_pins[] = {
405 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
406 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
407 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
408 0x58, 0x59, 0x5a, 0x5b,
409 };
410 static int jz4760_pwm_pwm0_pins[] = { 0x80, };
411 static int jz4760_pwm_pwm1_pins[] = { 0x81, };
412 static int jz4760_pwm_pwm2_pins[] = { 0x82, };
413 static int jz4760_pwm_pwm3_pins[] = { 0x83, };
414 static int jz4760_pwm_pwm4_pins[] = { 0x84, };
415 static int jz4760_pwm_pwm5_pins[] = { 0x85, };
416 static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
417 static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
418
419 static int jz4760_uart0_data_funcs[] = { 0, 0, };
420 static int jz4760_uart0_hwflow_funcs[] = { 0, 0, };
421 static int jz4760_uart1_data_funcs[] = { 0, 0, };
422 static int jz4760_uart1_hwflow_funcs[] = { 0, 0, };
423 static int jz4760_uart2_data_funcs[] = { 0, 0, };
424 static int jz4760_uart2_hwflow_funcs[] = { 0, 0, };
425 static int jz4760_uart3_data_funcs[] = { 0, 1, };
426 static int jz4760_uart3_hwflow_funcs[] = { 0, 0, };
427 static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
428 static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
429 static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
430 static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
431 static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
432 static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
433 static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
434 static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
435 static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
436 static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
437 static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
438 static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
439 static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
440 static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
441 static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
442 static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
443 static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
444 static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, };
445 static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, };
446 static int jz4760_nemc_rd_we_funcs[] = { 0, 0, };
447 static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, };
448 static int jz4760_nemc_wait_funcs[] = { 0, };
449 static int jz4760_nemc_cs1_funcs[] = { 0, };
450 static int jz4760_nemc_cs2_funcs[] = { 0, };
451 static int jz4760_nemc_cs3_funcs[] = { 0, };
452 static int jz4760_nemc_cs4_funcs[] = { 0, };
453 static int jz4760_nemc_cs5_funcs[] = { 0, };
454 static int jz4760_nemc_cs6_funcs[] = { 0, };
455 static int jz4760_i2c0_funcs[] = { 0, 0, };
456 static int jz4760_i2c1_funcs[] = { 0, 0, };
457 static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
458 static int jz4760_lcd_24bit_funcs[] = {
459 0, 0, 0, 0, 0, 0, 0, 0,
460 0, 0, 0, 0, 0, 0, 0, 0,
461 0, 0, 0, 0, 0, 0, 0, 0,
462 0, 0, 0, 0,
463 };
464 static int jz4760_pwm_pwm0_funcs[] = { 0, };
465 static int jz4760_pwm_pwm1_funcs[] = { 0, };
466 static int jz4760_pwm_pwm2_funcs[] = { 0, };
467 static int jz4760_pwm_pwm3_funcs[] = { 0, };
468 static int jz4760_pwm_pwm4_funcs[] = { 0, };
469 static int jz4760_pwm_pwm5_funcs[] = { 0, };
470 static int jz4760_pwm_pwm6_funcs[] = { 0, };
471 static int jz4760_pwm_pwm7_funcs[] = { 0, };
472
473 static const struct group_desc jz4760_groups[] = {
474 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data),
475 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow),
476 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data),
477 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow),
478 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data),
479 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow),
480 INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data),
481 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow),
482 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a),
483 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a),
484 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e),
485 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e),
486 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e),
487 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d),
488 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d),
489 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e),
490 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e),
491 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e),
492 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b),
493 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b),
494 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e),
495 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e),
496 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e),
497 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data),
498 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data),
499 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale),
500 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr),
501 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we),
502 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe),
503 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait),
504 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1),
505 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2),
506 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3),
507 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4),
508 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5),
509 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6),
510 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0),
511 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1),
512 INGENIC_PIN_GROUP("cim-data", jz4760_cim),
513 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit),
514 { "lcd-no-pins", },
515 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0),
516 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1),
517 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2),
518 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3),
519 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4),
520 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5),
521 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6),
522 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7),
523 };
524
525 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
526 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
527 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
528 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
529 static const char *jz4760_mmc0_groups[] = {
530 "mmc0-1bit-a", "mmc0-4bit-a",
531 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
532 };
533 static const char *jz4760_mmc1_groups[] = {
534 "mmc1-1bit-d", "mmc1-4bit-d",
535 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
536 };
537 static const char *jz4760_mmc2_groups[] = {
538 "mmc2-1bit-b", "mmc2-4bit-b",
539 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
540 };
541 static const char *jz4760_nemc_groups[] = {
542 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
543 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
544 };
545 static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
546 static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
547 static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
548 static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
549 static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
550 static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
551 static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
552 static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
553 static const char *jz4760_cim_groups[] = { "cim-data", };
554 static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
555 static const char *jz4760_pwm0_groups[] = { "pwm0", };
556 static const char *jz4760_pwm1_groups[] = { "pwm1", };
557 static const char *jz4760_pwm2_groups[] = { "pwm2", };
558 static const char *jz4760_pwm3_groups[] = { "pwm3", };
559 static const char *jz4760_pwm4_groups[] = { "pwm4", };
560 static const char *jz4760_pwm5_groups[] = { "pwm5", };
561 static const char *jz4760_pwm6_groups[] = { "pwm6", };
562 static const char *jz4760_pwm7_groups[] = { "pwm7", };
563
564 static const struct function_desc jz4760_functions[] = {
565 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
566 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
567 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
568 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
569 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
570 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
571 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
572 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
573 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
574 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
575 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
576 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
577 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
578 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
579 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
580 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
581 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
582 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
583 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
584 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
585 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
586 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
587 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
588 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
589 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
590 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
591 };
592
593 static const struct ingenic_chip_info jz4760_chip_info = {
594 .num_chips = 6,
595 .groups = jz4760_groups,
596 .num_groups = ARRAY_SIZE(jz4760_groups),
597 .functions = jz4760_functions,
598 .num_functions = ARRAY_SIZE(jz4760_functions),
599 .pull_ups = jz4760_pull_ups,
600 .pull_downs = jz4760_pull_downs,
601 };
602
603 static const struct ingenic_chip_info jz4760b_chip_info = {
604 .num_chips = 6,
605 .groups = jz4760_groups,
606 .num_groups = ARRAY_SIZE(jz4760_groups),
607 .functions = jz4760_functions,
608 .num_functions = ARRAY_SIZE(jz4760_functions),
609 .pull_ups = jz4760_pull_ups,
610 .pull_downs = jz4760_pull_downs,
611 };
612
613 static const u32 jz4770_pull_ups[6] = {
614 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f,
615 };
616
617 static const u32 jz4770_pull_downs[6] = {
618 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
619 };
620
621 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
622 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
623 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
624 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
625 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
626 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
627 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
628 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
629 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
630 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
631 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
632 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
633 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
634 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
635 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
636 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
637 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
638 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
639 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
640 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
641 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
642 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
643 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
644 static int jz4770_nemc_8bit_data_pins[] = {
645 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
646 };
647 static int jz4770_nemc_16bit_data_pins[] = {
648 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
649 };
650 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
651 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
652 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
653 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
654 static int jz4770_nemc_wait_pins[] = { 0x1b, };
655 static int jz4770_nemc_cs1_pins[] = { 0x15, };
656 static int jz4770_nemc_cs2_pins[] = { 0x16, };
657 static int jz4770_nemc_cs3_pins[] = { 0x17, };
658 static int jz4770_nemc_cs4_pins[] = { 0x18, };
659 static int jz4770_nemc_cs5_pins[] = { 0x19, };
660 static int jz4770_nemc_cs6_pins[] = { 0x1a, };
661 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
662 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
663 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
664 static int jz4770_cim_8bit_pins[] = {
665 0x26, 0x27, 0x28, 0x29,
666 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
667 };
668 static int jz4770_cim_12bit_pins[] = {
669 0x32, 0x33, 0xb0, 0xb1,
670 };
671 static int jz4770_lcd_24bit_pins[] = {
672 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
673 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
674 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
675 0x58, 0x59, 0x5a, 0x5b,
676 };
677 static int jz4770_pwm_pwm0_pins[] = { 0x80, };
678 static int jz4770_pwm_pwm1_pins[] = { 0x81, };
679 static int jz4770_pwm_pwm2_pins[] = { 0x82, };
680 static int jz4770_pwm_pwm3_pins[] = { 0x83, };
681 static int jz4770_pwm_pwm4_pins[] = { 0x84, };
682 static int jz4770_pwm_pwm5_pins[] = { 0x85, };
683 static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
684 static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
685 static int jz4770_mac_rmii_pins[] = {
686 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
687 };
688 static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
689
690 static int jz4770_uart0_data_funcs[] = { 0, 0, };
691 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
692 static int jz4770_uart1_data_funcs[] = { 0, 0, };
693 static int jz4770_uart1_hwflow_funcs[] = { 0, 0, };
694 static int jz4770_uart2_data_funcs[] = { 0, 0, };
695 static int jz4770_uart2_hwflow_funcs[] = { 0, 0, };
696 static int jz4770_uart3_data_funcs[] = { 0, 1, };
697 static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
698 static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
699 static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
700 static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
701 static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
702 static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
703 static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
704 static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
705 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
706 static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
707 static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
708 static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
709 static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
710 static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
711 static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
712 static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
713 static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
714 static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
715 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
716 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
717 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
718 static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
719 static int jz4770_nemc_wait_funcs[] = { 0, };
720 static int jz4770_nemc_cs1_funcs[] = { 0, };
721 static int jz4770_nemc_cs2_funcs[] = { 0, };
722 static int jz4770_nemc_cs3_funcs[] = { 0, };
723 static int jz4770_nemc_cs4_funcs[] = { 0, };
724 static int jz4770_nemc_cs5_funcs[] = { 0, };
725 static int jz4770_nemc_cs6_funcs[] = { 0, };
726 static int jz4770_i2c0_funcs[] = { 0, 0, };
727 static int jz4770_i2c1_funcs[] = { 0, 0, };
728 static int jz4770_i2c2_funcs[] = { 2, 2, };
729 static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
730 static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, };
731 static int jz4770_lcd_24bit_funcs[] = {
732 0, 0, 0, 0, 0, 0, 0, 0,
733 0, 0, 0, 0, 0, 0, 0, 0,
734 0, 0, 0, 0, 0, 0, 0, 0,
735 0, 0, 0, 0,
736 };
737 static int jz4770_pwm_pwm0_funcs[] = { 0, };
738 static int jz4770_pwm_pwm1_funcs[] = { 0, };
739 static int jz4770_pwm_pwm2_funcs[] = { 0, };
740 static int jz4770_pwm_pwm3_funcs[] = { 0, };
741 static int jz4770_pwm_pwm4_funcs[] = { 0, };
742 static int jz4770_pwm_pwm5_funcs[] = { 0, };
743 static int jz4770_pwm_pwm6_funcs[] = { 0, };
744 static int jz4770_pwm_pwm7_funcs[] = { 0, };
745 static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
746 static int jz4770_mac_mii_funcs[] = { 0, 0, };
747
748 static const struct group_desc jz4770_groups[] = {
749 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
750 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
751 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
752 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
753 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data),
754 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
755 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
756 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
757 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
758 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
759 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
760 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
761 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e),
762 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
763 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
764 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
765 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
766 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
767 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
768 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
769 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
770 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
771 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e),
772 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
773 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
774 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
775 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
776 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
777 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
778 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
779 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
780 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
781 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
782 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
783 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
784 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
785 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
786 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
787 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
788 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit),
789 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit),
790 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
791 { "lcd-no-pins", },
792 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
793 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
794 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
795 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
796 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
797 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
798 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
799 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
800 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii),
801 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
802 };
803
804 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
805 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
806 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
807 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
808 static const char *jz4770_mmc0_groups[] = {
809 "mmc0-1bit-a", "mmc0-4bit-a",
810 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
811 };
812 static const char *jz4770_mmc1_groups[] = {
813 "mmc1-1bit-d", "mmc1-4bit-d",
814 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
815 };
816 static const char *jz4770_mmc2_groups[] = {
817 "mmc2-1bit-b", "mmc2-4bit-b",
818 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
819 };
820 static const char *jz4770_nemc_groups[] = {
821 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
822 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
823 };
824 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
825 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
826 static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
827 static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
828 static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
829 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
830 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
831 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
832 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
833 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
834 static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
835 static const char *jz4770_pwm0_groups[] = { "pwm0", };
836 static const char *jz4770_pwm1_groups[] = { "pwm1", };
837 static const char *jz4770_pwm2_groups[] = { "pwm2", };
838 static const char *jz4770_pwm3_groups[] = { "pwm3", };
839 static const char *jz4770_pwm4_groups[] = { "pwm4", };
840 static const char *jz4770_pwm5_groups[] = { "pwm5", };
841 static const char *jz4770_pwm6_groups[] = { "pwm6", };
842 static const char *jz4770_pwm7_groups[] = { "pwm7", };
843 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
844
845 static const struct function_desc jz4770_functions[] = {
846 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
847 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
848 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
849 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
850 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
851 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
852 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
853 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
854 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
855 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
856 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
857 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
858 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
859 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
860 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
861 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
862 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
863 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
864 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
865 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
866 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
867 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
868 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
869 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
870 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
871 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
872 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
873 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
874 };
875
876 static const struct ingenic_chip_info jz4770_chip_info = {
877 .num_chips = 6,
878 .groups = jz4770_groups,
879 .num_groups = ARRAY_SIZE(jz4770_groups),
880 .functions = jz4770_functions,
881 .num_functions = ARRAY_SIZE(jz4770_functions),
882 .pull_ups = jz4770_pull_ups,
883 .pull_downs = jz4770_pull_downs,
884 };
885
886 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
887 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
888 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
889 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
890 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
891 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
892 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
893
894 static int jz4780_uart2_data_funcs[] = { 1, 1, };
895 static int jz4780_uart2_hwflow_funcs[] = { 1, 1, };
896 static int jz4780_uart4_data_funcs[] = { 2, 2, };
897 static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
898 static int jz4780_i2c3_funcs[] = { 1, 1, };
899 static int jz4780_i2c4_e_funcs[] = { 1, 1, };
900 static int jz4780_i2c4_f_funcs[] = { 1, 1, };
901
902 static const struct group_desc jz4780_groups[] = {
903 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
904 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
905 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
906 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
907 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data),
908 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow),
909 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
910 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
911 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data),
912 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
913 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
914 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a),
915 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
916 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
917 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
918 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
919 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
920 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
921 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
922 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
923 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
924 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
925 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
926 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
927 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
928 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
929 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
930 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
931 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
932 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
933 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
934 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
935 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
936 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
937 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
938 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
939 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
940 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
941 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
942 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
943 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
944 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
945 { "lcd-no-pins", },
946 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
947 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
948 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
949 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
950 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
951 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
952 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
953 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
954 };
955
956 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
957 static const char *jz4780_uart4_groups[] = { "uart4-data", };
958 static const char *jz4780_mmc0_groups[] = {
959 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
960 "mmc0-1bit-e", "mmc0-4bit-e",
961 };
962 static const char *jz4780_mmc1_groups[] = {
963 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
964 };
965 static const char *jz4780_mmc2_groups[] = {
966 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
967 };
968 static const char *jz4780_nemc_groups[] = {
969 "nemc-data", "nemc-cle-ale", "nemc-addr",
970 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
971 };
972 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
973 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
974 static const char *jz4780_cim_groups[] = { "cim-data", };
975
976 static const struct function_desc jz4780_functions[] = {
977 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
978 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
979 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
980 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
981 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
982 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
983 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
984 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
985 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
986 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
987 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
988 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
989 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
990 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
991 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
992 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
993 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
994 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
995 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
996 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
997 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
998 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
999 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1000 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1001 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1002 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1003 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1004 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1005 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1006 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
1007 };
1008
1009 static const struct ingenic_chip_info jz4780_chip_info = {
1010 .num_chips = 6,
1011 .groups = jz4780_groups,
1012 .num_groups = ARRAY_SIZE(jz4780_groups),
1013 .functions = jz4780_functions,
1014 .num_functions = ARRAY_SIZE(jz4780_functions),
1015 .pull_ups = jz4770_pull_ups,
1016 .pull_downs = jz4770_pull_downs,
1017 };
1018
1019 static const u32 x1000_pull_ups[4] = {
1020 0xffffffff, 0x8dffffff, 0x7d3fffff, 0xffffffff,
1021 };
1022
1023 static const u32 x1000_pull_downs[4] = {
1024 0x00000000, 0x02000000, 0x02000000, 0x00000000,
1025 };
1026
1027 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
1028 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1029 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
1030 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
1031 static int x1000_uart1_hwflow_d_pins[] = { 0x64, 0x65, };
1032 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
1033 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
1034 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
1035 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
1036 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
1037 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
1038 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
1039 static int x1000_nemc_8bit_data_pins[] = {
1040 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1041 };
1042 static int x1000_nemc_16bit_data_pins[] = {
1043 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1044 };
1045 static int x1000_nemc_addr_pins[] = {
1046 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
1047 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
1048 };
1049 static int x1000_nemc_rd_we_pins[] = { 0x30, 0x31, };
1050 static int x1000_nemc_wait_pins[] = { 0x34, };
1051 static int x1000_nemc_cs1_pins[] = { 0x32, };
1052 static int x1000_nemc_cs2_pins[] = { 0x33, };
1053 static int x1000_i2c0_pins[] = { 0x38, 0x37, };
1054 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
1055 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
1056 static int x1000_i2c2_pins[] = { 0x61, 0x60, };
1057 static int x1000_cim_pins[] = {
1058 0x08, 0x09, 0x0a, 0x0b,
1059 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
1060 };
1061 static int x1000_lcd_8bit_pins[] = {
1062 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1063 0x30, 0x31, 0x32, 0x33, 0x34,
1064 };
1065 static int x1000_lcd_16bit_pins[] = {
1066 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1067 };
1068 static int x1000_pwm_pwm0_pins[] = { 0x59, };
1069 static int x1000_pwm_pwm1_pins[] = { 0x5a, };
1070 static int x1000_pwm_pwm2_pins[] = { 0x5b, };
1071 static int x1000_pwm_pwm3_pins[] = { 0x26, };
1072 static int x1000_pwm_pwm4_pins[] = { 0x58, };
1073 static int x1000_mac_pins[] = {
1074 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
1075 };
1076
1077 static int x1000_uart0_data_funcs[] = { 0, 0, };
1078 static int x1000_uart0_hwflow_funcs[] = { 0, 0, };
1079 static int x1000_uart1_data_a_funcs[] = { 2, 2, };
1080 static int x1000_uart1_data_d_funcs[] = { 1, 1, };
1081 static int x1000_uart1_hwflow_d_funcs[] = { 1, 1, };
1082 static int x1000_uart2_data_a_funcs[] = { 2, 2, };
1083 static int x1000_uart2_data_d_funcs[] = { 0, 0, };
1084 static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, };
1085 static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, };
1086 static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, };
1087 static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, };
1088 static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, };
1089 static int x1000_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
1090 static int x1000_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
1091 static int x1000_nemc_addr_funcs[] = {
1092 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1093 };
1094 static int x1000_nemc_rd_we_funcs[] = { 0, 0, };
1095 static int x1000_nemc_wait_funcs[] = { 0, };
1096 static int x1000_nemc_cs1_funcs[] = { 0, };
1097 static int x1000_nemc_cs2_funcs[] = { 0, };
1098 static int x1000_i2c0_funcs[] = { 0, 0, };
1099 static int x1000_i2c1_a_funcs[] = { 2, 2, };
1100 static int x1000_i2c1_c_funcs[] = { 0, 0, };
1101 static int x1000_i2c2_funcs[] = { 1, 1, };
1102 static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
1103 static int x1000_lcd_8bit_funcs[] = {
1104 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1105 };
1106 static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
1107 static int x1000_pwm_pwm0_funcs[] = { 0, };
1108 static int x1000_pwm_pwm1_funcs[] = { 1, };
1109 static int x1000_pwm_pwm2_funcs[] = { 1, };
1110 static int x1000_pwm_pwm3_funcs[] = { 2, };
1111 static int x1000_pwm_pwm4_funcs[] = { 0, };
1112 static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
1113
1114 static const struct group_desc x1000_groups[] = {
1115 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data),
1116 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow),
1117 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a),
1118 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d),
1119 INGENIC_PIN_GROUP("uart1-hwflow-d", x1000_uart1_hwflow_d),
1120 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a),
1121 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d),
1122 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit),
1123 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit),
1124 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit),
1125 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit),
1126 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit),
1127 INGENIC_PIN_GROUP("nemc-8bit-data", x1000_nemc_8bit_data),
1128 INGENIC_PIN_GROUP("nemc-16bit-data", x1000_nemc_16bit_data),
1129 INGENIC_PIN_GROUP("nemc-addr", x1000_nemc_addr),
1130 INGENIC_PIN_GROUP("nemc-rd-we", x1000_nemc_rd_we),
1131 INGENIC_PIN_GROUP("nemc-wait", x1000_nemc_wait),
1132 INGENIC_PIN_GROUP("nemc-cs1", x1000_nemc_cs1),
1133 INGENIC_PIN_GROUP("nemc-cs2", x1000_nemc_cs2),
1134 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0),
1135 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a),
1136 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c),
1137 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2),
1138 INGENIC_PIN_GROUP("cim-data", x1000_cim),
1139 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit),
1140 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit),
1141 { "lcd-no-pins", },
1142 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0),
1143 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1),
1144 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2),
1145 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3),
1146 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4),
1147 INGENIC_PIN_GROUP("mac", x1000_mac),
1148 };
1149
1150 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1151 static const char *x1000_uart1_groups[] = {
1152 "uart1-data-a", "uart1-data-d", "uart1-hwflow-d",
1153 };
1154 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
1155 static const char *x1000_mmc0_groups[] = {
1156 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
1157 };
1158 static const char *x1000_mmc1_groups[] = {
1159 "mmc1-1bit-e", "mmc1-4bit-e",
1160 };
1161 static const char *x1000_nemc_groups[] = {
1162 "nemc-8bit-data", "nemc-16bit-data",
1163 "nemc-addr", "nemc-rd-we", "nemc-wait",
1164 };
1165 static const char *x1000_cs1_groups[] = { "nemc-cs1", };
1166 static const char *x1000_cs2_groups[] = { "nemc-cs2", };
1167 static const char *x1000_i2c0_groups[] = { "i2c0-data", };
1168 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1169 static const char *x1000_i2c2_groups[] = { "i2c2-data", };
1170 static const char *x1000_cim_groups[] = { "cim-data", };
1171 static const char *x1000_lcd_groups[] = {
1172 "lcd-8bit", "lcd-16bit", "lcd-no-pins",
1173 };
1174 static const char *x1000_pwm0_groups[] = { "pwm0", };
1175 static const char *x1000_pwm1_groups[] = { "pwm1", };
1176 static const char *x1000_pwm2_groups[] = { "pwm2", };
1177 static const char *x1000_pwm3_groups[] = { "pwm3", };
1178 static const char *x1000_pwm4_groups[] = { "pwm4", };
1179 static const char *x1000_mac_groups[] = { "mac", };
1180
1181 static const struct function_desc x1000_functions[] = {
1182 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
1183 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
1184 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
1185 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
1186 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
1187 { "nemc", x1000_nemc_groups, ARRAY_SIZE(x1000_nemc_groups), },
1188 { "nemc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
1189 { "nemc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
1190 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
1191 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
1192 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
1193 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
1194 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
1195 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
1196 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
1197 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
1198 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
1199 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
1200 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
1201 };
1202
1203 static const struct ingenic_chip_info x1000_chip_info = {
1204 .num_chips = 4,
1205 .groups = x1000_groups,
1206 .num_groups = ARRAY_SIZE(x1000_groups),
1207 .functions = x1000_functions,
1208 .num_functions = ARRAY_SIZE(x1000_functions),
1209 .pull_ups = x1000_pull_ups,
1210 .pull_downs = x1000_pull_downs,
1211 };
1212
1213 static const struct ingenic_chip_info x1000e_chip_info = {
1214 .num_chips = 4,
1215 .groups = x1000_groups,
1216 .num_groups = ARRAY_SIZE(x1000_groups),
1217 .functions = x1000_functions,
1218 .num_functions = ARRAY_SIZE(x1000_functions),
1219 .pull_ups = x1000_pull_ups,
1220 .pull_downs = x1000_pull_downs,
1221 };
1222
1223 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
1224 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1225 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
1226 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
1227 static int x1500_uart1_hwflow_d_pins[] = { 0x64, 0x65, };
1228 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
1229 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
1230 static int x1500_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
1231 static int x1500_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
1232 static int x1500_i2c0_pins[] = { 0x38, 0x37, };
1233 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
1234 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
1235 static int x1500_i2c2_pins[] = { 0x61, 0x60, };
1236 static int x1500_cim_pins[] = {
1237 0x08, 0x09, 0x0a, 0x0b,
1238 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
1239 };
1240 static int x1500_pwm_pwm0_pins[] = { 0x59, };
1241 static int x1500_pwm_pwm1_pins[] = { 0x5a, };
1242 static int x1500_pwm_pwm2_pins[] = { 0x5b, };
1243 static int x1500_pwm_pwm3_pins[] = { 0x26, };
1244 static int x1500_pwm_pwm4_pins[] = { 0x58, };
1245
1246 static int x1500_uart0_data_funcs[] = { 0, 0, };
1247 static int x1500_uart0_hwflow_funcs[] = { 0, 0, };
1248 static int x1500_uart1_data_a_funcs[] = { 2, 2, };
1249 static int x1500_uart1_data_d_funcs[] = { 1, 1, };
1250 static int x1500_uart1_hwflow_d_funcs[] = { 1, 1, };
1251 static int x1500_uart2_data_a_funcs[] = { 2, 2, };
1252 static int x1500_uart2_data_d_funcs[] = { 0, 0, };
1253 static int x1500_mmc0_1bit_funcs[] = { 1, 1, 1, };
1254 static int x1500_mmc0_4bit_funcs[] = { 1, 1, 1, };
1255 static int x1500_i2c0_funcs[] = { 0, 0, };
1256 static int x1500_i2c1_a_funcs[] = { 2, 2, };
1257 static int x1500_i2c1_c_funcs[] = { 0, 0, };
1258 static int x1500_i2c2_funcs[] = { 1, 1, };
1259 static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
1260 static int x1500_pwm_pwm0_funcs[] = { 0, };
1261 static int x1500_pwm_pwm1_funcs[] = { 1, };
1262 static int x1500_pwm_pwm2_funcs[] = { 1, };
1263 static int x1500_pwm_pwm3_funcs[] = { 2, };
1264 static int x1500_pwm_pwm4_funcs[] = { 0, };
1265
1266 static const struct group_desc x1500_groups[] = {
1267 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data),
1268 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow),
1269 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a),
1270 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d),
1271 INGENIC_PIN_GROUP("uart1-hwflow-d", x1500_uart1_hwflow_d),
1272 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a),
1273 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d),
1274 INGENIC_PIN_GROUP("mmc0-1bit", x1500_mmc0_1bit),
1275 INGENIC_PIN_GROUP("mmc0-4bit", x1500_mmc0_4bit),
1276 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0),
1277 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a),
1278 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c),
1279 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2),
1280 INGENIC_PIN_GROUP("cim-data", x1500_cim),
1281 { "lcd-no-pins", },
1282 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0),
1283 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1),
1284 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2),
1285 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3),
1286 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4),
1287 };
1288
1289 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1290 static const char *x1500_uart1_groups[] = {
1291 "uart1-data-a", "uart1-data-d", "uart1-hwflow-d",
1292 };
1293 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
1294 static const char *x1500_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
1295 static const char *x1500_i2c0_groups[] = { "i2c0-data", };
1296 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1297 static const char *x1500_i2c2_groups[] = { "i2c2-data", };
1298 static const char *x1500_cim_groups[] = { "cim-data", };
1299 static const char *x1500_lcd_groups[] = { "lcd-no-pins", };
1300 static const char *x1500_pwm0_groups[] = { "pwm0", };
1301 static const char *x1500_pwm1_groups[] = { "pwm1", };
1302 static const char *x1500_pwm2_groups[] = { "pwm2", };
1303 static const char *x1500_pwm3_groups[] = { "pwm3", };
1304 static const char *x1500_pwm4_groups[] = { "pwm4", };
1305
1306 static const struct function_desc x1500_functions[] = {
1307 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
1308 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
1309 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
1310 { "mmc0", x1500_mmc0_groups, ARRAY_SIZE(x1500_mmc0_groups), },
1311 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
1312 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
1313 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
1314 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
1315 { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), },
1316 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
1317 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
1318 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
1319 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
1320 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
1321 };
1322
1323 static const struct ingenic_chip_info x1500_chip_info = {
1324 .num_chips = 4,
1325 .groups = x1500_groups,
1326 .num_groups = ARRAY_SIZE(x1500_groups),
1327 .functions = x1500_functions,
1328 .num_functions = ARRAY_SIZE(x1500_functions),
1329 .pull_ups = x1000_pull_ups,
1330 .pull_downs = x1000_pull_downs,
1331 };
1332
1333 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
1334 {
1335 unsigned int val;
1336
1337 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
1338
1339 return (u32) val;
1340 }
1341
1342 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
1343 u8 reg, u8 offset, bool set)
1344 {
1345 if (set)
1346 reg = REG_SET(reg);
1347 else
1348 reg = REG_CLEAR(reg);
1349
1350 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
1351 }
1352
1353 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
1354 u8 reg, u8 offset, bool set)
1355 {
1356 if (set)
1357 reg = REG_SET(reg);
1358 else
1359 reg = REG_CLEAR(reg);
1360
1361 regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_BASE + reg, BIT(offset));
1362 }
1363
1364 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
1365 {
1366 regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_GID2LD,
1367 jzgc->gc.base / PINS_PER_GPIO_CHIP);
1368 }
1369
1370 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
1371 u8 offset)
1372 {
1373 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
1374
1375 return !!(val & BIT(offset));
1376 }
1377
1378 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
1379 u8 offset, int value)
1380 {
1381 if (jzgc->jzpc->version >= ID_JZ4760)
1382 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value);
1383 else
1384 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
1385 }
1386
1387 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
1388 u8 offset, unsigned int type)
1389 {
1390 u8 reg1, reg2;
1391
1392 if (jzgc->jzpc->version >= ID_JZ4760) {
1393 reg1 = JZ4760_GPIO_PAT1;
1394 reg2 = JZ4760_GPIO_PAT0;
1395 } else {
1396 reg1 = JZ4740_GPIO_TRIG;
1397 reg2 = JZ4740_GPIO_DIR;
1398 }
1399
1400 switch (type) {
1401 case IRQ_TYPE_EDGE_RISING:
1402 if (jzgc->jzpc->version >= ID_X1000) {
1403 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true);
1404 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true);
1405 ingenic_gpio_shadow_set_bit_load(jzgc);
1406 } else {
1407 ingenic_gpio_set_bit(jzgc, reg2, offset, true);
1408 ingenic_gpio_set_bit(jzgc, reg1, offset, true);
1409 }
1410 break;
1411 case IRQ_TYPE_EDGE_FALLING:
1412 if (jzgc->jzpc->version >= ID_X1000) {
1413 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false);
1414 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true);
1415 ingenic_gpio_shadow_set_bit_load(jzgc);
1416 } else {
1417 ingenic_gpio_set_bit(jzgc, reg2, offset, false);
1418 ingenic_gpio_set_bit(jzgc, reg1, offset, true);
1419 }
1420 break;
1421 case IRQ_TYPE_LEVEL_HIGH:
1422 if (jzgc->jzpc->version >= ID_X1000) {
1423 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true);
1424 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false);
1425 ingenic_gpio_shadow_set_bit_load(jzgc);
1426 } else {
1427 ingenic_gpio_set_bit(jzgc, reg2, offset, true);
1428 ingenic_gpio_set_bit(jzgc, reg1, offset, false);
1429 }
1430 break;
1431 case IRQ_TYPE_LEVEL_LOW:
1432 default:
1433 if (jzgc->jzpc->version >= ID_X1000) {
1434 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false);
1435 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false);
1436 ingenic_gpio_shadow_set_bit_load(jzgc);
1437 } else {
1438 ingenic_gpio_set_bit(jzgc, reg2, offset, false);
1439 ingenic_gpio_set_bit(jzgc, reg1, offset, false);
1440 }
1441 break;
1442 }
1443 }
1444
1445 static void ingenic_gpio_irq_mask(struct irq_data *irqd)
1446 {
1447 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1448 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1449
1450 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
1451 }
1452
1453 static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
1454 {
1455 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1456 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1457
1458 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
1459 }
1460
1461 static void ingenic_gpio_irq_enable(struct irq_data *irqd)
1462 {
1463 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1464 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1465 int irq = irqd->hwirq;
1466
1467 if (jzgc->jzpc->version >= ID_JZ4760)
1468 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true);
1469 else
1470 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
1471
1472 ingenic_gpio_irq_unmask(irqd);
1473 }
1474
1475 static void ingenic_gpio_irq_disable(struct irq_data *irqd)
1476 {
1477 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1478 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1479 int irq = irqd->hwirq;
1480
1481 ingenic_gpio_irq_mask(irqd);
1482
1483 if (jzgc->jzpc->version >= ID_JZ4760)
1484 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false);
1485 else
1486 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
1487 }
1488
1489 static void ingenic_gpio_irq_ack(struct irq_data *irqd)
1490 {
1491 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1492 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1493 int irq = irqd->hwirq;
1494 bool high;
1495
1496 if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) {
1497
1498
1499
1500
1501 high = ingenic_gpio_get_value(jzgc, irq);
1502 if (high)
1503 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_FALLING);
1504 else
1505 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING);
1506 }
1507
1508 if (jzgc->jzpc->version >= ID_JZ4760)
1509 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false);
1510 else
1511 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
1512 }
1513
1514 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
1515 {
1516 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1517 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1518
1519 switch (type) {
1520 case IRQ_TYPE_EDGE_BOTH:
1521 case IRQ_TYPE_EDGE_RISING:
1522 case IRQ_TYPE_EDGE_FALLING:
1523 irq_set_handler_locked(irqd, handle_edge_irq);
1524 break;
1525 case IRQ_TYPE_LEVEL_HIGH:
1526 case IRQ_TYPE_LEVEL_LOW:
1527 irq_set_handler_locked(irqd, handle_level_irq);
1528 break;
1529 default:
1530 irq_set_handler_locked(irqd, handle_bad_irq);
1531 }
1532
1533 if (type == IRQ_TYPE_EDGE_BOTH) {
1534
1535
1536
1537
1538
1539 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
1540
1541 type = high ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
1542 }
1543
1544 irq_set_type(jzgc, irqd->hwirq, type);
1545 return 0;
1546 }
1547
1548 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
1549 {
1550 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1551 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1552
1553 return irq_set_irq_wake(jzgc->irq, on);
1554 }
1555
1556 static void ingenic_gpio_irq_handler(struct irq_desc *desc)
1557 {
1558 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1559 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1560 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
1561 unsigned long flag, i;
1562
1563 chained_irq_enter(irq_chip, desc);
1564
1565 if (jzgc->jzpc->version >= ID_JZ4760)
1566 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG);
1567 else
1568 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
1569
1570 for_each_set_bit(i, &flag, 32)
1571 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
1572 chained_irq_exit(irq_chip, desc);
1573 }
1574
1575 static void ingenic_gpio_set(struct gpio_chip *gc,
1576 unsigned int offset, int value)
1577 {
1578 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1579
1580 ingenic_gpio_set_value(jzgc, offset, value);
1581 }
1582
1583 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
1584 {
1585 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1586
1587 return (int) ingenic_gpio_get_value(jzgc, offset);
1588 }
1589
1590 static int ingenic_gpio_direction_input(struct gpio_chip *gc,
1591 unsigned int offset)
1592 {
1593 return pinctrl_gpio_direction_input(gc->base + offset);
1594 }
1595
1596 static int ingenic_gpio_direction_output(struct gpio_chip *gc,
1597 unsigned int offset, int value)
1598 {
1599 ingenic_gpio_set(gc, offset, value);
1600 return pinctrl_gpio_direction_output(gc->base + offset);
1601 }
1602
1603 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
1604 unsigned int pin, u8 reg, bool set)
1605 {
1606 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1607 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1608
1609 regmap_write(jzpc->map, offt * 0x100 +
1610 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
1611 }
1612
1613 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
1614 unsigned int pin, u8 reg, bool set)
1615 {
1616 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1617
1618 regmap_write(jzpc->map, X1000_GPIO_PZ_BASE +
1619 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
1620 }
1621
1622 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
1623 unsigned int pin)
1624 {
1625 regmap_write(jzpc->map, X1000_GPIO_PZ_GID2LD, pin / PINS_PER_GPIO_CHIP);
1626 }
1627
1628 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
1629 unsigned int pin, u8 reg)
1630 {
1631 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1632 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1633 unsigned int val;
1634
1635 regmap_read(jzpc->map, offt * 0x100 + reg, &val);
1636
1637 return val & BIT(idx);
1638 }
1639
1640 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1641 {
1642 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1643 struct ingenic_pinctrl *jzpc = jzgc->jzpc;
1644 unsigned int pin = gc->base + offset;
1645
1646 if (jzpc->version >= ID_JZ4760)
1647 return ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1);
1648
1649 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
1650 return true;
1651
1652 return !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR);
1653 }
1654
1655 static const struct pinctrl_ops ingenic_pctlops = {
1656 .get_groups_count = pinctrl_generic_get_group_count,
1657 .get_group_name = pinctrl_generic_get_group_name,
1658 .get_group_pins = pinctrl_generic_get_group_pins,
1659 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
1660 .dt_free_map = pinconf_generic_dt_free_map,
1661 };
1662
1663 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
1664 int pin, int func)
1665 {
1666 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1667 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1668
1669 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
1670 'A' + offt, idx, func);
1671
1672 if (jzpc->version >= ID_X1000) {
1673 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
1674 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
1675 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
1676 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
1677 ingenic_shadow_config_pin_load(jzpc, pin);
1678 } else if (jzpc->version >= ID_JZ4760) {
1679 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
1680 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
1681 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
1682 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
1683 } else {
1684 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
1685 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
1686 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0);
1687 }
1688
1689 return 0;
1690 }
1691
1692 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
1693 unsigned int selector, unsigned int group)
1694 {
1695 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
1696 struct function_desc *func;
1697 struct group_desc *grp;
1698 unsigned int i;
1699
1700 func = pinmux_generic_get_function(pctldev, selector);
1701 if (!func)
1702 return -EINVAL;
1703
1704 grp = pinctrl_generic_get_group(pctldev, group);
1705 if (!grp)
1706 return -EINVAL;
1707
1708 dev_dbg(pctldev->dev, "enable function %s group %s\n",
1709 func->name, grp->name);
1710
1711 for (i = 0; i < grp->num_pins; i++) {
1712 int *pin_modes = grp->data;
1713
1714 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
1715 }
1716
1717 return 0;
1718 }
1719
1720 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
1721 struct pinctrl_gpio_range *range,
1722 unsigned int pin, bool input)
1723 {
1724 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
1725 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1726 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1727
1728 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
1729 'A' + offt, idx, input ? "in" : "out");
1730
1731 if (jzpc->version >= ID_X1000) {
1732 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
1733 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
1734 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
1735 ingenic_shadow_config_pin_load(jzpc, pin);
1736 } else if (jzpc->version >= ID_JZ4760) {
1737 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
1738 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
1739 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
1740 } else {
1741 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
1742 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
1743 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
1744 }
1745
1746 return 0;
1747 }
1748
1749 static const struct pinmux_ops ingenic_pmxops = {
1750 .get_functions_count = pinmux_generic_get_function_count,
1751 .get_function_name = pinmux_generic_get_function_name,
1752 .get_function_groups = pinmux_generic_get_function_groups,
1753 .set_mux = ingenic_pinmux_set_mux,
1754 .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
1755 };
1756
1757 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
1758 unsigned int pin, unsigned long *config)
1759 {
1760 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
1761 enum pin_config_param param = pinconf_to_config_param(*config);
1762 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1763 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1764 bool pull;
1765
1766 if (jzpc->version >= ID_JZ4760)
1767 pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN);
1768 else
1769 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
1770
1771 switch (param) {
1772 case PIN_CONFIG_BIAS_DISABLE:
1773 if (pull)
1774 return -EINVAL;
1775 break;
1776
1777 case PIN_CONFIG_BIAS_PULL_UP:
1778 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))
1779 return -EINVAL;
1780 break;
1781
1782 case PIN_CONFIG_BIAS_PULL_DOWN:
1783 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))
1784 return -EINVAL;
1785 break;
1786
1787 default:
1788 return -ENOTSUPP;
1789 }
1790
1791 *config = pinconf_to_config_packed(param, 1);
1792 return 0;
1793 }
1794
1795 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
1796 unsigned int pin, bool enabled)
1797 {
1798 if (jzpc->version >= ID_JZ4760)
1799 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !enabled);
1800 else
1801 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !enabled);
1802 }
1803
1804 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1805 unsigned long *configs, unsigned int num_configs)
1806 {
1807 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
1808 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1809 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1810 unsigned int cfg;
1811
1812 for (cfg = 0; cfg < num_configs; cfg++) {
1813 switch (pinconf_to_config_param(configs[cfg])) {
1814 case PIN_CONFIG_BIAS_DISABLE:
1815 case PIN_CONFIG_BIAS_PULL_UP:
1816 case PIN_CONFIG_BIAS_PULL_DOWN:
1817 continue;
1818 default:
1819 return -ENOTSUPP;
1820 }
1821 }
1822
1823 for (cfg = 0; cfg < num_configs; cfg++) {
1824 switch (pinconf_to_config_param(configs[cfg])) {
1825 case PIN_CONFIG_BIAS_DISABLE:
1826 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
1827 'A' + offt, idx);
1828 ingenic_set_bias(jzpc, pin, false);
1829 break;
1830
1831 case PIN_CONFIG_BIAS_PULL_UP:
1832 if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
1833 return -EINVAL;
1834 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
1835 'A' + offt, idx);
1836 ingenic_set_bias(jzpc, pin, true);
1837 break;
1838
1839 case PIN_CONFIG_BIAS_PULL_DOWN:
1840 if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
1841 return -EINVAL;
1842 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
1843 'A' + offt, idx);
1844 ingenic_set_bias(jzpc, pin, true);
1845 break;
1846
1847 default:
1848 unreachable();
1849 }
1850 }
1851
1852 return 0;
1853 }
1854
1855 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
1856 unsigned int group, unsigned long *config)
1857 {
1858 const unsigned int *pins;
1859 unsigned int i, npins, old = 0;
1860 int ret;
1861
1862 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1863 if (ret)
1864 return ret;
1865
1866 for (i = 0; i < npins; i++) {
1867 if (ingenic_pinconf_get(pctldev, pins[i], config))
1868 return -ENOTSUPP;
1869
1870
1871 if (i && (old != *config))
1872 return -ENOTSUPP;
1873
1874 old = *config;
1875 }
1876
1877 return 0;
1878 }
1879
1880 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
1881 unsigned int group, unsigned long *configs,
1882 unsigned int num_configs)
1883 {
1884 const unsigned int *pins;
1885 unsigned int i, npins;
1886 int ret;
1887
1888 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1889 if (ret)
1890 return ret;
1891
1892 for (i = 0; i < npins; i++) {
1893 ret = ingenic_pinconf_set(pctldev,
1894 pins[i], configs, num_configs);
1895 if (ret)
1896 return ret;
1897 }
1898
1899 return 0;
1900 }
1901
1902 static const struct pinconf_ops ingenic_confops = {
1903 .is_generic = true,
1904 .pin_config_get = ingenic_pinconf_get,
1905 .pin_config_set = ingenic_pinconf_set,
1906 .pin_config_group_get = ingenic_pinconf_group_get,
1907 .pin_config_group_set = ingenic_pinconf_group_set,
1908 };
1909
1910 static const struct regmap_config ingenic_pinctrl_regmap_config = {
1911 .reg_bits = 32,
1912 .val_bits = 32,
1913 .reg_stride = 4,
1914 };
1915
1916 static const struct of_device_id ingenic_pinctrl_of_match[] = {
1917 { .compatible = "ingenic,jz4740-pinctrl", .data = (void *) ID_JZ4740 },
1918 { .compatible = "ingenic,jz4725b-pinctrl", .data = (void *)ID_JZ4725B },
1919 { .compatible = "ingenic,jz4760-pinctrl", .data = (void *) ID_JZ4760 },
1920 { .compatible = "ingenic,jz4760b-pinctrl", .data = (void *) ID_JZ4760B },
1921 { .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 },
1922 { .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 },
1923 { .compatible = "ingenic,x1000-pinctrl", .data = (void *) ID_X1000 },
1924 { .compatible = "ingenic,x1000e-pinctrl", .data = (void *) ID_X1000E },
1925 { .compatible = "ingenic,x1500-pinctrl", .data = (void *) ID_X1500 },
1926 {},
1927 };
1928
1929 static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
1930 { .compatible = "ingenic,jz4740-gpio", },
1931 { .compatible = "ingenic,jz4760-gpio", },
1932 { .compatible = "ingenic,jz4770-gpio", },
1933 { .compatible = "ingenic,jz4780-gpio", },
1934 { .compatible = "ingenic,x1000-gpio", },
1935 {},
1936 };
1937
1938 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
1939 struct device_node *node)
1940 {
1941 struct ingenic_gpio_chip *jzgc;
1942 struct device *dev = jzpc->dev;
1943 unsigned int bank;
1944 int err;
1945
1946 err = of_property_read_u32(node, "reg", &bank);
1947 if (err) {
1948 dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
1949 return err;
1950 }
1951
1952 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
1953 if (!jzgc)
1954 return -ENOMEM;
1955
1956 jzgc->jzpc = jzpc;
1957 jzgc->reg_base = bank * 0x100;
1958
1959 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
1960 if (!jzgc->gc.label)
1961 return -ENOMEM;
1962
1963
1964
1965
1966
1967 jzgc->gc.base = bank * 32;
1968
1969 jzgc->gc.ngpio = 32;
1970 jzgc->gc.parent = dev;
1971 jzgc->gc.of_node = node;
1972 jzgc->gc.owner = THIS_MODULE;
1973
1974 jzgc->gc.set = ingenic_gpio_set;
1975 jzgc->gc.get = ingenic_gpio_get;
1976 jzgc->gc.direction_input = ingenic_gpio_direction_input;
1977 jzgc->gc.direction_output = ingenic_gpio_direction_output;
1978 jzgc->gc.get_direction = ingenic_gpio_get_direction;
1979
1980 if (of_property_read_bool(node, "gpio-ranges")) {
1981 jzgc->gc.request = gpiochip_generic_request;
1982 jzgc->gc.free = gpiochip_generic_free;
1983 }
1984
1985 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
1986 if (err)
1987 return err;
1988
1989 jzgc->irq = irq_of_parse_and_map(node, 0);
1990 if (!jzgc->irq)
1991 return -EINVAL;
1992
1993 jzgc->irq_chip.name = jzgc->gc.label;
1994 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
1995 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
1996 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
1997 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
1998 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
1999 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
2000 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
2001 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
2002
2003 err = gpiochip_irqchip_add(&jzgc->gc, &jzgc->irq_chip, 0,
2004 handle_level_irq, IRQ_TYPE_NONE);
2005 if (err)
2006 return err;
2007
2008 gpiochip_set_chained_irqchip(&jzgc->gc, &jzgc->irq_chip,
2009 jzgc->irq, ingenic_gpio_irq_handler);
2010 return 0;
2011 }
2012
2013 static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
2014 {
2015 struct device *dev = &pdev->dev;
2016 struct ingenic_pinctrl *jzpc;
2017 struct pinctrl_desc *pctl_desc;
2018 void __iomem *base;
2019 const struct platform_device_id *id = platform_get_device_id(pdev);
2020 const struct of_device_id *of_id = of_match_device(
2021 ingenic_pinctrl_of_match, dev);
2022 const struct ingenic_chip_info *chip_info;
2023 struct device_node *node;
2024 unsigned int i;
2025 int err;
2026
2027 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
2028 if (!jzpc)
2029 return -ENOMEM;
2030
2031 base = devm_ioremap_resource(dev,
2032 platform_get_resource(pdev, IORESOURCE_MEM, 0));
2033 if (IS_ERR(base))
2034 return PTR_ERR(base);
2035
2036 jzpc->map = devm_regmap_init_mmio(dev, base,
2037 &ingenic_pinctrl_regmap_config);
2038 if (IS_ERR(jzpc->map)) {
2039 dev_err(dev, "Failed to create regmap\n");
2040 return PTR_ERR(jzpc->map);
2041 }
2042
2043 jzpc->dev = dev;
2044
2045 if (of_id)
2046 jzpc->version = (enum jz_version)of_id->data;
2047 else
2048 jzpc->version = (enum jz_version)id->driver_data;
2049
2050 if (jzpc->version >= ID_X1500)
2051 chip_info = &x1500_chip_info;
2052 else if (jzpc->version >= ID_X1000E)
2053 chip_info = &x1000e_chip_info;
2054 else if (jzpc->version >= ID_X1000)
2055 chip_info = &x1000_chip_info;
2056 else if (jzpc->version >= ID_JZ4780)
2057 chip_info = &jz4780_chip_info;
2058 else if (jzpc->version >= ID_JZ4770)
2059 chip_info = &jz4770_chip_info;
2060 else if (jzpc->version >= ID_JZ4760B)
2061 chip_info = &jz4760b_chip_info;
2062 else if (jzpc->version >= ID_JZ4760)
2063 chip_info = &jz4760_chip_info;
2064 else if (jzpc->version >= ID_JZ4725B)
2065 chip_info = &jz4725b_chip_info;
2066 else
2067 chip_info = &jz4740_chip_info;
2068 jzpc->info = chip_info;
2069
2070 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
2071 if (!pctl_desc)
2072 return -ENOMEM;
2073
2074
2075 pctl_desc->name = dev_name(dev);
2076 pctl_desc->owner = THIS_MODULE;
2077 pctl_desc->pctlops = &ingenic_pctlops;
2078 pctl_desc->pmxops = &ingenic_pmxops;
2079 pctl_desc->confops = &ingenic_confops;
2080 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
2081 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
2082 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
2083 if (!jzpc->pdesc)
2084 return -ENOMEM;
2085
2086 for (i = 0; i < pctl_desc->npins; i++) {
2087 jzpc->pdesc[i].number = i;
2088 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
2089 'A' + (i / PINS_PER_GPIO_CHIP),
2090 i % PINS_PER_GPIO_CHIP);
2091 }
2092
2093 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
2094 if (IS_ERR(jzpc->pctl)) {
2095 dev_err(dev, "Failed to register pinctrl\n");
2096 return PTR_ERR(jzpc->pctl);
2097 }
2098
2099 for (i = 0; i < chip_info->num_groups; i++) {
2100 const struct group_desc *group = &chip_info->groups[i];
2101
2102 err = pinctrl_generic_add_group(jzpc->pctl, group->name,
2103 group->pins, group->num_pins, group->data);
2104 if (err < 0) {
2105 dev_err(dev, "Failed to register group %s\n",
2106 group->name);
2107 return err;
2108 }
2109 }
2110
2111 for (i = 0; i < chip_info->num_functions; i++) {
2112 const struct function_desc *func = &chip_info->functions[i];
2113
2114 err = pinmux_generic_add_function(jzpc->pctl, func->name,
2115 func->group_names, func->num_group_names,
2116 func->data);
2117 if (err < 0) {
2118 dev_err(dev, "Failed to register function %s\n",
2119 func->name);
2120 return err;
2121 }
2122 }
2123
2124 dev_set_drvdata(dev, jzpc->map);
2125
2126 for_each_child_of_node(dev->of_node, node) {
2127 if (of_match_node(ingenic_gpio_of_match, node)) {
2128 err = ingenic_gpio_probe(jzpc, node);
2129 if (err)
2130 return err;
2131 }
2132 }
2133
2134 return 0;
2135 }
2136
2137 static const struct platform_device_id ingenic_pinctrl_ids[] = {
2138 { "jz4740-pinctrl", ID_JZ4740 },
2139 { "jz4725b-pinctrl", ID_JZ4725B },
2140 { "jz4760-pinctrl", ID_JZ4760 },
2141 { "jz4760b-pinctrl", ID_JZ4760B },
2142 { "jz4770-pinctrl", ID_JZ4770 },
2143 { "jz4780-pinctrl", ID_JZ4780 },
2144 { "x1000-pinctrl", ID_X1000 },
2145 { "x1000e-pinctrl", ID_X1000E },
2146 { "x1500-pinctrl", ID_X1500 },
2147 {},
2148 };
2149
2150 static struct platform_driver ingenic_pinctrl_driver = {
2151 .driver = {
2152 .name = "pinctrl-ingenic",
2153 .of_match_table = of_match_ptr(ingenic_pinctrl_of_match),
2154 },
2155 .id_table = ingenic_pinctrl_ids,
2156 };
2157
2158 static int __init ingenic_pinctrl_drv_register(void)
2159 {
2160 return platform_driver_probe(&ingenic_pinctrl_driver,
2161 ingenic_pinctrl_probe);
2162 }
2163 subsys_initcall(ingenic_pinctrl_drv_register);