drivers/pinctrl/mvebu/pinctrl-armada-37xx.c

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This source file includes following definitions.
armada_37xx_update_reg
armada_37xx_find_next_grp_by_pin
armada_37xx_pin_config_group_get
armada_37xx_pin_config_group_set
armada_37xx_get_groups_count
armada_37xx_get_group_name
armada_37xx_get_group_pins
armada_37xx_pmx_get_funcs_count
armada_37xx_pmx_get_func_name
armada_37xx_pmx_get_groups
armada_37xx_pmx_set_by_name
armada_37xx_pmx_set
armada_37xx_irq_update_reg
armada_37xx_gpio_direction_input
armada_37xx_gpio_get_direction
armada_37xx_gpio_direction_output
armada_37xx_gpio_get
armada_37xx_gpio_set
armada_37xx_pmx_gpio_set_direction
armada_37xx_gpio_request_enable
armada_37xx_irq_ack
armada_37xx_irq_mask
armada_37xx_irq_unmask
armada_37xx_irq_set_wake
armada_37xx_irq_set_type
armada_37xx_edge_both_irq_swap_pol
armada_37xx_irq_handler
armada_37xx_irq_startup
armada_37xx_irqchip_register
armada_37xx_gpiochip_register
armada_37xx_add_function
armada_37xx_fill_group
armada_37xx_fill_func
armada_37xx_pinctrl_register
armada_3700_pinctrl_suspend
armada_3700_pinctrl_resume
armada_37xx_pinctrl_probe
   1 /*
   2  * Marvell 37xx SoC pinctrl driver
   3  *
   4  * Copyright (C) 2017 Marvell
   5  *
   6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2 or later. This program is licensed "as is"
  10  * without any warranty of any kind, whether express or implied.
  11  */
  12 
  13 #include <linux/gpio/driver.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/pinctrl/pinconf-generic.h>
  20 #include <linux/pinctrl/pinconf.h>
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regmap.h>
  25 #include <linux/slab.h>
  26 
  27 #include "../pinctrl-utils.h"
  28 
  29 #define OUTPUT_EN       0x0
  30 #define INPUT_VAL       0x10
  31 #define OUTPUT_VAL      0x18
  32 #define OUTPUT_CTL      0x20
  33 #define SELECTION       0x30
  34 
  35 #define IRQ_EN          0x0
  36 #define IRQ_POL         0x08
  37 #define IRQ_STATUS      0x10
  38 #define IRQ_WKUP        0x18
  39 
  40 #define NB_FUNCS 3
  41 #define GPIO_PER_REG    32
  42 
  43 /**
  44  * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
  45  * The pins of a pinmux groups are composed of one or two groups of contiguous
  46  * pins.
  47  * @name:       Name of the pin group, used to lookup the group.
  48  * @start_pins: Index of the first pin of the main range of pins belonging to
  49  *              the group
  50  * @npins:      Number of pins included in the first range
  51  * @reg_mask:   Bit mask matching the group in the selection register
  52  * @extra_pins: Index of the first pin of the optional second range of pins
  53  *              belonging to the group
  54  * @npins:      Number of pins included in the second optional range
  55  * @funcs:      A list of pinmux functions that can be selected for this group.
  56  * @pins:       List of the pins included in the group
  57  */
  58 struct armada_37xx_pin_group {
  59         const char      *name;
  60         unsigned int    start_pin;
  61         unsigned int    npins;
  62         u32             reg_mask;
  63         u32             val[NB_FUNCS];
  64         unsigned int    extra_pin;
  65         unsigned int    extra_npins;
  66         const char      *funcs[NB_FUNCS];
  67         unsigned int    *pins;
  68 };
  69 
  70 struct armada_37xx_pin_data {
  71         u8                              nr_pins;
  72         char                            *name;
  73         struct armada_37xx_pin_group    *groups;
  74         int                             ngroups;
  75 };
  76 
  77 struct armada_37xx_pmx_func {
  78         const char              *name;
  79         const char              **groups;
  80         unsigned int            ngroups;
  81 };
  82 
  83 struct armada_37xx_pm_state {
  84         u32 out_en_l;
  85         u32 out_en_h;
  86         u32 out_val_l;
  87         u32 out_val_h;
  88         u32 irq_en_l;
  89         u32 irq_en_h;
  90         u32 irq_pol_l;
  91         u32 irq_pol_h;
  92         u32 selection;
  93 };
  94 
  95 struct armada_37xx_pinctrl {
  96         struct regmap                   *regmap;
  97         void __iomem                    *base;
  98         const struct armada_37xx_pin_data       *data;
  99         struct device                   *dev;
 100         struct gpio_chip                gpio_chip;
 101         struct irq_chip                 irq_chip;
 102         spinlock_t                      irq_lock;
 103         struct pinctrl_desc             pctl;
 104         struct pinctrl_dev              *pctl_dev;
 105         struct armada_37xx_pin_group    *groups;
 106         unsigned int                    ngroups;
 107         struct armada_37xx_pmx_func     *funcs;
 108         unsigned int                    nfuncs;
 109         struct armada_37xx_pm_state     pm;
 110 };
 111 
 112 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2)      \
 113         {                                       \
 114                 .name = _name,                  \
 115                 .start_pin = _start,            \
 116                 .npins = _nr,                   \
 117                 .reg_mask = _mask,              \
 118                 .val = {0, _mask},              \
 119                 .funcs = {_func1, _func2}       \
 120         }
 121 
 122 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
 123         {                                       \
 124                 .name = _name,                  \
 125                 .start_pin = _start,            \
 126                 .npins = _nr,                   \
 127                 .reg_mask = _mask,              \
 128                 .val = {0, _mask},              \
 129                 .funcs = {_func1, "gpio"}       \
 130         }
 131 
 132 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1)   \
 133         {                                       \
 134                 .name = _name,                  \
 135                 .start_pin = _start,            \
 136                 .npins = _nr,                   \
 137                 .reg_mask = _mask,              \
 138                 .val = {_val1, _val2},          \
 139                 .funcs = {_func1, "gpio"}       \
 140         }
 141 
 142 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
 143         {                                       \
 144                 .name = _name,                  \
 145                 .start_pin = _start,            \
 146                 .npins = _nr,                   \
 147                 .reg_mask = _mask,              \
 148                 .val = {_v1, _v2, _v3}, \
 149                 .funcs = {_f1, _f2, "gpio"}     \
 150         }
 151 
 152 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
 153                       _f1, _f2)                         \
 154         {                                               \
 155                 .name = _name,                          \
 156                 .start_pin = _start,                    \
 157                 .npins = _nr,                           \
 158                 .reg_mask = _mask,                      \
 159                 .val = {_v1, _v2},                      \
 160                 .extra_pin = _start2,                   \
 161                 .extra_npins = _nr2,                    \
 162                 .funcs = {_f1, _f2}                     \
 163         }
 164 
 165 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
 166         PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
 167         PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
 168         PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
 169         PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
 170         PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
 171         PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
 172         PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
 173         PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
 174         PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
 175         PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
 176         PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
 177         PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
 178         PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
 179         PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
 180         PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
 181         PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
 182         PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
 183         PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
 184                       BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
 185                       18, 2, "gpio", "uart"),
 186         PIN_GRP_GPIO_2("led0_od", 11, 1, BIT(20), BIT(20), 0, "led"),
 187         PIN_GRP_GPIO_2("led1_od", 12, 1, BIT(21), BIT(21), 0, "led"),
 188         PIN_GRP_GPIO_2("led2_od", 13, 1, BIT(22), BIT(22), 0, "led"),
 189         PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"),
 190 
 191 };
 192 
 193 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
 194         PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
 195         PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
 196         PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
 197         PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
 198         PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
 199         PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"),
 200         PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
 201         PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
 202         PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
 203         PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
 204         PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
 205         PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
 206                        "mii", "mii_err"),
 207 };
 208 
 209 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
 210         .nr_pins = 36,
 211         .name = "GPIO1",
 212         .groups = armada_37xx_nb_groups,
 213         .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
 214 };
 215 
 216 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
 217         .nr_pins = 30,
 218         .name = "GPIO2",
 219         .groups = armada_37xx_sb_groups,
 220         .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
 221 };
 222 
 223 static inline void armada_37xx_update_reg(unsigned int *reg,
 224                                           unsigned int *offset)
 225 {
 226         /* We never have more than 2 registers */
 227         if (*offset >= GPIO_PER_REG) {
 228                 *offset -= GPIO_PER_REG;
 229                 *reg += sizeof(u32);
 230         }
 231 }
 232 
 233 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
 234         struct armada_37xx_pinctrl *info, int pin, int *grp)
 235 {
 236         while (*grp < info->ngroups) {
 237                 struct armada_37xx_pin_group *group = &info->groups[*grp];
 238                 int j;
 239 
 240                 *grp = *grp + 1;
 241                 for (j = 0; j < (group->npins + group->extra_npins); j++)
 242                         if (group->pins[j] == pin)
 243                                 return group;
 244         }
 245         return NULL;
 246 }
 247 
 248 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
 249                             unsigned int selector, unsigned long *config)
 250 {
 251         return -ENOTSUPP;
 252 }
 253 
 254 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
 255                             unsigned int selector, unsigned long *configs,
 256                             unsigned int num_configs)
 257 {
 258         return -ENOTSUPP;
 259 }
 260 
 261 static const struct pinconf_ops armada_37xx_pinconf_ops = {
 262         .is_generic = true,
 263         .pin_config_group_get = armada_37xx_pin_config_group_get,
 264         .pin_config_group_set = armada_37xx_pin_config_group_set,
 265 };
 266 
 267 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
 268 {
 269         struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 270 
 271         return info->ngroups;
 272 }
 273 
 274 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
 275                                               unsigned int group)
 276 {
 277         struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 278 
 279         return info->groups[group].name;
 280 }
 281 
 282 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
 283                                       unsigned int selector,
 284                                       const unsigned int **pins,
 285                                       unsigned int *npins)
 286 {
 287         struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 288 
 289         if (selector >= info->ngroups)
 290                 return -EINVAL;
 291 
 292         *pins = info->groups[selector].pins;
 293         *npins = info->groups[selector].npins +
 294                 info->groups[selector].extra_npins;
 295 
 296         return 0;
 297 }
 298 
 299 static const struct pinctrl_ops armada_37xx_pctrl_ops = {
 300         .get_groups_count       = armada_37xx_get_groups_count,
 301         .get_group_name         = armada_37xx_get_group_name,
 302         .get_group_pins         = armada_37xx_get_group_pins,
 303         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 304         .dt_free_map            = pinctrl_utils_free_map,
 305 };
 306 
 307 /*
 308  * Pinmux_ops handling
 309  */
 310 
 311 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 312 {
 313         struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 314 
 315         return info->nfuncs;
 316 }
 317 
 318 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
 319                                                  unsigned int selector)
 320 {
 321         struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 322 
 323         return info->funcs[selector].name;
 324 }
 325 
 326 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
 327                                       unsigned int selector,
 328                                       const char * const **groups,
 329                                       unsigned int * const num_groups)
 330 {
 331         struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 332 
 333         *groups = info->funcs[selector].groups;
 334         *num_groups = info->funcs[selector].ngroups;
 335 
 336         return 0;
 337 }
 338 
 339 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
 340                                        const char *name,
 341                                        struct armada_37xx_pin_group *grp)
 342 {
 343         struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 344         unsigned int reg = SELECTION;
 345         unsigned int mask = grp->reg_mask;
 346         int func, val;
 347 
 348         dev_dbg(info->dev, "enable function %s group %s\n",
 349                 name, grp->name);
 350 
 351         func = match_string(grp->funcs, NB_FUNCS, name);
 352         if (func < 0)
 353                 return -ENOTSUPP;
 354 
 355         val = grp->val[func];
 356 
 357         regmap_update_bits(info->regmap, reg, mask, val);
 358 
 359         return 0;
 360 }
 361 
 362 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
 363                                unsigned int selector,
 364                                unsigned int group)
 365 {
 366 
 367         struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 368         struct armada_37xx_pin_group *grp = &info->groups[group];
 369         const char *name = info->funcs[selector].name;
 370 
 371         return armada_37xx_pmx_set_by_name(pctldev, name, grp);
 372 }
 373 
 374 static inline void armada_37xx_irq_update_reg(unsigned int *reg,
 375                                           struct irq_data *d)
 376 {
 377         int offset = irqd_to_hwirq(d);
 378 
 379         armada_37xx_update_reg(reg, &offset);
 380 }
 381 
 382 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
 383                                             unsigned int offset)
 384 {
 385         struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
 386         unsigned int reg = OUTPUT_EN;
 387         unsigned int mask;
 388 
 389         armada_37xx_update_reg(&reg, &offset);
 390         mask = BIT(offset);
 391 
 392         return regmap_update_bits(info->regmap, reg, mask, 0);
 393 }
 394 
 395 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
 396                                           unsigned int offset)
 397 {
 398         struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
 399         unsigned int reg = OUTPUT_EN;
 400         unsigned int val, mask;
 401 
 402         armada_37xx_update_reg(&reg, &offset);
 403         mask = BIT(offset);
 404         regmap_read(info->regmap, reg, &val);
 405 
 406         return !(val & mask);
 407 }
 408 
 409 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
 410                                              unsigned int offset, int value)
 411 {
 412         struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
 413         unsigned int reg = OUTPUT_EN;
 414         unsigned int mask, val, ret;
 415 
 416         armada_37xx_update_reg(&reg, &offset);
 417         mask = BIT(offset);
 418 
 419         ret = regmap_update_bits(info->regmap, reg, mask, mask);
 420 
 421         if (ret)
 422                 return ret;
 423 
 424         reg = OUTPUT_VAL;
 425         val = value ? mask : 0;
 426         regmap_update_bits(info->regmap, reg, mask, val);
 427 
 428         return 0;
 429 }
 430 
 431 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
 432 {
 433         struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
 434         unsigned int reg = INPUT_VAL;
 435         unsigned int val, mask;
 436 
 437         armada_37xx_update_reg(&reg, &offset);
 438         mask = BIT(offset);
 439 
 440         regmap_read(info->regmap, reg, &val);
 441 
 442         return (val & mask) != 0;
 443 }
 444 
 445 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
 446                                  int value)
 447 {
 448         struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
 449         unsigned int reg = OUTPUT_VAL;
 450         unsigned int mask, val;
 451 
 452         armada_37xx_update_reg(&reg, &offset);
 453         mask = BIT(offset);
 454         val = value ? mask : 0;
 455 
 456         regmap_update_bits(info->regmap, reg, mask, val);
 457 }
 458 
 459 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 460                                               struct pinctrl_gpio_range *range,
 461                                               unsigned int offset, bool input)
 462 {
 463         struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 464         struct gpio_chip *chip = range->gc;
 465 
 466         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 467                 offset, range->name, offset, input ? "input" : "output");
 468 
 469         if (input)
 470                 armada_37xx_gpio_direction_input(chip, offset);
 471         else
 472                 armada_37xx_gpio_direction_output(chip, offset, 0);
 473 
 474         return 0;
 475 }
 476 
 477 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
 478                                            struct pinctrl_gpio_range *range,
 479                                            unsigned int offset)
 480 {
 481         struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 482         struct armada_37xx_pin_group *group;
 483         int grp = 0;
 484 
 485         dev_dbg(info->dev, "requesting gpio %d\n", offset);
 486 
 487         while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
 488                 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
 489 
 490         return 0;
 491 }
 492 
 493 static const struct pinmux_ops armada_37xx_pmx_ops = {
 494         .get_functions_count    = armada_37xx_pmx_get_funcs_count,
 495         .get_function_name      = armada_37xx_pmx_get_func_name,
 496         .get_function_groups    = armada_37xx_pmx_get_groups,
 497         .set_mux                = armada_37xx_pmx_set,
 498         .gpio_request_enable    = armada_37xx_gpio_request_enable,
 499         .gpio_set_direction     = armada_37xx_pmx_gpio_set_direction,
 500 };
 501 
 502 static const struct gpio_chip armada_37xx_gpiolib_chip = {
 503         .request = gpiochip_generic_request,
 504         .free = gpiochip_generic_free,
 505         .set = armada_37xx_gpio_set,
 506         .get = armada_37xx_gpio_get,
 507         .get_direction  = armada_37xx_gpio_get_direction,
 508         .direction_input = armada_37xx_gpio_direction_input,
 509         .direction_output = armada_37xx_gpio_direction_output,
 510         .owner = THIS_MODULE,
 511 };
 512 
 513 static void armada_37xx_irq_ack(struct irq_data *d)
 514 {
 515         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 516         struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
 517         u32 reg = IRQ_STATUS;
 518         unsigned long flags;
 519 
 520         armada_37xx_irq_update_reg(&reg, d);
 521         spin_lock_irqsave(&info->irq_lock, flags);
 522         writel(d->mask, info->base + reg);
 523         spin_unlock_irqrestore(&info->irq_lock, flags);
 524 }
 525 
 526 static void armada_37xx_irq_mask(struct irq_data *d)
 527 {
 528         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 529         struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
 530         u32 val, reg = IRQ_EN;
 531         unsigned long flags;
 532 
 533         armada_37xx_irq_update_reg(&reg, d);
 534         spin_lock_irqsave(&info->irq_lock, flags);
 535         val = readl(info->base + reg);
 536         writel(val & ~d->mask, info->base + reg);
 537         spin_unlock_irqrestore(&info->irq_lock, flags);
 538 }
 539 
 540 static void armada_37xx_irq_unmask(struct irq_data *d)
 541 {
 542         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 543         struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
 544         u32 val, reg = IRQ_EN;
 545         unsigned long flags;
 546 
 547         armada_37xx_irq_update_reg(&reg, d);
 548         spin_lock_irqsave(&info->irq_lock, flags);
 549         val = readl(info->base + reg);
 550         writel(val | d->mask, info->base + reg);
 551         spin_unlock_irqrestore(&info->irq_lock, flags);
 552 }
 553 
 554 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
 555 {
 556         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 557         struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
 558         u32 val, reg = IRQ_WKUP;
 559         unsigned long flags;
 560 
 561         armada_37xx_irq_update_reg(&reg, d);
 562         spin_lock_irqsave(&info->irq_lock, flags);
 563         val = readl(info->base + reg);
 564         if (on)
 565                 val |= (BIT(d->hwirq % GPIO_PER_REG));
 566         else
 567                 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
 568         writel(val, info->base + reg);
 569         spin_unlock_irqrestore(&info->irq_lock, flags);
 570 
 571         return 0;
 572 }
 573 
 574 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
 575 {
 576         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 577         struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
 578         u32 val, reg = IRQ_POL;
 579         unsigned long flags;
 580 
 581         spin_lock_irqsave(&info->irq_lock, flags);
 582         armada_37xx_irq_update_reg(&reg, d);
 583         val = readl(info->base + reg);
 584         switch (type) {
 585         case IRQ_TYPE_EDGE_RISING:
 586                 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
 587                 break;
 588         case IRQ_TYPE_EDGE_FALLING:
 589                 val |= (BIT(d->hwirq % GPIO_PER_REG));
 590                 break;
 591         case IRQ_TYPE_EDGE_BOTH: {
 592                 u32 in_val, in_reg = INPUT_VAL;
 593 
 594                 armada_37xx_irq_update_reg(&in_reg, d);
 595                 regmap_read(info->regmap, in_reg, &in_val);
 596 
 597                 /* Set initial polarity based on current input level. */
 598                 if (in_val & BIT(d->hwirq % GPIO_PER_REG))
 599                         val |= BIT(d->hwirq % GPIO_PER_REG);    /* falling */
 600                 else
 601                         val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */
 602                 break;
 603         }
 604         default:
 605                 spin_unlock_irqrestore(&info->irq_lock, flags);
 606                 return -EINVAL;
 607         }
 608         writel(val, info->base + reg);
 609         spin_unlock_irqrestore(&info->irq_lock, flags);
 610 
 611         return 0;
 612 }
 613 
 614 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
 615                                              u32 pin_idx)
 616 {
 617         u32 reg_idx = pin_idx / GPIO_PER_REG;
 618         u32 bit_num = pin_idx % GPIO_PER_REG;
 619         u32 p, l, ret;
 620         unsigned long flags;
 621 
 622         regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
 623 
 624         spin_lock_irqsave(&info->irq_lock, flags);
 625         p = readl(info->base + IRQ_POL + 4 * reg_idx);
 626         if ((p ^ l) & (1 << bit_num)) {
 627                 /*
 628                  * For the gpios which are used for both-edge irqs, when their
 629                  * interrupts happen, their input levels are changed,
 630                  * yet their interrupt polarities are kept in old values, we
 631                  * should synchronize their interrupt polarities; for example,
 632                  * at first a gpio's input level is low and its interrupt
 633                  * polarity control is "Detect rising edge", then the gpio has
 634                  * a interrupt , its level turns to high, we should change its
 635                  * polarity control to "Detect falling edge" correspondingly.
 636                  */
 637                 p ^= 1 << bit_num;
 638                 writel(p, info->base + IRQ_POL + 4 * reg_idx);
 639                 ret = 0;
 640         } else {
 641                 /* Spurious irq */
 642                 ret = -1;
 643         }
 644 
 645         spin_unlock_irqrestore(&info->irq_lock, flags);
 646         return ret;
 647 }
 648 
 649 static void armada_37xx_irq_handler(struct irq_desc *desc)
 650 {
 651         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 652         struct irq_chip *chip = irq_desc_get_chip(desc);
 653         struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
 654         struct irq_domain *d = gc->irq.domain;
 655         int i;
 656 
 657         chained_irq_enter(chip, desc);
 658         for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
 659                 u32 status;
 660                 unsigned long flags;
 661 
 662                 spin_lock_irqsave(&info->irq_lock, flags);
 663                 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
 664                 /* Manage only the interrupt that was enabled */
 665                 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
 666                 spin_unlock_irqrestore(&info->irq_lock, flags);
 667                 while (status) {
 668                         u32 hwirq = ffs(status) - 1;
 669                         u32 virq = irq_find_mapping(d, hwirq +
 670                                                      i * GPIO_PER_REG);
 671                         u32 t = irq_get_trigger_type(virq);
 672 
 673                         if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 674                                 /* Swap polarity (race with GPIO line) */
 675                                 if (armada_37xx_edge_both_irq_swap_pol(info,
 676                                         hwirq + i * GPIO_PER_REG)) {
 677                                         /*
 678                                          * For spurious irq, which gpio level
 679                                          * is not as expected after incoming
 680                                          * edge, just ack the gpio irq.
 681                                          */
 682                                         writel(1 << hwirq,
 683                                                info->base +
 684                                                IRQ_STATUS + 4 * i);
 685                                         goto update_status;
 686                                 }
 687                         }
 688 
 689                         generic_handle_irq(virq);
 690 
 691 update_status:
 692                         /* Update status in case a new IRQ appears */
 693                         spin_lock_irqsave(&info->irq_lock, flags);
 694                         status = readl_relaxed(info->base +
 695                                                IRQ_STATUS + 4 * i);
 696                         /* Manage only the interrupt that was enabled */
 697                         status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
 698                         spin_unlock_irqrestore(&info->irq_lock, flags);
 699                 }
 700         }
 701         chained_irq_exit(chip, desc);
 702 }
 703 
 704 static unsigned int armada_37xx_irq_startup(struct irq_data *d)
 705 {
 706         /*
 707          * The mask field is a "precomputed bitmask for accessing the
 708          * chip registers" which was introduced for the generic
 709          * irqchip framework. As we don't use this framework, we can
 710          * reuse this field for our own usage.
 711          */
 712         d->mask = BIT(d->hwirq % GPIO_PER_REG);
 713 
 714         armada_37xx_irq_unmask(d);
 715 
 716         return 0;
 717 }
 718 
 719 static int armada_37xx_irqchip_register(struct platform_device *pdev,
 720                                         struct armada_37xx_pinctrl *info)
 721 {
 722         struct device_node *np = info->dev->of_node;
 723         struct gpio_chip *gc = &info->gpio_chip;
 724         struct irq_chip *irqchip = &info->irq_chip;
 725         struct resource res;
 726         int ret = -ENODEV, i, nr_irq_parent;
 727 
 728         /* Check if we have at least one gpio-controller child node */
 729         for_each_child_of_node(info->dev->of_node, np) {
 730                 if (of_property_read_bool(np, "gpio-controller")) {
 731                         ret = 0;
 732                         break;
 733                 }
 734         };
 735         if (ret)
 736                 return ret;
 737 
 738         nr_irq_parent = of_irq_count(np);
 739         spin_lock_init(&info->irq_lock);
 740 
 741         if (!nr_irq_parent) {
 742                 dev_err(&pdev->dev, "Invalid or no IRQ\n");
 743                 return 0;
 744         }
 745 
 746         if (of_address_to_resource(info->dev->of_node, 1, &res)) {
 747                 dev_err(info->dev, "cannot find IO resource\n");
 748                 return -ENOENT;
 749         }
 750 
 751         info->base = devm_ioremap_resource(info->dev, &res);
 752         if (IS_ERR(info->base))
 753                 return PTR_ERR(info->base);
 754 
 755         irqchip->irq_ack = armada_37xx_irq_ack;
 756         irqchip->irq_mask = armada_37xx_irq_mask;
 757         irqchip->irq_unmask = armada_37xx_irq_unmask;
 758         irqchip->irq_set_wake = armada_37xx_irq_set_wake;
 759         irqchip->irq_set_type = armada_37xx_irq_set_type;
 760         irqchip->irq_startup = armada_37xx_irq_startup;
 761         irqchip->name = info->data->name;
 762         ret = gpiochip_irqchip_add(gc, irqchip, 0,
 763                                    handle_edge_irq, IRQ_TYPE_NONE);
 764         if (ret) {
 765                 dev_info(&pdev->dev, "could not add irqchip\n");
 766                 return ret;
 767         }
 768 
 769         /*
 770          * Many interrupts are connected to the parent interrupt
 771          * controller. But we do not take advantage of this and use
 772          * the chained irq with all of them.
 773          */
 774         for (i = 0; i < nr_irq_parent; i++) {
 775                 int irq = irq_of_parse_and_map(np, i);
 776 
 777                 if (irq < 0)
 778                         continue;
 779 
 780                 gpiochip_set_chained_irqchip(gc, irqchip, irq,
 781                                              armada_37xx_irq_handler);
 782         }
 783 
 784         return 0;
 785 }
 786 
 787 static int armada_37xx_gpiochip_register(struct platform_device *pdev,
 788                                         struct armada_37xx_pinctrl *info)
 789 {
 790         struct device_node *np;
 791         struct gpio_chip *gc;
 792         int ret = -ENODEV;
 793 
 794         for_each_child_of_node(info->dev->of_node, np) {
 795                 if (of_find_property(np, "gpio-controller", NULL)) {
 796                         ret = 0;
 797                         break;
 798                 }
 799         };
 800         if (ret)
 801                 return ret;
 802 
 803         info->gpio_chip = armada_37xx_gpiolib_chip;
 804 
 805         gc = &info->gpio_chip;
 806         gc->ngpio = info->data->nr_pins;
 807         gc->parent = &pdev->dev;
 808         gc->base = -1;
 809         gc->of_node = np;
 810         gc->label = info->data->name;
 811 
 812         ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
 813         if (ret)
 814                 return ret;
 815         ret = armada_37xx_irqchip_register(pdev, info);
 816         if (ret)
 817                 return ret;
 818 
 819         return 0;
 820 }
 821 
 822 /**
 823  * armada_37xx_add_function() - Add a new function to the list
 824  * @funcs: array of function to add the new one
 825  * @funcsize: size of the remaining space for the function
 826  * @name: name of the function to add
 827  *
 828  * If it is a new function then create it by adding its name else
 829  * increment the number of group associated to this function.
 830  */
 831 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
 832                                     int *funcsize, const char *name)
 833 {
 834         int i = 0;
 835 
 836         if (*funcsize <= 0)
 837                 return -EOVERFLOW;
 838 
 839         while (funcs->ngroups) {
 840                 /* function already there */
 841                 if (strcmp(funcs->name, name) == 0) {
 842                         funcs->ngroups++;
 843 
 844                         return -EEXIST;
 845                 }
 846                 funcs++;
 847                 i++;
 848         }
 849 
 850         /* append new unique function */
 851         funcs->name = name;
 852         funcs->ngroups = 1;
 853         (*funcsize)--;
 854 
 855         return 0;
 856 }
 857 
 858 /**
 859  * armada_37xx_fill_group() - complete the group array
 860  * @info: info driver instance
 861  *
 862  * Based on the data available from the armada_37xx_pin_group array
 863  * completes the last member of the struct for each function: the list
 864  * of the groups associated to this function.
 865  *
 866  */
 867 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
 868 {
 869         int n, num = 0, funcsize = info->data->nr_pins;
 870 
 871         for (n = 0; n < info->ngroups; n++) {
 872                 struct armada_37xx_pin_group *grp = &info->groups[n];
 873                 int i, j, f;
 874 
 875                 grp->pins = devm_kcalloc(info->dev,
 876                                          grp->npins + grp->extra_npins,
 877                                          sizeof(*grp->pins),
 878                                          GFP_KERNEL);
 879                 if (!grp->pins)
 880                         return -ENOMEM;
 881 
 882                 for (i = 0; i < grp->npins; i++)
 883                         grp->pins[i] = grp->start_pin + i;
 884 
 885                 for (j = 0; j < grp->extra_npins; j++)
 886                         grp->pins[i+j] = grp->extra_pin + j;
 887 
 888                 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
 889                         int ret;
 890                         /* check for unique functions and count groups */
 891                         ret = armada_37xx_add_function(info->funcs, &funcsize,
 892                                             grp->funcs[f]);
 893                         if (ret == -EOVERFLOW)
 894                                 dev_err(info->dev,
 895                                         "More functions than pins(%d)\n",
 896                                         info->data->nr_pins);
 897                         if (ret < 0)
 898                                 continue;
 899                         num++;
 900                 }
 901         }
 902 
 903         info->nfuncs = num;
 904 
 905         return 0;
 906 }
 907 
 908 /**
 909  * armada_37xx_fill_funcs() - complete the funcs array
 910  * @info: info driver instance
 911  *
 912  * Based on the data available from the armada_37xx_pin_group array
 913  * completes the last two member of the struct for each group:
 914  * - the list of the pins included in the group
 915  * - the list of pinmux functions that can be selected for this group
 916  *
 917  */
 918 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
 919 {
 920         struct armada_37xx_pmx_func *funcs = info->funcs;
 921         int n;
 922 
 923         for (n = 0; n < info->nfuncs; n++) {
 924                 const char *name = funcs[n].name;
 925                 const char **groups;
 926                 int g;
 927 
 928                 funcs[n].groups = devm_kcalloc(info->dev,
 929                                                funcs[n].ngroups,
 930                                                sizeof(*(funcs[n].groups)),
 931                                                GFP_KERNEL);
 932                 if (!funcs[n].groups)
 933                         return -ENOMEM;
 934 
 935                 groups = funcs[n].groups;
 936 
 937                 for (g = 0; g < info->ngroups; g++) {
 938                         struct armada_37xx_pin_group *gp = &info->groups[g];
 939                         int f;
 940 
 941                         f = match_string(gp->funcs, NB_FUNCS, name);
 942                         if (f < 0)
 943                                 continue;
 944 
 945                         *groups = gp->name;
 946                         groups++;
 947                 }
 948         }
 949         return 0;
 950 }
 951 
 952 static int armada_37xx_pinctrl_register(struct platform_device *pdev,
 953                                         struct armada_37xx_pinctrl *info)
 954 {
 955         const struct armada_37xx_pin_data *pin_data = info->data;
 956         struct pinctrl_desc *ctrldesc = &info->pctl;
 957         struct pinctrl_pin_desc *pindesc, *pdesc;
 958         int pin, ret;
 959 
 960         info->groups = pin_data->groups;
 961         info->ngroups = pin_data->ngroups;
 962 
 963         ctrldesc->name = "armada_37xx-pinctrl";
 964         ctrldesc->owner = THIS_MODULE;
 965         ctrldesc->pctlops = &armada_37xx_pctrl_ops;
 966         ctrldesc->pmxops = &armada_37xx_pmx_ops;
 967         ctrldesc->confops = &armada_37xx_pinconf_ops;
 968 
 969         pindesc = devm_kcalloc(&pdev->dev,
 970                                pin_data->nr_pins, sizeof(*pindesc),
 971                                GFP_KERNEL);
 972         if (!pindesc)
 973                 return -ENOMEM;
 974 
 975         ctrldesc->pins = pindesc;
 976         ctrldesc->npins = pin_data->nr_pins;
 977 
 978         pdesc = pindesc;
 979         for (pin = 0; pin < pin_data->nr_pins; pin++) {
 980                 pdesc->number = pin;
 981                 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
 982                                         pin_data->name, pin);
 983                 pdesc++;
 984         }
 985 
 986         /*
 987          * we allocate functions for number of pins and hope there are
 988          * fewer unique functions than pins available
 989          */
 990         info->funcs = devm_kcalloc(&pdev->dev,
 991                                    pin_data->nr_pins,
 992                                    sizeof(struct armada_37xx_pmx_func),
 993                                    GFP_KERNEL);
 994         if (!info->funcs)
 995                 return -ENOMEM;
 996 
 997 
 998         ret = armada_37xx_fill_group(info);
 999         if (ret)
1000                 return ret;
1001 
1002         ret = armada_37xx_fill_func(info);
1003         if (ret)
1004                 return ret;
1005 
1006         info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
1007         if (IS_ERR(info->pctl_dev)) {
1008                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1009                 return PTR_ERR(info->pctl_dev);
1010         }
1011 
1012         return 0;
1013 }
1014 
1015 #if defined(CONFIG_PM)
1016 static int armada_3700_pinctrl_suspend(struct device *dev)
1017 {
1018         struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1019 
1020         /* Save GPIO state */
1021         regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
1022         regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
1023         regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
1024         regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
1025                     &info->pm.out_val_h);
1026 
1027         info->pm.irq_en_l = readl(info->base + IRQ_EN);
1028         info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
1029         info->pm.irq_pol_l = readl(info->base + IRQ_POL);
1030         info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
1031 
1032         /* Save pinctrl state */
1033         regmap_read(info->regmap, SELECTION, &info->pm.selection);
1034 
1035         return 0;
1036 }
1037 
1038 static int armada_3700_pinctrl_resume(struct device *dev)
1039 {
1040         struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1041         struct gpio_chip *gc;
1042         struct irq_domain *d;
1043         int i;
1044 
1045         /* Restore GPIO state */
1046         regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
1047         regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
1048                      info->pm.out_en_h);
1049         regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
1050         regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
1051                      info->pm.out_val_h);
1052 
1053         /*
1054          * Input levels may change during suspend, which is not monitored at
1055          * that time. GPIOs used for both-edge IRQs may not be synchronized
1056          * anymore with their polarities (rising/falling edge) and must be
1057          * re-configured manually.
1058          */
1059         gc = &info->gpio_chip;
1060         d = gc->irq.domain;
1061         for (i = 0; i < gc->ngpio; i++) {
1062                 u32 irq_bit = BIT(i % GPIO_PER_REG);
1063                 u32 mask, *irq_pol, input_reg, virq, type, level;
1064 
1065                 if (i < GPIO_PER_REG) {
1066                         mask = info->pm.irq_en_l;
1067                         irq_pol = &info->pm.irq_pol_l;
1068                         input_reg = INPUT_VAL;
1069                 } else {
1070                         mask = info->pm.irq_en_h;
1071                         irq_pol = &info->pm.irq_pol_h;
1072                         input_reg = INPUT_VAL + sizeof(u32);
1073                 }
1074 
1075                 if (!(mask & irq_bit))
1076                         continue;
1077 
1078                 virq = irq_find_mapping(d, i);
1079                 type = irq_get_trigger_type(virq);
1080 
1081                 /*
1082                  * Synchronize level and polarity for both-edge irqs:
1083                  *     - a high input level expects a falling edge,
1084                  *     - a low input level exepects a rising edge.
1085                  */
1086                 if ((type & IRQ_TYPE_SENSE_MASK) ==
1087                     IRQ_TYPE_EDGE_BOTH) {
1088                         regmap_read(info->regmap, input_reg, &level);
1089                         if ((*irq_pol ^ level) & irq_bit)
1090                                 *irq_pol ^= irq_bit;
1091                 }
1092         }
1093 
1094         writel(info->pm.irq_en_l, info->base + IRQ_EN);
1095         writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
1096         writel(info->pm.irq_pol_l, info->base + IRQ_POL);
1097         writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
1098 
1099         /* Restore pinctrl state */
1100         regmap_write(info->regmap, SELECTION, info->pm.selection);
1101 
1102         return 0;
1103 }
1104 
1105 /*
1106  * Since pinctrl is an infrastructure module, its resume should be issued prior
1107  * to other IO drivers.
1108  */
1109 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
1110         .suspend_noirq = armada_3700_pinctrl_suspend,
1111         .resume_noirq = armada_3700_pinctrl_resume,
1112 };
1113 
1114 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
1115 #else
1116 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL
1117 #endif /* CONFIG_PM */
1118 
1119 static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
1120         {
1121                 .compatible = "marvell,armada3710-sb-pinctrl",
1122                 .data = &armada_37xx_pin_sb,
1123         },
1124         {
1125                 .compatible = "marvell,armada3710-nb-pinctrl",
1126                 .data = &armada_37xx_pin_nb,
1127         },
1128         { },
1129 };
1130 
1131 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
1132 {
1133         struct armada_37xx_pinctrl *info;
1134         struct device *dev = &pdev->dev;
1135         struct device_node *np = dev->of_node;
1136         struct regmap *regmap;
1137         int ret;
1138 
1139         info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
1140                             GFP_KERNEL);
1141         if (!info)
1142                 return -ENOMEM;
1143 
1144         info->dev = dev;
1145 
1146         regmap = syscon_node_to_regmap(np);
1147         if (IS_ERR(regmap)) {
1148                 dev_err(&pdev->dev, "cannot get regmap\n");
1149                 return PTR_ERR(regmap);
1150         }
1151         info->regmap = regmap;
1152 
1153         info->data = of_device_get_match_data(dev);
1154 
1155         ret = armada_37xx_pinctrl_register(pdev, info);
1156         if (ret)
1157                 return ret;
1158 
1159         ret = armada_37xx_gpiochip_register(pdev, info);
1160         if (ret)
1161                 return ret;
1162 
1163         platform_set_drvdata(pdev, info);
1164 
1165         return 0;
1166 }
1167 
1168 static struct platform_driver armada_37xx_pinctrl_driver = {
1169         .driver = {
1170                 .name = "armada-37xx-pinctrl",
1171                 .of_match_table = armada_37xx_pinctrl_of_match,
1172                 .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS,
1173         },
1174 };
1175 
1176 builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1177                               armada_37xx_pinctrl_probe);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c

DEFINITIONS
