This source file includes following definitions.
- mxs_get_groups_count
- mxs_get_group_name
- mxs_get_group_pins
- mxs_pin_dbg_show
- mxs_dt_node_to_map
- mxs_dt_free_map
- mxs_pinctrl_get_funcs_count
- mxs_pinctrl_get_func_name
- mxs_pinctrl_get_func_groups
- mxs_pinctrl_rmwl
- mxs_pinctrl_set_mux
- mxs_pinconf_get
- mxs_pinconf_set
- mxs_pinconf_group_get
- mxs_pinconf_group_set
- mxs_pinconf_dbg_show
- mxs_pinconf_group_dbg_show
- mxs_pinctrl_parse_group
- mxs_pinctrl_probe_dt
- mxs_pinctrl_probe
1
2
3
4
5 #include <linux/err.h>
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/of.h>
9 #include <linux/of_address.h>
10 #include <linux/pinctrl/machine.h>
11 #include <linux/pinctrl/pinconf.h>
12 #include <linux/pinctrl/pinctrl.h>
13 #include <linux/pinctrl/pinmux.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include "../core.h"
17 #include "pinctrl-mxs.h"
18
19 #define SUFFIX_LEN 4
20
21 struct mxs_pinctrl_data {
22 struct device *dev;
23 struct pinctrl_dev *pctl;
24 void __iomem *base;
25 struct mxs_pinctrl_soc_data *soc;
26 };
27
28 static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
29 {
30 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
31
32 return d->soc->ngroups;
33 }
34
35 static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
36 unsigned group)
37 {
38 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
39
40 return d->soc->groups[group].name;
41 }
42
43 static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
44 const unsigned **pins, unsigned *num_pins)
45 {
46 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
47
48 *pins = d->soc->groups[group].pins;
49 *num_pins = d->soc->groups[group].npins;
50
51 return 0;
52 }
53
54 static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
55 unsigned offset)
56 {
57 seq_printf(s, " %s", dev_name(pctldev->dev));
58 }
59
60 static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
61 struct device_node *np,
62 struct pinctrl_map **map, unsigned *num_maps)
63 {
64 struct pinctrl_map *new_map;
65 char *group = NULL;
66 unsigned new_num = 1;
67 unsigned long config = 0;
68 unsigned long *pconfig;
69 int length = strlen(np->name) + SUFFIX_LEN;
70 bool purecfg = false;
71 u32 val, reg;
72 int ret, i = 0;
73
74
75 if (of_property_read_u32(np, "reg", ®))
76 purecfg = true;
77
78 ret = of_property_read_u32(np, "fsl,drive-strength", &val);
79 if (!ret)
80 config = val | MA_PRESENT;
81 ret = of_property_read_u32(np, "fsl,voltage", &val);
82 if (!ret)
83 config |= val << VOL_SHIFT | VOL_PRESENT;
84 ret = of_property_read_u32(np, "fsl,pull-up", &val);
85 if (!ret)
86 config |= val << PULL_SHIFT | PULL_PRESENT;
87
88
89 if (!purecfg && config)
90 new_num = 2;
91
92 new_map = kcalloc(new_num, sizeof(*new_map), GFP_KERNEL);
93 if (!new_map)
94 return -ENOMEM;
95
96 if (!purecfg) {
97 new_map[i].type = PIN_MAP_TYPE_MUX_GROUP;
98 new_map[i].data.mux.function = np->name;
99
100
101 group = kzalloc(length, GFP_KERNEL);
102 if (!group) {
103 ret = -ENOMEM;
104 goto free;
105 }
106 snprintf(group, length, "%s.%d", np->name, reg);
107 new_map[i].data.mux.group = group;
108 i++;
109 }
110
111 if (config) {
112 pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
113 if (!pconfig) {
114 ret = -ENOMEM;
115 goto free_group;
116 }
117
118 new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
119 new_map[i].data.configs.group_or_pin = purecfg ? np->name :
120 group;
121 new_map[i].data.configs.configs = pconfig;
122 new_map[i].data.configs.num_configs = 1;
123 }
124
125 *map = new_map;
126 *num_maps = new_num;
127
128 return 0;
129
130 free_group:
131 if (!purecfg)
132 kfree(group);
133 free:
134 kfree(new_map);
135 return ret;
136 }
137
138 static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
139 struct pinctrl_map *map, unsigned num_maps)
140 {
141 u32 i;
142
143 for (i = 0; i < num_maps; i++) {
144 if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
145 kfree(map[i].data.mux.group);
146 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
147 kfree(map[i].data.configs.configs);
148 }
149
150 kfree(map);
151 }
152
153 static const struct pinctrl_ops mxs_pinctrl_ops = {
154 .get_groups_count = mxs_get_groups_count,
155 .get_group_name = mxs_get_group_name,
156 .get_group_pins = mxs_get_group_pins,
157 .pin_dbg_show = mxs_pin_dbg_show,
158 .dt_node_to_map = mxs_dt_node_to_map,
159 .dt_free_map = mxs_dt_free_map,
160 };
161
162 static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
163 {
164 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
165
166 return d->soc->nfunctions;
167 }
168
169 static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
170 unsigned function)
171 {
172 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
173
174 return d->soc->functions[function].name;
175 }
176
177 static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
178 unsigned group,
179 const char * const **groups,
180 unsigned * const num_groups)
181 {
182 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
183
184 *groups = d->soc->functions[group].groups;
185 *num_groups = d->soc->functions[group].ngroups;
186
187 return 0;
188 }
189
190 static void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift, void __iomem *reg)
191 {
192 u32 tmp;
193
194 tmp = readl(reg);
195 tmp &= ~(mask << shift);
196 tmp |= value << shift;
197 writel(tmp, reg);
198 }
199
200 static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
201 unsigned group)
202 {
203 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
204 struct mxs_group *g = &d->soc->groups[group];
205 void __iomem *reg;
206 u8 bank, shift;
207 u16 pin;
208 u32 i;
209
210 for (i = 0; i < g->npins; i++) {
211 bank = PINID_TO_BANK(g->pins[i]);
212 pin = PINID_TO_PIN(g->pins[i]);
213 reg = d->base + d->soc->regs->muxsel;
214 reg += bank * 0x20 + pin / 16 * 0x10;
215 shift = pin % 16 * 2;
216
217 mxs_pinctrl_rmwl(g->muxsel[i], 0x3, shift, reg);
218 }
219
220 return 0;
221 }
222
223 static const struct pinmux_ops mxs_pinmux_ops = {
224 .get_functions_count = mxs_pinctrl_get_funcs_count,
225 .get_function_name = mxs_pinctrl_get_func_name,
226 .get_function_groups = mxs_pinctrl_get_func_groups,
227 .set_mux = mxs_pinctrl_set_mux,
228 };
229
230 static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
231 unsigned pin, unsigned long *config)
232 {
233 return -ENOTSUPP;
234 }
235
236 static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
237 unsigned pin, unsigned long *configs,
238 unsigned num_configs)
239 {
240 return -ENOTSUPP;
241 }
242
243 static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
244 unsigned group, unsigned long *config)
245 {
246 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
247
248 *config = d->soc->groups[group].config;
249
250 return 0;
251 }
252
253 static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
254 unsigned group, unsigned long *configs,
255 unsigned num_configs)
256 {
257 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
258 struct mxs_group *g = &d->soc->groups[group];
259 void __iomem *reg;
260 u8 ma, vol, pull, bank, shift;
261 u16 pin;
262 u32 i;
263 int n;
264 unsigned long config;
265
266 for (n = 0; n < num_configs; n++) {
267 config = configs[n];
268
269 ma = CONFIG_TO_MA(config);
270 vol = CONFIG_TO_VOL(config);
271 pull = CONFIG_TO_PULL(config);
272
273 for (i = 0; i < g->npins; i++) {
274 bank = PINID_TO_BANK(g->pins[i]);
275 pin = PINID_TO_PIN(g->pins[i]);
276
277
278 reg = d->base + d->soc->regs->drive;
279 reg += bank * 0x40 + pin / 8 * 0x10;
280
281
282 if (config & MA_PRESENT) {
283 shift = pin % 8 * 4;
284 mxs_pinctrl_rmwl(ma, 0x3, shift, reg);
285 }
286
287
288 if (config & VOL_PRESENT) {
289 shift = pin % 8 * 4 + 2;
290 if (vol)
291 writel(1 << shift, reg + SET);
292 else
293 writel(1 << shift, reg + CLR);
294 }
295
296
297 if (config & PULL_PRESENT) {
298 reg = d->base + d->soc->regs->pull;
299 reg += bank * 0x10;
300 shift = pin;
301 if (pull)
302 writel(1 << shift, reg + SET);
303 else
304 writel(1 << shift, reg + CLR);
305 }
306 }
307
308
309 g->config = config;
310
311 }
312
313 return 0;
314 }
315
316 static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
317 struct seq_file *s, unsigned pin)
318 {
319
320 }
321
322 static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
323 struct seq_file *s, unsigned group)
324 {
325 unsigned long config;
326
327 if (!mxs_pinconf_group_get(pctldev, group, &config))
328 seq_printf(s, "0x%lx", config);
329 }
330
331 static const struct pinconf_ops mxs_pinconf_ops = {
332 .pin_config_get = mxs_pinconf_get,
333 .pin_config_set = mxs_pinconf_set,
334 .pin_config_group_get = mxs_pinconf_group_get,
335 .pin_config_group_set = mxs_pinconf_group_set,
336 .pin_config_dbg_show = mxs_pinconf_dbg_show,
337 .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
338 };
339
340 static struct pinctrl_desc mxs_pinctrl_desc = {
341 .pctlops = &mxs_pinctrl_ops,
342 .pmxops = &mxs_pinmux_ops,
343 .confops = &mxs_pinconf_ops,
344 .owner = THIS_MODULE,
345 };
346
347 static int mxs_pinctrl_parse_group(struct platform_device *pdev,
348 struct device_node *np, int idx,
349 const char **out_name)
350 {
351 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
352 struct mxs_group *g = &d->soc->groups[idx];
353 struct property *prop;
354 const char *propname = "fsl,pinmux-ids";
355 char *group;
356 int length = strlen(np->name) + SUFFIX_LEN;
357 u32 val, i;
358
359 group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
360 if (!group)
361 return -ENOMEM;
362 if (of_property_read_u32(np, "reg", &val))
363 snprintf(group, length, "%s", np->name);
364 else
365 snprintf(group, length, "%s.%d", np->name, val);
366 g->name = group;
367
368 prop = of_find_property(np, propname, &length);
369 if (!prop)
370 return -EINVAL;
371 g->npins = length / sizeof(u32);
372
373 g->pins = devm_kcalloc(&pdev->dev, g->npins, sizeof(*g->pins),
374 GFP_KERNEL);
375 if (!g->pins)
376 return -ENOMEM;
377
378 g->muxsel = devm_kcalloc(&pdev->dev, g->npins, sizeof(*g->muxsel),
379 GFP_KERNEL);
380 if (!g->muxsel)
381 return -ENOMEM;
382
383 of_property_read_u32_array(np, propname, g->pins, g->npins);
384 for (i = 0; i < g->npins; i++) {
385 g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
386 g->pins[i] = MUXID_TO_PINID(g->pins[i]);
387 }
388
389 if (out_name)
390 *out_name = g->name;
391
392 return 0;
393 }
394
395 static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
396 struct mxs_pinctrl_data *d)
397 {
398 struct mxs_pinctrl_soc_data *soc = d->soc;
399 struct device_node *np = pdev->dev.of_node;
400 struct device_node *child;
401 struct mxs_function *f;
402 const char *gpio_compat = "fsl,mxs-gpio";
403 const char *fn, *fnull = "";
404 int i = 0, idxf = 0, idxg = 0;
405 int ret;
406 u32 val;
407
408 child = of_get_next_child(np, NULL);
409 if (!child) {
410 dev_err(&pdev->dev, "no group is defined\n");
411 return -ENOENT;
412 }
413
414
415 fn = fnull;
416 for_each_child_of_node(np, child) {
417 if (of_device_is_compatible(child, gpio_compat))
418 continue;
419 soc->ngroups++;
420
421 if (of_property_read_u32(child, "reg", &val))
422 continue;
423 if (strcmp(fn, child->name)) {
424 fn = child->name;
425 soc->nfunctions++;
426 }
427 }
428
429 soc->functions = devm_kcalloc(&pdev->dev,
430 soc->nfunctions,
431 sizeof(*soc->functions),
432 GFP_KERNEL);
433 if (!soc->functions)
434 return -ENOMEM;
435
436 soc->groups = devm_kcalloc(&pdev->dev,
437 soc->ngroups, sizeof(*soc->groups),
438 GFP_KERNEL);
439 if (!soc->groups)
440 return -ENOMEM;
441
442
443 fn = fnull;
444 f = &soc->functions[idxf];
445 for_each_child_of_node(np, child) {
446 if (of_device_is_compatible(child, gpio_compat))
447 continue;
448 if (of_property_read_u32(child, "reg", &val))
449 continue;
450 if (strcmp(fn, child->name)) {
451 struct device_node *child2;
452
453
454
455
456
457 of_node_get(child);
458
459
460
461
462
463
464
465
466
467 for (child2 = of_get_next_child(np, child);
468 child2 != NULL;
469 child2 = of_get_next_child(np, child2)) {
470 if (!strcmp(child2->name, fn))
471 dev_warn(&pdev->dev,
472 "function nodes must be grouped by name (failed for: %s)",
473 fn);
474 }
475
476 f = &soc->functions[idxf++];
477 f->name = fn = child->name;
478 }
479 f->ngroups++;
480 }
481
482
483 idxf = 0;
484 fn = fnull;
485 for_each_child_of_node(np, child) {
486 if (of_device_is_compatible(child, gpio_compat))
487 continue;
488 if (of_property_read_u32(child, "reg", &val)) {
489 ret = mxs_pinctrl_parse_group(pdev, child,
490 idxg++, NULL);
491 if (ret) {
492 of_node_put(child);
493 return ret;
494 }
495 continue;
496 }
497
498 if (strcmp(fn, child->name)) {
499 f = &soc->functions[idxf++];
500 f->groups = devm_kcalloc(&pdev->dev,
501 f->ngroups,
502 sizeof(*f->groups),
503 GFP_KERNEL);
504 if (!f->groups) {
505 of_node_put(child);
506 return -ENOMEM;
507 }
508 fn = child->name;
509 i = 0;
510 }
511 ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
512 &f->groups[i++]);
513 if (ret) {
514 of_node_put(child);
515 return ret;
516 }
517 }
518
519 return 0;
520 }
521
522 int mxs_pinctrl_probe(struct platform_device *pdev,
523 struct mxs_pinctrl_soc_data *soc)
524 {
525 struct device_node *np = pdev->dev.of_node;
526 struct mxs_pinctrl_data *d;
527 int ret;
528
529 d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
530 if (!d)
531 return -ENOMEM;
532
533 d->dev = &pdev->dev;
534 d->soc = soc;
535
536 d->base = of_iomap(np, 0);
537 if (!d->base)
538 return -EADDRNOTAVAIL;
539
540 mxs_pinctrl_desc.pins = d->soc->pins;
541 mxs_pinctrl_desc.npins = d->soc->npins;
542 mxs_pinctrl_desc.name = dev_name(&pdev->dev);
543
544 platform_set_drvdata(pdev, d);
545
546 ret = mxs_pinctrl_probe_dt(pdev, d);
547 if (ret) {
548 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
549 goto err;
550 }
551
552 d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
553 if (IS_ERR(d->pctl)) {
554 dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
555 ret = PTR_ERR(d->pctl);
556 goto err;
557 }
558
559 return 0;
560
561 err:
562 iounmap(d->base);
563 return ret;
564 }