This source file includes following definitions.
- imx1_mem
- imx1_write_2bit
- imx1_write_bit
- imx1_read_2bit
- imx1_read_bit
- imx1_pinctrl_find_group_by_name
- imx1_get_groups_count
- imx1_get_group_name
- imx1_get_group_pins
- imx1_pin_dbg_show
- imx1_dt_node_to_map
- imx1_dt_free_map
- imx1_pmx_set
- imx1_pmx_get_funcs_count
- imx1_pmx_get_func_name
- imx1_pmx_get_groups
- imx1_pinconf_get
- imx1_pinconf_set
- imx1_pinconf_dbg_show
- imx1_pinconf_group_dbg_show
- imx1_pinctrl_parse_groups
- imx1_pinctrl_parse_functions
- imx1_pinctrl_parse_dt
- imx1_pinctrl_core_probe
1
2
3
4
5
6
7
8
9
10
11
12
13 #include <linux/bitops.h>
14 #include <linux/err.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/pinctrl/machine.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/slab.h>
24
25 #include "../core.h"
26 #include "pinctrl-imx1.h"
27
28 struct imx1_pinctrl {
29 struct device *dev;
30 struct pinctrl_dev *pctl;
31 void __iomem *base;
32 const struct imx1_pinctrl_soc_info *info;
33 };
34
35
36
37
38
39 #define MX1_DDIR 0x00
40 #define MX1_OCR 0x04
41 #define MX1_ICONFA 0x0c
42 #define MX1_ICONFB 0x14
43 #define MX1_GIUS 0x20
44 #define MX1_GPR 0x38
45 #define MX1_PUEN 0x40
46
47 #define MX1_PORT_STRIDE 0x100
48
49
50
51
52
53 #define MX1_MUX_FUNCTION(val) (BIT(0) & val)
54 #define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
55 #define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
56 #define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
57 #define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
58 #define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75 static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
76 {
77 unsigned int port = pin_id / 32;
78 return ipctl->base + port * MX1_PORT_STRIDE;
79 }
80
81
82
83
84
85 static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
86 u32 value, u32 reg_offset)
87 {
88 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
89 int offset = (pin_id % 16) * 2;
90 int mask = ~(0x3 << offset);
91 u32 old_val;
92 u32 new_val;
93
94
95 if (pin_id % 32 >= 16)
96 reg += 0x04;
97
98 dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
99 reg, offset, value);
100
101
102 old_val = readl(reg);
103 old_val &= mask;
104
105 new_val = value & 0x3;
106 new_val <<= offset;
107 new_val |= old_val;
108
109 writel(new_val, reg);
110 }
111
112 static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
113 u32 value, u32 reg_offset)
114 {
115 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
116 int offset = pin_id % 32;
117 int mask = ~BIT_MASK(offset);
118 u32 old_val;
119 u32 new_val;
120
121
122 old_val = readl(reg);
123 old_val &= mask;
124
125 new_val = value & 0x1;
126 new_val <<= offset;
127 new_val |= old_val;
128
129 writel(new_val, reg);
130 }
131
132 static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
133 u32 reg_offset)
134 {
135 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
136 int offset = (pin_id % 16) * 2;
137
138
139 if (pin_id % 32 >= 16)
140 reg += 0x04;
141
142 return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
143 }
144
145 static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
146 u32 reg_offset)
147 {
148 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
149 int offset = pin_id % 32;
150
151 return !!(readl(reg) & BIT(offset));
152 }
153
154 static inline const struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
155 const struct imx1_pinctrl_soc_info *info,
156 const char *name)
157 {
158 const struct imx1_pin_group *grp = NULL;
159 int i;
160
161 for (i = 0; i < info->ngroups; i++) {
162 if (!strcmp(info->groups[i].name, name)) {
163 grp = &info->groups[i];
164 break;
165 }
166 }
167
168 return grp;
169 }
170
171 static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
172 {
173 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
174 const struct imx1_pinctrl_soc_info *info = ipctl->info;
175
176 return info->ngroups;
177 }
178
179 static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
180 unsigned selector)
181 {
182 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
183 const struct imx1_pinctrl_soc_info *info = ipctl->info;
184
185 return info->groups[selector].name;
186 }
187
188 static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
189 const unsigned int **pins,
190 unsigned *npins)
191 {
192 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
193 const struct imx1_pinctrl_soc_info *info = ipctl->info;
194
195 if (selector >= info->ngroups)
196 return -EINVAL;
197
198 *pins = info->groups[selector].pin_ids;
199 *npins = info->groups[selector].npins;
200
201 return 0;
202 }
203
204 static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
205 unsigned offset)
206 {
207 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
208
209 seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
210 imx1_read_bit(ipctl, offset, MX1_GIUS),
211 imx1_read_bit(ipctl, offset, MX1_GPR),
212 imx1_read_bit(ipctl, offset, MX1_DDIR),
213 imx1_read_2bit(ipctl, offset, MX1_OCR),
214 imx1_read_2bit(ipctl, offset, MX1_ICONFA),
215 imx1_read_2bit(ipctl, offset, MX1_ICONFB));
216 }
217
218 static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
219 struct device_node *np,
220 struct pinctrl_map **map, unsigned *num_maps)
221 {
222 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
223 const struct imx1_pinctrl_soc_info *info = ipctl->info;
224 const struct imx1_pin_group *grp;
225 struct pinctrl_map *new_map;
226 struct device_node *parent;
227 int map_num = 1;
228 int i, j;
229
230
231
232
233
234 grp = imx1_pinctrl_find_group_by_name(info, np->name);
235 if (!grp) {
236 dev_err(info->dev, "unable to find group for node %pOFn\n",
237 np);
238 return -EINVAL;
239 }
240
241 for (i = 0; i < grp->npins; i++)
242 map_num++;
243
244 new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
245 GFP_KERNEL);
246 if (!new_map)
247 return -ENOMEM;
248
249 *map = new_map;
250 *num_maps = map_num;
251
252
253 parent = of_get_parent(np);
254 if (!parent) {
255 kfree(new_map);
256 return -EINVAL;
257 }
258 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
259 new_map[0].data.mux.function = parent->name;
260 new_map[0].data.mux.group = np->name;
261 of_node_put(parent);
262
263
264 new_map++;
265 for (i = j = 0; i < grp->npins; i++) {
266 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
267 new_map[j].data.configs.group_or_pin =
268 pin_get_name(pctldev, grp->pins[i].pin_id);
269 new_map[j].data.configs.configs = &grp->pins[i].config;
270 new_map[j].data.configs.num_configs = 1;
271 j++;
272 }
273
274 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
275 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
276
277 return 0;
278 }
279
280 static void imx1_dt_free_map(struct pinctrl_dev *pctldev,
281 struct pinctrl_map *map, unsigned num_maps)
282 {
283 kfree(map);
284 }
285
286 static const struct pinctrl_ops imx1_pctrl_ops = {
287 .get_groups_count = imx1_get_groups_count,
288 .get_group_name = imx1_get_group_name,
289 .get_group_pins = imx1_get_group_pins,
290 .pin_dbg_show = imx1_pin_dbg_show,
291 .dt_node_to_map = imx1_dt_node_to_map,
292 .dt_free_map = imx1_dt_free_map,
293
294 };
295
296 static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
297 unsigned group)
298 {
299 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
300 const struct imx1_pinctrl_soc_info *info = ipctl->info;
301 const struct imx1_pin *pins;
302 unsigned int npins;
303 int i;
304
305
306
307
308
309 pins = info->groups[group].pins;
310 npins = info->groups[group].npins;
311
312 WARN_ON(!pins || !npins);
313
314 dev_dbg(ipctl->dev, "enable function %s group %s\n",
315 info->functions[selector].name, info->groups[group].name);
316
317 for (i = 0; i < npins; i++) {
318 unsigned int mux = pins[i].mux_id;
319 unsigned int pin_id = pins[i].pin_id;
320 unsigned int afunction = MX1_MUX_FUNCTION(mux);
321 unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
322 unsigned int direction = MX1_MUX_DIR(mux);
323 unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
324 unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
325 unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
326
327 dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
328 __func__, pin_id, afunction, gpio_in_use,
329 direction, gpio_oconf, gpio_iconfa,
330 gpio_iconfb);
331
332 imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
333 imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
334
335 if (gpio_in_use) {
336 imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
337 imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
338 MX1_ICONFA);
339 imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
340 MX1_ICONFB);
341 } else {
342 imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
343 }
344 }
345
346 return 0;
347 }
348
349 static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
350 {
351 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
352 const struct imx1_pinctrl_soc_info *info = ipctl->info;
353
354 return info->nfunctions;
355 }
356
357 static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev,
358 unsigned selector)
359 {
360 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
361 const struct imx1_pinctrl_soc_info *info = ipctl->info;
362
363 return info->functions[selector].name;
364 }
365
366 static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
367 const char * const **groups,
368 unsigned * const num_groups)
369 {
370 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
371 const struct imx1_pinctrl_soc_info *info = ipctl->info;
372
373 *groups = info->functions[selector].groups;
374 *num_groups = info->functions[selector].num_groups;
375
376 return 0;
377 }
378
379 static const struct pinmux_ops imx1_pmx_ops = {
380 .get_functions_count = imx1_pmx_get_funcs_count,
381 .get_function_name = imx1_pmx_get_func_name,
382 .get_function_groups = imx1_pmx_get_groups,
383 .set_mux = imx1_pmx_set,
384 };
385
386 static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
387 unsigned pin_id, unsigned long *config)
388 {
389 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
390
391 *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
392
393 return 0;
394 }
395
396 static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
397 unsigned pin_id, unsigned long *configs,
398 unsigned num_configs)
399 {
400 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
401 int i;
402
403 for (i = 0; i != num_configs; ++i) {
404 imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
405
406 dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
407 pin_desc_get(pctldev, pin_id)->name);
408 }
409
410 return 0;
411 }
412
413 static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev,
414 struct seq_file *s, unsigned pin_id)
415 {
416 unsigned long config;
417
418 imx1_pinconf_get(pctldev, pin_id, &config);
419 seq_printf(s, "0x%lx", config);
420 }
421
422 static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
423 struct seq_file *s, unsigned group)
424 {
425 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
426 const struct imx1_pinctrl_soc_info *info = ipctl->info;
427 struct imx1_pin_group *grp;
428 unsigned long config;
429 const char *name;
430 int i, ret;
431
432 if (group >= info->ngroups)
433 return;
434
435 seq_puts(s, "\n");
436 grp = &info->groups[group];
437 for (i = 0; i < grp->npins; i++) {
438 name = pin_get_name(pctldev, grp->pins[i].pin_id);
439 ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config);
440 if (ret)
441 return;
442 seq_printf(s, "%s: 0x%lx", name, config);
443 }
444 }
445
446 static const struct pinconf_ops imx1_pinconf_ops = {
447 .pin_config_get = imx1_pinconf_get,
448 .pin_config_set = imx1_pinconf_set,
449 .pin_config_dbg_show = imx1_pinconf_dbg_show,
450 .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show,
451 };
452
453 static struct pinctrl_desc imx1_pinctrl_desc = {
454 .pctlops = &imx1_pctrl_ops,
455 .pmxops = &imx1_pmx_ops,
456 .confops = &imx1_pinconf_ops,
457 .owner = THIS_MODULE,
458 };
459
460 static int imx1_pinctrl_parse_groups(struct device_node *np,
461 struct imx1_pin_group *grp,
462 struct imx1_pinctrl_soc_info *info,
463 u32 index)
464 {
465 int size;
466 const __be32 *list;
467 int i;
468
469 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
470
471
472 grp->name = np->name;
473
474
475
476
477 list = of_get_property(np, "fsl,pins", &size);
478
479 if (!size || size % 12) {
480 dev_notice(info->dev, "Not a valid fsl,pins property (%pOFn)\n",
481 np);
482 return -EINVAL;
483 }
484
485 grp->npins = size / 12;
486 grp->pins = devm_kcalloc(info->dev,
487 grp->npins, sizeof(struct imx1_pin), GFP_KERNEL);
488 grp->pin_ids = devm_kcalloc(info->dev,
489 grp->npins, sizeof(unsigned int), GFP_KERNEL);
490
491 if (!grp->pins || !grp->pin_ids)
492 return -ENOMEM;
493
494 for (i = 0; i < grp->npins; i++) {
495 grp->pins[i].pin_id = be32_to_cpu(*list++);
496 grp->pins[i].mux_id = be32_to_cpu(*list++);
497 grp->pins[i].config = be32_to_cpu(*list++);
498
499 grp->pin_ids[i] = grp->pins[i].pin_id;
500 }
501
502 return 0;
503 }
504
505 static int imx1_pinctrl_parse_functions(struct device_node *np,
506 struct imx1_pinctrl_soc_info *info,
507 u32 index)
508 {
509 struct device_node *child;
510 struct imx1_pmx_func *func;
511 struct imx1_pin_group *grp;
512 int ret;
513 static u32 grp_index;
514 u32 i = 0;
515
516 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
517
518 func = &info->functions[index];
519
520
521 func->name = np->name;
522 func->num_groups = of_get_child_count(np);
523 if (func->num_groups == 0)
524 return -EINVAL;
525
526 func->groups = devm_kcalloc(info->dev,
527 func->num_groups, sizeof(char *), GFP_KERNEL);
528
529 if (!func->groups)
530 return -ENOMEM;
531
532 for_each_child_of_node(np, child) {
533 func->groups[i] = child->name;
534 grp = &info->groups[grp_index++];
535 ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
536 if (ret == -ENOMEM) {
537 of_node_put(child);
538 return ret;
539 }
540 }
541
542 return 0;
543 }
544
545 static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
546 struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
547 {
548 struct device_node *np = pdev->dev.of_node;
549 struct device_node *child;
550 int ret;
551 u32 nfuncs = 0;
552 u32 ngroups = 0;
553 u32 ifunc = 0;
554
555 if (!np)
556 return -ENODEV;
557
558 for_each_child_of_node(np, child) {
559 ++nfuncs;
560 ngroups += of_get_child_count(child);
561 }
562
563 if (!nfuncs) {
564 dev_err(&pdev->dev, "No pin functions defined\n");
565 return -EINVAL;
566 }
567
568 info->nfunctions = nfuncs;
569 info->functions = devm_kcalloc(&pdev->dev,
570 nfuncs, sizeof(struct imx1_pmx_func), GFP_KERNEL);
571
572 info->ngroups = ngroups;
573 info->groups = devm_kcalloc(&pdev->dev,
574 ngroups, sizeof(struct imx1_pin_group), GFP_KERNEL);
575
576
577 if (!info->functions || !info->groups)
578 return -ENOMEM;
579
580 for_each_child_of_node(np, child) {
581 ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
582 if (ret == -ENOMEM) {
583 of_node_put(child);
584 return -ENOMEM;
585 }
586 }
587
588 return 0;
589 }
590
591 int imx1_pinctrl_core_probe(struct platform_device *pdev,
592 struct imx1_pinctrl_soc_info *info)
593 {
594 struct imx1_pinctrl *ipctl;
595 struct resource *res;
596 struct pinctrl_desc *pctl_desc;
597 int ret;
598
599 if (!info || !info->pins || !info->npins) {
600 dev_err(&pdev->dev, "wrong pinctrl info\n");
601 return -EINVAL;
602 }
603 info->dev = &pdev->dev;
604
605
606 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
607 if (!ipctl)
608 return -ENOMEM;
609
610 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
611 if (!res)
612 return -ENOENT;
613
614 ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start,
615 resource_size(res));
616 if (!ipctl->base)
617 return -ENOMEM;
618
619 pctl_desc = &imx1_pinctrl_desc;
620 pctl_desc->name = dev_name(&pdev->dev);
621 pctl_desc->pins = info->pins;
622 pctl_desc->npins = info->npins;
623
624 ret = imx1_pinctrl_parse_dt(pdev, ipctl, info);
625 if (ret) {
626 dev_err(&pdev->dev, "fail to probe dt properties\n");
627 return ret;
628 }
629
630 ipctl->info = info;
631 ipctl->dev = info->dev;
632 platform_set_drvdata(pdev, ipctl);
633 ipctl->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, ipctl);
634 if (IS_ERR(ipctl->pctl)) {
635 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
636 return PTR_ERR(ipctl->pctl);
637 }
638
639 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
640 if (ret) {
641 pinctrl_unregister(ipctl->pctl);
642 dev_err(&pdev->dev, "Failed to populate subdevices\n");
643 return ret;
644 }
645
646 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
647
648 return 0;
649 }