root/drivers/pinctrl/bcm/pinctrl-bcm2835.c

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DEFINITIONS

This source file includes following definitions.
  1. bcm2835_gpio_rd
  2. bcm2835_gpio_wr
  3. bcm2835_gpio_get_bit
  4. bcm2835_gpio_set_bit
  5. bcm2835_pinctrl_fsel_get
  6. bcm2835_pinctrl_fsel_set
  7. bcm2835_gpio_direction_input
  8. bcm2835_gpio_get
  9. bcm2835_gpio_get_direction
  10. bcm2835_gpio_set
  11. bcm2835_gpio_direction_output
  12. bcm2835_gpio_irq_handle_bank
  13. bcm2835_gpio_irq_handler
  14. __bcm2835_gpio_irq_config
  15. bcm2835_gpio_irq_config
  16. bcm2835_gpio_irq_enable
  17. bcm2835_gpio_irq_disable
  18. __bcm2835_gpio_irq_set_type_disabled
  19. __bcm2835_gpio_irq_set_type_enabled
  20. bcm2835_gpio_irq_set_type
  21. bcm2835_gpio_irq_ack
  22. bcm2835_pctl_get_groups_count
  23. bcm2835_pctl_get_group_name
  24. bcm2835_pctl_get_group_pins
  25. bcm2835_pctl_pin_dbg_show
  26. bcm2835_pctl_dt_free_map
  27. bcm2835_pctl_dt_node_to_map_func
  28. bcm2835_pctl_dt_node_to_map_pull
  29. bcm2835_pctl_dt_node_to_map
  30. bcm2835_pmx_free
  31. bcm2835_pmx_get_functions_count
  32. bcm2835_pmx_get_function_name
  33. bcm2835_pmx_get_function_groups
  34. bcm2835_pmx_set
  35. bcm2835_pmx_gpio_disable_free
  36. bcm2835_pmx_gpio_set_direction
  37. bcm2835_pinconf_get
  38. bcm2835_pull_config_set
  39. bcm2835_pinconf_set
  40. bcm2711_pull_config_set
  41. bcm2711_pinconf_set
  42. bcm2835_pinctrl_probe

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
   4  *
   5  * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
   6  *
   7  * This driver is inspired by:
   8  * pinctrl-nomadik.c, please see original file for copyright information
   9  * pinctrl-tegra.c, please see original file for copyright information
  10  */
  11 
  12 #include <linux/bitmap.h>
  13 #include <linux/bug.h>
  14 #include <linux/delay.h>
  15 #include <linux/device.h>
  16 #include <linux/err.h>
  17 #include <linux/gpio/driver.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20 #include <linux/irqdesc.h>
  21 #include <linux/init.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/pinctrl/machine.h>
  27 #include <linux/pinctrl/pinconf.h>
  28 #include <linux/pinctrl/pinctrl.h>
  29 #include <linux/pinctrl/pinmux.h>
  30 #include <linux/pinctrl/pinconf-generic.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/slab.h>
  34 #include <linux/spinlock.h>
  35 #include <linux/types.h>
  36 #include <dt-bindings/pinctrl/bcm2835.h>
  37 
  38 #define MODULE_NAME "pinctrl-bcm2835"
  39 #define BCM2835_NUM_GPIOS 54
  40 #define BCM2835_NUM_BANKS 2
  41 #define BCM2835_NUM_IRQS  3
  42 
  43 #define BCM2835_PIN_BITMAP_SZ \
  44         DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
  45 
  46 /* GPIO register offsets */
  47 #define GPFSEL0         0x0     /* Function Select */
  48 #define GPSET0          0x1c    /* Pin Output Set */
  49 #define GPCLR0          0x28    /* Pin Output Clear */
  50 #define GPLEV0          0x34    /* Pin Level */
  51 #define GPEDS0          0x40    /* Pin Event Detect Status */
  52 #define GPREN0          0x4c    /* Pin Rising Edge Detect Enable */
  53 #define GPFEN0          0x58    /* Pin Falling Edge Detect Enable */
  54 #define GPHEN0          0x64    /* Pin High Detect Enable */
  55 #define GPLEN0          0x70    /* Pin Low Detect Enable */
  56 #define GPAREN0         0x7c    /* Pin Async Rising Edge Detect */
  57 #define GPAFEN0         0x88    /* Pin Async Falling Edge Detect */
  58 #define GPPUD           0x94    /* Pin Pull-up/down Enable */
  59 #define GPPUDCLK0       0x98    /* Pin Pull-up/down Enable Clock */
  60 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
  61 
  62 #define FSEL_REG(p)             (GPFSEL0 + (((p) / 10) * 4))
  63 #define FSEL_SHIFT(p)           (((p) % 10) * 3)
  64 #define GPIO_REG_OFFSET(p)      ((p) / 32)
  65 #define GPIO_REG_SHIFT(p)       ((p) % 32)
  66 
  67 #define PUD_2711_MASK           0x3
  68 #define PUD_2711_REG_OFFSET(p)  ((p) / 16)
  69 #define PUD_2711_REG_SHIFT(p)   (((p) % 16) * 2)
  70 
  71 /* argument: bcm2835_pinconf_pull */
  72 #define BCM2835_PINCONF_PARAM_PULL      (PIN_CONFIG_END + 1)
  73 
  74 #define BCM2711_PULL_NONE       0x0
  75 #define BCM2711_PULL_UP         0x1
  76 #define BCM2711_PULL_DOWN       0x2
  77 
  78 struct bcm2835_pinctrl {
  79         struct device *dev;
  80         void __iomem *base;
  81 
  82         /* note: locking assumes each bank will have its own unsigned long */
  83         unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
  84         unsigned int irq_type[BCM2835_NUM_GPIOS];
  85 
  86         struct pinctrl_dev *pctl_dev;
  87         struct gpio_chip gpio_chip;
  88         struct pinctrl_gpio_range gpio_range;
  89 
  90         raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
  91 };
  92 
  93 /* pins are just named GPIO0..GPIO53 */
  94 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
  95 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
  96         BCM2835_GPIO_PIN(0),
  97         BCM2835_GPIO_PIN(1),
  98         BCM2835_GPIO_PIN(2),
  99         BCM2835_GPIO_PIN(3),
 100         BCM2835_GPIO_PIN(4),
 101         BCM2835_GPIO_PIN(5),
 102         BCM2835_GPIO_PIN(6),
 103         BCM2835_GPIO_PIN(7),
 104         BCM2835_GPIO_PIN(8),
 105         BCM2835_GPIO_PIN(9),
 106         BCM2835_GPIO_PIN(10),
 107         BCM2835_GPIO_PIN(11),
 108         BCM2835_GPIO_PIN(12),
 109         BCM2835_GPIO_PIN(13),
 110         BCM2835_GPIO_PIN(14),
 111         BCM2835_GPIO_PIN(15),
 112         BCM2835_GPIO_PIN(16),
 113         BCM2835_GPIO_PIN(17),
 114         BCM2835_GPIO_PIN(18),
 115         BCM2835_GPIO_PIN(19),
 116         BCM2835_GPIO_PIN(20),
 117         BCM2835_GPIO_PIN(21),
 118         BCM2835_GPIO_PIN(22),
 119         BCM2835_GPIO_PIN(23),
 120         BCM2835_GPIO_PIN(24),
 121         BCM2835_GPIO_PIN(25),
 122         BCM2835_GPIO_PIN(26),
 123         BCM2835_GPIO_PIN(27),
 124         BCM2835_GPIO_PIN(28),
 125         BCM2835_GPIO_PIN(29),
 126         BCM2835_GPIO_PIN(30),
 127         BCM2835_GPIO_PIN(31),
 128         BCM2835_GPIO_PIN(32),
 129         BCM2835_GPIO_PIN(33),
 130         BCM2835_GPIO_PIN(34),
 131         BCM2835_GPIO_PIN(35),
 132         BCM2835_GPIO_PIN(36),
 133         BCM2835_GPIO_PIN(37),
 134         BCM2835_GPIO_PIN(38),
 135         BCM2835_GPIO_PIN(39),
 136         BCM2835_GPIO_PIN(40),
 137         BCM2835_GPIO_PIN(41),
 138         BCM2835_GPIO_PIN(42),
 139         BCM2835_GPIO_PIN(43),
 140         BCM2835_GPIO_PIN(44),
 141         BCM2835_GPIO_PIN(45),
 142         BCM2835_GPIO_PIN(46),
 143         BCM2835_GPIO_PIN(47),
 144         BCM2835_GPIO_PIN(48),
 145         BCM2835_GPIO_PIN(49),
 146         BCM2835_GPIO_PIN(50),
 147         BCM2835_GPIO_PIN(51),
 148         BCM2835_GPIO_PIN(52),
 149         BCM2835_GPIO_PIN(53),
 150 };
 151 
 152 /* one pin per group */
 153 static const char * const bcm2835_gpio_groups[] = {
 154         "gpio0",
 155         "gpio1",
 156         "gpio2",
 157         "gpio3",
 158         "gpio4",
 159         "gpio5",
 160         "gpio6",
 161         "gpio7",
 162         "gpio8",
 163         "gpio9",
 164         "gpio10",
 165         "gpio11",
 166         "gpio12",
 167         "gpio13",
 168         "gpio14",
 169         "gpio15",
 170         "gpio16",
 171         "gpio17",
 172         "gpio18",
 173         "gpio19",
 174         "gpio20",
 175         "gpio21",
 176         "gpio22",
 177         "gpio23",
 178         "gpio24",
 179         "gpio25",
 180         "gpio26",
 181         "gpio27",
 182         "gpio28",
 183         "gpio29",
 184         "gpio30",
 185         "gpio31",
 186         "gpio32",
 187         "gpio33",
 188         "gpio34",
 189         "gpio35",
 190         "gpio36",
 191         "gpio37",
 192         "gpio38",
 193         "gpio39",
 194         "gpio40",
 195         "gpio41",
 196         "gpio42",
 197         "gpio43",
 198         "gpio44",
 199         "gpio45",
 200         "gpio46",
 201         "gpio47",
 202         "gpio48",
 203         "gpio49",
 204         "gpio50",
 205         "gpio51",
 206         "gpio52",
 207         "gpio53",
 208 };
 209 
 210 enum bcm2835_fsel {
 211         BCM2835_FSEL_COUNT = 8,
 212         BCM2835_FSEL_MASK = 0x7,
 213 };
 214 
 215 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
 216         [BCM2835_FSEL_GPIO_IN] = "gpio_in",
 217         [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
 218         [BCM2835_FSEL_ALT0] = "alt0",
 219         [BCM2835_FSEL_ALT1] = "alt1",
 220         [BCM2835_FSEL_ALT2] = "alt2",
 221         [BCM2835_FSEL_ALT3] = "alt3",
 222         [BCM2835_FSEL_ALT4] = "alt4",
 223         [BCM2835_FSEL_ALT5] = "alt5",
 224 };
 225 
 226 static const char * const irq_type_names[] = {
 227         [IRQ_TYPE_NONE] = "none",
 228         [IRQ_TYPE_EDGE_RISING] = "edge-rising",
 229         [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
 230         [IRQ_TYPE_EDGE_BOTH] = "edge-both",
 231         [IRQ_TYPE_LEVEL_HIGH] = "level-high",
 232         [IRQ_TYPE_LEVEL_LOW] = "level-low",
 233 };
 234 
 235 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
 236 {
 237         return readl(pc->base + reg);
 238 }
 239 
 240 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
 241                 u32 val)
 242 {
 243         writel(val, pc->base + reg);
 244 }
 245 
 246 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
 247                 unsigned bit)
 248 {
 249         reg += GPIO_REG_OFFSET(bit) * 4;
 250         return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
 251 }
 252 
 253 /* note NOT a read/modify/write cycle */
 254 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
 255                 unsigned reg, unsigned bit)
 256 {
 257         reg += GPIO_REG_OFFSET(bit) * 4;
 258         bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
 259 }
 260 
 261 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
 262                 struct bcm2835_pinctrl *pc, unsigned pin)
 263 {
 264         u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
 265         enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
 266 
 267         dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
 268                         bcm2835_functions[status]);
 269 
 270         return status;
 271 }
 272 
 273 static inline void bcm2835_pinctrl_fsel_set(
 274                 struct bcm2835_pinctrl *pc, unsigned pin,
 275                 enum bcm2835_fsel fsel)
 276 {
 277         u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
 278         enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
 279 
 280         dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
 281                         bcm2835_functions[cur]);
 282 
 283         if (cur == fsel)
 284                 return;
 285 
 286         if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
 287                 /* always transition through GPIO_IN */
 288                 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
 289                 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
 290 
 291                 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
 292                                 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
 293                 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
 294         }
 295 
 296         val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
 297         val |= fsel << FSEL_SHIFT(pin);
 298 
 299         dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
 300                         bcm2835_functions[fsel]);
 301         bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
 302 }
 303 
 304 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 305 {
 306         return pinctrl_gpio_direction_input(chip->base + offset);
 307 }
 308 
 309 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
 310 {
 311         struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 312 
 313         return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
 314 }
 315 
 316 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 317 {
 318         struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 319         enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
 320 
 321         /* Alternative function doesn't clearly provide a direction */
 322         if (fsel > BCM2835_FSEL_GPIO_OUT)
 323                 return -EINVAL;
 324 
 325         return (fsel == BCM2835_FSEL_GPIO_IN);
 326 }
 327 
 328 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 329 {
 330         struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 331 
 332         bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
 333 }
 334 
 335 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
 336                 unsigned offset, int value)
 337 {
 338         bcm2835_gpio_set(chip, offset, value);
 339         return pinctrl_gpio_direction_output(chip->base + offset);
 340 }
 341 
 342 static const struct gpio_chip bcm2835_gpio_chip = {
 343         .label = MODULE_NAME,
 344         .owner = THIS_MODULE,
 345         .request = gpiochip_generic_request,
 346         .free = gpiochip_generic_free,
 347         .direction_input = bcm2835_gpio_direction_input,
 348         .direction_output = bcm2835_gpio_direction_output,
 349         .get_direction = bcm2835_gpio_get_direction,
 350         .get = bcm2835_gpio_get,
 351         .set = bcm2835_gpio_set,
 352         .set_config = gpiochip_generic_config,
 353         .base = -1,
 354         .ngpio = BCM2835_NUM_GPIOS,
 355         .can_sleep = false,
 356 };
 357 
 358 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
 359                                          unsigned int bank, u32 mask)
 360 {
 361         unsigned long events;
 362         unsigned offset;
 363         unsigned gpio;
 364 
 365         events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
 366         events &= mask;
 367         events &= pc->enabled_irq_map[bank];
 368         for_each_set_bit(offset, &events, 32) {
 369                 gpio = (32 * bank) + offset;
 370                 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
 371                                                      gpio));
 372         }
 373 }
 374 
 375 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
 376 {
 377         struct gpio_chip *chip = irq_desc_get_handler_data(desc);
 378         struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 379         struct irq_chip *host_chip = irq_desc_get_chip(desc);
 380         int irq = irq_desc_get_irq(desc);
 381         int group;
 382         int i;
 383 
 384         for (i = 0; i < BCM2835_NUM_IRQS; i++) {
 385                 if (chip->irq.parents[i] == irq) {
 386                         group = i;
 387                         break;
 388                 }
 389         }
 390         /* This should not happen, every IRQ has a bank */
 391         if (i == BCM2835_NUM_IRQS)
 392                 BUG();
 393 
 394         chained_irq_enter(host_chip, desc);
 395 
 396         switch (group) {
 397         case 0: /* IRQ0 covers GPIOs 0-27 */
 398                 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
 399                 break;
 400         case 1: /* IRQ1 covers GPIOs 28-45 */
 401                 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
 402                 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
 403                 break;
 404         case 2: /* IRQ2 covers GPIOs 46-53 */
 405                 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
 406                 break;
 407         }
 408 
 409         chained_irq_exit(host_chip, desc);
 410 }
 411 
 412 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
 413         unsigned reg, unsigned offset, bool enable)
 414 {
 415         u32 value;
 416         reg += GPIO_REG_OFFSET(offset) * 4;
 417         value = bcm2835_gpio_rd(pc, reg);
 418         if (enable)
 419                 value |= BIT(GPIO_REG_SHIFT(offset));
 420         else
 421                 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
 422         bcm2835_gpio_wr(pc, reg, value);
 423 }
 424 
 425 /* fast path for IRQ handler */
 426 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
 427         unsigned offset, bool enable)
 428 {
 429         switch (pc->irq_type[offset]) {
 430         case IRQ_TYPE_EDGE_RISING:
 431                 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
 432                 break;
 433 
 434         case IRQ_TYPE_EDGE_FALLING:
 435                 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
 436                 break;
 437 
 438         case IRQ_TYPE_EDGE_BOTH:
 439                 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
 440                 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
 441                 break;
 442 
 443         case IRQ_TYPE_LEVEL_HIGH:
 444                 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
 445                 break;
 446 
 447         case IRQ_TYPE_LEVEL_LOW:
 448                 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
 449                 break;
 450         }
 451 }
 452 
 453 static void bcm2835_gpio_irq_enable(struct irq_data *data)
 454 {
 455         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 456         struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 457         unsigned gpio = irqd_to_hwirq(data);
 458         unsigned offset = GPIO_REG_SHIFT(gpio);
 459         unsigned bank = GPIO_REG_OFFSET(gpio);
 460         unsigned long flags;
 461 
 462         raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
 463         set_bit(offset, &pc->enabled_irq_map[bank]);
 464         bcm2835_gpio_irq_config(pc, gpio, true);
 465         raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
 466 }
 467 
 468 static void bcm2835_gpio_irq_disable(struct irq_data *data)
 469 {
 470         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 471         struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 472         unsigned gpio = irqd_to_hwirq(data);
 473         unsigned offset = GPIO_REG_SHIFT(gpio);
 474         unsigned bank = GPIO_REG_OFFSET(gpio);
 475         unsigned long flags;
 476 
 477         raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
 478         bcm2835_gpio_irq_config(pc, gpio, false);
 479         /* Clear events that were latched prior to clearing event sources */
 480         bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
 481         clear_bit(offset, &pc->enabled_irq_map[bank]);
 482         raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
 483 }
 484 
 485 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
 486         unsigned offset, unsigned int type)
 487 {
 488         switch (type) {
 489         case IRQ_TYPE_NONE:
 490         case IRQ_TYPE_EDGE_RISING:
 491         case IRQ_TYPE_EDGE_FALLING:
 492         case IRQ_TYPE_EDGE_BOTH:
 493         case IRQ_TYPE_LEVEL_HIGH:
 494         case IRQ_TYPE_LEVEL_LOW:
 495                 pc->irq_type[offset] = type;
 496                 break;
 497 
 498         default:
 499                 return -EINVAL;
 500         }
 501         return 0;
 502 }
 503 
 504 /* slower path for reconfiguring IRQ type */
 505 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
 506         unsigned offset, unsigned int type)
 507 {
 508         switch (type) {
 509         case IRQ_TYPE_NONE:
 510                 if (pc->irq_type[offset] != type) {
 511                         bcm2835_gpio_irq_config(pc, offset, false);
 512                         pc->irq_type[offset] = type;
 513                 }
 514                 break;
 515 
 516         case IRQ_TYPE_EDGE_RISING:
 517                 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
 518                         /* RISING already enabled, disable FALLING */
 519                         pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
 520                         bcm2835_gpio_irq_config(pc, offset, false);
 521                         pc->irq_type[offset] = type;
 522                 } else if (pc->irq_type[offset] != type) {
 523                         bcm2835_gpio_irq_config(pc, offset, false);
 524                         pc->irq_type[offset] = type;
 525                         bcm2835_gpio_irq_config(pc, offset, true);
 526                 }
 527                 break;
 528 
 529         case IRQ_TYPE_EDGE_FALLING:
 530                 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
 531                         /* FALLING already enabled, disable RISING */
 532                         pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
 533                         bcm2835_gpio_irq_config(pc, offset, false);
 534                         pc->irq_type[offset] = type;
 535                 } else if (pc->irq_type[offset] != type) {
 536                         bcm2835_gpio_irq_config(pc, offset, false);
 537                         pc->irq_type[offset] = type;
 538                         bcm2835_gpio_irq_config(pc, offset, true);
 539                 }
 540                 break;
 541 
 542         case IRQ_TYPE_EDGE_BOTH:
 543                 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
 544                         /* RISING already enabled, enable FALLING too */
 545                         pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
 546                         bcm2835_gpio_irq_config(pc, offset, true);
 547                         pc->irq_type[offset] = type;
 548                 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
 549                         /* FALLING already enabled, enable RISING too */
 550                         pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
 551                         bcm2835_gpio_irq_config(pc, offset, true);
 552                         pc->irq_type[offset] = type;
 553                 } else if (pc->irq_type[offset] != type) {
 554                         bcm2835_gpio_irq_config(pc, offset, false);
 555                         pc->irq_type[offset] = type;
 556                         bcm2835_gpio_irq_config(pc, offset, true);
 557                 }
 558                 break;
 559 
 560         case IRQ_TYPE_LEVEL_HIGH:
 561         case IRQ_TYPE_LEVEL_LOW:
 562                 if (pc->irq_type[offset] != type) {
 563                         bcm2835_gpio_irq_config(pc, offset, false);
 564                         pc->irq_type[offset] = type;
 565                         bcm2835_gpio_irq_config(pc, offset, true);
 566                 }
 567                 break;
 568 
 569         default:
 570                 return -EINVAL;
 571         }
 572         return 0;
 573 }
 574 
 575 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
 576 {
 577         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 578         struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 579         unsigned gpio = irqd_to_hwirq(data);
 580         unsigned offset = GPIO_REG_SHIFT(gpio);
 581         unsigned bank = GPIO_REG_OFFSET(gpio);
 582         unsigned long flags;
 583         int ret;
 584 
 585         raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
 586 
 587         if (test_bit(offset, &pc->enabled_irq_map[bank]))
 588                 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
 589         else
 590                 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
 591 
 592         if (type & IRQ_TYPE_EDGE_BOTH)
 593                 irq_set_handler_locked(data, handle_edge_irq);
 594         else
 595                 irq_set_handler_locked(data, handle_level_irq);
 596 
 597         raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
 598 
 599         return ret;
 600 }
 601 
 602 static void bcm2835_gpio_irq_ack(struct irq_data *data)
 603 {
 604         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 605         struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 606         unsigned gpio = irqd_to_hwirq(data);
 607 
 608         bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
 609 }
 610 
 611 static struct irq_chip bcm2835_gpio_irq_chip = {
 612         .name = MODULE_NAME,
 613         .irq_enable = bcm2835_gpio_irq_enable,
 614         .irq_disable = bcm2835_gpio_irq_disable,
 615         .irq_set_type = bcm2835_gpio_irq_set_type,
 616         .irq_ack = bcm2835_gpio_irq_ack,
 617         .irq_mask = bcm2835_gpio_irq_disable,
 618         .irq_unmask = bcm2835_gpio_irq_enable,
 619 };
 620 
 621 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
 622 {
 623         return ARRAY_SIZE(bcm2835_gpio_groups);
 624 }
 625 
 626 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
 627                 unsigned selector)
 628 {
 629         return bcm2835_gpio_groups[selector];
 630 }
 631 
 632 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
 633                 unsigned selector,
 634                 const unsigned **pins,
 635                 unsigned *num_pins)
 636 {
 637         *pins = &bcm2835_gpio_pins[selector].number;
 638         *num_pins = 1;
 639 
 640         return 0;
 641 }
 642 
 643 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
 644                 struct seq_file *s,
 645                 unsigned offset)
 646 {
 647         struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
 648         struct gpio_chip *chip = &pc->gpio_chip;
 649         enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
 650         const char *fname = bcm2835_functions[fsel];
 651         int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
 652         int irq = irq_find_mapping(chip->irq.domain, offset);
 653 
 654         seq_printf(s, "function %s in %s; irq %d (%s)",
 655                 fname, value ? "hi" : "lo",
 656                 irq, irq_type_names[pc->irq_type[offset]]);
 657 }
 658 
 659 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
 660                 struct pinctrl_map *maps, unsigned num_maps)
 661 {
 662         int i;
 663 
 664         for (i = 0; i < num_maps; i++)
 665                 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
 666                         kfree(maps[i].data.configs.configs);
 667 
 668         kfree(maps);
 669 }
 670 
 671 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
 672                 struct device_node *np, u32 pin, u32 fnum,
 673                 struct pinctrl_map **maps)
 674 {
 675         struct pinctrl_map *map = *maps;
 676 
 677         if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
 678                 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
 679                 return -EINVAL;
 680         }
 681 
 682         map->type = PIN_MAP_TYPE_MUX_GROUP;
 683         map->data.mux.group = bcm2835_gpio_groups[pin];
 684         map->data.mux.function = bcm2835_functions[fnum];
 685         (*maps)++;
 686 
 687         return 0;
 688 }
 689 
 690 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
 691                 struct device_node *np, u32 pin, u32 pull,
 692                 struct pinctrl_map **maps)
 693 {
 694         struct pinctrl_map *map = *maps;
 695         unsigned long *configs;
 696 
 697         if (pull > 2) {
 698                 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
 699                 return -EINVAL;
 700         }
 701 
 702         configs = kzalloc(sizeof(*configs), GFP_KERNEL);
 703         if (!configs)
 704                 return -ENOMEM;
 705         configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
 706 
 707         map->type = PIN_MAP_TYPE_CONFIGS_PIN;
 708         map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
 709         map->data.configs.configs = configs;
 710         map->data.configs.num_configs = 1;
 711         (*maps)++;
 712 
 713         return 0;
 714 }
 715 
 716 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
 717                 struct device_node *np,
 718                 struct pinctrl_map **map, unsigned int *num_maps)
 719 {
 720         struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
 721         struct property *pins, *funcs, *pulls;
 722         int num_pins, num_funcs, num_pulls, maps_per_pin;
 723         struct pinctrl_map *maps, *cur_map;
 724         int i, err;
 725         u32 pin, func, pull;
 726 
 727         /* Check for generic binding in this node */
 728         err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
 729         if (err || *num_maps)
 730                 return err;
 731 
 732         /* Generic binding did not find anything continue with legacy parse */
 733         pins = of_find_property(np, "brcm,pins", NULL);
 734         if (!pins) {
 735                 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
 736                 return -EINVAL;
 737         }
 738 
 739         funcs = of_find_property(np, "brcm,function", NULL);
 740         pulls = of_find_property(np, "brcm,pull", NULL);
 741 
 742         if (!funcs && !pulls) {
 743                 dev_err(pc->dev,
 744                         "%pOF: neither brcm,function nor brcm,pull specified\n",
 745                         np);
 746                 return -EINVAL;
 747         }
 748 
 749         num_pins = pins->length / 4;
 750         num_funcs = funcs ? (funcs->length / 4) : 0;
 751         num_pulls = pulls ? (pulls->length / 4) : 0;
 752 
 753         if (num_funcs > 1 && num_funcs != num_pins) {
 754                 dev_err(pc->dev,
 755                         "%pOF: brcm,function must have 1 or %d entries\n",
 756                         np, num_pins);
 757                 return -EINVAL;
 758         }
 759 
 760         if (num_pulls > 1 && num_pulls != num_pins) {
 761                 dev_err(pc->dev,
 762                         "%pOF: brcm,pull must have 1 or %d entries\n",
 763                         np, num_pins);
 764                 return -EINVAL;
 765         }
 766 
 767         maps_per_pin = 0;
 768         if (num_funcs)
 769                 maps_per_pin++;
 770         if (num_pulls)
 771                 maps_per_pin++;
 772         cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
 773                                  GFP_KERNEL);
 774         if (!maps)
 775                 return -ENOMEM;
 776 
 777         for (i = 0; i < num_pins; i++) {
 778                 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
 779                 if (err)
 780                         goto out;
 781                 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
 782                         dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
 783                                 np, pin);
 784                         err = -EINVAL;
 785                         goto out;
 786                 }
 787 
 788                 if (num_funcs) {
 789                         err = of_property_read_u32_index(np, "brcm,function",
 790                                         (num_funcs > 1) ? i : 0, &func);
 791                         if (err)
 792                                 goto out;
 793                         err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
 794                                                         func, &cur_map);
 795                         if (err)
 796                                 goto out;
 797                 }
 798                 if (num_pulls) {
 799                         err = of_property_read_u32_index(np, "brcm,pull",
 800                                         (num_pulls > 1) ? i : 0, &pull);
 801                         if (err)
 802                                 goto out;
 803                         err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
 804                                                         pull, &cur_map);
 805                         if (err)
 806                                 goto out;
 807                 }
 808         }
 809 
 810         *map = maps;
 811         *num_maps = num_pins * maps_per_pin;
 812 
 813         return 0;
 814 
 815 out:
 816         bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
 817         return err;
 818 }
 819 
 820 static const struct pinctrl_ops bcm2835_pctl_ops = {
 821         .get_groups_count = bcm2835_pctl_get_groups_count,
 822         .get_group_name = bcm2835_pctl_get_group_name,
 823         .get_group_pins = bcm2835_pctl_get_group_pins,
 824         .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
 825         .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
 826         .dt_free_map = bcm2835_pctl_dt_free_map,
 827 };
 828 
 829 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
 830                 unsigned offset)
 831 {
 832         struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
 833 
 834         /* disable by setting to GPIO_IN */
 835         bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
 836         return 0;
 837 }
 838 
 839 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
 840 {
 841         return BCM2835_FSEL_COUNT;
 842 }
 843 
 844 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
 845                 unsigned selector)
 846 {
 847         return bcm2835_functions[selector];
 848 }
 849 
 850 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
 851                 unsigned selector,
 852                 const char * const **groups,
 853                 unsigned * const num_groups)
 854 {
 855         /* every pin can do every function */
 856         *groups = bcm2835_gpio_groups;
 857         *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
 858 
 859         return 0;
 860 }
 861 
 862 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
 863                 unsigned func_selector,
 864                 unsigned group_selector)
 865 {
 866         struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
 867 
 868         bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
 869 
 870         return 0;
 871 }
 872 
 873 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
 874                 struct pinctrl_gpio_range *range,
 875                 unsigned offset)
 876 {
 877         struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
 878 
 879         /* disable by setting to GPIO_IN */
 880         bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
 881 }
 882 
 883 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 884                 struct pinctrl_gpio_range *range,
 885                 unsigned offset,
 886                 bool input)
 887 {
 888         struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
 889         enum bcm2835_fsel fsel = input ?
 890                 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
 891 
 892         bcm2835_pinctrl_fsel_set(pc, offset, fsel);
 893 
 894         return 0;
 895 }
 896 
 897 static const struct pinmux_ops bcm2835_pmx_ops = {
 898         .free = bcm2835_pmx_free,
 899         .get_functions_count = bcm2835_pmx_get_functions_count,
 900         .get_function_name = bcm2835_pmx_get_function_name,
 901         .get_function_groups = bcm2835_pmx_get_function_groups,
 902         .set_mux = bcm2835_pmx_set,
 903         .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
 904         .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
 905 };
 906 
 907 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
 908                         unsigned pin, unsigned long *config)
 909 {
 910         /* No way to read back config in HW */
 911         return -ENOTSUPP;
 912 }
 913 
 914 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
 915                 unsigned int pin, unsigned int arg)
 916 {
 917         u32 off, bit;
 918 
 919         off = GPIO_REG_OFFSET(pin);
 920         bit = GPIO_REG_SHIFT(pin);
 921 
 922         bcm2835_gpio_wr(pc, GPPUD, arg & 3);
 923         /*
 924          * BCM2835 datasheet say to wait 150 cycles, but not of what.
 925          * But the VideoCore firmware delay for this operation
 926          * based nearly on the same amount of VPU cycles and this clock
 927          * runs at 250 MHz.
 928          */
 929         udelay(1);
 930         bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
 931         udelay(1);
 932         bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
 933 }
 934 
 935 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
 936                         unsigned int pin, unsigned long *configs,
 937                         unsigned int num_configs)
 938 {
 939         struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
 940         u32 param, arg;
 941         int i;
 942 
 943         for (i = 0; i < num_configs; i++) {
 944                 param = pinconf_to_config_param(configs[i]);
 945                 arg = pinconf_to_config_argument(configs[i]);
 946 
 947                 switch (param) {
 948                 /* Set legacy brcm,pull */
 949                 case BCM2835_PINCONF_PARAM_PULL:
 950                         bcm2835_pull_config_set(pc, pin, arg);
 951                         break;
 952 
 953                 /* Set pull generic bindings */
 954                 case PIN_CONFIG_BIAS_DISABLE:
 955                         bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
 956                         break;
 957 
 958                 case PIN_CONFIG_BIAS_PULL_DOWN:
 959                         bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
 960                         break;
 961 
 962                 case PIN_CONFIG_BIAS_PULL_UP:
 963                         bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
 964                         break;
 965 
 966                 /* Set output-high or output-low */
 967                 case PIN_CONFIG_OUTPUT:
 968                         bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
 969                         break;
 970 
 971                 default:
 972                         return -ENOTSUPP;
 973 
 974                 } /* switch param type */
 975         } /* for each config */
 976 
 977         return 0;
 978 }
 979 
 980 static const struct pinconf_ops bcm2835_pinconf_ops = {
 981         .is_generic = true,
 982         .pin_config_get = bcm2835_pinconf_get,
 983         .pin_config_set = bcm2835_pinconf_set,
 984 };
 985 
 986 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
 987                                     unsigned int pin, unsigned int arg)
 988 {
 989         u32 shifter;
 990         u32 value;
 991         u32 off;
 992 
 993         off = PUD_2711_REG_OFFSET(pin);
 994         shifter = PUD_2711_REG_SHIFT(pin);
 995 
 996         value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
 997         value &= ~(PUD_2711_MASK << shifter);
 998         value |= (arg << shifter);
 999         bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1000 }
1001 
1002 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1003                                unsigned int pin, unsigned long *configs,
1004                                unsigned int num_configs)
1005 {
1006         struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1007         u32 param, arg;
1008         int i;
1009 
1010         for (i = 0; i < num_configs; i++) {
1011                 param = pinconf_to_config_param(configs[i]);
1012                 arg = pinconf_to_config_argument(configs[i]);
1013 
1014                 switch (param) {
1015                 /* convert legacy brcm,pull */
1016                 case BCM2835_PINCONF_PARAM_PULL:
1017                         if (arg == BCM2835_PUD_UP)
1018                                 arg = BCM2711_PULL_UP;
1019                         else if (arg == BCM2835_PUD_DOWN)
1020                                 arg = BCM2711_PULL_DOWN;
1021                         else
1022                                 arg = BCM2711_PULL_NONE;
1023 
1024                         bcm2711_pull_config_set(pc, pin, arg);
1025                         break;
1026 
1027                 /* Set pull generic bindings */
1028                 case PIN_CONFIG_BIAS_DISABLE:
1029                         bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1030                         break;
1031                 case PIN_CONFIG_BIAS_PULL_DOWN:
1032                         bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1033                         break;
1034                 case PIN_CONFIG_BIAS_PULL_UP:
1035                         bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1036                         break;
1037 
1038                 /* Set output-high or output-low */
1039                 case PIN_CONFIG_OUTPUT:
1040                         bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1041                         break;
1042 
1043                 default:
1044                         return -ENOTSUPP;
1045                 }
1046         } /* for each config */
1047 
1048         return 0;
1049 }
1050 
1051 static const struct pinconf_ops bcm2711_pinconf_ops = {
1052         .is_generic = true,
1053         .pin_config_get = bcm2835_pinconf_get,
1054         .pin_config_set = bcm2711_pinconf_set,
1055 };
1056 
1057 static struct pinctrl_desc bcm2835_pinctrl_desc = {
1058         .name = MODULE_NAME,
1059         .pins = bcm2835_gpio_pins,
1060         .npins = ARRAY_SIZE(bcm2835_gpio_pins),
1061         .pctlops = &bcm2835_pctl_ops,
1062         .pmxops = &bcm2835_pmx_ops,
1063         .confops = &bcm2835_pinconf_ops,
1064         .owner = THIS_MODULE,
1065 };
1066 
1067 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1068         .name = MODULE_NAME,
1069         .npins = BCM2835_NUM_GPIOS,
1070 };
1071 
1072 static const struct of_device_id bcm2835_pinctrl_match[] = {
1073         {
1074                 .compatible = "brcm,bcm2835-gpio",
1075                 .data = &bcm2835_pinconf_ops,
1076         },
1077         {
1078                 .compatible = "brcm,bcm2711-gpio",
1079                 .data = &bcm2711_pinconf_ops,
1080         },
1081         {}
1082 };
1083 
1084 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1085 {
1086         struct device *dev = &pdev->dev;
1087         struct device_node *np = dev->of_node;
1088         struct bcm2835_pinctrl *pc;
1089         struct gpio_irq_chip *girq;
1090         struct resource iomem;
1091         int err, i;
1092         const struct of_device_id *match;
1093 
1094         BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
1095         BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
1096 
1097         pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1098         if (!pc)
1099                 return -ENOMEM;
1100 
1101         platform_set_drvdata(pdev, pc);
1102         pc->dev = dev;
1103 
1104         err = of_address_to_resource(np, 0, &iomem);
1105         if (err) {
1106                 dev_err(dev, "could not get IO memory\n");
1107                 return err;
1108         }
1109 
1110         pc->base = devm_ioremap_resource(dev, &iomem);
1111         if (IS_ERR(pc->base))
1112                 return PTR_ERR(pc->base);
1113 
1114         pc->gpio_chip = bcm2835_gpio_chip;
1115         pc->gpio_chip.parent = dev;
1116         pc->gpio_chip.of_node = np;
1117 
1118         for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1119                 unsigned long events;
1120                 unsigned offset;
1121 
1122                 /* clear event detection flags */
1123                 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1124                 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1125                 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1126                 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1127                 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1128                 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1129 
1130                 /* clear all the events */
1131                 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1132                 for_each_set_bit(offset, &events, 32)
1133                         bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1134 
1135                 raw_spin_lock_init(&pc->irq_lock[i]);
1136         }
1137 
1138         girq = &pc->gpio_chip.irq;
1139         girq->chip = &bcm2835_gpio_irq_chip;
1140         girq->parent_handler = bcm2835_gpio_irq_handler;
1141         girq->num_parents = BCM2835_NUM_IRQS;
1142         girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1143                                      sizeof(*girq->parents),
1144                                      GFP_KERNEL);
1145         if (!girq->parents)
1146                 return -ENOMEM;
1147         /*
1148          * Use the same handler for all groups: this is necessary
1149          * since we use one gpiochip to cover all lines - the
1150          * irq handler then needs to figure out which group and
1151          * bank that was firing the IRQ and look up the per-group
1152          * and bank data.
1153          */
1154         for (i = 0; i < BCM2835_NUM_IRQS; i++)
1155                 girq->parents[i] = irq_of_parse_and_map(np, i);
1156         girq->default_type = IRQ_TYPE_NONE;
1157         girq->handler = handle_level_irq;
1158 
1159         err = gpiochip_add_data(&pc->gpio_chip, pc);
1160         if (err) {
1161                 dev_err(dev, "could not add GPIO chip\n");
1162                 return err;
1163         }
1164 
1165         match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1166         if (match) {
1167                 bcm2835_pinctrl_desc.confops =
1168                         (const struct pinconf_ops *)match->data;
1169         }
1170 
1171         pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
1172         if (IS_ERR(pc->pctl_dev)) {
1173                 gpiochip_remove(&pc->gpio_chip);
1174                 return PTR_ERR(pc->pctl_dev);
1175         }
1176 
1177         pc->gpio_range = bcm2835_pinctrl_gpio_range;
1178         pc->gpio_range.base = pc->gpio_chip.base;
1179         pc->gpio_range.gc = &pc->gpio_chip;
1180         pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1181 
1182         return 0;
1183 }
1184 
1185 static struct platform_driver bcm2835_pinctrl_driver = {
1186         .probe = bcm2835_pinctrl_probe,
1187         .driver = {
1188                 .name = MODULE_NAME,
1189                 .of_match_table = bcm2835_pinctrl_match,
1190                 .suppress_bind_attrs = true,
1191         },
1192 };
1193 builtin_platform_driver(bcm2835_pinctrl_driver);

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