drivers/pinctrl/bcm/pinctrl-nsp-gpio.c

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This source file includes following definitions.
nsp_pin_to_gpio
nsp_set_bit
nsp_get_bit
nsp_gpio_irq_handler
nsp_gpio_irq_ack
nsp_gpio_irq_set_mask
nsp_gpio_irq_mask
nsp_gpio_irq_unmask
nsp_gpio_irq_set_type
nsp_gpio_direction_input
nsp_gpio_direction_output
nsp_gpio_set
nsp_gpio_get
nsp_gpio_to_irq
nsp_get_groups_count
nsp_get_group_name
nsp_gpio_set_slew
nsp_gpio_set_pull
nsp_gpio_get_pull
nsp_gpio_set_strength
nsp_gpio_get_strength
nsp_pin_config_group_get
nsp_pin_config_group_set
nsp_pin_config_get
nsp_pin_config_set
nsp_gpio_register_pinconf
nsp_gpio_probe
nsp_gpio_init
   1 /*
   2  * Copyright (C) 2014-2017 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13 
  14 /*
  15  * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that
  16  * supports the chipCommonA GPIO controller. Basic PINCONF such as bias,
  17  * pull up/down, slew and drive strength are also supported in this driver.
  18  *
  19  * Pins from the chipCommonA  GPIO can be individually muxed to GPIO function,
  20  * through the interaction with the NSP IOMUX controller.
  21  */
  22 
  23 #include <linux/gpio/driver.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/ioport.h>
  27 #include <linux/kernel.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_device.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/pinctrl/pinconf.h>
  32 #include <linux/pinctrl/pinconf-generic.h>
  33 #include <linux/pinctrl/pinctrl.h>
  34 #include <linux/slab.h>
  35 
  36 #include "../pinctrl-utils.h"
  37 
  38 #define NSP_CHIP_A_INT_STATUS           0x00
  39 #define NSP_CHIP_A_INT_MASK             0x04
  40 #define NSP_GPIO_DATA_IN                0x40
  41 #define NSP_GPIO_DATA_OUT               0x44
  42 #define NSP_GPIO_OUT_EN                 0x48
  43 #define NSP_GPIO_INT_POLARITY           0x50
  44 #define NSP_GPIO_INT_MASK               0x54
  45 #define NSP_GPIO_EVENT                  0x58
  46 #define NSP_GPIO_EVENT_INT_MASK         0x5c
  47 #define NSP_GPIO_EVENT_INT_POLARITY     0x64
  48 #define NSP_CHIP_A_GPIO_INT_BIT         0x01
  49 
  50 /* I/O parameters offset for chipcommon A GPIO */
  51 #define NSP_GPIO_DRV_CTRL               0x00
  52 #define NSP_GPIO_HYSTERESIS_EN          0x10
  53 #define NSP_GPIO_SLEW_RATE_EN           0x14
  54 #define NSP_PULL_UP_EN                  0x18
  55 #define NSP_PULL_DOWN_EN                0x1c
  56 #define GPIO_DRV_STRENGTH_BITS          0x03
  57 
  58 /*
  59  * nsp GPIO core
  60  *
  61  * @dev: pointer to device
  62  * @base: I/O register base for nsp GPIO controller
  63  * @io_ctrl: I/O register base for PINCONF support outside the GPIO block
  64  * @gc: GPIO chip
  65  * @pctl: pointer to pinctrl_dev
  66  * @pctldesc: pinctrl descriptor
  67  * @irq_domain: pointer to irq domain
  68  * @lock: lock to protect access to I/O registers
  69  */
  70 struct nsp_gpio {
  71         struct device *dev;
  72         void __iomem *base;
  73         void __iomem *io_ctrl;
  74         struct gpio_chip gc;
  75         struct pinctrl_dev *pctl;
  76         struct pinctrl_desc pctldesc;
  77         struct irq_domain *irq_domain;
  78         raw_spinlock_t lock;
  79 };
  80 
  81 enum base_type {
  82         REG,
  83         IO_CTRL
  84 };
  85 
  86 /*
  87  * Mapping from PINCONF pins to GPIO pins is 1-to-1
  88  */
  89 static inline unsigned nsp_pin_to_gpio(unsigned pin)
  90 {
  91         return pin;
  92 }
  93 
  94 /*
  95  *  nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
  96  *  nsp GPIO register
  97  *
  98  *  @nsp_gpio: nsp GPIO device
  99  *  @base_type: reg base to modify
 100  *  @reg: register offset
 101  *  @gpio: GPIO pin
 102  *  @set: set or clear
 103  */
 104 static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address,
 105                                unsigned int reg, unsigned gpio, bool set)
 106 {
 107         u32 val;
 108         void __iomem *base_address;
 109 
 110         if (address == IO_CTRL)
 111                 base_address = chip->io_ctrl;
 112         else
 113                 base_address = chip->base;
 114 
 115         val = readl(base_address + reg);
 116         if (set)
 117                 val |= BIT(gpio);
 118         else
 119                 val &= ~BIT(gpio);
 120 
 121         writel(val, base_address + reg);
 122 }
 123 
 124 /*
 125  *  nsp_get_bit - get one bit (corresponding to the GPIO pin) in a
 126  *  nsp GPIO register
 127  */
 128 static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address,
 129                                unsigned int reg, unsigned gpio)
 130 {
 131         if (address == IO_CTRL)
 132                 return !!(readl(chip->io_ctrl + reg) & BIT(gpio));
 133         else
 134                 return !!(readl(chip->base + reg) & BIT(gpio));
 135 }
 136 
 137 static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
 138 {
 139         struct nsp_gpio *chip = (struct nsp_gpio *)data;
 140         struct gpio_chip gc = chip->gc;
 141         int bit;
 142         unsigned long int_bits = 0;
 143         u32 int_status;
 144 
 145         /* go through the entire GPIOs and handle all interrupts */
 146         int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS);
 147         if (int_status & NSP_CHIP_A_GPIO_INT_BIT) {
 148                 unsigned int event, level;
 149 
 150                 /* Get level and edge interrupts */
 151                 event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) &
 152                               readl(chip->base + NSP_GPIO_EVENT);
 153                 level = readl(chip->base + NSP_GPIO_DATA_IN) ^
 154                               readl(chip->base + NSP_GPIO_INT_POLARITY);
 155                 level &= readl(chip->base + NSP_GPIO_INT_MASK);
 156                 int_bits = level | event;
 157 
 158                 for_each_set_bit(bit, &int_bits, gc.ngpio) {
 159                         /*
 160                          * Clear the interrupt before invoking the
 161                          * handler, so we do not leave any window
 162                          */
 163                         writel(BIT(bit), chip->base + NSP_GPIO_EVENT);
 164                         generic_handle_irq(
 165                                 irq_linear_revmap(chip->irq_domain, bit));
 166                 }
 167         }
 168 
 169         return  int_bits ? IRQ_HANDLED : IRQ_NONE;
 170 }
 171 
 172 static void nsp_gpio_irq_ack(struct irq_data *d)
 173 {
 174         struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
 175         unsigned gpio = d->hwirq;
 176         u32 val = BIT(gpio);
 177         u32 trigger_type;
 178 
 179         trigger_type = irq_get_trigger_type(d->irq);
 180         if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 181                 nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val);
 182 }
 183 
 184 /*
 185  *  nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt
 186  *
 187  *  @d: IRQ chip data
 188  *  @unmask: mask/unmask GPIO interrupt
 189  */
 190 static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
 191 {
 192         struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
 193         unsigned gpio = d->hwirq;
 194         u32 trigger_type;
 195 
 196         trigger_type = irq_get_trigger_type(d->irq);
 197         if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 198                 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
 199         else
 200                 nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
 201 }
 202 
 203 static void nsp_gpio_irq_mask(struct irq_data *d)
 204 {
 205         struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
 206         unsigned long flags;
 207 
 208         raw_spin_lock_irqsave(&chip->lock, flags);
 209         nsp_gpio_irq_set_mask(d, false);
 210         raw_spin_unlock_irqrestore(&chip->lock, flags);
 211 }
 212 
 213 static void nsp_gpio_irq_unmask(struct irq_data *d)
 214 {
 215         struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
 216         unsigned long flags;
 217 
 218         raw_spin_lock_irqsave(&chip->lock, flags);
 219         nsp_gpio_irq_set_mask(d, true);
 220         raw_spin_unlock_irqrestore(&chip->lock, flags);
 221 }
 222 
 223 static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 224 {
 225         struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
 226         unsigned gpio = d->hwirq;
 227         bool level_low;
 228         bool falling;
 229         unsigned long flags;
 230 
 231         raw_spin_lock_irqsave(&chip->lock, flags);
 232         falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
 233         level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
 234 
 235         switch (type & IRQ_TYPE_SENSE_MASK) {
 236         case IRQ_TYPE_EDGE_RISING:
 237                 falling = false;
 238                 break;
 239 
 240         case IRQ_TYPE_EDGE_FALLING:
 241                 falling = true;
 242                 break;
 243 
 244         case IRQ_TYPE_LEVEL_HIGH:
 245                 level_low = false;
 246                 break;
 247 
 248         case IRQ_TYPE_LEVEL_LOW:
 249                 level_low = true;
 250                 break;
 251 
 252         default:
 253                 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
 254                         type);
 255                 raw_spin_unlock_irqrestore(&chip->lock, flags);
 256                 return -EINVAL;
 257         }
 258 
 259         nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
 260         nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
 261         raw_spin_unlock_irqrestore(&chip->lock, flags);
 262 
 263         dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
 264                 level_low ? "true" : "false", falling ? "true" : "false");
 265         return 0;
 266 }
 267 
 268 static struct irq_chip nsp_gpio_irq_chip = {
 269         .name = "gpio-a",
 270         .irq_enable = nsp_gpio_irq_unmask,
 271         .irq_disable = nsp_gpio_irq_mask,
 272         .irq_ack = nsp_gpio_irq_ack,
 273         .irq_mask = nsp_gpio_irq_mask,
 274         .irq_unmask = nsp_gpio_irq_unmask,
 275         .irq_set_type = nsp_gpio_irq_set_type,
 276 };
 277 
 278 static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
 279 {
 280         struct nsp_gpio *chip = gpiochip_get_data(gc);
 281         unsigned long flags;
 282 
 283         raw_spin_lock_irqsave(&chip->lock, flags);
 284         nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
 285         raw_spin_unlock_irqrestore(&chip->lock, flags);
 286 
 287         dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
 288         return 0;
 289 }
 290 
 291 static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
 292                                      int val)
 293 {
 294         struct nsp_gpio *chip = gpiochip_get_data(gc);
 295         unsigned long flags;
 296 
 297         raw_spin_lock_irqsave(&chip->lock, flags);
 298         nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
 299         nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
 300         raw_spin_unlock_irqrestore(&chip->lock, flags);
 301 
 302         dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
 303         return 0;
 304 }
 305 
 306 static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
 307 {
 308         struct nsp_gpio *chip = gpiochip_get_data(gc);
 309         unsigned long flags;
 310 
 311         raw_spin_lock_irqsave(&chip->lock, flags);
 312         nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
 313         raw_spin_unlock_irqrestore(&chip->lock, flags);
 314 
 315         dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
 316 }
 317 
 318 static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
 319 {
 320         struct nsp_gpio *chip = gpiochip_get_data(gc);
 321 
 322         return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
 323 }
 324 
 325 static int nsp_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 326 {
 327         struct nsp_gpio *chip = gpiochip_get_data(gc);
 328 
 329         return irq_linear_revmap(chip->irq_domain, offset);
 330 }
 331 
 332 static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
 333 {
 334         return 1;
 335 }
 336 
 337 /*
 338  * Only one group: "gpio_grp", since this local pinctrl device only performs
 339  * GPIO specific PINCONF configurations
 340  */
 341 static const char *nsp_get_group_name(struct pinctrl_dev *pctldev,
 342                                       unsigned selector)
 343 {
 344         return "gpio_grp";
 345 }
 346 
 347 static const struct pinctrl_ops nsp_pctrl_ops = {
 348         .get_groups_count = nsp_get_groups_count,
 349         .get_group_name = nsp_get_group_name,
 350         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 351         .dt_free_map = pinctrl_utils_free_map,
 352 };
 353 
 354 static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u32 slew)
 355 {
 356         if (slew)
 357                 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true);
 358         else
 359                 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false);
 360 
 361         return 0;
 362 }
 363 
 364 static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
 365                              bool pull_up, bool pull_down)
 366 {
 367         unsigned long flags;
 368 
 369         raw_spin_lock_irqsave(&chip->lock, flags);
 370         nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
 371         nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
 372         raw_spin_unlock_irqrestore(&chip->lock, flags);
 373 
 374         dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
 375                 gpio, pull_up, pull_down);
 376         return 0;
 377 }
 378 
 379 static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
 380                               bool *pull_up, bool *pull_down)
 381 {
 382         unsigned long flags;
 383 
 384         raw_spin_lock_irqsave(&chip->lock, flags);
 385         *pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
 386         *pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
 387         raw_spin_unlock_irqrestore(&chip->lock, flags);
 388 }
 389 
 390 static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
 391                                  u32 strength)
 392 {
 393         u32 offset, shift, i;
 394         u32 val;
 395         unsigned long flags;
 396 
 397         /* make sure drive strength is supported */
 398         if (strength < 2 || strength > 16 || (strength % 2))
 399                 return -ENOTSUPP;
 400 
 401         shift = gpio;
 402         offset = NSP_GPIO_DRV_CTRL;
 403         dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
 404                 strength);
 405         raw_spin_lock_irqsave(&chip->lock, flags);
 406         strength = (strength / 2) - 1;
 407         for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
 408                 val = readl(chip->io_ctrl + offset);
 409                 val &= ~BIT(shift);
 410                 val |= ((strength >> (i-1)) & 0x1) << shift;
 411                 writel(val, chip->io_ctrl + offset);
 412                 offset += 4;
 413         }
 414         raw_spin_unlock_irqrestore(&chip->lock, flags);
 415 
 416         return 0;
 417 }
 418 
 419 static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
 420                                  u16 *strength)
 421 {
 422         unsigned int offset, shift;
 423         u32 val;
 424         unsigned long flags;
 425         int i;
 426 
 427         offset = NSP_GPIO_DRV_CTRL;
 428         shift = gpio;
 429 
 430         raw_spin_lock_irqsave(&chip->lock, flags);
 431         *strength = 0;
 432         for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
 433                 val = readl(chip->io_ctrl + offset) & BIT(shift);
 434                 val >>= shift;
 435                 *strength += (val << i);
 436                 offset += 4;
 437         }
 438 
 439         /* convert to mA */
 440         *strength = (*strength + 1) * 2;
 441         raw_spin_unlock_irqrestore(&chip->lock, flags);
 442 
 443         return 0;
 444 }
 445 
 446 static int nsp_pin_config_group_get(struct pinctrl_dev *pctldev,
 447                                     unsigned selector,
 448                              unsigned long *config)
 449 {
 450         return 0;
 451 }
 452 
 453 static int nsp_pin_config_group_set(struct pinctrl_dev *pctldev,
 454                                     unsigned selector,
 455                              unsigned long *configs, unsigned num_configs)
 456 {
 457         return 0;
 458 }
 459 
 460 static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
 461                               unsigned long *config)
 462 {
 463         struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
 464         enum pin_config_param param = pinconf_to_config_param(*config);
 465         unsigned int gpio;
 466         u16 arg = 0;
 467         bool pull_up, pull_down;
 468         int ret;
 469 
 470         gpio = nsp_pin_to_gpio(pin);
 471         switch (param) {
 472         case PIN_CONFIG_BIAS_DISABLE:
 473                 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
 474                 if ((pull_up == false) && (pull_down == false))
 475                         return 0;
 476                 else
 477                         return -EINVAL;
 478 
 479         case PIN_CONFIG_BIAS_PULL_UP:
 480                 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
 481                 if (pull_up)
 482                         return 0;
 483                 else
 484                         return -EINVAL;
 485 
 486         case PIN_CONFIG_BIAS_PULL_DOWN:
 487                 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
 488                 if (pull_down)
 489                         return 0;
 490                 else
 491                         return -EINVAL;
 492 
 493         case PIN_CONFIG_DRIVE_STRENGTH:
 494                 ret = nsp_gpio_get_strength(chip, gpio, &arg);
 495                 if (ret)
 496                         return ret;
 497                 *config = pinconf_to_config_packed(param, arg);
 498                 return 0;
 499 
 500         default:
 501                 return -ENOTSUPP;
 502         }
 503 }
 504 
 505 static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
 506                               unsigned long *configs, unsigned num_configs)
 507 {
 508         struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
 509         enum pin_config_param param;
 510         u32 arg;
 511         unsigned int i, gpio;
 512         int ret = -ENOTSUPP;
 513 
 514         gpio = nsp_pin_to_gpio(pin);
 515         for (i = 0; i < num_configs; i++) {
 516                 param = pinconf_to_config_param(configs[i]);
 517                 arg = pinconf_to_config_argument(configs[i]);
 518 
 519                 switch (param) {
 520                 case PIN_CONFIG_BIAS_DISABLE:
 521                         ret = nsp_gpio_set_pull(chip, gpio, false, false);
 522                         if (ret < 0)
 523                                 goto out;
 524                         break;
 525 
 526                 case PIN_CONFIG_BIAS_PULL_UP:
 527                         ret = nsp_gpio_set_pull(chip, gpio, true, false);
 528                         if (ret < 0)
 529                                 goto out;
 530                         break;
 531 
 532                 case PIN_CONFIG_BIAS_PULL_DOWN:
 533                         ret = nsp_gpio_set_pull(chip, gpio, false, true);
 534                         if (ret < 0)
 535                                 goto out;
 536                         break;
 537 
 538                 case PIN_CONFIG_DRIVE_STRENGTH:
 539                         ret = nsp_gpio_set_strength(chip, gpio, arg);
 540                         if (ret < 0)
 541                                 goto out;
 542                         break;
 543 
 544                 case PIN_CONFIG_SLEW_RATE:
 545                         ret = nsp_gpio_set_slew(chip, gpio, arg);
 546                         if (ret < 0)
 547                                 goto out;
 548                         break;
 549 
 550                 default:
 551                         dev_err(chip->dev, "invalid configuration\n");
 552                         return -ENOTSUPP;
 553                 }
 554         }
 555 
 556 out:
 557         return ret;
 558 }
 559 
 560 static const struct pinconf_ops nsp_pconf_ops = {
 561         .is_generic = true,
 562         .pin_config_get = nsp_pin_config_get,
 563         .pin_config_set = nsp_pin_config_set,
 564         .pin_config_group_get = nsp_pin_config_group_get,
 565         .pin_config_group_set = nsp_pin_config_group_set,
 566 };
 567 
 568 /*
 569  * NSP GPIO controller supports some PINCONF related configurations such as
 570  * pull up, pull down, slew and drive strength, when the pin is configured
 571  * to GPIO.
 572  *
 573  * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
 574  * local GPIO pins
 575  */
 576 static int nsp_gpio_register_pinconf(struct nsp_gpio *chip)
 577 {
 578         struct pinctrl_desc *pctldesc = &chip->pctldesc;
 579         struct pinctrl_pin_desc *pins;
 580         struct gpio_chip *gc = &chip->gc;
 581         int i;
 582 
 583         pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
 584         if (!pins)
 585                 return -ENOMEM;
 586         for (i = 0; i < gc->ngpio; i++) {
 587                 pins[i].number = i;
 588                 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
 589                                               "gpio-%d", i);
 590                 if (!pins[i].name)
 591                         return -ENOMEM;
 592         }
 593         pctldesc->name = dev_name(chip->dev);
 594         pctldesc->pctlops = &nsp_pctrl_ops;
 595         pctldesc->pins = pins;
 596         pctldesc->npins = gc->ngpio;
 597         pctldesc->confops = &nsp_pconf_ops;
 598 
 599         chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
 600         if (IS_ERR(chip->pctl)) {
 601                 dev_err(chip->dev, "unable to register pinctrl device\n");
 602                 return PTR_ERR(chip->pctl);
 603         }
 604 
 605         return 0;
 606 }
 607 
 608 static const struct of_device_id nsp_gpio_of_match[] = {
 609         {.compatible = "brcm,nsp-gpio-a",},
 610         {}
 611 };
 612 
 613 static int nsp_gpio_probe(struct platform_device *pdev)
 614 {
 615         struct device *dev = &pdev->dev;
 616         struct resource *res;
 617         struct nsp_gpio *chip;
 618         struct gpio_chip *gc;
 619         u32 val, count;
 620         int irq, ret;
 621 
 622         if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
 623                 dev_err(&pdev->dev, "Missing ngpios OF property\n");
 624                 return -ENODEV;
 625         }
 626 
 627         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
 628         if (!chip)
 629                 return -ENOMEM;
 630 
 631         chip->dev = dev;
 632         platform_set_drvdata(pdev, chip);
 633 
 634         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 635         chip->base = devm_ioremap_resource(dev, res);
 636         if (IS_ERR(chip->base)) {
 637                 dev_err(dev, "unable to map I/O memory\n");
 638                 return PTR_ERR(chip->base);
 639         }
 640 
 641         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 642         chip->io_ctrl = devm_ioremap_resource(dev, res);
 643         if (IS_ERR(chip->io_ctrl)) {
 644                 dev_err(dev, "unable to map I/O memory\n");
 645                 return PTR_ERR(chip->io_ctrl);
 646         }
 647 
 648         raw_spin_lock_init(&chip->lock);
 649         gc = &chip->gc;
 650         gc->base = -1;
 651         gc->can_sleep = false;
 652         gc->ngpio = val;
 653         gc->label = dev_name(dev);
 654         gc->parent = dev;
 655         gc->of_node = dev->of_node;
 656         gc->request = gpiochip_generic_request;
 657         gc->free = gpiochip_generic_free;
 658         gc->direction_input = nsp_gpio_direction_input;
 659         gc->direction_output = nsp_gpio_direction_output;
 660         gc->set = nsp_gpio_set;
 661         gc->get = nsp_gpio_get;
 662         gc->to_irq = nsp_gpio_to_irq;
 663 
 664         /* optional GPIO interrupt support */
 665         irq = platform_get_irq(pdev, 0);
 666         if (irq > 0) {
 667                 /* Create irq domain so that each pin can be assigned an IRQ.*/
 668                 chip->irq_domain = irq_domain_add_linear(gc->of_node, gc->ngpio,
 669                                                          &irq_domain_simple_ops,
 670                                                          chip);
 671                 if (!chip->irq_domain) {
 672                         dev_err(&pdev->dev, "Couldn't allocate IRQ domain\n");
 673                         return -ENXIO;
 674                 }
 675 
 676                 /* Map each gpio to an IRQ and set the handler for gpiolib. */
 677                 for (count = 0; count < gc->ngpio; count++) {
 678                         int irq = irq_create_mapping(chip->irq_domain, count);
 679 
 680                         irq_set_chip_and_handler(irq, &nsp_gpio_irq_chip,
 681                                                  handle_simple_irq);
 682                         irq_set_chip_data(irq, chip);
 683                 }
 684 
 685                 /* Install ISR for this GPIO controller. */
 686                 ret = devm_request_irq(&pdev->dev, irq, nsp_gpio_irq_handler,
 687                                        IRQF_SHARED, "gpio-a", chip);
 688                 if (ret) {
 689                         dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
 690                                 irq, ret);
 691                         goto err_rm_gpiochip;
 692                 }
 693 
 694                 val = readl(chip->base + NSP_CHIP_A_INT_MASK);
 695                 val = val | NSP_CHIP_A_GPIO_INT_BIT;
 696                 writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
 697         }
 698 
 699         ret = gpiochip_add_data(gc, chip);
 700         if (ret < 0) {
 701                 dev_err(dev, "unable to add GPIO chip\n");
 702                 return ret;
 703         }
 704 
 705         ret = nsp_gpio_register_pinconf(chip);
 706         if (ret) {
 707                 dev_err(dev, "unable to register pinconf\n");
 708                 goto err_rm_gpiochip;
 709         }
 710 
 711         return 0;
 712 
 713 err_rm_gpiochip:
 714         gpiochip_remove(gc);
 715 
 716         return ret;
 717 }
 718 
 719 static struct platform_driver nsp_gpio_driver = {
 720         .driver = {
 721                 .name = "nsp-gpio-a",
 722                 .of_match_table = nsp_gpio_of_match,
 723         },
 724         .probe = nsp_gpio_probe,
 725 };
 726 
 727 static int __init nsp_gpio_init(void)
 728 {
 729         return platform_driver_register(&nsp_gpio_driver);
 730 }
 731 arch_initcall_sync(nsp_gpio_init);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c

DEFINITIONS
